1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_mon.h"
8 #include "debug.h"
9 #include "dp_rx.h"
10 #include "dp_tx.h"
11 #include "peer.h"
12
13 static void
ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats * ppdu_end_user,struct hal_rx_user_status * rx_user_status)14 ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,
15 struct hal_rx_user_status *rx_user_status)
16 {
17 rx_user_status->ul_ofdma_user_v0_word0 =
18 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
19 rx_user_status->ul_ofdma_user_v0_word1 =
20 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
21 }
22
23 static void
ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats * stats,void * ppduinfo,struct hal_rx_user_status * rx_user_status)24 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
25 void *ppduinfo,
26 struct hal_rx_user_status *rx_user_status)
27 {
28 rx_user_status->mpdu_ok_byte_count =
29 le32_get_bits(stats->info7,
30 HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);
31 rx_user_status->mpdu_err_byte_count =
32 le32_get_bits(stats->info8,
33 HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);
34 }
35
36 static void
ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)37 ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,
38 struct hal_rx_mon_ppdu_info *ppdu_info,
39 struct hal_rx_user_status *rx_user_status)
40 {
41 rx_user_status->ast_index = ppdu_info->ast_index;
42 rx_user_status->tid = ppdu_info->tid;
43 rx_user_status->tcp_ack_msdu_count =
44 ppdu_info->tcp_ack_msdu_count;
45 rx_user_status->tcp_msdu_count =
46 ppdu_info->tcp_msdu_count;
47 rx_user_status->udp_msdu_count =
48 ppdu_info->udp_msdu_count;
49 rx_user_status->other_msdu_count =
50 ppdu_info->other_msdu_count;
51 rx_user_status->frame_control = ppdu_info->frame_control;
52 rx_user_status->frame_control_info_valid =
53 ppdu_info->frame_control_info_valid;
54 rx_user_status->data_sequence_control_info_valid =
55 ppdu_info->data_sequence_control_info_valid;
56 rx_user_status->first_data_seq_ctrl =
57 ppdu_info->first_data_seq_ctrl;
58 rx_user_status->preamble_type = ppdu_info->preamble_type;
59 rx_user_status->ht_flags = ppdu_info->ht_flags;
60 rx_user_status->vht_flags = ppdu_info->vht_flags;
61 rx_user_status->he_flags = ppdu_info->he_flags;
62 rx_user_status->rs_flags = ppdu_info->rs_flags;
63
64 rx_user_status->mpdu_cnt_fcs_ok =
65 ppdu_info->num_mpdu_fcs_ok;
66 rx_user_status->mpdu_cnt_fcs_err =
67 ppdu_info->num_mpdu_fcs_err;
68 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
69 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
70 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
71
72 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
73 }
74
ath12k_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info * vht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)75 static void ath12k_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info *vht_sig,
76 struct hal_rx_mon_ppdu_info *ppdu_info)
77 {
78 u32 nsts, group_id, info0, info1;
79 u8 gi_setting;
80
81 info0 = __le32_to_cpu(vht_sig->info0);
82 info1 = __le32_to_cpu(vht_sig->info1);
83
84 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
85 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
86 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
87 switch (gi_setting) {
88 case HAL_RX_VHT_SIG_A_NORMAL_GI:
89 ppdu_info->gi = HAL_RX_GI_0_8_US;
90 break;
91 case HAL_RX_VHT_SIG_A_SHORT_GI:
92 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
93 ppdu_info->gi = HAL_RX_GI_0_4_US;
94 break;
95 }
96
97 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
98 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
99 if (ppdu_info->is_stbc && nsts > 0)
100 nsts = ((nsts + 1) >> 1) - 1;
101
102 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK);
103 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
104 ppdu_info->beamformed = u32_get_bits(info1,
105 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
106 group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
107 if (group_id == 0 || group_id == 63)
108 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
109 else
110 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
111 ppdu_info->vht_flag_values5 = group_id;
112 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
113 ppdu_info->nss);
114 ppdu_info->vht_flag_values2 = ppdu_info->bw;
115 ppdu_info->vht_flag_values4 =
116 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
117 }
118
ath12k_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info * ht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)119 static void ath12k_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info *ht_sig,
120 struct hal_rx_mon_ppdu_info *ppdu_info)
121 {
122 u32 info0 = __le32_to_cpu(ht_sig->info0);
123 u32 info1 = __le32_to_cpu(ht_sig->info1);
124
125 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
126 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
127 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
128 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
129 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
130 ppdu_info->nss = (ppdu_info->mcs >> 3);
131 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
132 }
133
ath12k_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info * lsigb,struct hal_rx_mon_ppdu_info * ppdu_info)134 static void ath12k_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb,
135 struct hal_rx_mon_ppdu_info *ppdu_info)
136 {
137 u32 info0 = __le32_to_cpu(lsigb->info0);
138 u8 rate;
139
140 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
141 switch (rate) {
142 case 1:
143 rate = HAL_RX_LEGACY_RATE_1_MBPS;
144 break;
145 case 2:
146 case 5:
147 rate = HAL_RX_LEGACY_RATE_2_MBPS;
148 break;
149 case 3:
150 case 6:
151 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
152 break;
153 case 4:
154 case 7:
155 rate = HAL_RX_LEGACY_RATE_11_MBPS;
156 break;
157 default:
158 rate = HAL_RX_LEGACY_RATE_INVALID;
159 }
160
161 ppdu_info->rate = rate;
162 ppdu_info->cck_flag = 1;
163 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
164 }
165
ath12k_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info * lsiga,struct hal_rx_mon_ppdu_info * ppdu_info)166 static void ath12k_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info *lsiga,
167 struct hal_rx_mon_ppdu_info *ppdu_info)
168 {
169 u32 info0 = __le32_to_cpu(lsiga->info0);
170 u8 rate;
171
172 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
173 switch (rate) {
174 case 8:
175 rate = HAL_RX_LEGACY_RATE_48_MBPS;
176 break;
177 case 9:
178 rate = HAL_RX_LEGACY_RATE_24_MBPS;
179 break;
180 case 10:
181 rate = HAL_RX_LEGACY_RATE_12_MBPS;
182 break;
183 case 11:
184 rate = HAL_RX_LEGACY_RATE_6_MBPS;
185 break;
186 case 12:
187 rate = HAL_RX_LEGACY_RATE_54_MBPS;
188 break;
189 case 13:
190 rate = HAL_RX_LEGACY_RATE_36_MBPS;
191 break;
192 case 14:
193 rate = HAL_RX_LEGACY_RATE_18_MBPS;
194 break;
195 case 15:
196 rate = HAL_RX_LEGACY_RATE_9_MBPS;
197 break;
198 default:
199 rate = HAL_RX_LEGACY_RATE_INVALID;
200 }
201
202 ppdu_info->rate = rate;
203 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
204 }
205
206 static void
ath12k_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info * ofdma,struct hal_rx_mon_ppdu_info * ppdu_info)207 ath12k_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info *ofdma,
208 struct hal_rx_mon_ppdu_info *ppdu_info)
209 {
210 u32 info0, value;
211
212 info0 = __le32_to_cpu(ofdma->info0);
213
214 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
215
216 /* HE-data2 */
217 ppdu_info->he_data2 |= HE_TXBF_KNOWN;
218
219 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
220 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
221 ppdu_info->he_data3 |= value;
222
223 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
224 value = value << HE_DCM_SHIFT;
225 ppdu_info->he_data3 |= value;
226
227 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
228 ppdu_info->ldpc = value;
229 value = value << HE_CODING_SHIFT;
230 ppdu_info->he_data3 |= value;
231
232 /* HE-data4 */
233 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
234 value = value << HE_STA_ID_SHIFT;
235 ppdu_info->he_data4 |= value;
236
237 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS);
238 ppdu_info->beamformed = u32_get_bits(info0,
239 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
240 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
241 }
242
243 static void
ath12k_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info * he_sig_b2_mu,struct hal_rx_mon_ppdu_info * ppdu_info)244 ath12k_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu,
245 struct hal_rx_mon_ppdu_info *ppdu_info)
246 {
247 u32 info0, value;
248
249 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
250
251 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
252
253 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
254 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
255 ppdu_info->he_data3 |= value;
256
257 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
258 ppdu_info->ldpc = value;
259 value = value << HE_CODING_SHIFT;
260 ppdu_info->he_data3 |= value;
261
262 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
263 value = value << HE_STA_ID_SHIFT;
264 ppdu_info->he_data4 |= value;
265
266 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS);
267 }
268
269 static void
ath12k_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info * he_sig_b1_mu,struct hal_rx_mon_ppdu_info * ppdu_info)270 ath12k_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu,
271 struct hal_rx_mon_ppdu_info *ppdu_info)
272 {
273 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
274 u16 ru_tones;
275
276 ru_tones = u32_get_bits(info0,
277 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
278 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
279 ppdu_info->he_RU[0] = ru_tones;
280 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
281 }
282
283 static void
ath12k_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info * he_sig_a_mu_dl,struct hal_rx_mon_ppdu_info * ppdu_info)284 ath12k_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl,
285 struct hal_rx_mon_ppdu_info *ppdu_info)
286 {
287 u32 info0, info1, value;
288 u16 he_gi = 0, he_ltf = 0;
289
290 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
291 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
292
293 ppdu_info->he_mu_flags = 1;
294
295 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
296 ppdu_info->he_data1 |=
297 HE_BSS_COLOR_KNOWN |
298 HE_DL_UL_KNOWN |
299 HE_LDPC_EXTRA_SYMBOL_KNOWN |
300 HE_STBC_KNOWN |
301 HE_DATA_BW_RU_KNOWN |
302 HE_DOPPLER_KNOWN;
303
304 ppdu_info->he_data2 =
305 HE_GI_KNOWN |
306 HE_LTF_SYMBOLS_KNOWN |
307 HE_PRE_FEC_PADDING_KNOWN |
308 HE_PE_DISAMBIGUITY_KNOWN |
309 HE_TXOP_KNOWN |
310 HE_MIDABLE_PERIODICITY_KNOWN;
311
312 /* data3 */
313 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
314 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
315 value = value << HE_DL_UL_SHIFT;
316 ppdu_info->he_data3 |= value;
317
318 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
319 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
320 ppdu_info->he_data3 |= value;
321
322 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
323 value = value << HE_STBC_SHIFT;
324 ppdu_info->he_data3 |= value;
325
326 /* data4 */
327 ppdu_info->he_data4 = u32_get_bits(info0,
328 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
329 ppdu_info->he_data4 = value;
330
331 /* data5 */
332 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
333 ppdu_info->he_data5 = value;
334 ppdu_info->bw = value;
335
336 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
337 switch (value) {
338 case 0:
339 he_gi = HE_GI_0_8;
340 he_ltf = HE_LTF_4_X;
341 break;
342 case 1:
343 he_gi = HE_GI_0_8;
344 he_ltf = HE_LTF_2_X;
345 break;
346 case 2:
347 he_gi = HE_GI_1_6;
348 he_ltf = HE_LTF_2_X;
349 break;
350 case 3:
351 he_gi = HE_GI_3_2;
352 he_ltf = HE_LTF_4_X;
353 break;
354 }
355
356 ppdu_info->gi = he_gi;
357 value = he_gi << HE_GI_SHIFT;
358 ppdu_info->he_data5 |= value;
359
360 value = he_ltf << HE_LTF_SIZE_SHIFT;
361 ppdu_info->he_data5 |= value;
362
363 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
364 value = (value << HE_LTF_SYM_SHIFT);
365 ppdu_info->he_data5 |= value;
366
367 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
368 value = value << HE_PRE_FEC_PAD_SHIFT;
369 ppdu_info->he_data5 |= value;
370
371 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
372 value = value << HE_PE_DISAMBIGUITY_SHIFT;
373 ppdu_info->he_data5 |= value;
374
375 /*data6*/
376 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
377 value = value << HE_DOPPLER_SHIFT;
378 ppdu_info->he_data6 |= value;
379
380 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
381 value = value << HE_TXOP_SHIFT;
382 ppdu_info->he_data6 |= value;
383
384 /* HE-MU Flags */
385 /* HE-MU-flags1 */
386 ppdu_info->he_flags1 =
387 HE_SIG_B_MCS_KNOWN |
388 HE_SIG_B_DCM_KNOWN |
389 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
390 HE_SIG_B_SYM_NUM_KNOWN |
391 HE_RU_0_KNOWN;
392
393 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
394 ppdu_info->he_flags1 |= value;
395 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
396 value = value << HE_DCM_FLAG_1_SHIFT;
397 ppdu_info->he_flags1 |= value;
398
399 /* HE-MU-flags2 */
400 ppdu_info->he_flags2 = HE_BW_KNOWN;
401
402 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
403 ppdu_info->he_flags2 |= value;
404 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
405 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
406 ppdu_info->he_flags2 |= value;
407 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
408 value = value - 1;
409 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
410 ppdu_info->he_flags2 |= value;
411
412 ppdu_info->is_stbc = info1 &
413 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
414 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
415 }
416
ath12k_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info * he_sig_a,struct hal_rx_mon_ppdu_info * ppdu_info)417 static void ath12k_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info *he_sig_a,
418 struct hal_rx_mon_ppdu_info *ppdu_info)
419 {
420 u32 info0, info1, value;
421 u32 dcm;
422 u8 he_dcm = 0, he_stbc = 0;
423 u16 he_gi = 0, he_ltf = 0;
424
425 ppdu_info->he_flags = 1;
426
427 info0 = __le32_to_cpu(he_sig_a->info0);
428 info1 = __le32_to_cpu(he_sig_a->info1);
429
430 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
431 if (value == 0)
432 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
433 else
434 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
435
436 ppdu_info->he_data1 |=
437 HE_BSS_COLOR_KNOWN |
438 HE_BEAM_CHANGE_KNOWN |
439 HE_DL_UL_KNOWN |
440 HE_MCS_KNOWN |
441 HE_DCM_KNOWN |
442 HE_CODING_KNOWN |
443 HE_LDPC_EXTRA_SYMBOL_KNOWN |
444 HE_STBC_KNOWN |
445 HE_DATA_BW_RU_KNOWN |
446 HE_DOPPLER_KNOWN;
447
448 ppdu_info->he_data2 |=
449 HE_GI_KNOWN |
450 HE_TXBF_KNOWN |
451 HE_PE_DISAMBIGUITY_KNOWN |
452 HE_TXOP_KNOWN |
453 HE_LTF_SYMBOLS_KNOWN |
454 HE_PRE_FEC_PADDING_KNOWN |
455 HE_MIDABLE_PERIODICITY_KNOWN;
456
457 ppdu_info->he_data3 = u32_get_bits(info0,
458 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
459 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
460 value = value << HE_BEAM_CHANGE_SHIFT;
461 ppdu_info->he_data3 |= value;
462 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
463 value = value << HE_DL_UL_SHIFT;
464 ppdu_info->he_data3 |= value;
465
466 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
467 ppdu_info->mcs = value;
468 value = value << HE_TRANSMIT_MCS_SHIFT;
469 ppdu_info->he_data3 |= value;
470
471 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
472 he_dcm = value;
473 value = value << HE_DCM_SHIFT;
474 ppdu_info->he_data3 |= value;
475 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
476 value = value << HE_CODING_SHIFT;
477 ppdu_info->he_data3 |= value;
478 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
479 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
480 ppdu_info->he_data3 |= value;
481 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
482 he_stbc = value;
483 value = value << HE_STBC_SHIFT;
484 ppdu_info->he_data3 |= value;
485
486 /* data4 */
487 ppdu_info->he_data4 = u32_get_bits(info0,
488 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
489
490 /* data5 */
491 value = u32_get_bits(info0,
492 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
493 ppdu_info->he_data5 = value;
494 ppdu_info->bw = value;
495 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
496 switch (value) {
497 case 0:
498 he_gi = HE_GI_0_8;
499 he_ltf = HE_LTF_1_X;
500 break;
501 case 1:
502 he_gi = HE_GI_0_8;
503 he_ltf = HE_LTF_2_X;
504 break;
505 case 2:
506 he_gi = HE_GI_1_6;
507 he_ltf = HE_LTF_2_X;
508 break;
509 case 3:
510 if (he_dcm && he_stbc) {
511 he_gi = HE_GI_0_8;
512 he_ltf = HE_LTF_4_X;
513 } else {
514 he_gi = HE_GI_3_2;
515 he_ltf = HE_LTF_4_X;
516 }
517 break;
518 }
519 ppdu_info->gi = he_gi;
520 value = he_gi << HE_GI_SHIFT;
521 ppdu_info->he_data5 |= value;
522 value = he_ltf << HE_LTF_SIZE_SHIFT;
523 ppdu_info->ltf_size = he_ltf;
524 ppdu_info->he_data5 |= value;
525
526 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
527 value = (value << HE_LTF_SYM_SHIFT);
528 ppdu_info->he_data5 |= value;
529
530 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
531 value = value << HE_PRE_FEC_PAD_SHIFT;
532 ppdu_info->he_data5 |= value;
533
534 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
535 value = value << HE_TXBF_SHIFT;
536 ppdu_info->he_data5 |= value;
537 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
538 value = value << HE_PE_DISAMBIGUITY_SHIFT;
539 ppdu_info->he_data5 |= value;
540
541 /* data6 */
542 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
543 value++;
544 ppdu_info->he_data6 = value;
545 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
546 value = value << HE_DOPPLER_SHIFT;
547 ppdu_info->he_data6 |= value;
548 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
549 value = value << HE_TXOP_SHIFT;
550 ppdu_info->he_data6 |= value;
551
552 ppdu_info->mcs =
553 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
554 ppdu_info->bw =
555 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
556 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
557 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
558 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
559 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
560 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
561 ppdu_info->dcm = dcm;
562 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
563 }
564
565 static enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u32 tlv_tag,const void * tlv_data,u32 userid)566 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab,
567 struct ath12k_mon_data *pmon,
568 u32 tlv_tag, const void *tlv_data,
569 u32 userid)
570 {
571 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
572 u32 info[7];
573
574 switch (tlv_tag) {
575 case HAL_RX_PPDU_START: {
576 const struct hal_rx_ppdu_start *ppdu_start = tlv_data;
577
578 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32,
579 ppdu_start->ppdu_start_ts_31_0);
580
581 info[0] = __le32_to_cpu(ppdu_start->info0);
582
583 ppdu_info->ppdu_id = u32_get_bits(info[0],
584 HAL_RX_PPDU_START_INFO0_PPDU_ID);
585
586 info[1] = __le32_to_cpu(ppdu_start->info1);
587 ppdu_info->chan_num = u32_get_bits(info[1],
588 HAL_RX_PPDU_START_INFO1_CHAN_NUM);
589 ppdu_info->freq = u32_get_bits(info[1],
590 HAL_RX_PPDU_START_INFO1_CHAN_FREQ);
591 ppdu_info->ppdu_ts = ppdu_ts;
592
593 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
594 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
595 ppdu_info->num_users = 0;
596 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
597 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
598 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
599 }
600 break;
601 }
602 case HAL_RX_PPDU_END_USER_STATS: {
603 const struct hal_rx_ppdu_end_user_stats *eu_stats = tlv_data;
604 u32 tid_bitmap;
605
606 info[0] = __le32_to_cpu(eu_stats->info0);
607 info[1] = __le32_to_cpu(eu_stats->info1);
608 info[2] = __le32_to_cpu(eu_stats->info2);
609 info[4] = __le32_to_cpu(eu_stats->info4);
610 info[5] = __le32_to_cpu(eu_stats->info5);
611 info[6] = __le32_to_cpu(eu_stats->info6);
612
613 ppdu_info->ast_index =
614 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
615 ppdu_info->fc_valid =
616 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
617 tid_bitmap = u32_get_bits(info[6],
618 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP);
619 ppdu_info->tid = ffs(tid_bitmap) - 1;
620 ppdu_info->tcp_msdu_count =
621 u32_get_bits(info[4],
622 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
623 ppdu_info->udp_msdu_count =
624 u32_get_bits(info[4],
625 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
626 ppdu_info->other_msdu_count =
627 u32_get_bits(info[5],
628 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
629 ppdu_info->tcp_ack_msdu_count =
630 u32_get_bits(info[5],
631 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
632 ppdu_info->preamble_type =
633 u32_get_bits(info[1],
634 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
635 ppdu_info->num_mpdu_fcs_ok =
636 u32_get_bits(info[1],
637 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
638 ppdu_info->num_mpdu_fcs_err =
639 u32_get_bits(info[0],
640 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
641 switch (ppdu_info->preamble_type) {
642 case HAL_RX_PREAMBLE_11N:
643 ppdu_info->ht_flags = 1;
644 break;
645 case HAL_RX_PREAMBLE_11AC:
646 ppdu_info->vht_flags = 1;
647 break;
648 case HAL_RX_PREAMBLE_11AX:
649 ppdu_info->he_flags = 1;
650 break;
651 default:
652 break;
653 }
654
655 if (userid < HAL_MAX_UL_MU_USERS) {
656 struct hal_rx_user_status *rxuser_stats =
657 &ppdu_info->userstats[userid];
658 ppdu_info->num_users += 1;
659
660 ath12k_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats);
661 ath12k_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info,
662 rxuser_stats);
663 }
664 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
665 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
666 break;
667 }
668 case HAL_RX_PPDU_END_USER_STATS_EXT: {
669 const struct hal_rx_ppdu_end_user_stats_ext *eu_stats = tlv_data;
670
671 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
672 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
673 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
674 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
675 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
676 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
677 break;
678 }
679 case HAL_PHYRX_HT_SIG:
680 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
681 break;
682
683 case HAL_PHYRX_L_SIG_B:
684 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
685 break;
686
687 case HAL_PHYRX_L_SIG_A:
688 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
689 break;
690
691 case HAL_PHYRX_VHT_SIG_A:
692 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
693 break;
694
695 case HAL_PHYRX_HE_SIG_A_SU:
696 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
697 break;
698
699 case HAL_PHYRX_HE_SIG_A_MU_DL:
700 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
701 break;
702
703 case HAL_PHYRX_HE_SIG_B1_MU:
704 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
705 break;
706
707 case HAL_PHYRX_HE_SIG_B2_MU:
708 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
709 break;
710
711 case HAL_PHYRX_HE_SIG_B2_OFDMA:
712 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
713 break;
714
715 case HAL_PHYRX_RSSI_LEGACY: {
716 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data;
717
718 info[0] = __le32_to_cpu(rssi->info0);
719 info[1] = __le32_to_cpu(rssi->info1);
720
721 /* TODO: Please note that the combined rssi will not be accurate
722 * in MU case. Rssi in MU needs to be retrieved from
723 * PHYRX_OTHER_RECEIVE_INFO TLV.
724 */
725 ppdu_info->rssi_comb =
726 u32_get_bits(info[1],
727 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB);
728
729 ppdu_info->bw = u32_get_bits(info[0],
730 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW);
731 break;
732 }
733 case HAL_RXPCU_PPDU_END_INFO: {
734 const struct hal_rx_ppdu_end_duration *ppdu_rx_duration = tlv_data;
735
736 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
737 ppdu_info->rx_duration =
738 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
739 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
740 ppdu_info->tsft = (ppdu_info->tsft << 32) |
741 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
742 break;
743 }
744 case HAL_RX_MPDU_START: {
745 const struct hal_rx_mpdu_start *mpdu_start = tlv_data;
746 u16 peer_id;
747
748 info[1] = __le32_to_cpu(mpdu_start->info1);
749 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
750 if (peer_id)
751 ppdu_info->peer_id = peer_id;
752
753 ppdu_info->mpdu_len += u32_get_bits(info[1],
754 HAL_RX_MPDU_START_INFO2_MPDU_LEN);
755 if (userid < HAL_MAX_UL_MU_USERS) {
756 info[0] = __le32_to_cpu(mpdu_start->info0);
757 ppdu_info->userid = userid;
758 ppdu_info->ampdu_id[userid] =
759 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID);
760 }
761
762 break;
763 }
764 case HAL_RX_MSDU_START:
765 /* TODO: add msdu start parsing logic */
766 break;
767 case HAL_MON_BUF_ADDR:
768 return HAL_RX_MON_STATUS_BUF_ADDR;
769 case HAL_RX_MSDU_END:
770 return HAL_RX_MON_STATUS_MSDU_END;
771 case HAL_RX_MPDU_END:
772 return HAL_RX_MON_STATUS_MPDU_END;
773 case HAL_DUMMY:
774 return HAL_RX_MON_STATUS_BUF_DONE;
775 case HAL_RX_PPDU_END_STATUS_DONE:
776 case 0:
777 return HAL_RX_MON_STATUS_PPDU_DONE;
778 default:
779 break;
780 }
781
782 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
783 }
784
ath12k_dp_mon_rx_msdus_set_payload(struct ath12k * ar,struct sk_buff * head_msdu,struct sk_buff * tail_msdu)785 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar,
786 struct sk_buff *head_msdu,
787 struct sk_buff *tail_msdu)
788 {
789 u32 rx_pkt_offset, l2_hdr_offset;
790
791 rx_pkt_offset = ar->ab->hal.hal_desc_sz;
792 l2_hdr_offset =
793 ath12k_dp_rx_h_l3pad(ar->ab, (struct hal_rx_desc *)tail_msdu->data);
794 skb_pull(head_msdu, rx_pkt_offset + l2_hdr_offset);
795 }
796
797 static struct sk_buff *
ath12k_dp_mon_rx_merg_msdus(struct ath12k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)798 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, u32 mac_id,
799 struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
800 struct ieee80211_rx_status *rxs, bool *fcs_err)
801 {
802 struct ath12k_base *ab = ar->ab;
803 struct sk_buff *msdu, *mpdu_buf, *prev_buf, *head_frag_list;
804 struct hal_rx_desc *rx_desc, *tail_rx_desc;
805 u8 *hdr_desc, *dest, decap_format;
806 struct ieee80211_hdr_3addr *wh;
807 u32 err_bitmap, frag_list_sum_len = 0;
808
809 mpdu_buf = NULL;
810
811 if (!head_msdu)
812 goto err_merge_fail;
813
814 rx_desc = (struct hal_rx_desc *)head_msdu->data;
815 tail_rx_desc = (struct hal_rx_desc *)tail_msdu->data;
816
817 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, tail_rx_desc);
818 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
819 *fcs_err = true;
820
821 decap_format = ath12k_dp_rx_h_decap_type(ab, tail_rx_desc);
822
823 ath12k_dp_rx_h_ppdu(ar, tail_rx_desc, rxs);
824
825 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
826 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu, tail_msdu);
827
828 prev_buf = head_msdu;
829 msdu = head_msdu->next;
830 head_frag_list = NULL;
831
832 while (msdu) {
833 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
834
835 if (!head_frag_list)
836 head_frag_list = msdu;
837
838 frag_list_sum_len += msdu->len;
839 prev_buf = msdu;
840 msdu = msdu->next;
841 }
842
843 prev_buf->next = NULL;
844
845 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
846 if (head_frag_list) {
847 skb_shinfo(head_msdu)->frag_list = head_frag_list;
848 head_msdu->data_len = frag_list_sum_len;
849 head_msdu->len += head_msdu->data_len;
850 head_msdu->next = NULL;
851 }
852 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
853 u8 qos_pkt = 0;
854
855 rx_desc = (struct hal_rx_desc *)head_msdu->data;
856 hdr_desc =
857 ab->hal_rx_ops->rx_desc_get_msdu_payload(rx_desc);
858
859 /* Base size */
860 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
861
862 if (ieee80211_is_data_qos(wh->frame_control))
863 qos_pkt = 1;
864
865 msdu = head_msdu;
866
867 while (msdu) {
868 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
869 if (qos_pkt) {
870 dest = skb_push(msdu, sizeof(__le16));
871 if (!dest)
872 goto err_merge_fail;
873 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
874 }
875 prev_buf = msdu;
876 msdu = msdu->next;
877 }
878 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
879 if (!dest)
880 goto err_merge_fail;
881
882 ath12k_dbg(ab, ATH12K_DBG_DATA,
883 "mpdu_buf %p mpdu_buf->len %u",
884 prev_buf, prev_buf->len);
885 } else {
886 ath12k_dbg(ab, ATH12K_DBG_DATA,
887 "decap format %d is not supported!\n",
888 decap_format);
889 goto err_merge_fail;
890 }
891
892 return head_msdu;
893
894 err_merge_fail:
895 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
896 ath12k_dbg(ab, ATH12K_DBG_DATA,
897 "err_merge_fail mpdu_buf %p", mpdu_buf);
898 /* Free the head buffer */
899 dev_kfree_skb_any(mpdu_buf);
900 }
901 return NULL;
902 }
903
904 static void
ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)905 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
906 u8 *rtap_buf)
907 {
908 u32 rtap_len = 0;
909
910 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
911 rtap_len += 2;
912
913 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
914 rtap_len += 2;
915
916 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
917 rtap_len += 2;
918
919 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
920 rtap_len += 2;
921
922 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
923 rtap_len += 2;
924
925 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
926 }
927
928 static void
ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)929 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
930 u8 *rtap_buf)
931 {
932 u32 rtap_len = 0;
933
934 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
935 rtap_len += 2;
936
937 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
938 rtap_len += 2;
939
940 rtap_buf[rtap_len] = rx_status->he_RU[0];
941 rtap_len += 1;
942
943 rtap_buf[rtap_len] = rx_status->he_RU[1];
944 rtap_len += 1;
945
946 rtap_buf[rtap_len] = rx_status->he_RU[2];
947 rtap_len += 1;
948
949 rtap_buf[rtap_len] = rx_status->he_RU[3];
950 }
951
ath12k_dp_mon_update_radiotap(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)952 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar,
953 struct hal_rx_mon_ppdu_info *ppduinfo,
954 struct sk_buff *mon_skb,
955 struct ieee80211_rx_status *rxs)
956 {
957 struct ieee80211_supported_band *sband;
958 u8 *ptr = NULL;
959 u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid];
960
961 rxs->flag |= RX_FLAG_MACTIME_START;
962 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR;
963 rxs->nss = ppduinfo->nss + 1;
964
965 if (ampdu_id) {
966 rxs->flag |= RX_FLAG_AMPDU_DETAILS;
967 rxs->ampdu_reference = ampdu_id;
968 }
969
970 if (ppduinfo->he_mu_flags) {
971 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
972 rxs->encoding = RX_ENC_HE;
973 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
974 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr);
975 } else if (ppduinfo->he_flags) {
976 rxs->flag |= RX_FLAG_RADIOTAP_HE;
977 rxs->encoding = RX_ENC_HE;
978 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
979 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr);
980 rxs->rate_idx = ppduinfo->rate;
981 } else if (ppduinfo->vht_flags) {
982 rxs->encoding = RX_ENC_VHT;
983 rxs->rate_idx = ppduinfo->rate;
984 } else if (ppduinfo->ht_flags) {
985 rxs->encoding = RX_ENC_HT;
986 rxs->rate_idx = ppduinfo->rate;
987 } else {
988 rxs->encoding = RX_ENC_LEGACY;
989 sband = &ar->mac.sbands[rxs->band];
990 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
991 ppduinfo->cck_flag);
992 }
993
994 rxs->mactime = ppduinfo->tsft;
995 }
996
ath12k_dp_mon_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)997 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
998 struct sk_buff *msdu,
999 struct ieee80211_rx_status *status)
1000 {
1001 static const struct ieee80211_radiotap_he known = {
1002 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1003 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1004 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1005 };
1006 struct ieee80211_rx_status *rx_status;
1007 struct ieee80211_radiotap_he *he = NULL;
1008 struct ieee80211_sta *pubsta = NULL;
1009 struct ath12k_peer *peer;
1010 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1011 u8 decap = DP_RX_DECAP_TYPE_RAW;
1012 bool is_mcbc = rxcb->is_mcbc;
1013 bool is_eapol_tkip = rxcb->is_eapol;
1014
1015 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
1016 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
1017 he = skb_push(msdu, sizeof(known));
1018 memcpy(he, &known, sizeof(known));
1019 status->flag |= RX_FLAG_RADIOTAP_HE;
1020 }
1021
1022 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
1023 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc);
1024 spin_lock_bh(&ar->ab->base_lock);
1025 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
1026 if (peer && peer->sta) {
1027 pubsta = peer->sta;
1028 if (pubsta->valid_links) {
1029 status->link_valid = 1;
1030 status->link_id = peer->link_id;
1031 }
1032 }
1033
1034 spin_unlock_bh(&ar->ab->base_lock);
1035
1036 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
1037 "rx skb %p len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
1038 msdu,
1039 msdu->len,
1040 peer ? peer->addr : NULL,
1041 rxcb->tid,
1042 (is_mcbc) ? "mcast" : "ucast",
1043 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
1044 (status->encoding == RX_ENC_HT) ? "ht" : "",
1045 (status->encoding == RX_ENC_VHT) ? "vht" : "",
1046 (status->encoding == RX_ENC_HE) ? "he" : "",
1047 (status->bw == RATE_INFO_BW_40) ? "40" : "",
1048 (status->bw == RATE_INFO_BW_80) ? "80" : "",
1049 (status->bw == RATE_INFO_BW_160) ? "160" : "",
1050 (status->bw == RATE_INFO_BW_320) ? "320" : "",
1051 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
1052 status->rate_idx,
1053 status->nss,
1054 status->freq,
1055 status->band, status->flag,
1056 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
1057 !!(status->flag & RX_FLAG_MMIC_ERROR),
1058 !!(status->flag & RX_FLAG_AMSDU_MORE));
1059
1060 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
1061 msdu->data, msdu->len);
1062 rx_status = IEEE80211_SKB_RXCB(msdu);
1063 *rx_status = *status;
1064
1065 /* TODO: trace rx packet */
1066
1067 /* PN for multicast packets are not validate in HW,
1068 * so skip 802.3 rx path
1069 * Also, fast_rx expects the STA to be authorized, hence
1070 * eapol packets are sent in slow path.
1071 */
1072 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip &&
1073 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
1074 rx_status->flag |= RX_FLAG_8023;
1075
1076 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
1077 }
1078
ath12k_dp_mon_rx_deliver(struct ath12k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct napi_struct * napi)1079 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id,
1080 struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
1081 struct hal_rx_mon_ppdu_info *ppduinfo,
1082 struct napi_struct *napi)
1083 {
1084 struct ath12k_pdev_dp *dp = &ar->dp;
1085 struct sk_buff *mon_skb, *skb_next, *header;
1086 struct ieee80211_rx_status *rxs = &dp->rx_status;
1087 bool fcs_err = false;
1088
1089 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id,
1090 head_msdu, tail_msdu,
1091 rxs, &fcs_err);
1092 if (!mon_skb)
1093 goto mon_deliver_fail;
1094
1095 header = mon_skb;
1096 rxs->flag = 0;
1097
1098 if (fcs_err)
1099 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
1100
1101 do {
1102 skb_next = mon_skb->next;
1103 if (!skb_next)
1104 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
1105 else
1106 rxs->flag |= RX_FLAG_AMSDU_MORE;
1107
1108 if (mon_skb == header) {
1109 header = NULL;
1110 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
1111 } else {
1112 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
1113 }
1114 rxs->flag |= RX_FLAG_ONLY_MONITOR;
1115 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs);
1116 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs);
1117 mon_skb = skb_next;
1118 } while (mon_skb);
1119 rxs->flag = 0;
1120
1121 return 0;
1122
1123 mon_deliver_fail:
1124 mon_skb = head_msdu;
1125 while (mon_skb) {
1126 skb_next = mon_skb->next;
1127 dev_kfree_skb_any(mon_skb);
1128 mon_skb = skb_next;
1129 }
1130 return -EINVAL;
1131 }
1132
1133 static enum hal_rx_mon_status
ath12k_dp_mon_parse_rx_dest(struct ath12k_base * ab,struct ath12k_mon_data * pmon,struct sk_buff * skb)1134 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon,
1135 struct sk_buff *skb)
1136 {
1137 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1138 struct hal_tlv_64_hdr *tlv;
1139 enum hal_rx_mon_status hal_status;
1140 u32 tlv_userid;
1141 u16 tlv_tag, tlv_len;
1142 u8 *ptr = skb->data;
1143
1144 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info));
1145
1146 do {
1147 tlv = (struct hal_tlv_64_hdr *)ptr;
1148 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG);
1149 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN);
1150 tlv_userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID);
1151 ptr += sizeof(*tlv);
1152
1153 /* The actual length of PPDU_END is the combined length of many PHY
1154 * TLVs that follow. Skip the TLV header and
1155 * rx_rxpcu_classification_overview that follows the header to get to
1156 * next TLV.
1157 */
1158
1159 if (tlv_tag == HAL_RX_PPDU_END)
1160 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1161
1162 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon,
1163 tlv_tag, ptr, tlv_userid);
1164 ptr += tlv_len;
1165 ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN);
1166
1167 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1168 break;
1169
1170 } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) ||
1171 (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) ||
1172 (hal_status == HAL_RX_MON_STATUS_MPDU_END) ||
1173 (hal_status == HAL_RX_MON_STATUS_MSDU_END));
1174
1175 return hal_status;
1176 }
1177
1178 enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,int mac_id,struct sk_buff * skb,struct napi_struct * napi)1179 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,
1180 struct ath12k_mon_data *pmon,
1181 int mac_id,
1182 struct sk_buff *skb,
1183 struct napi_struct *napi)
1184 {
1185 struct ath12k_base *ab = ar->ab;
1186 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1187 struct dp_mon_mpdu *tmp;
1188 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
1189 struct sk_buff *head_msdu, *tail_msdu;
1190 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1191
1192 ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
1193
1194 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
1195 list_del(&mon_mpdu->list);
1196 head_msdu = mon_mpdu->head;
1197 tail_msdu = mon_mpdu->tail;
1198
1199 if (head_msdu && tail_msdu) {
1200 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1201 tail_msdu, ppdu_info, napi);
1202 }
1203
1204 kfree(mon_mpdu);
1205 }
1206 return hal_status;
1207 }
1208
ath12k_dp_mon_buf_replenish(struct ath12k_base * ab,struct dp_rxdma_mon_ring * buf_ring,int req_entries)1209 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,
1210 struct dp_rxdma_mon_ring *buf_ring,
1211 int req_entries)
1212 {
1213 struct hal_mon_buf_ring *mon_buf;
1214 struct sk_buff *skb;
1215 struct hal_srng *srng;
1216 dma_addr_t paddr;
1217 u32 cookie;
1218 int buf_id;
1219
1220 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id];
1221 spin_lock_bh(&srng->lock);
1222 ath12k_hal_srng_access_begin(ab, srng);
1223
1224 while (req_entries > 0) {
1225 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE);
1226 if (unlikely(!skb))
1227 goto fail_alloc_skb;
1228
1229 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) {
1230 skb_pull(skb,
1231 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
1232 skb->data);
1233 }
1234
1235 paddr = dma_map_single(ab->dev, skb->data,
1236 skb->len + skb_tailroom(skb),
1237 DMA_FROM_DEVICE);
1238
1239 if (unlikely(dma_mapping_error(ab->dev, paddr)))
1240 goto fail_free_skb;
1241
1242 spin_lock_bh(&buf_ring->idr_lock);
1243 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0,
1244 buf_ring->bufs_max * 3, GFP_ATOMIC);
1245 spin_unlock_bh(&buf_ring->idr_lock);
1246
1247 if (unlikely(buf_id < 0))
1248 goto fail_dma_unmap;
1249
1250 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng);
1251 if (unlikely(!mon_buf))
1252 goto fail_idr_remove;
1253
1254 ATH12K_SKB_RXCB(skb)->paddr = paddr;
1255
1256 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
1257
1258 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr));
1259 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr));
1260 mon_buf->cookie = cpu_to_le64(cookie);
1261
1262 req_entries--;
1263 }
1264
1265 ath12k_hal_srng_access_end(ab, srng);
1266 spin_unlock_bh(&srng->lock);
1267 return 0;
1268
1269 fail_idr_remove:
1270 spin_lock_bh(&buf_ring->idr_lock);
1271 idr_remove(&buf_ring->bufs_idr, buf_id);
1272 spin_unlock_bh(&buf_ring->idr_lock);
1273 fail_dma_unmap:
1274 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
1275 DMA_FROM_DEVICE);
1276 fail_free_skb:
1277 dev_kfree_skb_any(skb);
1278 fail_alloc_skb:
1279 ath12k_hal_srng_access_end(ab, srng);
1280 spin_unlock_bh(&srng->lock);
1281 return -ENOMEM;
1282 }
1283
1284 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data * pmon,unsigned int ppdu_id,enum dp_mon_tx_ppdu_info_type type)1285 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
1286 unsigned int ppdu_id,
1287 enum dp_mon_tx_ppdu_info_type type)
1288 {
1289 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1290
1291 if (type == DP_MON_TX_PROT_PPDU_INFO) {
1292 tx_ppdu_info = pmon->tx_prot_ppdu_info;
1293
1294 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1295 return tx_ppdu_info;
1296 kfree(tx_ppdu_info);
1297 } else {
1298 tx_ppdu_info = pmon->tx_data_ppdu_info;
1299
1300 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1301 return tx_ppdu_info;
1302 kfree(tx_ppdu_info);
1303 }
1304
1305 /* allocate new tx_ppdu_info */
1306 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC);
1307 if (!tx_ppdu_info)
1308 return NULL;
1309
1310 tx_ppdu_info->is_used = 0;
1311 tx_ppdu_info->ppdu_id = ppdu_id;
1312
1313 if (type == DP_MON_TX_PROT_PPDU_INFO)
1314 pmon->tx_prot_ppdu_info = tx_ppdu_info;
1315 else
1316 pmon->tx_data_ppdu_info = tx_ppdu_info;
1317
1318 return tx_ppdu_info;
1319 }
1320
1321 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data * pmon,u16 tlv_tag)1322 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
1323 u16 tlv_tag)
1324 {
1325 switch (tlv_tag) {
1326 case HAL_TX_FES_SETUP:
1327 case HAL_TX_FLUSH:
1328 case HAL_PCU_PPDU_SETUP_INIT:
1329 case HAL_TX_PEER_ENTRY:
1330 case HAL_TX_QUEUE_EXTENSION:
1331 case HAL_TX_MPDU_START:
1332 case HAL_TX_MSDU_START:
1333 case HAL_TX_DATA:
1334 case HAL_MON_BUF_ADDR:
1335 case HAL_TX_MPDU_END:
1336 case HAL_TX_LAST_MPDU_FETCHED:
1337 case HAL_TX_LAST_MPDU_END:
1338 case HAL_COEX_TX_REQ:
1339 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
1340 case HAL_SCH_CRITICAL_TLV_REFERENCE:
1341 case HAL_TX_FES_SETUP_COMPLETE:
1342 case HAL_TQM_MPDU_GLOBAL_START:
1343 case HAL_SCHEDULER_END:
1344 case HAL_TX_FES_STATUS_USER_PPDU:
1345 break;
1346 case HAL_TX_FES_STATUS_PROT: {
1347 if (!pmon->tx_prot_ppdu_info->is_used)
1348 pmon->tx_prot_ppdu_info->is_used = true;
1349
1350 return pmon->tx_prot_ppdu_info;
1351 }
1352 }
1353
1354 if (!pmon->tx_data_ppdu_info->is_used)
1355 pmon->tx_data_ppdu_info->is_used = true;
1356
1357 return pmon->tx_data_ppdu_info;
1358 }
1359
1360 #define MAX_MONITOR_HEADER 512
1361 #define MAX_DUMMY_FRM_BODY 128
1362
ath12k_dp_mon_tx_alloc_skb(void)1363 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void)
1364 {
1365 struct sk_buff *skb;
1366
1367 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
1368 if (!skb)
1369 return NULL;
1370
1371 skb_reserve(skb, MAX_MONITOR_HEADER);
1372
1373 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1374 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
1375
1376 return skb;
1377 }
1378
1379 static int
ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1380 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1381 {
1382 struct sk_buff *skb;
1383 struct ieee80211_cts *cts;
1384
1385 skb = ath12k_dp_mon_tx_alloc_skb();
1386 if (!skb)
1387 return -ENOMEM;
1388
1389 cts = (struct ieee80211_cts *)skb->data;
1390 memset(cts, 0, MAX_DUMMY_FRM_BODY);
1391 cts->frame_control =
1392 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
1393 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1394 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
1395
1396 skb_put(skb, sizeof(*cts));
1397 tx_ppdu_info->tx_mon_mpdu->head = skb;
1398 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1399 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1400 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1401
1402 return 0;
1403 }
1404
1405 static int
ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1406 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1407 {
1408 struct sk_buff *skb;
1409 struct ieee80211_rts *rts;
1410
1411 skb = ath12k_dp_mon_tx_alloc_skb();
1412 if (!skb)
1413 return -ENOMEM;
1414
1415 rts = (struct ieee80211_rts *)skb->data;
1416 memset(rts, 0, MAX_DUMMY_FRM_BODY);
1417 rts->frame_control =
1418 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
1419 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1420 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
1421 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
1422
1423 skb_put(skb, sizeof(*rts));
1424 tx_ppdu_info->tx_mon_mpdu->head = skb;
1425 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1426 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1427 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1428
1429 return 0;
1430 }
1431
1432 static int
ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1433 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1434 {
1435 struct sk_buff *skb;
1436 struct ieee80211_qos_hdr *qhdr;
1437
1438 skb = ath12k_dp_mon_tx_alloc_skb();
1439 if (!skb)
1440 return -ENOMEM;
1441
1442 qhdr = (struct ieee80211_qos_hdr *)skb->data;
1443 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1444 qhdr->frame_control =
1445 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1446 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1447 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1448 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1449 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1450
1451 skb_put(skb, sizeof(*qhdr));
1452 tx_ppdu_info->tx_mon_mpdu->head = skb;
1453 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1454 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1455 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1456
1457 return 0;
1458 }
1459
1460 static int
ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1461 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1462 {
1463 struct sk_buff *skb;
1464 struct dp_mon_qosframe_addr4 *qhdr;
1465
1466 skb = ath12k_dp_mon_tx_alloc_skb();
1467 if (!skb)
1468 return -ENOMEM;
1469
1470 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
1471 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1472 qhdr->frame_control =
1473 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1474 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1475 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1476 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1477 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1478 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
1479
1480 skb_put(skb, sizeof(*qhdr));
1481 tx_ppdu_info->tx_mon_mpdu->head = skb;
1482 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1483 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1484 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1485
1486 return 0;
1487 }
1488
1489 static int
ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1490 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1491 {
1492 struct sk_buff *skb;
1493 struct dp_mon_frame_min_one *fbmhdr;
1494
1495 skb = ath12k_dp_mon_tx_alloc_skb();
1496 if (!skb)
1497 return -ENOMEM;
1498
1499 fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
1500 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
1501 fbmhdr->frame_control =
1502 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
1503 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1504
1505 /* set duration zero for ack frame */
1506 fbmhdr->duration = 0;
1507
1508 skb_put(skb, sizeof(*fbmhdr));
1509 tx_ppdu_info->tx_mon_mpdu->head = skb;
1510 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1511 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1512 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1513
1514 return 0;
1515 }
1516
1517 static int
ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1518 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1519 {
1520 int ret = 0;
1521
1522 switch (tx_ppdu_info->rx_status.medium_prot_type) {
1523 case DP_MON_TX_MEDIUM_RTS_LEGACY:
1524 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
1525 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
1526 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
1527 break;
1528 case DP_MON_TX_MEDIUM_CTS2SELF:
1529 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1530 break;
1531 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
1532 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
1533 break;
1534 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
1535 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
1536 break;
1537 }
1538
1539 return ret;
1540 }
1541
1542 static enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u16 tlv_tag,const void * tlv_data,u32 userid)1543 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
1544 struct ath12k_mon_data *pmon,
1545 u16 tlv_tag, const void *tlv_data, u32 userid)
1546 {
1547 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1548 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1549 u32 info[7];
1550
1551 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
1552
1553 switch (tlv_tag) {
1554 case HAL_TX_FES_SETUP: {
1555 const struct hal_tx_fes_setup *tx_fes_setup = tlv_data;
1556
1557 info[0] = __le32_to_cpu(tx_fes_setup->info0);
1558 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
1559 tx_ppdu_info->num_users =
1560 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1561 status = DP_MON_TX_FES_SETUP;
1562 break;
1563 }
1564
1565 case HAL_TX_FES_STATUS_END: {
1566 const struct hal_tx_fes_status_end *tx_fes_status_end = tlv_data;
1567 u32 tst_15_0, tst_31_16;
1568
1569 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
1570 tst_15_0 =
1571 u32_get_bits(info[0],
1572 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
1573 tst_31_16 =
1574 u32_get_bits(info[0],
1575 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
1576
1577 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
1578 status = DP_MON_TX_FES_STATUS_END;
1579 break;
1580 }
1581
1582 case HAL_RX_RESPONSE_REQUIRED_INFO: {
1583 const struct hal_rx_resp_req_info *rx_resp_req_info = tlv_data;
1584 u32 addr_32;
1585 u16 addr_16;
1586
1587 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
1588 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
1589 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
1590 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
1591 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
1592 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
1593
1594 tx_ppdu_info->rx_status.ppdu_id =
1595 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
1596 tx_ppdu_info->rx_status.reception_type =
1597 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
1598 tx_ppdu_info->rx_status.rx_duration =
1599 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
1600 tx_ppdu_info->rx_status.mcs =
1601 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
1602 tx_ppdu_info->rx_status.sgi =
1603 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
1604 tx_ppdu_info->rx_status.is_stbc =
1605 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
1606 tx_ppdu_info->rx_status.ldpc =
1607 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
1608 tx_ppdu_info->rx_status.is_ampdu =
1609 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
1610 tx_ppdu_info->rx_status.num_users =
1611 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
1612
1613 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
1614 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
1615 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1616
1617 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
1618 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
1619 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1620
1621 if (tx_ppdu_info->rx_status.reception_type == 0)
1622 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1623 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1624 break;
1625 }
1626
1627 case HAL_PCU_PPDU_SETUP_INIT: {
1628 const struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = tlv_data;
1629 u32 addr_32;
1630 u16 addr_16;
1631
1632 info[0] = __le32_to_cpu(ppdu_setup->info0);
1633 info[1] = __le32_to_cpu(ppdu_setup->info1);
1634 info[2] = __le32_to_cpu(ppdu_setup->info2);
1635 info[3] = __le32_to_cpu(ppdu_setup->info3);
1636 info[4] = __le32_to_cpu(ppdu_setup->info4);
1637 info[5] = __le32_to_cpu(ppdu_setup->info5);
1638 info[6] = __le32_to_cpu(ppdu_setup->info6);
1639
1640 /* protection frame address 1 */
1641 addr_32 = u32_get_bits(info[1],
1642 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
1643 addr_16 = u32_get_bits(info[2],
1644 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
1645 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1646
1647 /* protection frame address 2 */
1648 addr_16 = u32_get_bits(info[2],
1649 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
1650 addr_32 = u32_get_bits(info[3],
1651 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
1652 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1653
1654 /* protection frame address 3 */
1655 addr_32 = u32_get_bits(info[4],
1656 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
1657 addr_16 = u32_get_bits(info[5],
1658 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
1659 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
1660
1661 /* protection frame address 4 */
1662 addr_16 = u32_get_bits(info[5],
1663 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
1664 addr_32 = u32_get_bits(info[6],
1665 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
1666 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
1667
1668 status = u32_get_bits(info[0],
1669 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
1670 break;
1671 }
1672
1673 case HAL_TX_QUEUE_EXTENSION: {
1674 const struct hal_tx_queue_exten *tx_q_exten = tlv_data;
1675
1676 info[0] = __le32_to_cpu(tx_q_exten->info0);
1677
1678 tx_ppdu_info->rx_status.frame_control =
1679 u32_get_bits(info[0],
1680 HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
1681 tx_ppdu_info->rx_status.fc_valid = true;
1682 break;
1683 }
1684
1685 case HAL_TX_FES_STATUS_START: {
1686 const struct hal_tx_fes_status_start *tx_fes_start = tlv_data;
1687
1688 info[0] = __le32_to_cpu(tx_fes_start->info0);
1689
1690 tx_ppdu_info->rx_status.medium_prot_type =
1691 u32_get_bits(info[0],
1692 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
1693 break;
1694 }
1695
1696 case HAL_TX_FES_STATUS_PROT: {
1697 const struct hal_tx_fes_status_prot *tx_fes_status = tlv_data;
1698 u32 start_timestamp;
1699 u32 end_timestamp;
1700
1701 info[0] = __le32_to_cpu(tx_fes_status->info0);
1702 info[1] = __le32_to_cpu(tx_fes_status->info1);
1703
1704 start_timestamp =
1705 u32_get_bits(info[0],
1706 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
1707 start_timestamp |=
1708 u32_get_bits(info[0],
1709 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
1710 end_timestamp =
1711 u32_get_bits(info[1],
1712 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
1713 end_timestamp |=
1714 u32_get_bits(info[1],
1715 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
1716 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
1717
1718 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
1719 break;
1720 }
1721
1722 case HAL_TX_FES_STATUS_START_PPDU:
1723 case HAL_TX_FES_STATUS_START_PROT: {
1724 const struct hal_tx_fes_status_start_prot *tx_fes_stat_start = tlv_data;
1725 u64 ppdu_ts;
1726
1727 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
1728
1729 tx_ppdu_info->rx_status.ppdu_ts =
1730 u32_get_bits(info[0],
1731 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
1732 ppdu_ts = (u32_get_bits(info[1],
1733 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
1734 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
1735 break;
1736 }
1737
1738 case HAL_TX_FES_STATUS_USER_PPDU: {
1739 const struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = tlv_data;
1740
1741 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
1742
1743 tx_ppdu_info->rx_status.rx_duration =
1744 u32_get_bits(info[0],
1745 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
1746 break;
1747 }
1748
1749 case HAL_MACTX_HE_SIG_A_SU:
1750 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status);
1751 break;
1752
1753 case HAL_MACTX_HE_SIG_A_MU_DL:
1754 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
1755 break;
1756
1757 case HAL_MACTX_HE_SIG_B1_MU:
1758 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status);
1759 break;
1760
1761 case HAL_MACTX_HE_SIG_B2_MU:
1762 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status);
1763 break;
1764
1765 case HAL_MACTX_HE_SIG_B2_OFDMA:
1766 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status);
1767 break;
1768
1769 case HAL_MACTX_VHT_SIG_A:
1770 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1771 break;
1772
1773 case HAL_MACTX_L_SIG_A:
1774 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1775 break;
1776
1777 case HAL_MACTX_L_SIG_B:
1778 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
1779 break;
1780
1781 case HAL_RX_FRAME_BITMAP_ACK: {
1782 const struct hal_rx_frame_bitmap_ack *fbm_ack = tlv_data;
1783 u32 addr_32;
1784 u16 addr_16;
1785
1786 info[0] = __le32_to_cpu(fbm_ack->info0);
1787 info[1] = __le32_to_cpu(fbm_ack->info1);
1788
1789 addr_32 = u32_get_bits(info[0],
1790 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
1791 addr_16 = u32_get_bits(info[1],
1792 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
1793 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1794
1795 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
1796 break;
1797 }
1798
1799 case HAL_MACTX_PHY_DESC: {
1800 const struct hal_tx_phy_desc *tx_phy_desc = tlv_data;
1801
1802 info[0] = __le32_to_cpu(tx_phy_desc->info0);
1803 info[1] = __le32_to_cpu(tx_phy_desc->info1);
1804 info[2] = __le32_to_cpu(tx_phy_desc->info2);
1805 info[3] = __le32_to_cpu(tx_phy_desc->info3);
1806
1807 tx_ppdu_info->rx_status.beamformed =
1808 u32_get_bits(info[0],
1809 HAL_TX_PHY_DESC_INFO0_BF_TYPE);
1810 tx_ppdu_info->rx_status.preamble_type =
1811 u32_get_bits(info[0],
1812 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
1813 tx_ppdu_info->rx_status.mcs =
1814 u32_get_bits(info[1],
1815 HAL_TX_PHY_DESC_INFO1_MCS);
1816 tx_ppdu_info->rx_status.ltf_size =
1817 u32_get_bits(info[3],
1818 HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
1819 tx_ppdu_info->rx_status.nss =
1820 u32_get_bits(info[2],
1821 HAL_TX_PHY_DESC_INFO2_NSS);
1822 tx_ppdu_info->rx_status.chan_num =
1823 u32_get_bits(info[3],
1824 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
1825 tx_ppdu_info->rx_status.bw =
1826 u32_get_bits(info[0],
1827 HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
1828 break;
1829 }
1830
1831 case HAL_TX_MPDU_START: {
1832 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
1833
1834 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
1835 if (!mon_mpdu)
1836 return DP_MON_TX_STATUS_PPDU_NOT_DONE;
1837 status = DP_MON_TX_MPDU_START;
1838 break;
1839 }
1840
1841 case HAL_TX_MPDU_END:
1842 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1843 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1844 break;
1845 }
1846
1847 return status;
1848 }
1849
1850 enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,struct hal_tlv_hdr * tx_tlv,u8 * num_users)1851 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,
1852 struct hal_tlv_hdr *tx_tlv,
1853 u8 *num_users)
1854 {
1855 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1856 u32 info0;
1857
1858 switch (tlv_tag) {
1859 case HAL_TX_FES_SETUP: {
1860 struct hal_tx_fes_setup *tx_fes_setup =
1861 (struct hal_tx_fes_setup *)tx_tlv;
1862
1863 info0 = __le32_to_cpu(tx_fes_setup->info0);
1864
1865 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1866 tlv_status = DP_MON_TX_FES_SETUP;
1867 break;
1868 }
1869
1870 case HAL_RX_RESPONSE_REQUIRED_INFO: {
1871 /* TODO: need to update *num_users */
1872 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1873 break;
1874 }
1875 }
1876
1877 return tlv_status;
1878 }
1879
1880 static void
ath12k_dp_mon_tx_process_ppdu_info(struct ath12k * ar,int mac_id,struct napi_struct * napi,struct dp_mon_tx_ppdu_info * tx_ppdu_info)1881 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id,
1882 struct napi_struct *napi,
1883 struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1884 {
1885 struct dp_mon_mpdu *tmp, *mon_mpdu;
1886 struct sk_buff *head_msdu, *tail_msdu;
1887
1888 list_for_each_entry_safe(mon_mpdu, tmp,
1889 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
1890 list_del(&mon_mpdu->list);
1891 head_msdu = mon_mpdu->head;
1892 tail_msdu = mon_mpdu->tail;
1893
1894 if (head_msdu)
1895 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, tail_msdu,
1896 &tx_ppdu_info->rx_status, napi);
1897
1898 kfree(mon_mpdu);
1899 }
1900 }
1901
1902 enum hal_rx_mon_status
ath12k_dp_mon_tx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,int mac_id,struct sk_buff * skb,struct napi_struct * napi,u32 ppdu_id)1903 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar,
1904 struct ath12k_mon_data *pmon,
1905 int mac_id,
1906 struct sk_buff *skb,
1907 struct napi_struct *napi,
1908 u32 ppdu_id)
1909 {
1910 struct ath12k_base *ab = ar->ab;
1911 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
1912 struct hal_tlv_hdr *tlv;
1913 u8 *ptr = skb->data;
1914 u16 tlv_tag;
1915 u16 tlv_len;
1916 u32 tlv_userid = 0;
1917 u8 num_user;
1918 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1919
1920 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
1921 DP_MON_TX_PROT_PPDU_INFO);
1922 if (!tx_prot_ppdu_info)
1923 return -ENOMEM;
1924
1925 tlv = (struct hal_tlv_hdr *)ptr;
1926 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1927
1928 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user);
1929 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
1930 return -EINVAL;
1931
1932 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
1933 DP_MON_TX_DATA_PPDU_INFO);
1934 if (!tx_data_ppdu_info)
1935 return -ENOMEM;
1936
1937 do {
1938 tlv = (struct hal_tlv_hdr *)ptr;
1939 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1940 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
1941 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
1942
1943 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon,
1944 tlv_tag, ptr,
1945 tlv_userid);
1946 ptr += tlv_len;
1947 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1948 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
1949 break;
1950 } while (tlv_status != DP_MON_TX_FES_STATUS_END);
1951
1952 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info);
1953 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info);
1954
1955 return tlv_status;
1956 }
1957
ath12k_dp_mon_srng_process(struct ath12k * ar,int mac_id,int * budget,enum dp_monitor_mode monitor_mode,struct napi_struct * napi)1958 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget,
1959 enum dp_monitor_mode monitor_mode,
1960 struct napi_struct *napi)
1961 {
1962 struct hal_mon_dest_desc *mon_dst_desc;
1963 struct ath12k_pdev_dp *pdev_dp = &ar->dp;
1964 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
1965 struct ath12k_base *ab = ar->ab;
1966 struct ath12k_dp *dp = &ab->dp;
1967 struct sk_buff *skb;
1968 struct ath12k_skb_rxcb *rxcb;
1969 struct dp_srng *mon_dst_ring;
1970 struct hal_srng *srng;
1971 struct dp_rxdma_mon_ring *buf_ring;
1972 u64 cookie;
1973 u32 ppdu_id;
1974 int num_buffs_reaped = 0, srng_id, buf_id;
1975 u8 dest_idx = 0, i;
1976 bool end_of_ppdu;
1977 struct hal_rx_mon_ppdu_info *ppdu_info;
1978 struct ath12k_peer *peer = NULL;
1979
1980 ppdu_info = &pmon->mon_ppdu_info;
1981 memset(ppdu_info, 0, sizeof(*ppdu_info));
1982 ppdu_info->peer_id = HAL_INVALID_PEERID;
1983
1984 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
1985
1986 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) {
1987 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
1988 buf_ring = &dp->rxdma_mon_buf_ring;
1989 } else {
1990 return 0;
1991 }
1992
1993 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
1994
1995 spin_lock_bh(&srng->lock);
1996 ath12k_hal_srng_access_begin(ab, srng);
1997
1998 while (likely(*budget)) {
1999 *budget -= 1;
2000 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2001 if (unlikely(!mon_dst_desc))
2002 break;
2003
2004 cookie = le32_to_cpu(mon_dst_desc->cookie);
2005 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2006
2007 spin_lock_bh(&buf_ring->idr_lock);
2008 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2009 spin_unlock_bh(&buf_ring->idr_lock);
2010
2011 if (unlikely(!skb)) {
2012 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2013 buf_id);
2014 goto move_next;
2015 }
2016
2017 rxcb = ATH12K_SKB_RXCB(skb);
2018 dma_unmap_single(ab->dev, rxcb->paddr,
2019 skb->len + skb_tailroom(skb),
2020 DMA_FROM_DEVICE);
2021
2022 pmon->dest_skb_q[dest_idx] = skb;
2023 dest_idx++;
2024 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id);
2025 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2026 HAL_MON_DEST_INFO0_END_OF_PPDU);
2027 if (!end_of_ppdu)
2028 continue;
2029
2030 for (i = 0; i < dest_idx; i++) {
2031 skb = pmon->dest_skb_q[i];
2032
2033 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
2034 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id,
2035 skb, napi);
2036 else
2037 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id,
2038 skb, napi, ppdu_id);
2039
2040 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2041
2042 if (!peer || !peer->sta) {
2043 ath12k_dbg(ab, ATH12K_DBG_DATA,
2044 "failed to find the peer with peer_id %d\n",
2045 ppdu_info->peer_id);
2046 dev_kfree_skb_any(skb);
2047 continue;
2048 }
2049
2050 dev_kfree_skb_any(skb);
2051 pmon->dest_skb_q[i] = NULL;
2052 }
2053
2054 dest_idx = 0;
2055 move_next:
2056 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2057 ath12k_hal_srng_dst_get_next_entry(ab, srng);
2058 num_buffs_reaped++;
2059 }
2060
2061 ath12k_hal_srng_access_end(ab, srng);
2062 spin_unlock_bh(&srng->lock);
2063
2064 return num_buffs_reaped;
2065 }
2066
2067 static void
ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats * rx_stats,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * user_stats,u32 num_msdu)2068 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats,
2069 struct hal_rx_mon_ppdu_info *ppdu_info,
2070 struct hal_rx_user_status *user_stats,
2071 u32 num_msdu)
2072 {
2073 u32 rate_idx = 0;
2074 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs;
2075 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1;
2076 u32 bw_idx = ppdu_info->bw;
2077 u32 gi_idx = ppdu_info->gi;
2078
2079 if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) ||
2080 (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) {
2081 return;
2082 }
2083
2084 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N ||
2085 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) {
2086 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx;
2087 rate_idx += bw_idx * 2 + gi_idx;
2088 } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) {
2089 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi);
2090 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx;
2091 rate_idx += bw_idx * 3 + gi_idx;
2092 } else {
2093 return;
2094 }
2095
2096 rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu;
2097 if (user_stats)
2098 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count;
2099 else
2100 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len;
2101 }
2102
ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k * ar,struct ath12k_link_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2103 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar,
2104 struct ath12k_link_sta *arsta,
2105 struct hal_rx_mon_ppdu_info *ppdu_info)
2106 {
2107 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats;
2108 u32 num_msdu;
2109
2110 if (!rx_stats)
2111 return;
2112
2113 arsta->rssi_comb = ppdu_info->rssi_comb;
2114
2115 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2116 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2117
2118 rx_stats->num_msdu += num_msdu;
2119 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2120 ppdu_info->tcp_ack_msdu_count;
2121 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2122 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2123
2124 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2125 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2126 ppdu_info->nss = 1;
2127 ppdu_info->mcs = HAL_RX_MAX_MCS;
2128 ppdu_info->tid = IEEE80211_NUM_TIDS;
2129 }
2130
2131 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2132 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2133
2134 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2135 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2136
2137 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2138 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2139
2140 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2141 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2142
2143 if (ppdu_info->is_stbc)
2144 rx_stats->stbc_count += num_msdu;
2145
2146 if (ppdu_info->beamformed)
2147 rx_stats->beamformed_count += num_msdu;
2148
2149 if (ppdu_info->num_mpdu_fcs_ok > 1)
2150 rx_stats->ampdu_msdu_count += num_msdu;
2151 else
2152 rx_stats->non_ampdu_msdu_count += num_msdu;
2153
2154 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2155 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2156 rx_stats->dcm_count += ppdu_info->dcm;
2157
2158 rx_stats->rx_duration += ppdu_info->rx_duration;
2159 arsta->rx_duration = rx_stats->rx_duration;
2160
2161 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) {
2162 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu;
2163 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len;
2164 }
2165
2166 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N &&
2167 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) {
2168 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu;
2169 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2170 /* To fit into rate table for HT packets */
2171 ppdu_info->mcs = ppdu_info->mcs % 8;
2172 }
2173
2174 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC &&
2175 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) {
2176 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu;
2177 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2178 }
2179
2180 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX &&
2181 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) {
2182 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu;
2183 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2184 }
2185
2186 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2187 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) &&
2188 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) {
2189 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu;
2190 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len;
2191 }
2192
2193 if (ppdu_info->gi < HAL_RX_GI_MAX) {
2194 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2195 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len;
2196 }
2197
2198 if (ppdu_info->bw < HAL_RX_BW_MAX) {
2199 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2200 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len;
2201 }
2202
2203 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2204 NULL, num_msdu);
2205 }
2206
ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info * ppdu_info)2207 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info)
2208 {
2209 struct hal_rx_user_status *rx_user_status;
2210 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size;
2211
2212 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
2213 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2214 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
2215 return;
2216
2217 num_users = ppdu_info->num_users;
2218 if (num_users > HAL_MAX_UL_MU_USERS)
2219 num_users = HAL_MAX_UL_MU_USERS;
2220
2221 for (i = 0; i < num_users; i++) {
2222 rx_user_status = &ppdu_info->userstats[i];
2223 mu_ul_user_v0_word0 =
2224 rx_user_status->ul_ofdma_user_v0_word0;
2225 mu_ul_user_v0_word1 =
2226 rx_user_status->ul_ofdma_user_v0_word1;
2227
2228 if (u32_get_bits(mu_ul_user_v0_word0,
2229 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) &&
2230 !u32_get_bits(mu_ul_user_v0_word0,
2231 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) {
2232 rx_user_status->mcs =
2233 u32_get_bits(mu_ul_user_v0_word1,
2234 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS);
2235 rx_user_status->nss =
2236 u32_get_bits(mu_ul_user_v0_word1,
2237 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1;
2238
2239 rx_user_status->ofdma_info_valid = 1;
2240 rx_user_status->ul_ofdma_ru_start_index =
2241 u32_get_bits(mu_ul_user_v0_word1,
2242 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START);
2243
2244 ru_size = u32_get_bits(mu_ul_user_v0_word1,
2245 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE);
2246 rx_user_status->ul_ofdma_ru_width = ru_size;
2247 rx_user_status->ul_ofdma_ru_size = ru_size;
2248 }
2249 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1,
2250 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC);
2251 }
2252 ppdu_info->ldpc = 1;
2253 }
2254
2255 static void
ath12k_dp_mon_rx_update_user_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info,u32 uid)2256 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar,
2257 struct hal_rx_mon_ppdu_info *ppdu_info,
2258 u32 uid)
2259 {
2260 struct ath12k_sta *ahsta;
2261 struct ath12k_link_sta *arsta;
2262 struct ath12k_rx_peer_stats *rx_stats = NULL;
2263 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid];
2264 struct ath12k_peer *peer;
2265 u32 num_msdu;
2266
2267 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF)
2268 return;
2269
2270 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index);
2271
2272 if (!peer) {
2273 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n",
2274 user_stats->ast_index);
2275 return;
2276 }
2277
2278 ahsta = ath12k_sta_to_ahsta(peer->sta);
2279 arsta = &ahsta->deflink;
2280 rx_stats = arsta->rx_stats;
2281
2282 if (!rx_stats)
2283 return;
2284
2285 arsta->rssi_comb = ppdu_info->rssi_comb;
2286
2287 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count +
2288 user_stats->udp_msdu_count + user_stats->other_msdu_count;
2289
2290 rx_stats->num_msdu += num_msdu;
2291 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count +
2292 user_stats->tcp_ack_msdu_count;
2293 rx_stats->udp_msdu_count += user_stats->udp_msdu_count;
2294 rx_stats->other_msdu_count += user_stats->other_msdu_count;
2295
2296 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2297 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2298
2299 if (user_stats->tid <= IEEE80211_NUM_TIDS)
2300 rx_stats->tid_count[user_stats->tid] += num_msdu;
2301
2302 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX)
2303 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu;
2304
2305 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2306 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2307
2308 if (ppdu_info->is_stbc)
2309 rx_stats->stbc_count += num_msdu;
2310
2311 if (ppdu_info->beamformed)
2312 rx_stats->beamformed_count += num_msdu;
2313
2314 if (user_stats->mpdu_cnt_fcs_ok > 1)
2315 rx_stats->ampdu_msdu_count += num_msdu;
2316 else
2317 rx_stats->non_ampdu_msdu_count += num_msdu;
2318
2319 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok;
2320 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err;
2321 rx_stats->dcm_count += ppdu_info->dcm;
2322 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2323 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)
2324 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu;
2325
2326 rx_stats->rx_duration += ppdu_info->rx_duration;
2327 arsta->rx_duration = rx_stats->rx_duration;
2328
2329 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) {
2330 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu;
2331 rx_stats->byte_stats.nss_count[user_stats->nss - 1] +=
2332 user_stats->mpdu_ok_byte_count;
2333 }
2334
2335 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX &&
2336 user_stats->mcs <= HAL_RX_MAX_MCS_HE) {
2337 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu;
2338 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] +=
2339 user_stats->mpdu_ok_byte_count;
2340 }
2341
2342 if (ppdu_info->gi < HAL_RX_GI_MAX) {
2343 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2344 rx_stats->byte_stats.gi_count[ppdu_info->gi] +=
2345 user_stats->mpdu_ok_byte_count;
2346 }
2347
2348 if (ppdu_info->bw < HAL_RX_BW_MAX) {
2349 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2350 rx_stats->byte_stats.bw_count[ppdu_info->bw] +=
2351 user_stats->mpdu_ok_byte_count;
2352 }
2353
2354 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2355 user_stats, num_msdu);
2356 }
2357
2358 static void
ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info)2359 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar,
2360 struct hal_rx_mon_ppdu_info *ppdu_info)
2361 {
2362 u32 num_users, i;
2363
2364 num_users = ppdu_info->num_users;
2365 if (num_users > HAL_MAX_UL_MU_USERS)
2366 num_users = HAL_MAX_UL_MU_USERS;
2367
2368 for (i = 0; i < num_users; i++)
2369 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i);
2370 }
2371
ath12k_dp_mon_rx_process_stats(struct ath12k * ar,int mac_id,struct napi_struct * napi,int * budget)2372 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id,
2373 struct napi_struct *napi, int *budget)
2374 {
2375 struct ath12k_base *ab = ar->ab;
2376 struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2377 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2378 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2379 struct ath12k_dp *dp = &ab->dp;
2380 struct hal_mon_dest_desc *mon_dst_desc;
2381 struct sk_buff *skb;
2382 struct ath12k_skb_rxcb *rxcb;
2383 struct dp_srng *mon_dst_ring;
2384 struct hal_srng *srng;
2385 struct dp_rxdma_mon_ring *buf_ring;
2386 struct ath12k_sta *ahsta = NULL;
2387 struct ath12k_link_sta *arsta;
2388 struct ath12k_peer *peer;
2389 u64 cookie;
2390 int num_buffs_reaped = 0, srng_id, buf_id;
2391 u8 dest_idx = 0, i;
2392 bool end_of_ppdu;
2393 u32 hal_status;
2394
2395 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2396 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2397 buf_ring = &dp->rxdma_mon_buf_ring;
2398
2399 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2400 spin_lock_bh(&srng->lock);
2401 ath12k_hal_srng_access_begin(ab, srng);
2402
2403 while (likely(*budget)) {
2404 *budget -= 1;
2405 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2406 if (unlikely(!mon_dst_desc))
2407 break;
2408 cookie = le32_to_cpu(mon_dst_desc->cookie);
2409 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2410
2411 spin_lock_bh(&buf_ring->idr_lock);
2412 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2413 spin_unlock_bh(&buf_ring->idr_lock);
2414
2415 if (unlikely(!skb)) {
2416 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2417 buf_id);
2418 goto move_next;
2419 }
2420
2421 rxcb = ATH12K_SKB_RXCB(skb);
2422 dma_unmap_single(ab->dev, rxcb->paddr,
2423 skb->len + skb_tailroom(skb),
2424 DMA_FROM_DEVICE);
2425 pmon->dest_skb_q[dest_idx] = skb;
2426 dest_idx++;
2427 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2428 HAL_MON_DEST_INFO0_END_OF_PPDU);
2429 if (!end_of_ppdu)
2430 continue;
2431
2432 for (i = 0; i < dest_idx; i++) {
2433 skb = pmon->dest_skb_q[i];
2434 hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
2435
2436 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
2437 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2438 dev_kfree_skb_any(skb);
2439 continue;
2440 }
2441
2442 rcu_read_lock();
2443 spin_lock_bh(&ab->base_lock);
2444 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2445 if (!peer || !peer->sta) {
2446 ath12k_dbg(ab, ATH12K_DBG_DATA,
2447 "failed to find the peer with peer_id %d\n",
2448 ppdu_info->peer_id);
2449 spin_unlock_bh(&ab->base_lock);
2450 rcu_read_unlock();
2451 dev_kfree_skb_any(skb);
2452 continue;
2453 }
2454
2455 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
2456 ahsta = ath12k_sta_to_ahsta(peer->sta);
2457 arsta = &ahsta->deflink;
2458 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta,
2459 ppdu_info);
2460 } else if ((ppdu_info->fc_valid) &&
2461 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
2462 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
2463 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info);
2464 }
2465
2466 spin_unlock_bh(&ab->base_lock);
2467 rcu_read_unlock();
2468 dev_kfree_skb_any(skb);
2469 memset(ppdu_info, 0, sizeof(*ppdu_info));
2470 ppdu_info->peer_id = HAL_INVALID_PEERID;
2471 }
2472
2473 dest_idx = 0;
2474 move_next:
2475 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2476 ath12k_hal_srng_src_get_next_entry(ab, srng);
2477 num_buffs_reaped++;
2478 }
2479
2480 ath12k_hal_srng_access_end(ab, srng);
2481 spin_unlock_bh(&srng->lock);
2482 return num_buffs_reaped;
2483 }
2484
ath12k_dp_mon_process_ring(struct ath12k_base * ab,int mac_id,struct napi_struct * napi,int budget,enum dp_monitor_mode monitor_mode)2485 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id,
2486 struct napi_struct *napi, int budget,
2487 enum dp_monitor_mode monitor_mode)
2488 {
2489 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id);
2490 int num_buffs_reaped = 0;
2491
2492 if (!ar->monitor_started)
2493 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget);
2494 else
2495 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget,
2496 monitor_mode, napi);
2497
2498 return num_buffs_reaped;
2499 }
2500