1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_DP_H
8 #define ATH12K_DP_H
9
10 #include "hal_rx.h"
11 #include "hw.h"
12
13 #define MAX_RXDMA_PER_PDEV 2
14
15 struct ath12k_base;
16 struct ath12k_peer;
17 struct ath12k_dp;
18 struct ath12k_vif;
19 struct ath12k_link_vif;
20 struct hal_tcl_status_ring;
21 struct ath12k_ext_irq_grp;
22
23 #define DP_MON_PURGE_TIMEOUT_MS 100
24 #define DP_MON_SERVICE_BUDGET 128
25
26 struct dp_srng {
27 u32 *vaddr_unaligned;
28 u32 *vaddr;
29 dma_addr_t paddr_unaligned;
30 dma_addr_t paddr;
31 int size;
32 u32 ring_id;
33 };
34
35 struct dp_rxdma_mon_ring {
36 struct dp_srng refill_buf_ring;
37 struct idr bufs_idr;
38 /* Protects bufs_idr */
39 spinlock_t idr_lock;
40 int bufs_max;
41 };
42
43 struct dp_rxdma_ring {
44 struct dp_srng refill_buf_ring;
45 int bufs_max;
46 };
47
48 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
49
50 struct dp_tx_ring {
51 u8 tcl_data_ring_id;
52 struct dp_srng tcl_data_ring;
53 struct dp_srng tcl_comp_ring;
54 struct hal_wbm_completion_ring_tx *tx_status;
55 int tx_status_head;
56 int tx_status_tail;
57 };
58
59 struct ath12k_pdev_mon_stats {
60 u32 status_ppdu_state;
61 u32 status_ppdu_start;
62 u32 status_ppdu_end;
63 u32 status_ppdu_compl;
64 u32 status_ppdu_start_mis;
65 u32 status_ppdu_end_mis;
66 u32 status_ppdu_done;
67 u32 dest_ppdu_done;
68 u32 dest_mpdu_done;
69 u32 dest_mpdu_drop;
70 u32 dup_mon_linkdesc_cnt;
71 u32 dup_mon_buf_cnt;
72 };
73
74 struct dp_link_desc_bank {
75 void *vaddr_unaligned;
76 void *vaddr;
77 dma_addr_t paddr_unaligned;
78 dma_addr_t paddr;
79 u32 size;
80 };
81
82 /* Size to enforce scatter idle list mode */
83 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
84 #define DP_LINK_DESC_BANKS_MAX 8
85
86 #define DP_LINK_DESC_START 0x4000
87 #define DP_LINK_DESC_SHIFT 3
88
89 #define DP_LINK_DESC_COOKIE_SET(id, page) \
90 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
91
92 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
93
94 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
95 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
96 #define DP_RX_DESC_COOKIE_MAX \
97 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
98 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
99
100 enum ath12k_dp_ppdu_state {
101 DP_PPDU_STATUS_START,
102 DP_PPDU_STATUS_DONE,
103 };
104
105 struct dp_mon_mpdu {
106 struct list_head list;
107 struct sk_buff *head;
108 struct sk_buff *tail;
109 };
110
111 #define DP_MON_MAX_STATUS_BUF 32
112
113 struct ath12k_mon_data {
114 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
115 struct hal_rx_mon_ppdu_info mon_ppdu_info;
116
117 u32 mon_ppdu_status;
118 u32 mon_last_buf_cookie;
119 u64 mon_last_linkdesc_paddr;
120 u16 chan_noise_floor;
121
122 struct ath12k_pdev_mon_stats rx_mon_stats;
123 /* lock for monitor data */
124 spinlock_t mon_lock;
125 struct sk_buff_head rx_status_q;
126 struct dp_mon_mpdu *mon_mpdu;
127 struct list_head dp_rx_mon_mpdu_list;
128 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF];
129 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;
130 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;
131 };
132
133 struct ath12k_pdev_dp {
134 u32 mac_id;
135 atomic_t num_tx_pending;
136 wait_queue_head_t tx_empty_waitq;
137 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
138 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
139
140 struct ieee80211_rx_status rx_status;
141 struct ath12k_mon_data mon_data;
142 };
143
144 #define DP_NUM_CLIENTS_MAX 64
145 #define DP_AVG_TIDS_PER_CLIENT 2
146 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
147 #define DP_AVG_MSDUS_PER_FLOW 128
148 #define DP_AVG_FLOWS_PER_TID 2
149 #define DP_AVG_MPDUS_PER_TID_MAX 128
150 #define DP_AVG_MSDUS_PER_MPDU 4
151
152 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
153
154 #define DP_BA_WIN_SZ_MAX 1024
155
156 #define DP_TCL_NUM_RING_MAX 4
157
158 #define DP_IDLE_SCATTER_BUFS_MAX 16
159
160 #define DP_WBM_RELEASE_RING_SIZE 64
161 #define DP_TCL_DATA_RING_SIZE 512
162 #define DP_TX_COMP_RING_SIZE 32768
163 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
164 #define DP_TCL_CMD_RING_SIZE 32
165 #define DP_TCL_STATUS_RING_SIZE 32
166 #define DP_REO_DST_RING_MAX 8
167 #define DP_REO_DST_RING_SIZE 2048
168 #define DP_REO_REINJECT_RING_SIZE 32
169 #define DP_RX_RELEASE_RING_SIZE 1024
170 #define DP_REO_EXCEPTION_RING_SIZE 128
171 #define DP_REO_CMD_RING_SIZE 128
172 #define DP_REO_STATUS_RING_SIZE 2048
173 #define DP_RXDMA_BUF_RING_SIZE 4096
174 #define DP_RX_MAC_BUF_RING_SIZE 2048
175 #define DP_RXDMA_REFILL_RING_SIZE 2048
176 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
177 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
178 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
179 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
180 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
181 #define DP_TX_MONITOR_BUF_RING_SIZE 4096
182 #define DP_TX_MONITOR_DEST_RING_SIZE 2048
183
184 #define DP_TX_MONITOR_BUF_SIZE 2048
185 #define DP_TX_MONITOR_BUF_SIZE_MIN 48
186 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192
187
188 #define DP_RX_BUFFER_SIZE 2048
189 #define DP_RX_BUFFER_SIZE_LITE 1024
190 #define DP_RX_BUFFER_ALIGN_SIZE 128
191
192 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
193 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)
194
195 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
196 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
197
198 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
199 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
200 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
201
202 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
203 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10
204
205 #define ATH12K_NUM_POOL_TX_DESC 32768
206
207 /* TODO: revisit this count during testing */
208 #define ATH12K_RX_DESC_COUNT (12288)
209
210 #define ATH12K_PAGE_SIZE PAGE_SIZE
211
212 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
213 * SPT pages which makes lower 12bits 0
214 */
215 #define ATH12K_MAX_PPT_ENTRIES 1024
216
217 /* Total 512 entries in a SPT, i.e 4K Page/8 */
218 #define ATH12K_MAX_SPT_ENTRIES 512
219
220 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)
221
222 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \
223 ATH12K_MAX_SPT_ENTRIES)
224 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)
225 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)
226
227 #define ATH12K_TX_SPT_PAGE_OFFSET 0
228 #define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES
229
230 /* The SPT pages are divided for RX and TX, first block for RX
231 * and remaining for TX
232 */
233 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES
234
235 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA
236
237 /* 4K aligned address have last 12 bits set to 0, this check is done
238 * so that two spt pages address can be stored per 8bytes
239 * of CMEM (PPT)
240 */
241 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
242 #define ATH12K_SPT_4K_ALIGN_OFFSET 12
243 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
244
245 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
246 #define ATH12K_CMEM_ADDR_MSB 0x10
247
248 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
249 #define ATH12K_CC_SPT_MSB 8
250 #define ATH12K_CC_PPT_MSB 19
251 #define ATH12K_CC_PPT_SHIFT 9
252 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
253 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
254
255 #define DP_REO_QREF_NUM GENMASK(31, 16)
256 #define DP_MAX_PEER_ID 2047
257
258 /* Total size of the LUT is based on 2K peers, each having reference
259 * for 17tids, note each entry is of type ath12k_reo_queue_ref
260 * hence total size is 2048 * 17 * 8 = 278528
261 */
262 #define DP_REOQ_LUT_SIZE 278528
263
264 /* Invalid TX Bank ID value */
265 #define DP_INVALID_BANK_ID -1
266
267 struct ath12k_dp_tx_bank_profile {
268 u8 is_configured;
269 u32 num_users;
270 u32 bank_config;
271 };
272
273 struct ath12k_hp_update_timer {
274 struct timer_list timer;
275 bool started;
276 bool init;
277 u32 tx_num;
278 u32 timer_tx_num;
279 u32 ring_id;
280 u32 interval;
281 struct ath12k_base *ab;
282 };
283
284 struct ath12k_rx_desc_info {
285 struct list_head list;
286 struct sk_buff *skb;
287 u32 cookie;
288 u32 magic;
289 u8 in_use : 1,
290 device_id : 3,
291 reserved : 4;
292 };
293
294 struct ath12k_tx_desc_info {
295 struct list_head list;
296 struct sk_buff *skb;
297 u32 desc_id; /* Cookie */
298 u8 mac_id;
299 u8 pool_id;
300 };
301
302 struct ath12k_spt_info {
303 dma_addr_t paddr;
304 u64 *vaddr;
305 };
306
307 struct ath12k_reo_queue_ref {
308 u32 info0;
309 u32 info1;
310 } __packed;
311
312 struct ath12k_reo_q_addr_lut {
313 dma_addr_t paddr;
314 u32 *vaddr;
315 };
316
317 struct ath12k_dp {
318 struct ath12k_base *ab;
319 u8 num_bank_profiles;
320 /* protects the access and update of bank_profiles */
321 spinlock_t tx_bank_lock;
322 struct ath12k_dp_tx_bank_profile *bank_profiles;
323 enum ath12k_htc_ep_id eid;
324 struct completion htt_tgt_version_received;
325 u8 htt_tgt_ver_major;
326 u8 htt_tgt_ver_minor;
327 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
328 enum hal_rx_buf_return_buf_manager idle_link_rbm;
329 struct dp_srng wbm_idle_ring;
330 struct dp_srng wbm_desc_rel_ring;
331 struct dp_srng reo_reinject_ring;
332 struct dp_srng rx_rel_ring;
333 struct dp_srng reo_except_ring;
334 struct dp_srng reo_cmd_ring;
335 struct dp_srng reo_status_ring;
336 enum ath12k_peer_metadata_version peer_metadata_ver;
337 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
338 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
339 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
340 struct list_head reo_cmd_list;
341 struct list_head reo_cmd_cache_flush_list;
342 u32 reo_cmd_cache_flush_count;
343
344 /* protects access to below fields,
345 * - reo_cmd_list
346 * - reo_cmd_cache_flush_list
347 * - reo_cmd_cache_flush_count
348 */
349 spinlock_t reo_cmd_lock;
350 struct ath12k_hp_update_timer reo_cmd_timer;
351 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
352 struct ath12k_spt_info *spt_info;
353 u32 num_spt_pages;
354 u32 rx_ppt_base;
355 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];
356 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];
357 struct list_head rx_desc_free_list;
358 /* protects the free desc list */
359 spinlock_t rx_desc_lock;
360
361 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
362 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
363 /* protects the free and used desc lists */
364 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
365
366 struct dp_rxdma_ring rx_refill_buf_ring;
367 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
368 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
369 struct dp_rxdma_mon_ring rxdma_mon_buf_ring;
370 struct dp_rxdma_mon_ring tx_mon_buf_ring;
371 struct ath12k_reo_q_addr_lut reoq_lut;
372 struct ath12k_reo_q_addr_lut ml_reoq_lut;
373 };
374
375 /* HTT definitions */
376
377 #define HTT_TCL_META_DATA_TYPE BIT(0)
378 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
379
380 /* vdev meta data */
381 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
382 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
383 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
384
385 /* peer meta data */
386 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
387
388 /* HTT tx completion is overlaid in wbm_release_ring */
389 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)
390 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)
391 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)
392
393 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)
394
395 struct htt_tx_wbm_completion {
396 __le32 rsvd0[2];
397 __le32 info0;
398 __le32 info1;
399 __le32 info2;
400 __le32 info3;
401 __le32 info4;
402 __le32 rsvd1;
403
404 } __packed;
405
406 enum htt_h2t_msg_type {
407 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
408 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
409 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
410 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
411 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
412 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a,
413 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
414 };
415
416 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
417
418 struct htt_ver_req_cmd {
419 __le32 ver_reg_info;
420 } __packed;
421
422 enum htt_srng_ring_type {
423 HTT_HW_TO_SW_RING,
424 HTT_SW_TO_HW_RING,
425 HTT_SW_TO_SW_RING,
426 };
427
428 enum htt_srng_ring_id {
429 HTT_RXDMA_HOST_BUF_RING,
430 HTT_RXDMA_MONITOR_STATUS_RING,
431 HTT_RXDMA_MONITOR_BUF_RING,
432 HTT_RXDMA_MONITOR_DESC_RING,
433 HTT_RXDMA_MONITOR_DEST_RING,
434 HTT_HOST1_TO_FW_RXBUF_RING,
435 HTT_HOST2_TO_FW_RXBUF_RING,
436 HTT_RXDMA_NON_MONITOR_DEST_RING,
437 HTT_TX_MON_HOST2MON_BUF_RING,
438 HTT_TX_MON_MON2HOST_DEST_RING,
439 };
440
441 /* host -> target HTT_SRING_SETUP message
442 *
443 * After target is booted up, Host can send SRING setup message for
444 * each host facing LMAC SRING. Target setups up HW registers based
445 * on setup message and confirms back to Host if response_required is set.
446 * Host should wait for confirmation message before sending new SRING
447 * setup message
448 *
449 * The message would appear as follows:
450 *
451 * |31 24|23 20|19|18 16|15|14 8|7 0|
452 * |--------------- +-----------------+----------------+------------------|
453 * | ring_type | ring_id | pdev_id | msg_type |
454 * |----------------------------------------------------------------------|
455 * | ring_base_addr_lo |
456 * |----------------------------------------------------------------------|
457 * | ring_base_addr_hi |
458 * |----------------------------------------------------------------------|
459 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
460 * |----------------------------------------------------------------------|
461 * | ring_head_offset32_remote_addr_lo |
462 * |----------------------------------------------------------------------|
463 * | ring_head_offset32_remote_addr_hi |
464 * |----------------------------------------------------------------------|
465 * | ring_tail_offset32_remote_addr_lo |
466 * |----------------------------------------------------------------------|
467 * | ring_tail_offset32_remote_addr_hi |
468 * |----------------------------------------------------------------------|
469 * | ring_msi_addr_lo |
470 * |----------------------------------------------------------------------|
471 * | ring_msi_addr_hi |
472 * |----------------------------------------------------------------------|
473 * | ring_msi_data |
474 * |----------------------------------------------------------------------|
475 * | intr_timer_th |IM| intr_batch_counter_th |
476 * |----------------------------------------------------------------------|
477 * | reserved |RR|PTCF| intr_low_threshold |
478 * |----------------------------------------------------------------------|
479 * Where
480 * IM = sw_intr_mode
481 * RR = response_required
482 * PTCF = prefetch_timer_cfg
483 *
484 * The message is interpreted as follows:
485 * dword0 - b'0:7 - msg_type: This will be set to
486 * HTT_H2T_MSG_TYPE_SRING_SETUP
487 * b'8:15 - pdev_id:
488 * 0 (for rings at SOC/UMAC level),
489 * 1/2/3 mac id (for rings at LMAC level)
490 * b'16:23 - ring_id: identify which ring is to setup,
491 * more details can be got from enum htt_srng_ring_id
492 * b'24:31 - ring_type: identify type of host rings,
493 * more details can be got from enum htt_srng_ring_type
494 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
495 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
496 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
497 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
498 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
499 * SW_TO_HW_RING.
500 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
501 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
502 * Lower 32 bits of memory address of the remote variable
503 * storing the 4-byte word offset that identifies the head
504 * element within the ring.
505 * (The head offset variable has type u32.)
506 * Valid for HW_TO_SW and SW_TO_SW rings.
507 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
508 * Upper 32 bits of memory address of the remote variable
509 * storing the 4-byte word offset that identifies the head
510 * element within the ring.
511 * (The head offset variable has type u32.)
512 * Valid for HW_TO_SW and SW_TO_SW rings.
513 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
514 * Lower 32 bits of memory address of the remote variable
515 * storing the 4-byte word offset that identifies the tail
516 * element within the ring.
517 * (The tail offset variable has type u32.)
518 * Valid for HW_TO_SW and SW_TO_SW rings.
519 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
520 * Upper 32 bits of memory address of the remote variable
521 * storing the 4-byte word offset that identifies the tail
522 * element within the ring.
523 * (The tail offset variable has type u32.)
524 * Valid for HW_TO_SW and SW_TO_SW rings.
525 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
526 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
527 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
528 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
529 * dword10 - b'0:31 - ring_msi_data: MSI data
530 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
531 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
532 * dword11 - b'0:14 - intr_batch_counter_th:
533 * batch counter threshold is in units of 4-byte words.
534 * HW internally maintains and increments batch count.
535 * (see SRING spec for detail description).
536 * When batch count reaches threshold value, an interrupt
537 * is generated by HW.
538 * b'15 - sw_intr_mode:
539 * This configuration shall be static.
540 * Only programmed at power up.
541 * 0: generate pulse style sw interrupts
542 * 1: generate level style sw interrupts
543 * b'16:31 - intr_timer_th:
544 * The timer init value when timer is idle or is
545 * initialized to start downcounting.
546 * In 8us units (to cover a range of 0 to 524 ms)
547 * dword12 - b'0:15 - intr_low_threshold:
548 * Used only by Consumer ring to generate ring_sw_int_p.
549 * Ring entries low threshold water mark, that is used
550 * in combination with the interrupt timer as well as
551 * the clearing of the level interrupt.
552 * b'16:18 - prefetch_timer_cfg:
553 * Used only by Consumer ring to set timer mode to
554 * support Application prefetch handling.
555 * The external tail offset/pointer will be updated
556 * at following intervals:
557 * 3'b000: (Prefetch feature disabled; used only for debug)
558 * 3'b001: 1 usec
559 * 3'b010: 4 usec
560 * 3'b011: 8 usec (default)
561 * 3'b100: 16 usec
562 * Others: Reserved
563 * b'19 - response_required:
564 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
565 * b'20:31 - reserved: reserved for future use
566 */
567
568 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
569 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
570 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
571 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
572
573 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
574 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
575 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
576 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
577 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
578 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
579
580 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
581 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
582 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
583
584 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
585 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)
586 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
587
588 struct htt_srng_setup_cmd {
589 __le32 info0;
590 __le32 ring_base_addr_lo;
591 __le32 ring_base_addr_hi;
592 __le32 info1;
593 __le32 ring_head_off32_remote_addr_lo;
594 __le32 ring_head_off32_remote_addr_hi;
595 __le32 ring_tail_off32_remote_addr_lo;
596 __le32 ring_tail_off32_remote_addr_hi;
597 __le32 ring_msi_addr_lo;
598 __le32 ring_msi_addr_hi;
599 __le32 msi_data;
600 __le32 intr_info;
601 __le32 info2;
602 } __packed;
603
604 /* host -> target FW PPDU_STATS config message
605 *
606 * @details
607 * The following field definitions describe the format of the HTT host
608 * to target FW for PPDU_STATS_CFG msg.
609 * The message allows the host to configure the PPDU_STATS_IND messages
610 * produced by the target.
611 *
612 * |31 24|23 16|15 8|7 0|
613 * |-----------------------------------------------------------|
614 * | REQ bit mask | pdev_mask | msg type |
615 * |-----------------------------------------------------------|
616 * Header fields:
617 * - MSG_TYPE
618 * Bits 7:0
619 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
620 * Value: 0x11
621 * - PDEV_MASK
622 * Bits 8:15
623 * Purpose: identifies which pdevs this PPDU stats configuration applies to
624 * Value: This is a overloaded field, refer to usage and interpretation of
625 * PDEV in interface document.
626 * Bit 8 : Reserved for SOC stats
627 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
628 * Indicates MACID_MASK in DBS
629 * - REQ_TLV_BIT_MASK
630 * Bits 16:31
631 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
632 * needs to be included in the target's PPDU_STATS_IND messages.
633 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
634 *
635 */
636
637 struct htt_ppdu_stats_cfg_cmd {
638 __le32 msg;
639 } __packed;
640
641 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
642 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8)
643 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
644
645 enum htt_ppdu_stats_tag_type {
646 HTT_PPDU_STATS_TAG_COMMON,
647 HTT_PPDU_STATS_TAG_USR_COMMON,
648 HTT_PPDU_STATS_TAG_USR_RATE,
649 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
650 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
651 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
652 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
653 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
654 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
655 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
656 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
657 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
658 HTT_PPDU_STATS_TAG_INFO,
659 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
660
661 /* New TLV's are added above to this line */
662 HTT_PPDU_STATS_TAG_MAX,
663 };
664
665 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
666 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
667 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
668 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
669 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
670 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
671 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
672 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
673
674 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
675 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
676 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
677 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
678 BIT(HTT_PPDU_STATS_TAG_INFO) | \
679 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
680 HTT_PPDU_STATS_TAG_DEFAULT)
681
682 enum htt_stats_internal_ppdu_frametype {
683 HTT_STATS_PPDU_FTYPE_CTRL,
684 HTT_STATS_PPDU_FTYPE_DATA,
685 HTT_STATS_PPDU_FTYPE_BAR,
686 HTT_STATS_PPDU_FTYPE_MAX
687 };
688
689 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
690 *
691 * details:
692 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
693 * configure RXDMA rings.
694 * The configuration is per ring based and includes both packet subtypes
695 * and PPDU/MPDU TLVs.
696 *
697 * The message would appear as follows:
698 *
699 * |31 29|28|27|26|25|24|23 16|15 8|7 0|
700 * |-------+--+--+--+--+--+-----------+----------------+---------------|
701 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
702 * |-------------------------------------------------------------------|
703 * | rsvd2 | ring_buffer_size |
704 * |-------------------------------------------------------------------|
705 * | packet_type_enable_flags_0 |
706 * |-------------------------------------------------------------------|
707 * | packet_type_enable_flags_1 |
708 * |-------------------------------------------------------------------|
709 * | packet_type_enable_flags_2 |
710 * |-------------------------------------------------------------------|
711 * | packet_type_enable_flags_3 |
712 * |-------------------------------------------------------------------|
713 * | tlv_filter_in_flags |
714 * |-------------------------------------------------------------------|
715 * Where:
716 * PS = pkt_swap
717 * SS = status_swap
718 * The message is interpreted as follows:
719 * dword0 - b'0:7 - msg_type: This will be set to
720 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
721 * b'8:15 - pdev_id:
722 * 0 (for rings at SOC/UMAC level),
723 * 1/2/3 mac id (for rings at LMAC level)
724 * b'16:23 - ring_id : Identify the ring to configure.
725 * More details can be got from enum htt_srng_ring_id
726 * b'24 - status_swap: 1 is to swap status TLV
727 * b'25 - pkt_swap: 1 is to swap packet TLV
728 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets
729 * configuration fields are valid
730 * b'27 - drop_thresh_valid (DT): flag to indicate if the
731 * rx_drop_threshold field is valid
732 * b'28 - rx_mon_global_en: Enable/Disable global register
733 * configuration in Rx monitor module.
734 * b'29:31 - rsvd1: reserved for future use
735 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
736 * in byte units.
737 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
738 * - b'16:31 - rsvd2: Reserved for future use
739 * dword2 - b'0:31 - packet_type_enable_flags_0:
740 * Enable MGMT packet from 0b0000 to 0b1001
741 * bits from low to high: FP, MD, MO - 3 bits
742 * FP: Filter_Pass
743 * MD: Monitor_Direct
744 * MO: Monitor_Other
745 * 10 mgmt subtypes * 3 bits -> 30 bits
746 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
747 * dword3 - b'0:31 - packet_type_enable_flags_1:
748 * Enable MGMT packet from 0b1010 to 0b1111
749 * bits from low to high: FP, MD, MO - 3 bits
750 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
751 * dword4 - b'0:31 - packet_type_enable_flags_2:
752 * Enable CTRL packet from 0b0000 to 0b1001
753 * bits from low to high: FP, MD, MO - 3 bits
754 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
755 * dword5 - b'0:31 - packet_type_enable_flags_3:
756 * Enable CTRL packet from 0b1010 to 0b1111,
757 * MCAST_DATA, UCAST_DATA, NULL_DATA
758 * bits from low to high: FP, MD, MO - 3 bits
759 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
760 * dword6 - b'0:31 - tlv_filter_in_flags:
761 * Filter in Attention/MPDU/PPDU/Header/User tlvs
762 * Refer to CFG_TLV_FILTER_IN_FLAG defs
763 */
764
765 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
766 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
767 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
768 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
769 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
770 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
771 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26)
772
773 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)
774 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)
775 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)
776 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)
777 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)
778 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)
779 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)
780
781 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23)
782 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)
783 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)
784 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)
785
786 enum htt_rx_filter_tlv_flags {
787 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
788 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
789 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
790 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
791 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
792 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
793 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
794 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
795 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
796 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
797 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
798 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
799 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
800 };
801
802 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
803 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
804 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
805 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
806 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
807 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
808 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
809 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
810 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
811 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
812 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
813 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
814 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
815 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
816 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
817 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
818 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
819 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
820 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
821 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
822 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
823 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
824 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
825 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
826 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
827 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
828 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
829 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
830 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
831 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
832 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
833 };
834
835 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
836 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
837 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
838 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
839 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
840 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
841 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
842 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
843 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
844 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
845 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
846 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
847 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
848 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
849 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
850 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
851 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
852 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
853 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
854 };
855
856 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
857 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
858 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
859 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
860 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
861 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
862 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
863 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
864 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
865 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
866 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
867 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
868 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
869 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
870 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
871 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
872 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
873 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
874 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
875 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
876 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
877 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
878 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
879 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
880 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
881 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
882 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
883 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
884 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
885 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
886 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
887 };
888
889 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
891 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
892 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
894 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
895 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
896 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
897 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
899 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
900 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
902 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
903 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
904 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
905 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
906 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
907 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
908 };
909
910 enum htt_rx_data_pkt_filter_tlv_flasg3 {
911 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
912 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
913 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
914 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
915 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
916 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
917 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
918 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
919 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
920 };
921
922 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
923 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
924 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
925 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
926 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
927 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
928 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
929 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
930 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
931 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
932
933 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
934 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
935 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
936 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
937 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
938 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
939 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
940 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
941 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
942 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
943
944 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
945 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
946 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
947 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
948 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
949 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
950 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
951 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
952 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
953 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
954
955 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
956 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
957 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
958 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
959 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
960
961 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
962 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
963 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
964 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
965 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
966
967 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
968 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
969 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
970 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
971 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
972
973 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
974 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
975 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
976
977 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
978 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
979 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
980
981 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
982 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
983 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
984
985 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
986 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
987 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
988 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
989 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
990 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
991
992 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
993 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
994 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
995 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
996 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
997 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
998
999 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
1000 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
1001 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
1002 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
1003 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
1004 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
1005
1006 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1007 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1008 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1009
1010 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1011 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1012 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1013
1014 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1015 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1016 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1017
1018 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
1019 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
1020 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1021
1022 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
1023 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
1024 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1025
1026 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
1027 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
1028 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1029
1030 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
1031 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
1032 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1033
1034 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
1035 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
1036 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1037 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1038 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1039 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1040 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1041 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1042 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1043
1044 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
1045 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
1046 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1047 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1048 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1049 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1050 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1051 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1052 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1053
1054 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
1055
1056 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
1057
1058 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
1059
1060 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
1061
1062 #define HTT_RX_MON_FILTER_TLV_FLAGS \
1063 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1064 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1065 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1066 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1067 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1068 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1069
1070 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
1071 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1072 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1073 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1074 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1075 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1076 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1077
1078 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
1079 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1080 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1081 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1082 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1083 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1084 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1085 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1086 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
1087
1088 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
1089 #define HTT_RX_TLV_FLAGS_RXDMA_RING \
1090 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1091 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1092 HTT_RX_FILTER_TLV_FLAGS_MSDU_END)
1093
1094 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1095 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1096
1097 struct htt_rx_ring_selection_cfg_cmd {
1098 __le32 info0;
1099 __le32 info1;
1100 __le32 pkt_type_en_flags0;
1101 __le32 pkt_type_en_flags1;
1102 __le32 pkt_type_en_flags2;
1103 __le32 pkt_type_en_flags3;
1104 __le32 rx_filter_tlv;
1105 __le32 rx_packet_offset;
1106 __le32 rx_mpdu_offset;
1107 __le32 rx_msdu_offset;
1108 __le32 rx_attn_offset;
1109 __le32 info2;
1110 __le32 reserved[2];
1111 __le32 rx_mpdu_start_end_mask;
1112 __le32 rx_msdu_end_word_mask;
1113 __le32 info3;
1114 } __packed;
1115
1116 struct htt_rx_ring_tlv_filter {
1117 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
1118 u32 pkt_filter_flags0; /* MGMT */
1119 u32 pkt_filter_flags1; /* MGMT */
1120 u32 pkt_filter_flags2; /* CTRL */
1121 u32 pkt_filter_flags3; /* DATA */
1122 bool offset_valid;
1123 u16 rx_packet_offset;
1124 u16 rx_header_offset;
1125 u16 rx_mpdu_end_offset;
1126 u16 rx_mpdu_start_offset;
1127 u16 rx_msdu_end_offset;
1128 u16 rx_msdu_start_offset;
1129 u16 rx_attn_offset;
1130 u16 rx_mpdu_start_wmask;
1131 u16 rx_mpdu_end_wmask;
1132 u32 rx_msdu_end_wmask;
1133 };
1134
1135 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0
1136 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1
1137 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2
1138 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3
1139
1140 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1141 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1142 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
1143 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
1144 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
1145
1146 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)
1147 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)
1148 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)
1149 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)
1150 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)
1151
1152 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)
1153
1154 struct htt_tx_ring_selection_cfg_cmd {
1155 __le32 info0;
1156 __le32 info1;
1157 __le32 info2;
1158 __le32 tlv_filter_mask_in0;
1159 __le32 tlv_filter_mask_in1;
1160 __le32 tlv_filter_mask_in2;
1161 __le32 tlv_filter_mask_in3;
1162 __le32 reserved[3];
1163 } __packed;
1164
1165 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)
1166 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)
1167 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)
1168
1169 #define HTT_TX_MON_FILTER_HYBRID_MODE \
1170 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \
1171 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \
1172 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \
1173 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \
1174 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \
1175 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \
1176 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \
1177 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \
1178 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \
1179 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \
1180 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \
1181 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \
1182 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)
1183
1184 struct htt_tx_ring_tlv_filter {
1185 u32 tx_mon_downstream_tlv_flags;
1186 u32 tx_mon_upstream_tlv_flags0;
1187 u32 tx_mon_upstream_tlv_flags1;
1188 u32 tx_mon_upstream_tlv_flags2;
1189 bool tx_mon_mgmt_filter;
1190 bool tx_mon_data_filter;
1191 bool tx_mon_ctrl_filter;
1192 u16 tx_mon_pkt_dma_len;
1193 } __packed;
1194
1195 enum htt_tx_mon_upstream_tlv_flags0 {
1196 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),
1197 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),
1198 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),
1199 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),
1200 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),
1201 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),
1202 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),
1203 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),
1204 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),
1205 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),
1206 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),
1207 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),
1208 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),
1209 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),
1210 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),
1211 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),
1212 };
1213
1214 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)
1215
1216 /* HTT message target->host */
1217
1218 enum htt_t2h_msg_type {
1219 HTT_T2H_MSG_TYPE_VERSION_CONF,
1220 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1221 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1222 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1223 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1224 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1225 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1226 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1227 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1228 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1229 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1230 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
1231 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b,
1232 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,
1233 };
1234
1235 #define HTT_TARGET_VERSION_MAJOR 3
1236
1237 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1238 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1239 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1240
1241 struct htt_t2h_version_conf_msg {
1242 __le32 version;
1243 } __packed;
1244
1245 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1246 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1247 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1248 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1249 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1250 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1251 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1252
1253 struct htt_t2h_peer_map_event {
1254 __le32 info;
1255 __le32 mac_addr_l32;
1256 __le32 info1;
1257 __le32 info2;
1258 } __packed;
1259
1260 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1261 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1262 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1263 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1264 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1265 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1266
1267 struct htt_t2h_peer_unmap_event {
1268 __le32 info;
1269 __le32 mac_addr_l32;
1270 __le32 info1;
1271 } __packed;
1272
1273 struct htt_resp_msg {
1274 union {
1275 struct htt_t2h_version_conf_msg version_msg;
1276 struct htt_t2h_peer_map_event peer_map_ev;
1277 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1278 };
1279 } __packed;
1280
1281 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\
1282 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))
1283 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)
1284 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)
1285 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)
1286 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)
1287 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0
1288 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1
1289
1290 struct htt_t2h_vdev_txrx_stats_ind {
1291 __le32 vdev_id;
1292 __le32 rx_msdu_byte_cnt_lo;
1293 __le32 rx_msdu_byte_cnt_hi;
1294 __le32 rx_msdu_cnt_lo;
1295 __le32 rx_msdu_cnt_hi;
1296 __le32 tx_msdu_byte_cnt_lo;
1297 __le32 tx_msdu_byte_cnt_hi;
1298 __le32 tx_msdu_cnt_lo;
1299 __le32 tx_msdu_cnt_hi;
1300 __le32 tx_retry_cnt_lo;
1301 __le32 tx_retry_cnt_hi;
1302 __le32 tx_retry_byte_cnt_lo;
1303 __le32 tx_retry_byte_cnt_hi;
1304 __le32 tx_drop_cnt_lo;
1305 __le32 tx_drop_cnt_hi;
1306 __le32 tx_drop_byte_cnt_lo;
1307 __le32 tx_drop_byte_cnt_hi;
1308 __le32 msdu_ttl_cnt_lo;
1309 __le32 msdu_ttl_cnt_hi;
1310 __le32 msdu_ttl_byte_cnt_lo;
1311 __le32 msdu_ttl_byte_cnt_hi;
1312 } __packed;
1313
1314 struct htt_t2h_vdev_common_stats_tlv {
1315 __le32 soc_drop_count_lo;
1316 __le32 soc_drop_count_hi;
1317 } __packed;
1318
1319 /* ppdu stats
1320 *
1321 * @details
1322 * The following field definitions describe the format of the HTT target
1323 * to host ppdu stats indication message.
1324 *
1325 *
1326 * |31 16|15 12|11 10|9 8|7 0 |
1327 * |----------------------------------------------------------------------|
1328 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1329 * |----------------------------------------------------------------------|
1330 * | ppdu_id |
1331 * |----------------------------------------------------------------------|
1332 * | Timestamp in us |
1333 * |----------------------------------------------------------------------|
1334 * | reserved |
1335 * |----------------------------------------------------------------------|
1336 * | type-specific stats info |
1337 * | (see htt_ppdu_stats.h) |
1338 * |----------------------------------------------------------------------|
1339 * Header fields:
1340 * - MSG_TYPE
1341 * Bits 7:0
1342 * Purpose: Identifies this is a PPDU STATS indication
1343 * message.
1344 * Value: 0x1d
1345 * - mac_id
1346 * Bits 9:8
1347 * Purpose: mac_id of this ppdu_id
1348 * Value: 0-3
1349 * - pdev_id
1350 * Bits 11:10
1351 * Purpose: pdev_id of this ppdu_id
1352 * Value: 0-3
1353 * 0 (for rings at SOC level),
1354 * 1/2/3 PDEV -> 0/1/2
1355 * - payload_size
1356 * Bits 31:16
1357 * Purpose: total tlv size
1358 * Value: payload_size in bytes
1359 */
1360
1361 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1362 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1363
1364 struct ath12k_htt_ppdu_stats_msg {
1365 __le32 info;
1366 __le32 ppdu_id;
1367 __le32 timestamp;
1368 __le32 rsvd;
1369 u8 data[];
1370 } __packed;
1371
1372 struct htt_tlv {
1373 __le32 header;
1374 u8 value[];
1375 } __packed;
1376
1377 #define HTT_TLV_TAG GENMASK(11, 0)
1378 #define HTT_TLV_LEN GENMASK(23, 12)
1379
1380 enum HTT_PPDU_STATS_BW {
1381 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1382 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1383 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1384 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1385 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1386 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1387 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1388 };
1389
1390 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1391 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1392 /* bw - HTT_PPDU_STATS_BW */
1393 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1394
1395 struct htt_ppdu_stats_common {
1396 __le32 ppdu_id;
1397 __le16 sched_cmdid;
1398 u8 ring_id;
1399 u8 num_users;
1400 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1401 __le32 chain_mask;
1402 __le32 fes_duration_us; /* frame exchange sequence */
1403 __le32 ppdu_sch_eval_start_tstmp_us;
1404 __le32 ppdu_sch_end_tstmp_us;
1405 __le32 ppdu_start_tstmp_us;
1406 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1407 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1408 */
1409 __le16 phy_mode;
1410 __le16 bw_mhz;
1411 } __packed;
1412
1413 enum htt_ppdu_stats_gi {
1414 HTT_PPDU_STATS_SGI_0_8_US,
1415 HTT_PPDU_STATS_SGI_0_4_US,
1416 HTT_PPDU_STATS_SGI_1_6_US,
1417 HTT_PPDU_STATS_SGI_3_2_US,
1418 };
1419
1420 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1421 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1422
1423 enum HTT_PPDU_STATS_PPDU_TYPE {
1424 HTT_PPDU_STATS_PPDU_TYPE_SU,
1425 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
1426 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,
1427 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,
1428 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,
1429 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,
1430 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,
1431 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,
1432 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,
1433 HTT_PPDU_STATS_PPDU_TYPE_MAX
1434 };
1435
1436 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1437 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1438
1439 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1440 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1441 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1442 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1443 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1444 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1445 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1446 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1447 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1448 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1449 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1450
1451 #define HTT_USR_RATE_PREAMBLE(_val) \
1452 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)
1453 #define HTT_USR_RATE_BW(_val) \
1454 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)
1455 #define HTT_USR_RATE_NSS(_val) \
1456 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)
1457 #define HTT_USR_RATE_MCS(_val) \
1458 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)
1459 #define HTT_USR_RATE_GI(_val) \
1460 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)
1461 #define HTT_USR_RATE_DCM(_val) \
1462 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)
1463
1464 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1465 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1466 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1467 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1468 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1469 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1470 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1471 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1472 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1473 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1474 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1475
1476 struct htt_ppdu_stats_user_rate {
1477 u8 tid_num;
1478 u8 reserved0;
1479 __le16 sw_peer_id;
1480 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1481 __le16 ru_end;
1482 __le16 ru_start;
1483 __le16 resp_ru_end;
1484 __le16 resp_ru_start;
1485 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1486 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1487 /* Note: resp_rate_info is only valid for if resp_type is UL */
1488 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1489 } __packed;
1490
1491 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1492 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1493 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1494 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1495 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1496 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1497
1498 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1499 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)
1500 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1501 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)
1502 #define HTT_TX_INFO_RATECODE(_flags) \
1503 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)
1504 #define HTT_TX_INFO_PEERID(_flags) \
1505 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)
1506
1507 enum htt_ppdu_stats_usr_compln_status {
1508 HTT_PPDU_STATS_USER_STATUS_OK,
1509 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1510 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1511 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1512 HTT_PPDU_STATS_USER_STATUS_ABORT,
1513 };
1514
1515 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1516 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1517 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1518 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1519
1520 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1521 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)
1522 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1523 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)
1524 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1525 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)
1526
1527 struct htt_ppdu_stats_usr_cmpltn_cmn {
1528 u8 status;
1529 u8 tid_num;
1530 __le16 sw_peer_id;
1531 /* RSSI value of last ack packet (units = dB above noise floor) */
1532 __le32 ack_rssi;
1533 __le16 mpdu_tried;
1534 __le16 mpdu_success;
1535 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1536 } __packed;
1537
1538 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1539 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1540 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1541
1542 #define HTT_PPDU_STATS_NON_QOS_TID 16
1543
1544 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1545 __le32 ppdu_id;
1546 __le16 sw_peer_id;
1547 __le16 reserved0;
1548 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1549 __le16 current_seq;
1550 __le16 start_seq;
1551 __le32 success_bytes;
1552 } __packed;
1553
1554 struct htt_ppdu_user_stats {
1555 u16 peer_id;
1556 u16 delay_ba;
1557 u32 tlv_flags;
1558 bool is_valid_peer_id;
1559 struct htt_ppdu_stats_user_rate rate;
1560 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1561 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1562 };
1563
1564 #define HTT_PPDU_STATS_MAX_USERS 8
1565 #define HTT_PPDU_DESC_MAX_DEPTH 16
1566
1567 struct htt_ppdu_stats {
1568 struct htt_ppdu_stats_common common;
1569 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1570 };
1571
1572 struct htt_ppdu_stats_info {
1573 u32 tlv_bitmap;
1574 u32 ppdu_id;
1575 u32 frame_type;
1576 u32 frame_ctrl;
1577 u32 delay_ba;
1578 u32 bar_num_users;
1579 struct htt_ppdu_stats ppdu_stats;
1580 struct list_head list;
1581 };
1582
1583 /* @brief target -> host MLO offset indiciation message
1584 *
1585 * @details
1586 * The following field definitions describe the format of the HTT target
1587 * to host mlo offset indication message.
1588 *
1589 *
1590 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0|
1591 * |---------------------------------------------------------------------|
1592 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype|
1593 * |---------------------------------------------------------------------|
1594 * | sync_timestamp_lo_us |
1595 * |---------------------------------------------------------------------|
1596 * | sync_timestamp_hi_us |
1597 * |---------------------------------------------------------------------|
1598 * | mlo_offset_lo |
1599 * |---------------------------------------------------------------------|
1600 * | mlo_offset_hi |
1601 * |---------------------------------------------------------------------|
1602 * | mlo_offset_clcks |
1603 * |---------------------------------------------------------------------|
1604 * | rsvd2 | mlo_comp_clks |mlo_comp_us |
1605 * |---------------------------------------------------------------------|
1606 * | rsvd3 |mlo_comp_timer |
1607 * |---------------------------------------------------------------------|
1608 * Header fields
1609 * - MSG_TYPE
1610 * Bits 7:0
1611 * Purpose: Identifies this is a MLO offset indication msg
1612 * - PDEV_ID
1613 * Bits 9:8
1614 * Purpose: Pdev of this MLO offset
1615 * - CHIP_ID
1616 * Bits 12:10
1617 * Purpose: chip_id of this MLO offset
1618 * - MAC_FREQ
1619 * Bits 28:13
1620 * - SYNC_TIMESTAMP_LO_US
1621 * Purpose: clock frequency of the mac HW block in MHz
1622 * Bits: 31:0
1623 * Purpose: lower 32 bits of the WLAN global time stamp at which
1624 * last sync interrupt was received
1625 * - SYNC_TIMESTAMP_HI_US
1626 * Bits: 31:0
1627 * Purpose: upper 32 bits of WLAN global time stamp at which
1628 * last sync interrupt was received
1629 * - MLO_OFFSET_LO
1630 * Bits: 31:0
1631 * Purpose: lower 32 bits of the MLO offset in us
1632 * - MLO_OFFSET_HI
1633 * Bits: 31:0
1634 * Purpose: upper 32 bits of the MLO offset in us
1635 * - MLO_COMP_US
1636 * Bits: 15:0
1637 * Purpose: MLO time stamp compensation applied in us
1638 * - MLO_COMP_CLCKS
1639 * Bits: 25:16
1640 * Purpose: MLO time stamp compensation applied in clock ticks
1641 * - MLO_COMP_TIMER
1642 * Bits: 21:0
1643 * Purpose: Periodic timer at which compensation is applied
1644 */
1645
1646 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)
1647 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)
1648
1649 struct ath12k_htt_mlo_offset_msg {
1650 __le32 info;
1651 __le32 sync_timestamp_lo_us;
1652 __le32 sync_timestamp_hi_us;
1653 __le32 mlo_offset_hi;
1654 __le32 mlo_offset_lo;
1655 __le32 mlo_offset_clks;
1656 __le32 mlo_comp_clks;
1657 __le32 mlo_comp_timer;
1658 } __packed;
1659
1660 /* @brief host -> target FW extended statistics retrieve
1661 *
1662 * @details
1663 * The following field definitions describe the format of the HTT host
1664 * to target FW extended stats retrieve message.
1665 * The message specifies the type of stats the host wants to retrieve.
1666 *
1667 * |31 24|23 16|15 8|7 0|
1668 * |-----------------------------------------------------------|
1669 * | reserved | stats type | pdev_mask | msg type |
1670 * |-----------------------------------------------------------|
1671 * | config param [0] |
1672 * |-----------------------------------------------------------|
1673 * | config param [1] |
1674 * |-----------------------------------------------------------|
1675 * | config param [2] |
1676 * |-----------------------------------------------------------|
1677 * | config param [3] |
1678 * |-----------------------------------------------------------|
1679 * | reserved |
1680 * |-----------------------------------------------------------|
1681 * | cookie LSBs |
1682 * |-----------------------------------------------------------|
1683 * | cookie MSBs |
1684 * |-----------------------------------------------------------|
1685 * Header fields:
1686 * - MSG_TYPE
1687 * Bits 7:0
1688 * Purpose: identifies this is a extended stats upload request message
1689 * Value: 0x10
1690 * - PDEV_MASK
1691 * Bits 8:15
1692 * Purpose: identifies the mask of PDEVs to retrieve stats from
1693 * Value: This is a overloaded field, refer to usage and interpretation of
1694 * PDEV in interface document.
1695 * Bit 8 : Reserved for SOC stats
1696 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1697 * Indicates MACID_MASK in DBS
1698 * - STATS_TYPE
1699 * Bits 23:16
1700 * Purpose: identifies which FW statistics to upload
1701 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1702 * - Reserved
1703 * Bits 31:24
1704 * - CONFIG_PARAM [0]
1705 * Bits 31:0
1706 * Purpose: give an opaque configuration value to the specified stats type
1707 * Value: stats-type specific configuration value
1708 * Refer to htt_stats.h for interpretation for each stats sub_type
1709 * - CONFIG_PARAM [1]
1710 * Bits 31:0
1711 * Purpose: give an opaque configuration value to the specified stats type
1712 * Value: stats-type specific configuration value
1713 * Refer to htt_stats.h for interpretation for each stats sub_type
1714 * - CONFIG_PARAM [2]
1715 * Bits 31:0
1716 * Purpose: give an opaque configuration value to the specified stats type
1717 * Value: stats-type specific configuration value
1718 * Refer to htt_stats.h for interpretation for each stats sub_type
1719 * - CONFIG_PARAM [3]
1720 * Bits 31:0
1721 * Purpose: give an opaque configuration value to the specified stats type
1722 * Value: stats-type specific configuration value
1723 * Refer to htt_stats.h for interpretation for each stats sub_type
1724 * - Reserved [31:0] for future use.
1725 * - COOKIE_LSBS
1726 * Bits 31:0
1727 * Purpose: Provide a mechanism to match a target->host stats confirmation
1728 * message with its preceding host->target stats request message.
1729 * Value: LSBs of the opaque cookie specified by the host-side requestor
1730 * - COOKIE_MSBS
1731 * Bits 31:0
1732 * Purpose: Provide a mechanism to match a target->host stats confirmation
1733 * message with its preceding host->target stats request message.
1734 * Value: MSBs of the opaque cookie specified by the host-side requestor
1735 */
1736
1737 struct htt_ext_stats_cfg_hdr {
1738 u8 msg_type;
1739 u8 pdev_mask;
1740 u8 stats_type;
1741 u8 reserved;
1742 } __packed;
1743
1744 struct htt_ext_stats_cfg_cmd {
1745 struct htt_ext_stats_cfg_hdr hdr;
1746 __le32 cfg_param0;
1747 __le32 cfg_param1;
1748 __le32 cfg_param2;
1749 __le32 cfg_param3;
1750 __le32 reserved;
1751 __le32 cookie_lsb;
1752 __le32 cookie_msb;
1753 } __packed;
1754
1755 /* htt stats config default params */
1756 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1757 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1758 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1759 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1760 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1761 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1762 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1763 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1764
1765 /* HTT_DBG_EXT_STATS_PEER_INFO
1766 * PARAMS:
1767 * @config_param0:
1768 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1769 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1770 * [Bit31 : Bit16] sw_peer_id
1771 * @config_param1:
1772 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1773 * 0 bit htt_peer_stats_cmn_tlv
1774 * 1 bit htt_peer_details_tlv
1775 * 2 bit htt_tx_peer_rate_stats_tlv
1776 * 3 bit htt_rx_peer_rate_stats_tlv
1777 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1778 * 5 bit htt_rx_tid_stats_tlv
1779 * 6 bit htt_msdu_flow_stats_tlv
1780 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1781 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1782 * [Bit31 : Bit16] reserved
1783 */
1784 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1785 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1786
1787 /* Used to set different configs to the specified stats type.*/
1788 struct htt_ext_stats_cfg_params {
1789 u32 cfg0;
1790 u32 cfg1;
1791 u32 cfg2;
1792 u32 cfg3;
1793 };
1794
1795 enum vdev_stats_offload_timer_duration {
1796 ATH12K_STATS_TIMER_DUR_500MS = 1,
1797 ATH12K_STATS_TIMER_DUR_1SEC = 2,
1798 ATH12K_STATS_TIMER_DUR_2SEC = 3,
1799 };
1800
1801 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
1802 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
1803 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
1804 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
1805 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
1806 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
1807
1808 struct htt_mac_addr {
1809 __le32 mac_addr_l32;
1810 __le32 mac_addr_h16;
1811 } __packed;
1812
ath12k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1813 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1814 {
1815 memcpy(addr, &addr_l32, 4);
1816 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1817 }
1818
1819 int ath12k_dp_service_srng(struct ath12k_base *ab,
1820 struct ath12k_ext_irq_grp *irq_grp,
1821 int budget);
1822 int ath12k_dp_htt_connect(struct ath12k_dp *dp);
1823 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif);
1824 void ath12k_dp_free(struct ath12k_base *ab);
1825 int ath12k_dp_alloc(struct ath12k_base *ab);
1826 void ath12k_dp_cc_config(struct ath12k_base *ab);
1827 void ath12k_dp_partner_cc_init(struct ath12k_base *ab);
1828 int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
1829 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar);
1830 void ath12k_dp_pdev_free(struct ath12k_base *ab);
1831 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
1832 int mac_id, enum hal_ring_type ring_type);
1833 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
1834 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
1835 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
1836 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
1837 enum hal_ring_type type, int ring_num,
1838 int mac_id, int num_entries);
1839 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
1840 struct dp_link_desc_bank *desc_bank,
1841 u32 ring_type, struct dp_srng *ring);
1842 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
1843 struct dp_link_desc_bank *link_desc_banks,
1844 u32 ring_type, struct hal_srng *srng,
1845 u32 n_link_desc);
1846 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1847 u32 cookie);
1848 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1849 u32 desc_id);
1850 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab);
1851 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab);
1852 #endif
1853