1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_DP_H
8 #define ATH11K_DP_H
9
10 #include "hal_rx.h"
11
12 #define MAX_RXDMA_PER_PDEV 2
13
14 struct ath11k_base;
15 struct ath11k_peer;
16 struct ath11k_dp;
17 struct ath11k_vif;
18 struct hal_tcl_status_ring;
19 struct ath11k_ext_irq_grp;
20
21 struct dp_rx_tid {
22 u8 tid;
23 u32 *vaddr;
24 dma_addr_t paddr;
25 u32 size;
26 u32 ba_win_sz;
27 bool active;
28
29 /* Info related to rx fragments */
30 u32 cur_sn;
31 u16 last_frag_no;
32 u16 rx_frag_bitmap;
33
34 struct sk_buff_head rx_frags;
35 struct hal_reo_dest_ring *dst_ring_desc;
36
37 /* Timer info related to fragments */
38 struct timer_list frag_timer;
39 struct ath11k_base *ab;
40 };
41
42 #define DP_REO_DESC_FREE_THRESHOLD 64
43 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
44 #define DP_MON_PURGE_TIMEOUT_MS 100
45 #define DP_MON_SERVICE_BUDGET 128
46
47 struct dp_reo_cache_flush_elem {
48 struct list_head list;
49 struct dp_rx_tid data;
50 unsigned long ts;
51 };
52
53 struct dp_reo_cmd {
54 struct list_head list;
55 struct dp_rx_tid data;
56 int cmd_num;
57 void (*handler)(struct ath11k_dp *, void *,
58 enum hal_reo_cmd_status status);
59 };
60
61 struct dp_srng {
62 u32 *vaddr_unaligned;
63 u32 *vaddr;
64 dma_addr_t paddr_unaligned;
65 dma_addr_t paddr;
66 int size;
67 u32 ring_id;
68 u8 cached;
69 };
70
71 struct dp_rxdma_ring {
72 struct dp_srng refill_buf_ring;
73 struct idr bufs_idr;
74 /* Protects bufs_idr */
75 spinlock_t idr_lock;
76 int bufs_max;
77 };
78
79 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
80
81 struct dp_tx_ring {
82 u8 tcl_data_ring_id;
83 struct dp_srng tcl_data_ring;
84 struct dp_srng tcl_comp_ring;
85 struct idr txbuf_idr;
86 /* Protects txbuf_idr and num_pending */
87 spinlock_t tx_idr_lock;
88 struct hal_wbm_release_ring *tx_status;
89 int tx_status_head;
90 int tx_status_tail;
91 };
92
93 enum dp_mon_status_buf_state {
94 /* PPDU id matches in dst ring and status ring */
95 DP_MON_STATUS_MATCH,
96 /* status ring dma is not done */
97 DP_MON_STATUS_NO_DMA,
98 /* status ring is lagging, reap status ring */
99 DP_MON_STATUS_LAG,
100 /* status ring is leading, reap dst ring and drop */
101 DP_MON_STATUS_LEAD,
102 /* replinish monitor status ring */
103 DP_MON_STATUS_REPLINISH,
104 };
105
106 struct ath11k_pdev_mon_stats {
107 u32 status_ppdu_state;
108 u32 status_ppdu_start;
109 u32 status_ppdu_end;
110 u32 status_ppdu_compl;
111 u32 status_ppdu_start_mis;
112 u32 status_ppdu_end_mis;
113 u32 status_ppdu_done;
114 u32 dest_ppdu_done;
115 u32 dest_mpdu_done;
116 u32 dest_mpdu_drop;
117 u32 dup_mon_linkdesc_cnt;
118 u32 dup_mon_buf_cnt;
119 u32 dest_mon_stuck;
120 u32 dest_mon_not_reaped;
121 };
122
123 struct dp_full_mon_mpdu {
124 struct list_head list;
125 struct sk_buff *head;
126 struct sk_buff *tail;
127 };
128
129 struct dp_link_desc_bank {
130 void *vaddr_unaligned;
131 void *vaddr;
132 dma_addr_t paddr_unaligned;
133 dma_addr_t paddr;
134 u32 size;
135 };
136
137 /* Size to enforce scatter idle list mode */
138 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
139 #define DP_LINK_DESC_BANKS_MAX 8
140
141 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
142 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
143 #define DP_RX_DESC_COOKIE_MAX \
144 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
145 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
146
147 enum ath11k_dp_ppdu_state {
148 DP_PPDU_STATUS_START,
149 DP_PPDU_STATUS_DONE,
150 };
151
152 struct ath11k_mon_data {
153 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
154 struct hal_rx_mon_ppdu_info mon_ppdu_info;
155
156 u32 mon_ppdu_status;
157 u32 mon_last_buf_cookie;
158 u64 mon_last_linkdesc_paddr;
159 u16 chan_noise_floor;
160 bool hold_mon_dst_ring;
161 enum dp_mon_status_buf_state buf_state;
162 dma_addr_t mon_status_paddr;
163 struct dp_full_mon_mpdu *mon_mpdu;
164 struct hal_sw_mon_ring_entries sw_mon_entries;
165 struct ath11k_pdev_mon_stats rx_mon_stats;
166 /* lock for monitor data */
167 spinlock_t mon_lock;
168 };
169
170 struct ath11k_pdev_dp {
171 u32 mac_id;
172 u32 mon_dest_ring_stuck_cnt;
173 atomic_t num_tx_pending;
174 wait_queue_head_t tx_empty_waitq;
175 struct dp_rxdma_ring rx_refill_buf_ring;
176 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
177 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
178 struct dp_srng rxdma_mon_dst_ring;
179 struct dp_srng rxdma_mon_desc_ring;
180
181 struct dp_rxdma_ring rxdma_mon_buf_ring;
182 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
183 struct ieee80211_rx_status rx_status;
184 struct ath11k_mon_data mon_data;
185 };
186
187 #define DP_NUM_CLIENTS_MAX 64
188 #define DP_AVG_TIDS_PER_CLIENT 2
189 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
190 #define DP_AVG_MSDUS_PER_FLOW 128
191 #define DP_AVG_FLOWS_PER_TID 2
192 #define DP_AVG_MPDUS_PER_TID_MAX 128
193 #define DP_AVG_MSDUS_PER_MPDU 4
194
195 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
196
197 #define DP_BA_WIN_SZ_MAX 256
198
199 #define DP_TCL_NUM_RING_MAX 3
200 #define DP_TCL_NUM_RING_MAX_QCA6390 1
201
202 #define DP_IDLE_SCATTER_BUFS_MAX 16
203
204 #define DP_WBM_RELEASE_RING_SIZE 64
205 #define DP_TCL_DATA_RING_SIZE 512
206 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048
207 #define DP_TX_COMP_RING_SIZE 32768
208 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
209 #define DP_TCL_CMD_RING_SIZE 32
210 #define DP_TCL_STATUS_RING_SIZE 32
211 #define DP_REO_DST_RING_MAX 4
212 #define DP_REO_DST_RING_SIZE 2048
213 #define DP_REO_REINJECT_RING_SIZE 32
214 #define DP_RX_RELEASE_RING_SIZE 1024
215 #define DP_REO_EXCEPTION_RING_SIZE 128
216 #define DP_REO_CMD_RING_SIZE 256
217 #define DP_REO_STATUS_RING_SIZE 2048
218 #define DP_RXDMA_BUF_RING_SIZE 4096
219 #define DP_RXDMA_REFILL_RING_SIZE 2048
220 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
221 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
222 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
223 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
224 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
225
226 #define DP_RX_RELEASE_RING_NUM 3
227
228 #define DP_RX_BUFFER_SIZE 2048
229 #define DP_RX_BUFFER_SIZE_LITE 1024
230 #define DP_RX_BUFFER_ALIGN_SIZE 128
231
232 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
233 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
234
235 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
236 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
237
238 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
239 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
240 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
241
242 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
243 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
244
245 struct ath11k_hp_update_timer {
246 struct timer_list timer;
247 bool started;
248 bool init;
249 u32 tx_num;
250 u32 timer_tx_num;
251 u32 ring_id;
252 u32 interval;
253 struct ath11k_base *ab;
254 };
255
256 struct ath11k_dp {
257 struct ath11k_base *ab;
258 enum ath11k_htc_ep_id eid;
259 struct completion htt_tgt_version_received;
260 u8 htt_tgt_ver_major;
261 u8 htt_tgt_ver_minor;
262 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
263 struct dp_srng wbm_idle_ring;
264 struct dp_srng wbm_desc_rel_ring;
265 struct dp_srng tcl_cmd_ring;
266 struct dp_srng tcl_status_ring;
267 struct dp_srng reo_reinject_ring;
268 struct dp_srng rx_rel_ring;
269 struct dp_srng reo_except_ring;
270 struct dp_srng reo_cmd_ring;
271 struct dp_srng reo_status_ring;
272 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
273 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
274 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
275 struct list_head reo_cmd_list;
276 struct list_head reo_cmd_cache_flush_list;
277 struct list_head dp_full_mon_mpdu_list;
278 u32 reo_cmd_cache_flush_count;
279 /**
280 * protects access to below fields,
281 * - reo_cmd_list
282 * - reo_cmd_cache_flush_list
283 * - reo_cmd_cache_flush_count
284 */
285 spinlock_t reo_cmd_lock;
286 struct ath11k_hp_update_timer reo_cmd_timer;
287 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
288 };
289
290 /* HTT definitions */
291
292 #define HTT_TCL_META_DATA_TYPE BIT(0)
293 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
294
295 /* vdev meta data */
296 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
297 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
298 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
299
300 /* peer meta data */
301 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
302
303 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
304
305 #define HTT_INVALID_PEER_ID 0xffff
306
307 /* HTT tx completion is overlaid in wbm_release_ring */
308 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
309 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
310 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
311
312 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
313 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0)
314 #define HTT_TX_WBM_COMP_INFO2_VALID BIT(21)
315
316 struct htt_tx_wbm_completion {
317 u32 info0;
318 u32 info1;
319 u32 info2;
320 u32 info3;
321 } __packed;
322
323 enum htt_h2t_msg_type {
324 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
325 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
326 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
327 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
328 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
329 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17,
330 };
331
332 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
333
334 struct htt_ver_req_cmd {
335 u32 ver_reg_info;
336 } __packed;
337
338 enum htt_srng_ring_type {
339 HTT_HW_TO_SW_RING,
340 HTT_SW_TO_HW_RING,
341 HTT_SW_TO_SW_RING,
342 };
343
344 enum htt_srng_ring_id {
345 HTT_RXDMA_HOST_BUF_RING,
346 HTT_RXDMA_MONITOR_STATUS_RING,
347 HTT_RXDMA_MONITOR_BUF_RING,
348 HTT_RXDMA_MONITOR_DESC_RING,
349 HTT_RXDMA_MONITOR_DEST_RING,
350 HTT_HOST1_TO_FW_RXBUF_RING,
351 HTT_HOST2_TO_FW_RXBUF_RING,
352 HTT_RXDMA_NON_MONITOR_DEST_RING,
353 };
354
355 /* host -> target HTT_SRING_SETUP message
356 *
357 * After target is booted up, Host can send SRING setup message for
358 * each host facing LMAC SRING. Target setups up HW registers based
359 * on setup message and confirms back to Host if response_required is set.
360 * Host should wait for confirmation message before sending new SRING
361 * setup message
362 *
363 * The message would appear as follows:
364 *
365 * |31 24|23 20|19|18 16|15|14 8|7 0|
366 * |--------------- +-----------------+----------------+------------------|
367 * | ring_type | ring_id | pdev_id | msg_type |
368 * |----------------------------------------------------------------------|
369 * | ring_base_addr_lo |
370 * |----------------------------------------------------------------------|
371 * | ring_base_addr_hi |
372 * |----------------------------------------------------------------------|
373 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
374 * |----------------------------------------------------------------------|
375 * | ring_head_offset32_remote_addr_lo |
376 * |----------------------------------------------------------------------|
377 * | ring_head_offset32_remote_addr_hi |
378 * |----------------------------------------------------------------------|
379 * | ring_tail_offset32_remote_addr_lo |
380 * |----------------------------------------------------------------------|
381 * | ring_tail_offset32_remote_addr_hi |
382 * |----------------------------------------------------------------------|
383 * | ring_msi_addr_lo |
384 * |----------------------------------------------------------------------|
385 * | ring_msi_addr_hi |
386 * |----------------------------------------------------------------------|
387 * | ring_msi_data |
388 * |----------------------------------------------------------------------|
389 * | intr_timer_th |IM| intr_batch_counter_th |
390 * |----------------------------------------------------------------------|
391 * | reserved |RR|PTCF| intr_low_threshold |
392 * |----------------------------------------------------------------------|
393 * Where
394 * IM = sw_intr_mode
395 * RR = response_required
396 * PTCF = prefetch_timer_cfg
397 *
398 * The message is interpreted as follows:
399 * dword0 - b'0:7 - msg_type: This will be set to
400 * HTT_H2T_MSG_TYPE_SRING_SETUP
401 * b'8:15 - pdev_id:
402 * 0 (for rings at SOC/UMAC level),
403 * 1/2/3 mac id (for rings at LMAC level)
404 * b'16:23 - ring_id: identify which ring is to setup,
405 * more details can be got from enum htt_srng_ring_id
406 * b'24:31 - ring_type: identify type of host rings,
407 * more details can be got from enum htt_srng_ring_type
408 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
409 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
410 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
411 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
412 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
413 * SW_TO_HW_RING.
414 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
415 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
416 * Lower 32 bits of memory address of the remote variable
417 * storing the 4-byte word offset that identifies the head
418 * element within the ring.
419 * (The head offset variable has type u32.)
420 * Valid for HW_TO_SW and SW_TO_SW rings.
421 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
422 * Upper 32 bits of memory address of the remote variable
423 * storing the 4-byte word offset that identifies the head
424 * element within the ring.
425 * (The head offset variable has type u32.)
426 * Valid for HW_TO_SW and SW_TO_SW rings.
427 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
428 * Lower 32 bits of memory address of the remote variable
429 * storing the 4-byte word offset that identifies the tail
430 * element within the ring.
431 * (The tail offset variable has type u32.)
432 * Valid for HW_TO_SW and SW_TO_SW rings.
433 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
434 * Upper 32 bits of memory address of the remote variable
435 * storing the 4-byte word offset that identifies the tail
436 * element within the ring.
437 * (The tail offset variable has type u32.)
438 * Valid for HW_TO_SW and SW_TO_SW rings.
439 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
440 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
441 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
442 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
443 * dword10 - b'0:31 - ring_msi_data: MSI data
444 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
445 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
446 * dword11 - b'0:14 - intr_batch_counter_th:
447 * batch counter threshold is in units of 4-byte words.
448 * HW internally maintains and increments batch count.
449 * (see SRING spec for detail description).
450 * When batch count reaches threshold value, an interrupt
451 * is generated by HW.
452 * b'15 - sw_intr_mode:
453 * This configuration shall be static.
454 * Only programmed at power up.
455 * 0: generate pulse style sw interrupts
456 * 1: generate level style sw interrupts
457 * b'16:31 - intr_timer_th:
458 * The timer init value when timer is idle or is
459 * initialized to start downcounting.
460 * In 8us units (to cover a range of 0 to 524 ms)
461 * dword12 - b'0:15 - intr_low_threshold:
462 * Used only by Consumer ring to generate ring_sw_int_p.
463 * Ring entries low threshold water mark, that is used
464 * in combination with the interrupt timer as well as
465 * the clearing of the level interrupt.
466 * b'16:18 - prefetch_timer_cfg:
467 * Used only by Consumer ring to set timer mode to
468 * support Application prefetch handling.
469 * The external tail offset/pointer will be updated
470 * at following intervals:
471 * 3'b000: (Prefetch feature disabled; used only for debug)
472 * 3'b001: 1 usec
473 * 3'b010: 4 usec
474 * 3'b011: 8 usec (default)
475 * 3'b100: 16 usec
476 * Others: Reserved
477 * b'19 - response_required:
478 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
479 * b'20:31 - reserved: reserved for future use
480 */
481
482 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
483 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
484 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
485 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
486
487 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
488 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
489 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
490 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
491 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
492 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
493
494 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
495 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
496 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
497
498 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
499 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
500 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
501
502 struct htt_srng_setup_cmd {
503 u32 info0;
504 u32 ring_base_addr_lo;
505 u32 ring_base_addr_hi;
506 u32 info1;
507 u32 ring_head_off32_remote_addr_lo;
508 u32 ring_head_off32_remote_addr_hi;
509 u32 ring_tail_off32_remote_addr_lo;
510 u32 ring_tail_off32_remote_addr_hi;
511 u32 ring_msi_addr_lo;
512 u32 ring_msi_addr_hi;
513 u32 msi_data;
514 u32 intr_info;
515 u32 info2;
516 } __packed;
517
518 /* host -> target FW PPDU_STATS config message
519 *
520 * @details
521 * The following field definitions describe the format of the HTT host
522 * to target FW for PPDU_STATS_CFG msg.
523 * The message allows the host to configure the PPDU_STATS_IND messages
524 * produced by the target.
525 *
526 * |31 24|23 16|15 8|7 0|
527 * |-----------------------------------------------------------|
528 * | REQ bit mask | pdev_mask | msg type |
529 * |-----------------------------------------------------------|
530 * Header fields:
531 * - MSG_TYPE
532 * Bits 7:0
533 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
534 * Value: 0x11
535 * - PDEV_MASK
536 * Bits 8:15
537 * Purpose: identifies which pdevs this PPDU stats configuration applies to
538 * Value: This is a overloaded field, refer to usage and interpretation of
539 * PDEV in interface document.
540 * Bit 8 : Reserved for SOC stats
541 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
542 * Indicates MACID_MASK in DBS
543 * - REQ_TLV_BIT_MASK
544 * Bits 16:31
545 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
546 * needs to be included in the target's PPDU_STATS_IND messages.
547 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
548 *
549 */
550
551 struct htt_ppdu_stats_cfg_cmd {
552 u32 msg;
553 } __packed;
554
555 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
556 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
557 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
558 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
559
560 enum htt_ppdu_stats_tag_type {
561 HTT_PPDU_STATS_TAG_COMMON,
562 HTT_PPDU_STATS_TAG_USR_COMMON,
563 HTT_PPDU_STATS_TAG_USR_RATE,
564 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
565 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
566 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
567 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
568 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
569 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
570 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
571 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
572 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
573 HTT_PPDU_STATS_TAG_INFO,
574 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
575
576 /* New TLV's are added above to this line */
577 HTT_PPDU_STATS_TAG_MAX,
578 };
579
580 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
581 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
582 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
583 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
584 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
585 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
586 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
587 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
588
589 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
590 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
591 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
592 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
593 BIT(HTT_PPDU_STATS_TAG_INFO) | \
594 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
595 HTT_PPDU_STATS_TAG_DEFAULT)
596
597 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
598 *
599 * details:
600 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
601 * configure RXDMA rings.
602 * The configuration is per ring based and includes both packet subtypes
603 * and PPDU/MPDU TLVs.
604 *
605 * The message would appear as follows:
606 *
607 * |31 26|25|24|23 16|15 8|7 0|
608 * |-----------------+----------------+----------------+---------------|
609 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
610 * |-------------------------------------------------------------------|
611 * | rsvd2 | ring_buffer_size |
612 * |-------------------------------------------------------------------|
613 * | packet_type_enable_flags_0 |
614 * |-------------------------------------------------------------------|
615 * | packet_type_enable_flags_1 |
616 * |-------------------------------------------------------------------|
617 * | packet_type_enable_flags_2 |
618 * |-------------------------------------------------------------------|
619 * | packet_type_enable_flags_3 |
620 * |-------------------------------------------------------------------|
621 * | tlv_filter_in_flags |
622 * |-------------------------------------------------------------------|
623 * Where:
624 * PS = pkt_swap
625 * SS = status_swap
626 * The message is interpreted as follows:
627 * dword0 - b'0:7 - msg_type: This will be set to
628 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
629 * b'8:15 - pdev_id:
630 * 0 (for rings at SOC/UMAC level),
631 * 1/2/3 mac id (for rings at LMAC level)
632 * b'16:23 - ring_id : Identify the ring to configure.
633 * More details can be got from enum htt_srng_ring_id
634 * b'24 - status_swap: 1 is to swap status TLV
635 * b'25 - pkt_swap: 1 is to swap packet TLV
636 * b'26:31 - rsvd1: reserved for future use
637 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
638 * in byte units.
639 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
640 * - b'16:31 - rsvd2: Reserved for future use
641 * dword2 - b'0:31 - packet_type_enable_flags_0:
642 * Enable MGMT packet from 0b0000 to 0b1001
643 * bits from low to high: FP, MD, MO - 3 bits
644 * FP: Filter_Pass
645 * MD: Monitor_Direct
646 * MO: Monitor_Other
647 * 10 mgmt subtypes * 3 bits -> 30 bits
648 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
649 * dword3 - b'0:31 - packet_type_enable_flags_1:
650 * Enable MGMT packet from 0b1010 to 0b1111
651 * bits from low to high: FP, MD, MO - 3 bits
652 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
653 * dword4 - b'0:31 - packet_type_enable_flags_2:
654 * Enable CTRL packet from 0b0000 to 0b1001
655 * bits from low to high: FP, MD, MO - 3 bits
656 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
657 * dword5 - b'0:31 - packet_type_enable_flags_3:
658 * Enable CTRL packet from 0b1010 to 0b1111,
659 * MCAST_DATA, UCAST_DATA, NULL_DATA
660 * bits from low to high: FP, MD, MO - 3 bits
661 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
662 * dword6 - b'0:31 - tlv_filter_in_flags:
663 * Filter in Attention/MPDU/PPDU/Header/User tlvs
664 * Refer to CFG_TLV_FILTER_IN_FLAG defs
665 */
666
667 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
668 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
669 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
670 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
671 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
672
673 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
674
675 enum htt_rx_filter_tlv_flags {
676 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
677 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
678 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
679 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
680 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
681 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
682 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
683 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
684 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
685 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
686 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
687 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
688 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
689 };
690
691 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
692 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
693 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
694 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
695 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
696 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
697 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
698 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
699 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
700 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
701 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
702 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
703 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
704 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
705 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
706 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
707 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
708 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
709 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
710 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
711 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
712 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
713 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
714 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
715 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
716 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
717 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
718 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
719 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
720 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
721 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
722 };
723
724 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
725 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
726 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
727 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
728 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
729 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
730 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
731 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
732 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
733 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
734 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
735 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
736 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
737 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
738 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
739 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
740 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
741 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
742 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
743 };
744
745 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
746 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
747 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
748 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
749 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
750 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
751 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
752 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
753 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
754 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
755 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
756 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
757 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
758 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
759 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
760 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
761 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
762 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
763 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
764 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
765 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
766 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
767 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
768 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
769 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
770 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
771 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
772 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
773 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
774 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
775 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
776 };
777
778 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
779 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
780 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
781 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
782 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
783 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
784 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
785 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
786 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
787 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
788 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
789 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
790 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
791 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
792 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
793 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
794 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
795 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
796 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
797 };
798
799 enum htt_rx_data_pkt_filter_tlv_flasg3 {
800 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
801 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
802 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
803 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
804 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
805 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
806 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
807 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
808 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
809 };
810
811 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
812 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
813 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
814 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
815 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
816 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
817 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
818 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
819 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
820 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
821
822 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
823 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
824 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
825 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
826 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
827 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
828 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
829 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
830 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
831 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
832
833 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
834 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
835 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
836 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
837 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
838 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
839 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
840 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
841 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
842 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
843
844 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
845 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
846 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
847 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
848 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
849
850 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
851 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
852 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
853 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
854 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
855
856 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
857 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
858 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
859 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
860 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
861
862 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
863 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
864 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
865
866 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
867 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
868 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
869
870 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
871 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
872 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
873
874 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
875 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
876 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
877 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
878 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
879 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
880
881 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
882 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
883 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
884 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
885 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
886 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
887
888 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
889 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
890 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
891 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
892 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
893 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
894
895 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
896 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
897 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
898
899 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
900 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
901 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
902
903 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
904 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
905 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
906
907 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
908 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
909 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
910
911 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
912 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
913 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
914
915 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
916 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
917 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
918
919 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
920 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
921 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
922
923 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
924 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
925 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
926 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
927 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
928 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
929 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
930 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
931 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
932
933 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
934 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
935 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
936 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
937 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
938 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
939 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
940 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
941 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
942
943 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
944
945 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
946
947 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
948
949 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
950
951 #define HTT_RX_MON_FILTER_TLV_FLAGS \
952 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
953 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
954 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
955 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
956 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
957 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
958
959 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
960 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
961 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
962 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
963 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
964 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
965 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
966
967 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
968 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
969 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
970 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
971 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
972 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
973 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
974 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
975 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
976
977 struct htt_rx_ring_selection_cfg_cmd {
978 u32 info0;
979 u32 info1;
980 u32 pkt_type_en_flags0;
981 u32 pkt_type_en_flags1;
982 u32 pkt_type_en_flags2;
983 u32 pkt_type_en_flags3;
984 u32 rx_filter_tlv;
985 } __packed;
986
987 struct htt_rx_ring_tlv_filter {
988 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
989 u32 pkt_filter_flags0; /* MGMT */
990 u32 pkt_filter_flags1; /* MGMT */
991 u32 pkt_filter_flags2; /* CTRL */
992 u32 pkt_filter_flags3; /* DATA */
993 };
994
995 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
996 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
997
998 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0)
999 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1)
1000 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2)
1001 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)
1002
1003 /* Enumeration for full monitor mode destination ring select
1004 * 0 - REO destination ring select
1005 * 1 - FW destination ring select
1006 * 2 - SW destination ring select
1007 * 3 - Release destination ring select
1008 */
1009 enum htt_rx_full_mon_release_ring {
1010 HTT_RX_MON_RING_REO,
1011 HTT_RX_MON_RING_FW,
1012 HTT_RX_MON_RING_SW,
1013 HTT_RX_MON_RING_RELEASE,
1014 };
1015
1016 struct htt_rx_full_monitor_mode_cfg_cmd {
1017 u32 info0;
1018 u32 cfg;
1019 } __packed;
1020
1021 /* HTT message target->host */
1022
1023 enum htt_t2h_msg_type {
1024 HTT_T2H_MSG_TYPE_VERSION_CONF,
1025 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1026 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1027 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1028 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1029 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1030 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1031 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1032 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1033 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1034 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1035 };
1036
1037 #define HTT_TARGET_VERSION_MAJOR 3
1038
1039 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1040 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1041 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1042
1043 struct htt_t2h_version_conf_msg {
1044 u32 version;
1045 } __packed;
1046
1047 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1048 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1049 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1050 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1051 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1052 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1053 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1054
1055 struct htt_t2h_peer_map_event {
1056 u32 info;
1057 u32 mac_addr_l32;
1058 u32 info1;
1059 u32 info2;
1060 } __packed;
1061
1062 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1063 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1064 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1065 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1066 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1067 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1068
1069 struct htt_t2h_peer_unmap_event {
1070 u32 info;
1071 u32 mac_addr_l32;
1072 u32 info1;
1073 } __packed;
1074
1075 struct htt_resp_msg {
1076 union {
1077 struct htt_t2h_version_conf_msg version_msg;
1078 struct htt_t2h_peer_map_event peer_map_ev;
1079 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1080 };
1081 } __packed;
1082
1083 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1084 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1085 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1086
1087 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1088 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1089
1090 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1091 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1092
1093 enum htt_backpressure_umac_ringid {
1094 HTT_SW_RING_IDX_REO_REO2SW1_RING,
1095 HTT_SW_RING_IDX_REO_REO2SW2_RING,
1096 HTT_SW_RING_IDX_REO_REO2SW3_RING,
1097 HTT_SW_RING_IDX_REO_REO2SW4_RING,
1098 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1099 HTT_SW_RING_IDX_REO_REO2TCL_RING,
1100 HTT_SW_RING_IDX_REO_REO2FW_RING,
1101 HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1102 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1103 HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1104 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1105 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1106 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1107 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1108 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1109 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1110 HTT_SW_RING_IDX_REO_REO_CMD_RING,
1111 HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1112 HTT_SW_UMAC_RING_IDX_MAX,
1113 };
1114
1115 enum htt_backpressure_lmac_ringid {
1116 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1117 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1118 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1119 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1120 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1121 HTT_SW_RING_IDX_RXDMA2FW_RING,
1122 HTT_SW_RING_IDX_RXDMA2SW_RING,
1123 HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1124 HTT_SW_RING_IDX_RXDMA2REO_RING,
1125 HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1126 HTT_SW_RING_IDX_MONITOR_BUF_RING,
1127 HTT_SW_RING_IDX_MONITOR_DESC_RING,
1128 HTT_SW_RING_IDX_MONITOR_DEST_RING,
1129 HTT_SW_LMAC_RING_IDX_MAX,
1130 };
1131
1132 /* ppdu stats
1133 *
1134 * @details
1135 * The following field definitions describe the format of the HTT target
1136 * to host ppdu stats indication message.
1137 *
1138 *
1139 * |31 16|15 12|11 10|9 8|7 0 |
1140 * |----------------------------------------------------------------------|
1141 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1142 * |----------------------------------------------------------------------|
1143 * | ppdu_id |
1144 * |----------------------------------------------------------------------|
1145 * | Timestamp in us |
1146 * |----------------------------------------------------------------------|
1147 * | reserved |
1148 * |----------------------------------------------------------------------|
1149 * | type-specific stats info |
1150 * | (see htt_ppdu_stats.h) |
1151 * |----------------------------------------------------------------------|
1152 * Header fields:
1153 * - MSG_TYPE
1154 * Bits 7:0
1155 * Purpose: Identifies this is a PPDU STATS indication
1156 * message.
1157 * Value: 0x1d
1158 * - mac_id
1159 * Bits 9:8
1160 * Purpose: mac_id of this ppdu_id
1161 * Value: 0-3
1162 * - pdev_id
1163 * Bits 11:10
1164 * Purpose: pdev_id of this ppdu_id
1165 * Value: 0-3
1166 * 0 (for rings at SOC level),
1167 * 1/2/3 PDEV -> 0/1/2
1168 * - payload_size
1169 * Bits 31:16
1170 * Purpose: total tlv size
1171 * Value: payload_size in bytes
1172 */
1173
1174 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1175 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1176
1177 struct ath11k_htt_ppdu_stats_msg {
1178 u32 info;
1179 u32 ppdu_id;
1180 u32 timestamp;
1181 u32 rsvd;
1182 u8 data[];
1183 } __packed;
1184
1185 struct htt_tlv {
1186 u32 header;
1187 u8 value[];
1188 } __packed;
1189
1190 #define HTT_TLV_TAG GENMASK(11, 0)
1191 #define HTT_TLV_LEN GENMASK(23, 12)
1192
1193 enum HTT_PPDU_STATS_BW {
1194 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1195 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1196 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1197 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1198 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1199 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1200 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1201 };
1202
1203 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1204 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1205 /* bw - HTT_PPDU_STATS_BW */
1206 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1207
1208 struct htt_ppdu_stats_common {
1209 u32 ppdu_id;
1210 u16 sched_cmdid;
1211 u8 ring_id;
1212 u8 num_users;
1213 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1214 u32 chain_mask;
1215 u32 fes_duration_us; /* frame exchange sequence */
1216 u32 ppdu_sch_eval_start_tstmp_us;
1217 u32 ppdu_sch_end_tstmp_us;
1218 u32 ppdu_start_tstmp_us;
1219 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1220 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1221 */
1222 u16 phy_mode;
1223 u16 bw_mhz;
1224 } __packed;
1225
1226 enum htt_ppdu_stats_gi {
1227 HTT_PPDU_STATS_SGI_0_8_US,
1228 HTT_PPDU_STATS_SGI_0_4_US,
1229 HTT_PPDU_STATS_SGI_1_6_US,
1230 HTT_PPDU_STATS_SGI_3_2_US,
1231 };
1232
1233 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1234 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1235
1236 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1237 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1238
1239 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1240 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1241 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1242 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1243 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1244 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1245 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1246 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1247 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1248 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1249 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1250
1251 #define HTT_USR_RATE_PREAMBLE(_val) \
1252 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1253 #define HTT_USR_RATE_BW(_val) \
1254 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1255 #define HTT_USR_RATE_NSS(_val) \
1256 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1257 #define HTT_USR_RATE_MCS(_val) \
1258 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1259 #define HTT_USR_RATE_GI(_val) \
1260 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1261 #define HTT_USR_RATE_DCM(_val) \
1262 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1263
1264 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1265 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1266 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1267 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1268 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1269 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1270 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1271 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1272 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1273 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1274 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1275
1276 struct htt_ppdu_stats_user_rate {
1277 u8 tid_num;
1278 u8 reserved0;
1279 u16 sw_peer_id;
1280 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1281 u16 ru_end;
1282 u16 ru_start;
1283 u16 resp_ru_end;
1284 u16 resp_ru_start;
1285 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1286 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1287 /* Note: resp_rate_info is only valid for if resp_type is UL */
1288 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1289 } __packed;
1290
1291 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1292 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1293 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1294 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1295 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1296 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1297
1298 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1299 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1300 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1301 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1302 #define HTT_TX_INFO_RATECODE(_flags) \
1303 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1304 #define HTT_TX_INFO_PEERID(_flags) \
1305 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1306
1307 enum htt_ppdu_stats_usr_compln_status {
1308 HTT_PPDU_STATS_USER_STATUS_OK,
1309 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1310 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1311 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1312 HTT_PPDU_STATS_USER_STATUS_ABORT,
1313 };
1314
1315 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1316 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1317 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1318 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1319
1320 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1321 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1322 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1323 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1324 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1325 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1326
1327 struct htt_ppdu_stats_usr_cmpltn_cmn {
1328 u8 status;
1329 u8 tid_num;
1330 u16 sw_peer_id;
1331 /* RSSI value of last ack packet (units = dB above noise floor) */
1332 u32 ack_rssi;
1333 u16 mpdu_tried;
1334 u16 mpdu_success;
1335 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1336 } __packed;
1337
1338 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1339 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1340 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1341
1342 #define HTT_PPDU_STATS_NON_QOS_TID 16
1343
1344 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1345 u32 ppdu_id;
1346 u16 sw_peer_id;
1347 u16 reserved0;
1348 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1349 u16 current_seq;
1350 u16 start_seq;
1351 u32 success_bytes;
1352 } __packed;
1353
1354 struct htt_ppdu_user_stats {
1355 u16 peer_id;
1356 u32 tlv_flags;
1357 bool is_valid_peer_id;
1358 struct htt_ppdu_stats_user_rate rate;
1359 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1360 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1361 };
1362
1363 #define HTT_PPDU_STATS_MAX_USERS 8
1364 #define HTT_PPDU_DESC_MAX_DEPTH 16
1365
1366 struct htt_ppdu_stats {
1367 struct htt_ppdu_stats_common common;
1368 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1369 };
1370
1371 struct htt_ppdu_stats_info {
1372 u32 ppdu_id;
1373 struct htt_ppdu_stats ppdu_stats;
1374 struct list_head list;
1375 };
1376
1377 /* @brief target -> host packet log message
1378 *
1379 * @details
1380 * The following field definitions describe the format of the packet log
1381 * message sent from the target to the host.
1382 * The message consists of a 4-octet header,followed by a variable number
1383 * of 32-bit character values.
1384 *
1385 * |31 16|15 12|11 10|9 8|7 0|
1386 * |------------------------------------------------------------------|
1387 * | payload_size | rsvd |pdev_id|mac_id| msg type |
1388 * |------------------------------------------------------------------|
1389 * | payload |
1390 * |------------------------------------------------------------------|
1391 * - MSG_TYPE
1392 * Bits 7:0
1393 * Purpose: identifies this as a pktlog message
1394 * Value: HTT_T2H_MSG_TYPE_PKTLOG
1395 * - mac_id
1396 * Bits 9:8
1397 * Purpose: identifies which MAC/PHY instance generated this pktlog info
1398 * Value: 0-3
1399 * - pdev_id
1400 * Bits 11:10
1401 * Purpose: pdev_id
1402 * Value: 0-3
1403 * 0 (for rings at SOC level),
1404 * 1/2/3 PDEV -> 0/1/2
1405 * - payload_size
1406 * Bits 31:16
1407 * Purpose: explicitly specify the payload size
1408 * Value: payload size in bytes (payload size is a multiple of 4 bytes)
1409 */
1410 struct htt_pktlog_msg {
1411 u32 hdr;
1412 u8 payload[];
1413 };
1414
1415 /* @brief host -> target FW extended statistics retrieve
1416 *
1417 * @details
1418 * The following field definitions describe the format of the HTT host
1419 * to target FW extended stats retrieve message.
1420 * The message specifies the type of stats the host wants to retrieve.
1421 *
1422 * |31 24|23 16|15 8|7 0|
1423 * |-----------------------------------------------------------|
1424 * | reserved | stats type | pdev_mask | msg type |
1425 * |-----------------------------------------------------------|
1426 * | config param [0] |
1427 * |-----------------------------------------------------------|
1428 * | config param [1] |
1429 * |-----------------------------------------------------------|
1430 * | config param [2] |
1431 * |-----------------------------------------------------------|
1432 * | config param [3] |
1433 * |-----------------------------------------------------------|
1434 * | reserved |
1435 * |-----------------------------------------------------------|
1436 * | cookie LSBs |
1437 * |-----------------------------------------------------------|
1438 * | cookie MSBs |
1439 * |-----------------------------------------------------------|
1440 * Header fields:
1441 * - MSG_TYPE
1442 * Bits 7:0
1443 * Purpose: identifies this is a extended stats upload request message
1444 * Value: 0x10
1445 * - PDEV_MASK
1446 * Bits 8:15
1447 * Purpose: identifies the mask of PDEVs to retrieve stats from
1448 * Value: This is a overloaded field, refer to usage and interpretation of
1449 * PDEV in interface document.
1450 * Bit 8 : Reserved for SOC stats
1451 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1452 * Indicates MACID_MASK in DBS
1453 * - STATS_TYPE
1454 * Bits 23:16
1455 * Purpose: identifies which FW statistics to upload
1456 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1457 * - Reserved
1458 * Bits 31:24
1459 * - CONFIG_PARAM [0]
1460 * Bits 31:0
1461 * Purpose: give an opaque configuration value to the specified stats type
1462 * Value: stats-type specific configuration value
1463 * Refer to htt_stats.h for interpretation for each stats sub_type
1464 * - CONFIG_PARAM [1]
1465 * Bits 31:0
1466 * Purpose: give an opaque configuration value to the specified stats type
1467 * Value: stats-type specific configuration value
1468 * Refer to htt_stats.h for interpretation for each stats sub_type
1469 * - CONFIG_PARAM [2]
1470 * Bits 31:0
1471 * Purpose: give an opaque configuration value to the specified stats type
1472 * Value: stats-type specific configuration value
1473 * Refer to htt_stats.h for interpretation for each stats sub_type
1474 * - CONFIG_PARAM [3]
1475 * Bits 31:0
1476 * Purpose: give an opaque configuration value to the specified stats type
1477 * Value: stats-type specific configuration value
1478 * Refer to htt_stats.h for interpretation for each stats sub_type
1479 * - Reserved [31:0] for future use.
1480 * - COOKIE_LSBS
1481 * Bits 31:0
1482 * Purpose: Provide a mechanism to match a target->host stats confirmation
1483 * message with its preceding host->target stats request message.
1484 * Value: LSBs of the opaque cookie specified by the host-side requestor
1485 * - COOKIE_MSBS
1486 * Bits 31:0
1487 * Purpose: Provide a mechanism to match a target->host stats confirmation
1488 * message with its preceding host->target stats request message.
1489 * Value: MSBs of the opaque cookie specified by the host-side requestor
1490 */
1491
1492 struct htt_ext_stats_cfg_hdr {
1493 u8 msg_type;
1494 u8 pdev_mask;
1495 u8 stats_type;
1496 u8 reserved;
1497 } __packed;
1498
1499 struct htt_ext_stats_cfg_cmd {
1500 struct htt_ext_stats_cfg_hdr hdr;
1501 u32 cfg_param0;
1502 u32 cfg_param1;
1503 u32 cfg_param2;
1504 u32 cfg_param3;
1505 u32 reserved;
1506 u32 cookie_lsb;
1507 u32 cookie_msb;
1508 } __packed;
1509
1510 /* htt stats config default params */
1511 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1512 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1513 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1514 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1515 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1516 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1517 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1518 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1519
1520 /* HTT_DBG_EXT_STATS_PEER_INFO
1521 * PARAMS:
1522 * @config_param0:
1523 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1524 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1525 * [Bit31 : Bit16] sw_peer_id
1526 * @config_param1:
1527 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1528 * 0 bit htt_peer_stats_cmn_tlv
1529 * 1 bit htt_peer_details_tlv
1530 * 2 bit htt_tx_peer_rate_stats_tlv
1531 * 3 bit htt_rx_peer_rate_stats_tlv
1532 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1533 * 5 bit htt_rx_tid_stats_tlv
1534 * 6 bit htt_msdu_flow_stats_tlv
1535 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1536 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1537 * [Bit31 : Bit16] reserved
1538 */
1539 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1540 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1541
1542 /* Used to set different configs to the specified stats type.*/
1543 struct htt_ext_stats_cfg_params {
1544 u32 cfg0;
1545 u32 cfg1;
1546 u32 cfg2;
1547 u32 cfg3;
1548 };
1549
1550 /* @brief target -> host extended statistics upload
1551 *
1552 * @details
1553 * The following field definitions describe the format of the HTT target
1554 * to host stats upload confirmation message.
1555 * The message contains a cookie echoed from the HTT host->target stats
1556 * upload request, which identifies which request the confirmation is
1557 * for, and a single stats can span over multiple HTT stats indication
1558 * due to the HTT message size limitation so every HTT ext stats indication
1559 * will have tag-length-value stats information elements.
1560 * The tag-length header for each HTT stats IND message also includes a
1561 * status field, to indicate whether the request for the stat type in
1562 * question was fully met, partially met, unable to be met, or invalid
1563 * (if the stat type in question is disabled in the target).
1564 * A Done bit 1's indicate the end of the of stats info elements.
1565 *
1566 *
1567 * |31 16|15 12|11|10 8|7 5|4 0|
1568 * |--------------------------------------------------------------|
1569 * | reserved | msg type |
1570 * |--------------------------------------------------------------|
1571 * | cookie LSBs |
1572 * |--------------------------------------------------------------|
1573 * | cookie MSBs |
1574 * |--------------------------------------------------------------|
1575 * | stats entry length | rsvd | D| S | stat type |
1576 * |--------------------------------------------------------------|
1577 * | type-specific stats info |
1578 * | (see htt_stats.h) |
1579 * |--------------------------------------------------------------|
1580 * Header fields:
1581 * - MSG_TYPE
1582 * Bits 7:0
1583 * Purpose: Identifies this is a extended statistics upload confirmation
1584 * message.
1585 * Value: 0x1c
1586 * - COOKIE_LSBS
1587 * Bits 31:0
1588 * Purpose: Provide a mechanism to match a target->host stats confirmation
1589 * message with its preceding host->target stats request message.
1590 * Value: LSBs of the opaque cookie specified by the host-side requestor
1591 * - COOKIE_MSBS
1592 * Bits 31:0
1593 * Purpose: Provide a mechanism to match a target->host stats confirmation
1594 * message with its preceding host->target stats request message.
1595 * Value: MSBs of the opaque cookie specified by the host-side requestor
1596 *
1597 * Stats Information Element tag-length header fields:
1598 * - STAT_TYPE
1599 * Bits 7:0
1600 * Purpose: identifies the type of statistics info held in the
1601 * following information element
1602 * Value: htt_dbg_ext_stats_type
1603 * - STATUS
1604 * Bits 10:8
1605 * Purpose: indicate whether the requested stats are present
1606 * Value: htt_dbg_ext_stats_status
1607 * - DONE
1608 * Bits 11
1609 * Purpose:
1610 * Indicates the completion of the stats entry, this will be the last
1611 * stats conf HTT segment for the requested stats type.
1612 * Value:
1613 * 0 -> the stats retrieval is ongoing
1614 * 1 -> the stats retrieval is complete
1615 * - LENGTH
1616 * Bits 31:16
1617 * Purpose: indicate the stats information size
1618 * Value: This field specifies the number of bytes of stats information
1619 * that follows the element tag-length header.
1620 * It is expected but not required that this length is a multiple of
1621 * 4 bytes.
1622 */
1623
1624 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
1625 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
1626
1627 struct ath11k_htt_extd_stats_msg {
1628 u32 info0;
1629 u64 cookie;
1630 u32 info1;
1631 u8 data[];
1632 } __packed;
1633
1634 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
1635 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
1636 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
1637 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
1638 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
1639 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
1640
1641 struct htt_mac_addr {
1642 u32 mac_addr_l32;
1643 u32 mac_addr_h16;
1644 };
1645
ath11k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1646 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1647 {
1648 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1649 addr_l32 = swab32(addr_l32);
1650 addr_h16 = swab16(addr_h16);
1651 }
1652
1653 memcpy(addr, &addr_l32, 4);
1654 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1655 }
1656
1657 int ath11k_dp_service_srng(struct ath11k_base *ab,
1658 struct ath11k_ext_irq_grp *irq_grp,
1659 int budget);
1660 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1661 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1662 void ath11k_dp_free(struct ath11k_base *ab);
1663 int ath11k_dp_alloc(struct ath11k_base *ab);
1664 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1665 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1666 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1667 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1668 int mac_id, enum hal_ring_type ring_type);
1669 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1670 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1671 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1672 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1673 enum hal_ring_type type, int ring_num,
1674 int mac_id, int num_entries);
1675 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1676 struct dp_link_desc_bank *desc_bank,
1677 u32 ring_type, struct dp_srng *ring);
1678 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1679 struct dp_link_desc_bank *link_desc_banks,
1680 u32 ring_type, struct hal_srng *srng,
1681 u32 n_link_desc);
1682 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1683 struct hal_srng *srng,
1684 struct ath11k_hp_update_timer *update_timer);
1685 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1686 struct ath11k_hp_update_timer *update_timer);
1687 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1688 struct ath11k_hp_update_timer *update_timer,
1689 u32 interval, u32 ring_id);
1690 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab);
1691
1692 #endif
1693