1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19 #include "fw.h"
20
21 unsigned int ath11k_debug_mask;
22 EXPORT_SYMBOL(ath11k_debug_mask);
23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
24 MODULE_PARM_DESC(debug_mask, "Debugging mask");
25
26 static unsigned int ath11k_crypto_mode;
27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
29
30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
33 MODULE_PARM_DESC(frame_mode,
34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
35
36 bool ath11k_ftm_mode;
37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
39
40 static const struct ath11k_hw_params ath11k_hw_params[] = {
41 {
42 .hw_rev = ATH11K_HW_IPQ8074,
43 .name = "ipq8074 hw2.0",
44 .fw = {
45 .dir = "IPQ8074/hw2.0",
46 .board_size = 256 * 1024,
47 .cal_offset = 128 * 1024,
48 },
49 .max_radios = 3,
50 .bdf_addr = 0x4B0C0000,
51 .hw_ops = &ipq8074_ops,
52 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
53 .internal_sleep_clock = false,
54 .regs = &ipq8074_regs,
55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
56 .host_ce_config = ath11k_host_ce_config_ipq8074,
57 .ce_count = 12,
58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
59 .target_ce_count = 11,
60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
61 .svc_to_ce_map_len = 21,
62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
63 .single_pdev_only = false,
64 .rxdma1_enable = true,
65 .num_rxdma_per_pdev = 1,
66 .rx_mac_buf_ring = false,
67 .vdev_start_delay = false,
68 .htt_peer_map_v2 = true,
69
70 .spectral = {
71 .fft_sz = 2,
72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
73 * so added pad size as 2 bytes to compensate the BIN size
74 */
75 .fft_pad_sz = 2,
76 .summary_pad_sz = 0,
77 .fft_hdr_len = 16,
78 .max_fft_bins = 512,
79 .fragment_160mhz = true,
80 },
81
82 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
83 BIT(NL80211_IFTYPE_AP) |
84 BIT(NL80211_IFTYPE_MESH_POINT),
85 .supports_monitor = true,
86 .full_monitor_mode = false,
87 .supports_shadow_regs = false,
88 .idle_ps = false,
89 .supports_sta_ps = false,
90 .coldboot_cal_mm = true,
91 .coldboot_cal_ftm = true,
92 .cbcal_restart_fw = true,
93 .fw_mem_mode = 0,
94 .num_vdevs = 16 + 1,
95 .num_peers = 512,
96 .supports_suspend = false,
97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
98 .supports_regdb = false,
99 .fix_l1ss = true,
100 .credit_flow = false,
101 .max_tx_ring = DP_TCL_NUM_RING_MAX,
102 .hal_params = &ath11k_hw_hal_params_ipq8074,
103 .supports_dynamic_smps_6ghz = false,
104 .alloc_cacheable_memory = true,
105 .supports_rssi_stats = false,
106 .fw_wmi_diag_event = false,
107 .current_cc_support = false,
108 .dbr_debug_support = true,
109 .global_reset = false,
110 .bios_sar_capa = NULL,
111 .m3_fw_support = false,
112 .fixed_bdf_addr = true,
113 .fixed_mem_region = true,
114 .static_window_map = false,
115 .hybrid_bus_type = false,
116 .fixed_fw_mem = false,
117 .support_off_channel_tx = false,
118 .supports_multi_bssid = false,
119
120 .sram_dump = {},
121
122 .tcl_ring_retry = true,
123 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
124 .smp2p_wow_exit = false,
125 .support_dual_stations = false,
126 .pdev_suspend = false,
127 },
128 {
129 .hw_rev = ATH11K_HW_IPQ6018_HW10,
130 .name = "ipq6018 hw1.0",
131 .fw = {
132 .dir = "IPQ6018/hw1.0",
133 .board_size = 256 * 1024,
134 .cal_offset = 128 * 1024,
135 },
136 .max_radios = 2,
137 .bdf_addr = 0x4ABC0000,
138 .hw_ops = &ipq6018_ops,
139 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
140 .internal_sleep_clock = false,
141 .regs = &ipq8074_regs,
142 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
143 .host_ce_config = ath11k_host_ce_config_ipq8074,
144 .ce_count = 12,
145 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
146 .target_ce_count = 11,
147 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
148 .svc_to_ce_map_len = 19,
149 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
150 .single_pdev_only = false,
151 .rxdma1_enable = true,
152 .num_rxdma_per_pdev = 1,
153 .rx_mac_buf_ring = false,
154 .vdev_start_delay = false,
155 .htt_peer_map_v2 = true,
156
157 .spectral = {
158 .fft_sz = 4,
159 .fft_pad_sz = 0,
160 .summary_pad_sz = 0,
161 .fft_hdr_len = 16,
162 .max_fft_bins = 512,
163 .fragment_160mhz = true,
164 },
165
166 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
167 BIT(NL80211_IFTYPE_AP) |
168 BIT(NL80211_IFTYPE_MESH_POINT),
169 .supports_monitor = true,
170 .full_monitor_mode = false,
171 .supports_shadow_regs = false,
172 .idle_ps = false,
173 .supports_sta_ps = false,
174 .coldboot_cal_mm = true,
175 .coldboot_cal_ftm = true,
176 .cbcal_restart_fw = true,
177 .fw_mem_mode = 0,
178 .num_vdevs = 16 + 1,
179 .num_peers = 512,
180 .supports_suspend = false,
181 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
182 .supports_regdb = false,
183 .fix_l1ss = true,
184 .credit_flow = false,
185 .max_tx_ring = DP_TCL_NUM_RING_MAX,
186 .hal_params = &ath11k_hw_hal_params_ipq8074,
187 .supports_dynamic_smps_6ghz = false,
188 .alloc_cacheable_memory = true,
189 .supports_rssi_stats = false,
190 .fw_wmi_diag_event = false,
191 .current_cc_support = false,
192 .dbr_debug_support = true,
193 .global_reset = false,
194 .bios_sar_capa = NULL,
195 .m3_fw_support = false,
196 .fixed_bdf_addr = true,
197 .fixed_mem_region = true,
198 .static_window_map = false,
199 .hybrid_bus_type = false,
200 .fixed_fw_mem = false,
201 .support_off_channel_tx = false,
202 .supports_multi_bssid = false,
203
204 .sram_dump = {},
205
206 .tcl_ring_retry = true,
207 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
208 .smp2p_wow_exit = false,
209 .support_fw_mac_sequence = false,
210 .support_dual_stations = false,
211 .pdev_suspend = false,
212 },
213 {
214 .name = "qca6390 hw2.0",
215 .hw_rev = ATH11K_HW_QCA6390_HW20,
216 .fw = {
217 .dir = "QCA6390/hw2.0",
218 .board_size = 256 * 1024,
219 .cal_offset = 128 * 1024,
220 },
221 .max_radios = 3,
222 .bdf_addr = 0x4B0C0000,
223 .hw_ops = &qca6390_ops,
224 .ring_mask = &ath11k_hw_ring_mask_qca6390,
225 .internal_sleep_clock = true,
226 .regs = &qca6390_regs,
227 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
228 .host_ce_config = ath11k_host_ce_config_qca6390,
229 .ce_count = 9,
230 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
231 .target_ce_count = 9,
232 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
233 .svc_to_ce_map_len = 14,
234 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
235 .single_pdev_only = true,
236 .rxdma1_enable = false,
237 .num_rxdma_per_pdev = 2,
238 .rx_mac_buf_ring = true,
239 .vdev_start_delay = true,
240 .htt_peer_map_v2 = false,
241
242 .spectral = {
243 .fft_sz = 0,
244 .fft_pad_sz = 0,
245 .summary_pad_sz = 0,
246 .fft_hdr_len = 0,
247 .max_fft_bins = 0,
248 .fragment_160mhz = false,
249 },
250
251 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
252 BIT(NL80211_IFTYPE_AP) |
253 BIT(NL80211_IFTYPE_P2P_DEVICE) |
254 BIT(NL80211_IFTYPE_P2P_CLIENT) |
255 BIT(NL80211_IFTYPE_P2P_GO),
256 .supports_monitor = false,
257 .full_monitor_mode = false,
258 .supports_shadow_regs = true,
259 .idle_ps = true,
260 .supports_sta_ps = true,
261 .coldboot_cal_mm = false,
262 .coldboot_cal_ftm = false,
263 .cbcal_restart_fw = false,
264 .fw_mem_mode = 0,
265 .num_vdevs = 2 + 1,
266 .num_peers = 512,
267 .supports_suspend = true,
268 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
269 .supports_regdb = false,
270 .fix_l1ss = true,
271 .credit_flow = true,
272 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
273 .hal_params = &ath11k_hw_hal_params_qca6390,
274 .supports_dynamic_smps_6ghz = false,
275 .alloc_cacheable_memory = false,
276 .supports_rssi_stats = true,
277 .fw_wmi_diag_event = true,
278 .current_cc_support = true,
279 .dbr_debug_support = false,
280 .global_reset = true,
281 .bios_sar_capa = NULL,
282 .m3_fw_support = true,
283 .fixed_bdf_addr = false,
284 .fixed_mem_region = false,
285 .static_window_map = false,
286 .hybrid_bus_type = false,
287 .fixed_fw_mem = false,
288 .support_off_channel_tx = true,
289 .supports_multi_bssid = true,
290
291 .sram_dump = {
292 .start = 0x01400000,
293 .end = 0x0171ffff,
294 },
295
296 .tcl_ring_retry = true,
297 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
298 .smp2p_wow_exit = false,
299 .support_fw_mac_sequence = true,
300 .support_dual_stations = true,
301 .pdev_suspend = false,
302 },
303 {
304 .name = "qcn9074 hw1.0",
305 .hw_rev = ATH11K_HW_QCN9074_HW10,
306 .fw = {
307 .dir = "QCN9074/hw1.0",
308 .board_size = 256 * 1024,
309 .cal_offset = 128 * 1024,
310 },
311 .max_radios = 1,
312 .single_pdev_only = false,
313 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
314 .hw_ops = &qcn9074_ops,
315 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
316 .internal_sleep_clock = false,
317 .regs = &qcn9074_regs,
318 .host_ce_config = ath11k_host_ce_config_qcn9074,
319 .ce_count = 6,
320 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
321 .target_ce_count = 9,
322 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
323 .svc_to_ce_map_len = 18,
324 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
325 .rxdma1_enable = true,
326 .num_rxdma_per_pdev = 1,
327 .rx_mac_buf_ring = false,
328 .vdev_start_delay = false,
329 .htt_peer_map_v2 = true,
330
331 .spectral = {
332 .fft_sz = 2,
333 .fft_pad_sz = 0,
334 .summary_pad_sz = 16,
335 .fft_hdr_len = 24,
336 .max_fft_bins = 1024,
337 .fragment_160mhz = false,
338 },
339
340 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
341 BIT(NL80211_IFTYPE_AP) |
342 BIT(NL80211_IFTYPE_MESH_POINT),
343 .supports_monitor = true,
344 .full_monitor_mode = true,
345 .supports_shadow_regs = false,
346 .idle_ps = false,
347 .supports_sta_ps = false,
348 .coldboot_cal_mm = false,
349 .coldboot_cal_ftm = true,
350 .cbcal_restart_fw = true,
351 .fw_mem_mode = 2,
352 .num_vdevs = 8,
353 .num_peers = 128,
354 .supports_suspend = false,
355 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
356 .supports_regdb = false,
357 .fix_l1ss = true,
358 .credit_flow = false,
359 .max_tx_ring = DP_TCL_NUM_RING_MAX,
360 .hal_params = &ath11k_hw_hal_params_ipq8074,
361 .supports_dynamic_smps_6ghz = true,
362 .alloc_cacheable_memory = true,
363 .supports_rssi_stats = false,
364 .fw_wmi_diag_event = false,
365 .current_cc_support = false,
366 .dbr_debug_support = true,
367 .global_reset = false,
368 .bios_sar_capa = NULL,
369 .m3_fw_support = true,
370 .fixed_bdf_addr = false,
371 .fixed_mem_region = false,
372 .static_window_map = true,
373 .hybrid_bus_type = false,
374 .fixed_fw_mem = false,
375 .support_off_channel_tx = false,
376 .supports_multi_bssid = false,
377
378 .sram_dump = {},
379
380 .tcl_ring_retry = true,
381 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
382 .smp2p_wow_exit = false,
383 .support_fw_mac_sequence = false,
384 .support_dual_stations = false,
385 .pdev_suspend = false,
386 },
387 {
388 .name = "wcn6855 hw2.0",
389 .hw_rev = ATH11K_HW_WCN6855_HW20,
390 .fw = {
391 .dir = "WCN6855/hw2.0",
392 .board_size = 256 * 1024,
393 .cal_offset = 128 * 1024,
394 },
395 .max_radios = 3,
396 .bdf_addr = 0x4B0C0000,
397 .hw_ops = &wcn6855_ops,
398 .ring_mask = &ath11k_hw_ring_mask_qca6390,
399 .internal_sleep_clock = true,
400 .regs = &wcn6855_regs,
401 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
402 .host_ce_config = ath11k_host_ce_config_qca6390,
403 .ce_count = 9,
404 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
405 .target_ce_count = 9,
406 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
407 .svc_to_ce_map_len = 14,
408 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
409 .single_pdev_only = true,
410 .rxdma1_enable = false,
411 .num_rxdma_per_pdev = 2,
412 .rx_mac_buf_ring = true,
413 .vdev_start_delay = true,
414 .htt_peer_map_v2 = false,
415
416 .spectral = {
417 .fft_sz = 0,
418 .fft_pad_sz = 0,
419 .summary_pad_sz = 0,
420 .fft_hdr_len = 0,
421 .max_fft_bins = 0,
422 .fragment_160mhz = false,
423 },
424
425 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
426 BIT(NL80211_IFTYPE_AP) |
427 BIT(NL80211_IFTYPE_P2P_DEVICE) |
428 BIT(NL80211_IFTYPE_P2P_CLIENT) |
429 BIT(NL80211_IFTYPE_P2P_GO),
430 .supports_monitor = false,
431 .full_monitor_mode = false,
432 .supports_shadow_regs = true,
433 .idle_ps = true,
434 .supports_sta_ps = true,
435 .coldboot_cal_mm = false,
436 .coldboot_cal_ftm = false,
437 .cbcal_restart_fw = false,
438 .fw_mem_mode = 0,
439 .num_vdevs = 2 + 1,
440 .num_peers = 512,
441 .supports_suspend = true,
442 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
443 .supports_regdb = true,
444 .fix_l1ss = false,
445 .credit_flow = true,
446 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
447 .hal_params = &ath11k_hw_hal_params_qca6390,
448 .supports_dynamic_smps_6ghz = false,
449 .alloc_cacheable_memory = false,
450 .supports_rssi_stats = true,
451 .fw_wmi_diag_event = true,
452 .current_cc_support = true,
453 .dbr_debug_support = false,
454 .global_reset = true,
455 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
456 .m3_fw_support = true,
457 .fixed_bdf_addr = false,
458 .fixed_mem_region = false,
459 .static_window_map = false,
460 .hybrid_bus_type = false,
461 .fixed_fw_mem = false,
462 .support_off_channel_tx = true,
463 .supports_multi_bssid = true,
464
465 .sram_dump = {
466 .start = 0x01400000,
467 .end = 0x0177ffff,
468 },
469
470 .tcl_ring_retry = true,
471 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
472 .smp2p_wow_exit = false,
473 .support_fw_mac_sequence = true,
474 .support_dual_stations = true,
475 .pdev_suspend = false,
476 },
477 {
478 .name = "wcn6855 hw2.1",
479 .hw_rev = ATH11K_HW_WCN6855_HW21,
480 .fw = {
481 .dir = "WCN6855/hw2.1",
482 .board_size = 256 * 1024,
483 .cal_offset = 128 * 1024,
484 },
485 .max_radios = 3,
486 .bdf_addr = 0x4B0C0000,
487 .hw_ops = &wcn6855_ops,
488 .ring_mask = &ath11k_hw_ring_mask_qca6390,
489 .internal_sleep_clock = true,
490 .regs = &wcn6855_regs,
491 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
492 .host_ce_config = ath11k_host_ce_config_qca6390,
493 .ce_count = 9,
494 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
495 .target_ce_count = 9,
496 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
497 .svc_to_ce_map_len = 14,
498 .single_pdev_only = true,
499 .rxdma1_enable = false,
500 .num_rxdma_per_pdev = 2,
501 .rx_mac_buf_ring = true,
502 .vdev_start_delay = true,
503 .htt_peer_map_v2 = false,
504
505 .spectral = {
506 .fft_sz = 0,
507 .fft_pad_sz = 0,
508 .summary_pad_sz = 0,
509 .fft_hdr_len = 0,
510 .max_fft_bins = 0,
511 .fragment_160mhz = false,
512 },
513
514 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
515 BIT(NL80211_IFTYPE_AP) |
516 BIT(NL80211_IFTYPE_P2P_DEVICE) |
517 BIT(NL80211_IFTYPE_P2P_CLIENT) |
518 BIT(NL80211_IFTYPE_P2P_GO),
519 .supports_monitor = false,
520 .supports_shadow_regs = true,
521 .idle_ps = true,
522 .supports_sta_ps = true,
523 .coldboot_cal_mm = false,
524 .coldboot_cal_ftm = false,
525 .cbcal_restart_fw = false,
526 .fw_mem_mode = 0,
527 .num_vdevs = 2 + 1,
528 .num_peers = 512,
529 .supports_suspend = true,
530 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
531 .supports_regdb = true,
532 .fix_l1ss = false,
533 .credit_flow = true,
534 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
535 .hal_params = &ath11k_hw_hal_params_qca6390,
536 .supports_dynamic_smps_6ghz = false,
537 .alloc_cacheable_memory = false,
538 .supports_rssi_stats = true,
539 .fw_wmi_diag_event = true,
540 .current_cc_support = true,
541 .dbr_debug_support = false,
542 .global_reset = true,
543 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
544 .m3_fw_support = true,
545 .fixed_bdf_addr = false,
546 .fixed_mem_region = false,
547 .static_window_map = false,
548 .hybrid_bus_type = false,
549 .fixed_fw_mem = false,
550 .support_off_channel_tx = true,
551 .supports_multi_bssid = true,
552
553 .sram_dump = {
554 .start = 0x01400000,
555 .end = 0x0177ffff,
556 },
557
558 .tcl_ring_retry = true,
559 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
560 .smp2p_wow_exit = false,
561 .support_fw_mac_sequence = true,
562 .support_dual_stations = true,
563 .pdev_suspend = false,
564 },
565 {
566 .name = "wcn6750 hw1.0",
567 .hw_rev = ATH11K_HW_WCN6750_HW10,
568 .fw = {
569 .dir = "WCN6750/hw1.0",
570 .board_size = 256 * 1024,
571 .cal_offset = 128 * 1024,
572 },
573 .max_radios = 1,
574 .bdf_addr = 0x4B0C0000,
575 .hw_ops = &wcn6750_ops,
576 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
577 .internal_sleep_clock = false,
578 .regs = &wcn6750_regs,
579 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
580 .host_ce_config = ath11k_host_ce_config_qca6390,
581 .ce_count = 9,
582 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
583 .target_ce_count = 9,
584 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
585 .svc_to_ce_map_len = 14,
586 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
587 .single_pdev_only = true,
588 .rxdma1_enable = false,
589 .num_rxdma_per_pdev = 1,
590 .rx_mac_buf_ring = true,
591 .vdev_start_delay = true,
592 .htt_peer_map_v2 = false,
593
594 .spectral = {
595 .fft_sz = 0,
596 .fft_pad_sz = 0,
597 .summary_pad_sz = 0,
598 .fft_hdr_len = 0,
599 .max_fft_bins = 0,
600 .fragment_160mhz = false,
601 },
602
603 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
604 BIT(NL80211_IFTYPE_AP),
605 .supports_monitor = false,
606 .supports_shadow_regs = true,
607 .idle_ps = true,
608 .supports_sta_ps = true,
609 .coldboot_cal_mm = true,
610 .coldboot_cal_ftm = true,
611 .cbcal_restart_fw = false,
612 .fw_mem_mode = 0,
613 .num_vdevs = 3,
614 .num_peers = 512,
615 .supports_suspend = false,
616 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
617 .supports_regdb = true,
618 .fix_l1ss = false,
619 .credit_flow = true,
620 .max_tx_ring = DP_TCL_NUM_RING_MAX,
621 .hal_params = &ath11k_hw_hal_params_wcn6750,
622 .supports_dynamic_smps_6ghz = false,
623 .alloc_cacheable_memory = false,
624 .supports_rssi_stats = true,
625 .fw_wmi_diag_event = true,
626 .current_cc_support = true,
627 .dbr_debug_support = false,
628 .global_reset = false,
629 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
630 .m3_fw_support = false,
631 .fixed_bdf_addr = false,
632 .fixed_mem_region = false,
633 .static_window_map = true,
634 .hybrid_bus_type = true,
635 .fixed_fw_mem = true,
636 .support_off_channel_tx = true,
637 .supports_multi_bssid = true,
638
639 .sram_dump = {},
640
641 .tcl_ring_retry = false,
642 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
643 .smp2p_wow_exit = true,
644 .support_fw_mac_sequence = true,
645 .support_dual_stations = false,
646 .pdev_suspend = true,
647 },
648 {
649 .hw_rev = ATH11K_HW_IPQ5018_HW10,
650 .name = "ipq5018 hw1.0",
651 .fw = {
652 .dir = "IPQ5018/hw1.0",
653 .board_size = 256 * 1024,
654 .cal_offset = 128 * 1024,
655 },
656 .max_radios = MAX_RADIOS_5018,
657 .bdf_addr = 0x4BA00000,
658 /* hal_desc_sz and hw ops are similar to qcn9074 */
659 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
660 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
661 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
662 .credit_flow = false,
663 .max_tx_ring = 1,
664 .spectral = {
665 .fft_sz = 2,
666 .fft_pad_sz = 0,
667 .summary_pad_sz = 16,
668 .fft_hdr_len = 24,
669 .max_fft_bins = 1024,
670 },
671 .internal_sleep_clock = false,
672 .regs = &ipq5018_regs,
673 .hw_ops = &ipq5018_ops,
674 .host_ce_config = ath11k_host_ce_config_qcn9074,
675 .ce_count = CE_CNT_5018,
676 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
677 .target_ce_count = TARGET_CE_CNT_5018,
678 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
679 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
680 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
681 .ce_remap = &ath11k_ce_remap_ipq5018,
682 .rxdma1_enable = true,
683 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
684 .rx_mac_buf_ring = false,
685 .vdev_start_delay = false,
686 .htt_peer_map_v2 = true,
687 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
688 BIT(NL80211_IFTYPE_AP) |
689 BIT(NL80211_IFTYPE_MESH_POINT),
690 .supports_monitor = false,
691 .supports_sta_ps = false,
692 .supports_shadow_regs = false,
693 .fw_mem_mode = 0,
694 .num_vdevs = 16 + 1,
695 .num_peers = 512,
696 .supports_regdb = false,
697 .idle_ps = false,
698 .supports_suspend = false,
699 .hal_params = &ath11k_hw_hal_params_ipq8074,
700 .single_pdev_only = false,
701 .coldboot_cal_mm = true,
702 .coldboot_cal_ftm = true,
703 .cbcal_restart_fw = true,
704 .fix_l1ss = true,
705 .supports_dynamic_smps_6ghz = false,
706 .alloc_cacheable_memory = true,
707 .supports_rssi_stats = false,
708 .fw_wmi_diag_event = false,
709 .current_cc_support = false,
710 .dbr_debug_support = true,
711 .global_reset = false,
712 .bios_sar_capa = NULL,
713 .m3_fw_support = false,
714 .fixed_bdf_addr = true,
715 .fixed_mem_region = true,
716 .static_window_map = false,
717 .hybrid_bus_type = false,
718 .fixed_fw_mem = false,
719 .support_off_channel_tx = false,
720 .supports_multi_bssid = false,
721
722 .sram_dump = {},
723
724 .tcl_ring_retry = true,
725 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
726 .smp2p_wow_exit = false,
727 .support_fw_mac_sequence = false,
728 .support_dual_stations = false,
729 .pdev_suspend = false,
730 },
731 {
732 .name = "qca2066 hw2.1",
733 .hw_rev = ATH11K_HW_QCA2066_HW21,
734 .fw = {
735 .dir = "QCA2066/hw2.1",
736 .board_size = 256 * 1024,
737 .cal_offset = 128 * 1024,
738 },
739 .max_radios = 3,
740 .bdf_addr = 0x4B0C0000,
741 .hw_ops = &wcn6855_ops,
742 .ring_mask = &ath11k_hw_ring_mask_qca6390,
743 .internal_sleep_clock = true,
744 .regs = &wcn6855_regs,
745 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
746 .host_ce_config = ath11k_host_ce_config_qca6390,
747 .ce_count = 9,
748 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
749 .target_ce_count = 9,
750 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
751 .svc_to_ce_map_len = 14,
752 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
753 .single_pdev_only = true,
754 .rxdma1_enable = false,
755 .num_rxdma_per_pdev = 2,
756 .rx_mac_buf_ring = true,
757 .vdev_start_delay = true,
758 .htt_peer_map_v2 = false,
759
760 .spectral = {
761 .fft_sz = 0,
762 .fft_pad_sz = 0,
763 .summary_pad_sz = 0,
764 .fft_hdr_len = 0,
765 .max_fft_bins = 0,
766 .fragment_160mhz = false,
767 },
768
769 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
770 BIT(NL80211_IFTYPE_AP) |
771 BIT(NL80211_IFTYPE_P2P_DEVICE) |
772 BIT(NL80211_IFTYPE_P2P_CLIENT) |
773 BIT(NL80211_IFTYPE_P2P_GO),
774 .supports_monitor = false,
775 .full_monitor_mode = false,
776 .supports_shadow_regs = true,
777 .idle_ps = true,
778 .supports_sta_ps = true,
779 .coldboot_cal_mm = false,
780 .coldboot_cal_ftm = false,
781 .cbcal_restart_fw = false,
782 .fw_mem_mode = 0,
783 .num_vdevs = 2 + 1,
784 .num_peers = 512,
785 .supports_suspend = true,
786 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
787 .supports_regdb = true,
788 .fix_l1ss = false,
789 .credit_flow = true,
790 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
791 .hal_params = &ath11k_hw_hal_params_qca6390,
792 .supports_dynamic_smps_6ghz = false,
793 .alloc_cacheable_memory = false,
794 .supports_rssi_stats = true,
795 .fw_wmi_diag_event = true,
796 .current_cc_support = true,
797 .dbr_debug_support = false,
798 .global_reset = true,
799 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
800 .m3_fw_support = true,
801 .fixed_bdf_addr = false,
802 .fixed_mem_region = false,
803 .static_window_map = false,
804 .hybrid_bus_type = false,
805 .fixed_fw_mem = false,
806 .support_off_channel_tx = true,
807 .supports_multi_bssid = true,
808
809 .sram_dump = {
810 .start = 0x01400000,
811 .end = 0x0177ffff,
812 },
813
814 .tcl_ring_retry = true,
815 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
816 .smp2p_wow_exit = false,
817 .support_fw_mac_sequence = true,
818 .support_dual_stations = true,
819 },
820 {
821 .name = "qca6698aq hw2.1",
822 .hw_rev = ATH11K_HW_QCA6698AQ_HW21,
823 .fw = {
824 .dir = "QCA6698AQ/hw2.1",
825 .board_size = 256 * 1024,
826 .cal_offset = 128 * 1024,
827 },
828 .max_radios = 3,
829 .bdf_addr = 0x4B0C0000,
830 .hw_ops = &wcn6855_ops,
831 .ring_mask = &ath11k_hw_ring_mask_qca6390,
832 .internal_sleep_clock = true,
833 .regs = &wcn6855_regs,
834 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
835 .host_ce_config = ath11k_host_ce_config_qca6390,
836 .ce_count = 9,
837 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
838 .target_ce_count = 9,
839 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
840 .svc_to_ce_map_len = 14,
841 .single_pdev_only = true,
842 .rxdma1_enable = false,
843 .num_rxdma_per_pdev = 2,
844 .rx_mac_buf_ring = true,
845 .vdev_start_delay = true,
846 .htt_peer_map_v2 = false,
847
848 .spectral = {
849 .fft_sz = 0,
850 .fft_pad_sz = 0,
851 .summary_pad_sz = 0,
852 .fft_hdr_len = 0,
853 .max_fft_bins = 0,
854 .fragment_160mhz = false,
855 },
856
857 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
858 BIT(NL80211_IFTYPE_AP) |
859 BIT(NL80211_IFTYPE_P2P_DEVICE) |
860 BIT(NL80211_IFTYPE_P2P_CLIENT) |
861 BIT(NL80211_IFTYPE_P2P_GO),
862 .supports_monitor = false,
863 .supports_shadow_regs = true,
864 .idle_ps = true,
865 .supports_sta_ps = true,
866 .coldboot_cal_mm = false,
867 .coldboot_cal_ftm = false,
868 .cbcal_restart_fw = false,
869 .fw_mem_mode = 0,
870 .num_vdevs = 2 + 1,
871 .num_peers = 512,
872 .supports_suspend = true,
873 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
874 .supports_regdb = true,
875 .fix_l1ss = false,
876 .credit_flow = true,
877 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
878 .hal_params = &ath11k_hw_hal_params_qca6390,
879 .supports_dynamic_smps_6ghz = false,
880 .alloc_cacheable_memory = false,
881 .supports_rssi_stats = true,
882 .fw_wmi_diag_event = true,
883 .current_cc_support = true,
884 .dbr_debug_support = false,
885 .global_reset = true,
886 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
887 .m3_fw_support = true,
888 .fixed_bdf_addr = false,
889 .fixed_mem_region = false,
890 .static_window_map = false,
891 .hybrid_bus_type = false,
892 .fixed_fw_mem = false,
893 .support_off_channel_tx = true,
894 .supports_multi_bssid = true,
895
896 .sram_dump = {
897 .start = 0x01400000,
898 .end = 0x0177ffff,
899 },
900
901 .tcl_ring_retry = true,
902 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
903 .smp2p_wow_exit = false,
904 .support_fw_mac_sequence = true,
905 .support_dual_stations = true,
906 .pdev_suspend = false,
907 },
908 };
909
ath11k_core_get_single_pdev(struct ath11k_base * ab)910 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
911 {
912 WARN_ON(!ab->hw_params.single_pdev_only);
913
914 return &ab->pdevs[0];
915 }
916
ath11k_fw_stats_pdevs_free(struct list_head * head)917 void ath11k_fw_stats_pdevs_free(struct list_head *head)
918 {
919 struct ath11k_fw_stats_pdev *i, *tmp;
920
921 list_for_each_entry_safe(i, tmp, head, list) {
922 list_del(&i->list);
923 kfree(i);
924 }
925 }
926
ath11k_fw_stats_vdevs_free(struct list_head * head)927 void ath11k_fw_stats_vdevs_free(struct list_head *head)
928 {
929 struct ath11k_fw_stats_vdev *i, *tmp;
930
931 list_for_each_entry_safe(i, tmp, head, list) {
932 list_del(&i->list);
933 kfree(i);
934 }
935 }
936
ath11k_fw_stats_bcn_free(struct list_head * head)937 void ath11k_fw_stats_bcn_free(struct list_head *head)
938 {
939 struct ath11k_fw_stats_bcn *i, *tmp;
940
941 list_for_each_entry_safe(i, tmp, head, list) {
942 list_del(&i->list);
943 kfree(i);
944 }
945 }
946
ath11k_fw_stats_init(struct ath11k * ar)947 void ath11k_fw_stats_init(struct ath11k *ar)
948 {
949 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
950 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
951 INIT_LIST_HEAD(&ar->fw_stats.bcn);
952
953 init_completion(&ar->fw_stats_complete);
954 }
955
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)956 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
957 {
958 ath11k_fw_stats_pdevs_free(&stats->pdevs);
959 ath11k_fw_stats_vdevs_free(&stats->vdevs);
960 ath11k_fw_stats_bcn_free(&stats->bcn);
961 }
962
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)963 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
964 {
965 if (!ath11k_cold_boot_cal)
966 return false;
967
968 if (ath11k_ftm_mode)
969 return ab->hw_params.coldboot_cal_ftm;
970
971 else
972 return ab->hw_params.coldboot_cal_mm;
973 }
974
ath11k_core_suspend(struct ath11k_base * ab)975 int ath11k_core_suspend(struct ath11k_base *ab)
976 {
977 int ret;
978 struct ath11k_pdev *pdev;
979 struct ath11k *ar;
980
981 if (!ab->hw_params.supports_suspend)
982 return -EOPNOTSUPP;
983
984 /* so far single_pdev_only chips have supports_suspend as true
985 * and only the first pdev is valid.
986 */
987 pdev = ath11k_core_get_single_pdev(ab);
988 ar = pdev->ar;
989 if (!ar || ar->state != ATH11K_STATE_OFF)
990 return 0;
991
992 ret = ath11k_dp_rx_pktlog_stop(ab, true);
993 if (ret) {
994 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
995 ret);
996 return ret;
997 }
998
999 ret = ath11k_mac_wait_tx_complete(ar);
1000 if (ret) {
1001 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1002 return ret;
1003 }
1004
1005 ret = ath11k_wow_enable(ab);
1006 if (ret) {
1007 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
1008 return ret;
1009 }
1010
1011 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1012 if (ret) {
1013 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1014 ret);
1015 return ret;
1016 }
1017
1018 ath11k_ce_stop_shadow_timers(ab);
1019 ath11k_dp_stop_shadow_timers(ab);
1020
1021 ath11k_hif_irq_disable(ab);
1022 ath11k_hif_ce_irq_disable(ab);
1023
1024 ret = ath11k_hif_suspend(ab);
1025 if (ret) {
1026 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
1027 return ret;
1028 }
1029
1030 return 0;
1031 }
1032 EXPORT_SYMBOL(ath11k_core_suspend);
1033
ath11k_core_resume(struct ath11k_base * ab)1034 int ath11k_core_resume(struct ath11k_base *ab)
1035 {
1036 int ret;
1037 struct ath11k_pdev *pdev;
1038 struct ath11k *ar;
1039
1040 if (!ab->hw_params.supports_suspend)
1041 return -EOPNOTSUPP;
1042
1043 /* so far signle_pdev_only chips have supports_suspend as true
1044 * and only the first pdev is valid.
1045 */
1046 pdev = ath11k_core_get_single_pdev(ab);
1047 ar = pdev->ar;
1048 if (!ar || ar->state != ATH11K_STATE_OFF)
1049 return 0;
1050
1051 ret = ath11k_hif_resume(ab);
1052 if (ret) {
1053 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1054 return ret;
1055 }
1056
1057 ath11k_hif_ce_irq_enable(ab);
1058 ath11k_hif_irq_enable(ab);
1059
1060 ret = ath11k_dp_rx_pktlog_start(ab);
1061 if (ret) {
1062 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1063 ret);
1064 return ret;
1065 }
1066
1067 ret = ath11k_wow_wakeup(ab);
1068 if (ret) {
1069 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1070 return ret;
1071 }
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL(ath11k_core_resume);
1076
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1077 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1078 {
1079 struct ath11k_base *ab = data;
1080 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1081 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1082 ssize_t copied;
1083 size_t len;
1084 int i;
1085
1086 if (ab->qmi.target.bdf_ext[0] != '\0')
1087 return;
1088
1089 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1090 return;
1091
1092 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1093 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1094 "wrong smbios bdf ext type length (%d).\n",
1095 hdr->length);
1096 return;
1097 }
1098
1099 spin_lock_bh(&ab->base_lock);
1100
1101 switch (smbios->country_code_flag) {
1102 case ATH11K_SMBIOS_CC_ISO:
1103 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1104 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1105 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1106 ab->new_alpha2[0], ab->new_alpha2[1]);
1107 break;
1108 case ATH11K_SMBIOS_CC_WW:
1109 ab->new_alpha2[0] = '0';
1110 ab->new_alpha2[1] = '0';
1111 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1112 break;
1113 default:
1114 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1115 smbios->country_code_flag);
1116 break;
1117 }
1118
1119 spin_unlock_bh(&ab->base_lock);
1120
1121 if (!smbios->bdf_enabled) {
1122 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1123 return;
1124 }
1125
1126 /* Only one string exists (per spec) */
1127 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1128 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1129 "bdf variant magic does not match.\n");
1130 return;
1131 }
1132
1133 len = min_t(size_t,
1134 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1135 for (i = 0; i < len; i++) {
1136 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1137 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1138 "bdf variant name contains non ascii chars.\n");
1139 return;
1140 }
1141 }
1142
1143 /* Copy extension name without magic prefix */
1144 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1145 sizeof(ab->qmi.target.bdf_ext));
1146 if (copied < 0) {
1147 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1148 "bdf variant string is longer than the buffer can accommodate\n");
1149 return;
1150 }
1151
1152 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1153 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1154 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1155 }
1156
ath11k_core_check_smbios(struct ath11k_base * ab)1157 int ath11k_core_check_smbios(struct ath11k_base *ab)
1158 {
1159 ab->qmi.target.bdf_ext[0] = '\0';
1160 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1161
1162 if (ab->qmi.target.bdf_ext[0] == '\0')
1163 return -ENODATA;
1164
1165 return 0;
1166 }
1167
ath11k_core_check_dt(struct ath11k_base * ab)1168 int ath11k_core_check_dt(struct ath11k_base *ab)
1169 {
1170 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1171 const char *variant = NULL;
1172 struct device_node *node;
1173
1174 node = ab->dev->of_node;
1175 if (!node)
1176 return -ENOENT;
1177
1178 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1179 &variant);
1180 if (!variant)
1181 return -ENODATA;
1182
1183 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1184 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1185 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1186 variant);
1187
1188 return 0;
1189 }
1190
1191 enum ath11k_bdf_name_type {
1192 ATH11K_BDF_NAME_FULL,
1193 ATH11K_BDF_NAME_BUS_NAME,
1194 ATH11K_BDF_NAME_CHIP_ID,
1195 };
1196
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1197 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1198 size_t name_len, bool with_variant,
1199 enum ath11k_bdf_name_type name_type)
1200 {
1201 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1202 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1203
1204 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1205 scnprintf(variant, sizeof(variant), ",variant=%s",
1206 ab->qmi.target.bdf_ext);
1207
1208 switch (ab->id.bdf_search) {
1209 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1210 switch (name_type) {
1211 case ATH11K_BDF_NAME_FULL:
1212 scnprintf(name, name_len,
1213 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1214 ath11k_bus_str(ab->hif.bus),
1215 ab->id.vendor, ab->id.device,
1216 ab->id.subsystem_vendor,
1217 ab->id.subsystem_device,
1218 ab->qmi.target.chip_id,
1219 ab->qmi.target.board_id,
1220 variant);
1221 break;
1222 case ATH11K_BDF_NAME_BUS_NAME:
1223 scnprintf(name, name_len,
1224 "bus=%s",
1225 ath11k_bus_str(ab->hif.bus));
1226 break;
1227 case ATH11K_BDF_NAME_CHIP_ID:
1228 scnprintf(name, name_len,
1229 "bus=%s,qmi-chip-id=%d",
1230 ath11k_bus_str(ab->hif.bus),
1231 ab->qmi.target.chip_id);
1232 break;
1233 }
1234 break;
1235 default:
1236 scnprintf(name, name_len,
1237 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1238 ath11k_bus_str(ab->hif.bus),
1239 ab->qmi.target.chip_id,
1240 ab->qmi.target.board_id, variant);
1241 break;
1242 }
1243
1244 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1245
1246 return 0;
1247 }
1248
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1249 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1250 size_t name_len)
1251 {
1252 return __ath11k_core_create_board_name(ab, name, name_len, true,
1253 ATH11K_BDF_NAME_FULL);
1254 }
1255
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1256 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1257 size_t name_len)
1258 {
1259 return __ath11k_core_create_board_name(ab, name, name_len, false,
1260 ATH11K_BDF_NAME_FULL);
1261 }
1262
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1263 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1264 size_t name_len)
1265 {
1266 return __ath11k_core_create_board_name(ab, name, name_len, false,
1267 ATH11K_BDF_NAME_BUS_NAME);
1268 }
1269
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1270 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1271 size_t name_len)
1272 {
1273 return __ath11k_core_create_board_name(ab, name, name_len, false,
1274 ATH11K_BDF_NAME_CHIP_ID);
1275 }
1276
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1277 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1278 const char *file)
1279 {
1280 const struct firmware *fw;
1281 char path[100];
1282 int ret;
1283
1284 if (file == NULL)
1285 return ERR_PTR(-ENOENT);
1286
1287 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1288
1289 ret = firmware_request_nowarn(&fw, path, ab->dev);
1290 if (ret)
1291 return ERR_PTR(ret);
1292
1293 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1294 path, fw->size);
1295
1296 return fw;
1297 }
1298
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1299 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1300 {
1301 if (!IS_ERR(bd->fw))
1302 release_firmware(bd->fw);
1303
1304 memset(bd, 0, sizeof(*bd));
1305 }
1306
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1307 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1308 struct ath11k_board_data *bd,
1309 const void *buf, size_t buf_len,
1310 const char *boardname,
1311 int ie_id,
1312 int name_id,
1313 int data_id)
1314 {
1315 const struct ath11k_fw_ie *hdr;
1316 bool name_match_found;
1317 int ret, board_ie_id;
1318 size_t board_ie_len;
1319 const void *board_ie_data;
1320
1321 name_match_found = false;
1322
1323 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1324 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1325 hdr = buf;
1326 board_ie_id = le32_to_cpu(hdr->id);
1327 board_ie_len = le32_to_cpu(hdr->len);
1328 board_ie_data = hdr->data;
1329
1330 buf_len -= sizeof(*hdr);
1331 buf += sizeof(*hdr);
1332
1333 if (buf_len < ALIGN(board_ie_len, 4)) {
1334 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1335 ath11k_bd_ie_type_str(ie_id),
1336 buf_len, ALIGN(board_ie_len, 4));
1337 ret = -EINVAL;
1338 goto out;
1339 }
1340
1341 if (board_ie_id == name_id) {
1342 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1343 board_ie_data, board_ie_len);
1344
1345 if (board_ie_len != strlen(boardname))
1346 goto next;
1347
1348 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1349 if (ret)
1350 goto next;
1351
1352 name_match_found = true;
1353 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1354 "found match %s for name '%s'",
1355 ath11k_bd_ie_type_str(ie_id),
1356 boardname);
1357 } else if (board_ie_id == data_id) {
1358 if (!name_match_found)
1359 /* no match found */
1360 goto next;
1361
1362 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1363 "found %s for '%s'",
1364 ath11k_bd_ie_type_str(ie_id),
1365 boardname);
1366
1367 bd->data = board_ie_data;
1368 bd->len = board_ie_len;
1369
1370 ret = 0;
1371 goto out;
1372 } else {
1373 ath11k_warn(ab, "unknown %s id found: %d\n",
1374 ath11k_bd_ie_type_str(ie_id),
1375 board_ie_id);
1376 }
1377 next:
1378 /* jump over the padding */
1379 board_ie_len = ALIGN(board_ie_len, 4);
1380
1381 buf_len -= board_ie_len;
1382 buf += board_ie_len;
1383 }
1384
1385 /* no match found */
1386 ret = -ENOENT;
1387
1388 out:
1389 return ret;
1390 }
1391
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1392 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1393 struct ath11k_board_data *bd,
1394 const char *boardname,
1395 int ie_id_match,
1396 int name_id,
1397 int data_id)
1398 {
1399 size_t len, magic_len;
1400 const u8 *data;
1401 char *filename, filepath[100];
1402 size_t ie_len;
1403 struct ath11k_fw_ie *hdr;
1404 int ret, ie_id;
1405
1406 filename = ATH11K_BOARD_API2_FILE;
1407
1408 if (!bd->fw)
1409 bd->fw = ath11k_core_firmware_request(ab, filename);
1410
1411 if (IS_ERR(bd->fw))
1412 return PTR_ERR(bd->fw);
1413
1414 data = bd->fw->data;
1415 len = bd->fw->size;
1416
1417 ath11k_core_create_firmware_path(ab, filename,
1418 filepath, sizeof(filepath));
1419
1420 /* magic has extra null byte padded */
1421 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1422 if (len < magic_len) {
1423 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1424 filepath, len);
1425 ret = -EINVAL;
1426 goto err;
1427 }
1428
1429 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1430 ath11k_err(ab, "found invalid board magic\n");
1431 ret = -EINVAL;
1432 goto err;
1433 }
1434
1435 /* magic is padded to 4 bytes */
1436 magic_len = ALIGN(magic_len, 4);
1437 if (len < magic_len) {
1438 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1439 filepath, len);
1440 ret = -EINVAL;
1441 goto err;
1442 }
1443
1444 data += magic_len;
1445 len -= magic_len;
1446
1447 while (len > sizeof(struct ath11k_fw_ie)) {
1448 hdr = (struct ath11k_fw_ie *)data;
1449 ie_id = le32_to_cpu(hdr->id);
1450 ie_len = le32_to_cpu(hdr->len);
1451
1452 len -= sizeof(*hdr);
1453 data = hdr->data;
1454
1455 if (len < ALIGN(ie_len, 4)) {
1456 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1457 ie_id, ie_len, len);
1458 ret = -EINVAL;
1459 goto err;
1460 }
1461
1462 if (ie_id == ie_id_match) {
1463 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1464 ie_len,
1465 boardname,
1466 ie_id_match,
1467 name_id,
1468 data_id);
1469 if (ret == -ENOENT)
1470 /* no match found, continue */
1471 goto next;
1472 else if (ret)
1473 /* there was an error, bail out */
1474 goto err;
1475 /* either found or error, so stop searching */
1476 goto out;
1477 }
1478 next:
1479 /* jump over the padding */
1480 ie_len = ALIGN(ie_len, 4);
1481
1482 len -= ie_len;
1483 data += ie_len;
1484 }
1485
1486 out:
1487 if (!bd->data || !bd->len) {
1488 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1489 "failed to fetch %s for %s from %s\n",
1490 ath11k_bd_ie_type_str(ie_id_match),
1491 boardname, filepath);
1492 ret = -ENODATA;
1493 goto err;
1494 }
1495
1496 return 0;
1497
1498 err:
1499 ath11k_core_free_bdf(ab, bd);
1500 return ret;
1501 }
1502
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1503 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1504 struct ath11k_board_data *bd,
1505 const char *name)
1506 {
1507 bd->fw = ath11k_core_firmware_request(ab, name);
1508
1509 if (IS_ERR(bd->fw))
1510 return PTR_ERR(bd->fw);
1511
1512 bd->data = bd->fw->data;
1513 bd->len = bd->fw->size;
1514
1515 return 0;
1516 }
1517
1518 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1519 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1520 {
1521 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1522 char *filename, filepath[100];
1523 int bd_api;
1524 int ret = 0;
1525
1526 filename = ATH11K_BOARD_API2_FILE;
1527 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1528 if (!boardname) {
1529 ret = -ENOMEM;
1530 goto exit;
1531 }
1532
1533 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1534 if (ret) {
1535 ath11k_err(ab, "failed to create board name: %d", ret);
1536 goto exit;
1537 }
1538
1539 bd_api = 2;
1540 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1541 ATH11K_BD_IE_BOARD,
1542 ATH11K_BD_IE_BOARD_NAME,
1543 ATH11K_BD_IE_BOARD_DATA);
1544 if (!ret)
1545 goto exit;
1546
1547 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1548 if (!fallback_boardname) {
1549 ret = -ENOMEM;
1550 goto exit;
1551 }
1552
1553 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1554 BOARD_NAME_SIZE);
1555 if (ret) {
1556 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1557 goto exit;
1558 }
1559
1560 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1561 ATH11K_BD_IE_BOARD,
1562 ATH11K_BD_IE_BOARD_NAME,
1563 ATH11K_BD_IE_BOARD_DATA);
1564 if (!ret)
1565 goto exit;
1566
1567 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1568 if (!chip_id_boardname) {
1569 ret = -ENOMEM;
1570 goto exit;
1571 }
1572
1573 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1574 BOARD_NAME_SIZE);
1575 if (ret) {
1576 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1577 goto exit;
1578 }
1579
1580 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1581 ATH11K_BD_IE_BOARD,
1582 ATH11K_BD_IE_BOARD_NAME,
1583 ATH11K_BD_IE_BOARD_DATA);
1584
1585 if (!ret)
1586 goto exit;
1587
1588 bd_api = 1;
1589 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1590 if (ret) {
1591 ath11k_core_create_firmware_path(ab, filename,
1592 filepath, sizeof(filepath));
1593 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1594 boardname, filepath);
1595 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1596 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1597 fallback_boardname, filepath);
1598
1599 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1600 chip_id_boardname, filepath);
1601
1602 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1603 ab->hw_params.fw.dir);
1604 }
1605
1606 exit:
1607 kfree(boardname);
1608 kfree(fallback_boardname);
1609 kfree(chip_id_boardname);
1610
1611 if (!ret)
1612 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1613
1614 return ret;
1615 }
1616
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1617 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1618 {
1619 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1620 int ret;
1621
1622 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1623 if (ret) {
1624 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1625 "failed to create board name for regdb: %d", ret);
1626 goto exit;
1627 }
1628
1629 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1630 ATH11K_BD_IE_REGDB,
1631 ATH11K_BD_IE_REGDB_NAME,
1632 ATH11K_BD_IE_REGDB_DATA);
1633 if (!ret)
1634 goto exit;
1635
1636 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1637 BOARD_NAME_SIZE);
1638 if (ret) {
1639 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1640 "failed to create default board name for regdb: %d", ret);
1641 goto exit;
1642 }
1643
1644 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1645 ATH11K_BD_IE_REGDB,
1646 ATH11K_BD_IE_REGDB_NAME,
1647 ATH11K_BD_IE_REGDB_DATA);
1648 if (!ret)
1649 goto exit;
1650
1651 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1652 if (ret)
1653 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1654 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1655
1656 exit:
1657 if (!ret)
1658 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1659
1660 return ret;
1661 }
1662
ath11k_core_stop(struct ath11k_base * ab)1663 static void ath11k_core_stop(struct ath11k_base *ab)
1664 {
1665 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1666 ath11k_qmi_firmware_stop(ab);
1667
1668 ath11k_hif_stop(ab);
1669 ath11k_wmi_detach(ab);
1670 ath11k_dp_pdev_reo_cleanup(ab);
1671
1672 /* De-Init of components as needed */
1673 }
1674
ath11k_core_soc_create(struct ath11k_base * ab)1675 static int ath11k_core_soc_create(struct ath11k_base *ab)
1676 {
1677 int ret;
1678
1679 if (ath11k_ftm_mode) {
1680 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1681 ath11k_info(ab, "Booting in factory test mode\n");
1682 }
1683
1684 ret = ath11k_qmi_init_service(ab);
1685 if (ret) {
1686 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1687 return ret;
1688 }
1689
1690 ret = ath11k_debugfs_soc_create(ab);
1691 if (ret) {
1692 ath11k_err(ab, "failed to create ath11k debugfs\n");
1693 goto err_qmi_deinit;
1694 }
1695
1696 ret = ath11k_hif_power_up(ab);
1697 if (ret) {
1698 ath11k_err(ab, "failed to power up :%d\n", ret);
1699 goto err_debugfs_reg;
1700 }
1701
1702 return 0;
1703
1704 err_debugfs_reg:
1705 ath11k_debugfs_soc_destroy(ab);
1706 err_qmi_deinit:
1707 ath11k_qmi_deinit_service(ab);
1708 return ret;
1709 }
1710
ath11k_core_soc_destroy(struct ath11k_base * ab)1711 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1712 {
1713 ath11k_debugfs_soc_destroy(ab);
1714 ath11k_dp_free(ab);
1715 ath11k_reg_free(ab);
1716 ath11k_qmi_deinit_service(ab);
1717 }
1718
ath11k_core_pdev_create(struct ath11k_base * ab)1719 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1720 {
1721 int ret;
1722
1723 ret = ath11k_debugfs_pdev_create(ab);
1724 if (ret) {
1725 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1726 return ret;
1727 }
1728
1729 ret = ath11k_dp_pdev_alloc(ab);
1730 if (ret) {
1731 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1732 goto err_pdev_debug;
1733 }
1734
1735 ret = ath11k_mac_register(ab);
1736 if (ret) {
1737 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1738 goto err_dp_pdev_free;
1739 }
1740
1741 ret = ath11k_thermal_register(ab);
1742 if (ret) {
1743 ath11k_err(ab, "could not register thermal device: %d\n",
1744 ret);
1745 goto err_mac_unregister;
1746 }
1747
1748 ret = ath11k_spectral_init(ab);
1749 if (ret) {
1750 ath11k_err(ab, "failed to init spectral %d\n", ret);
1751 goto err_thermal_unregister;
1752 }
1753
1754 return 0;
1755
1756 err_thermal_unregister:
1757 ath11k_thermal_unregister(ab);
1758 err_mac_unregister:
1759 ath11k_mac_unregister(ab);
1760 err_dp_pdev_free:
1761 ath11k_dp_pdev_free(ab);
1762 err_pdev_debug:
1763 ath11k_debugfs_pdev_destroy(ab);
1764
1765 return ret;
1766 }
1767
ath11k_core_pdev_suspend_target(struct ath11k_base * ab)1768 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
1769 {
1770 struct ath11k *ar;
1771 struct ath11k_pdev *pdev;
1772 unsigned long time_left;
1773 int ret;
1774 int i;
1775
1776 if (!ab->hw_params.pdev_suspend)
1777 return;
1778
1779 for (i = 0; i < ab->num_radios; i++) {
1780 pdev = &ab->pdevs[i];
1781 ar = pdev->ar;
1782
1783 reinit_completion(&ab->htc_suspend);
1784
1785 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1786 pdev->pdev_id);
1787 if (ret) {
1788 ath11k_warn(ab, "could not suspend target :%d\n", ret);
1789 /* pointless to try other pdevs */
1790 return;
1791 }
1792
1793 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ);
1794
1795 if (!time_left) {
1796 ath11k_warn(ab, "suspend timed out - target pause event never came\n");
1797 /* pointless to try other pdevs */
1798 return;
1799 }
1800 }
1801 }
1802
ath11k_core_pdev_destroy(struct ath11k_base * ab)1803 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1804 {
1805 ath11k_spectral_deinit(ab);
1806 ath11k_thermal_unregister(ab);
1807 ath11k_mac_unregister(ab);
1808 ath11k_core_pdev_suspend_target(ab);
1809 ath11k_hif_irq_disable(ab);
1810 ath11k_dp_pdev_free(ab);
1811 ath11k_debugfs_pdev_destroy(ab);
1812 }
1813
ath11k_core_start(struct ath11k_base * ab)1814 static int ath11k_core_start(struct ath11k_base *ab)
1815 {
1816 int ret;
1817
1818 ret = ath11k_wmi_attach(ab);
1819 if (ret) {
1820 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1821 return ret;
1822 }
1823
1824 ret = ath11k_htc_init(ab);
1825 if (ret) {
1826 ath11k_err(ab, "failed to init htc: %d\n", ret);
1827 goto err_wmi_detach;
1828 }
1829
1830 ret = ath11k_hif_start(ab);
1831 if (ret) {
1832 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1833 goto err_wmi_detach;
1834 }
1835
1836 ret = ath11k_htc_wait_target(&ab->htc);
1837 if (ret) {
1838 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1839 goto err_hif_stop;
1840 }
1841
1842 ret = ath11k_dp_htt_connect(&ab->dp);
1843 if (ret) {
1844 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1845 goto err_hif_stop;
1846 }
1847
1848 ret = ath11k_wmi_connect(ab);
1849 if (ret) {
1850 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1851 goto err_hif_stop;
1852 }
1853
1854 ret = ath11k_htc_start(&ab->htc);
1855 if (ret) {
1856 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1857 goto err_hif_stop;
1858 }
1859
1860 ret = ath11k_wmi_wait_for_service_ready(ab);
1861 if (ret) {
1862 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1863 ret);
1864 goto err_hif_stop;
1865 }
1866
1867 ret = ath11k_mac_allocate(ab);
1868 if (ret) {
1869 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1870 ret);
1871 goto err_hif_stop;
1872 }
1873
1874 ath11k_dp_pdev_pre_alloc(ab);
1875
1876 ret = ath11k_dp_pdev_reo_setup(ab);
1877 if (ret) {
1878 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1879 goto err_mac_destroy;
1880 }
1881
1882 ret = ath11k_wmi_cmd_init(ab);
1883 if (ret) {
1884 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1885 goto err_reo_cleanup;
1886 }
1887
1888 ret = ath11k_wmi_wait_for_unified_ready(ab);
1889 if (ret) {
1890 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1891 ret);
1892 goto err_reo_cleanup;
1893 }
1894
1895 /* put hardware to DBS mode */
1896 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
1897 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1898 if (ret) {
1899 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1900 goto err_hif_stop;
1901 }
1902 }
1903
1904 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1905 if (ret) {
1906 ath11k_err(ab, "failed to send htt version request message: %d\n",
1907 ret);
1908 goto err_reo_cleanup;
1909 }
1910
1911 return 0;
1912
1913 err_reo_cleanup:
1914 ath11k_dp_pdev_reo_cleanup(ab);
1915 err_mac_destroy:
1916 ath11k_mac_destroy(ab);
1917 err_hif_stop:
1918 ath11k_hif_stop(ab);
1919 err_wmi_detach:
1920 ath11k_wmi_detach(ab);
1921
1922 return ret;
1923 }
1924
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1925 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1926 enum ath11k_firmware_mode mode)
1927 {
1928 int ret;
1929
1930 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1931 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1932
1933 ret = ath11k_qmi_firmware_start(ab, mode);
1934 if (ret) {
1935 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1936 return ret;
1937 }
1938
1939 return ret;
1940 }
1941
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1942 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1943 {
1944 int ret;
1945
1946 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1947 if (ret) {
1948 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1949 return ret;
1950 }
1951
1952 ret = ath11k_ce_init_pipes(ab);
1953 if (ret) {
1954 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1955 goto err_firmware_stop;
1956 }
1957
1958 ret = ath11k_dp_alloc(ab);
1959 if (ret) {
1960 ath11k_err(ab, "failed to init DP: %d\n", ret);
1961 goto err_firmware_stop;
1962 }
1963
1964 switch (ath11k_crypto_mode) {
1965 case ATH11K_CRYPT_MODE_SW:
1966 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1967 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1968 break;
1969 case ATH11K_CRYPT_MODE_HW:
1970 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1971 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1972 break;
1973 default:
1974 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1975 return -EINVAL;
1976 }
1977
1978 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1979 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1980
1981 mutex_lock(&ab->core_lock);
1982 ret = ath11k_core_start(ab);
1983 if (ret) {
1984 ath11k_err(ab, "failed to start core: %d\n", ret);
1985 goto err_dp_free;
1986 }
1987
1988 ret = ath11k_core_pdev_create(ab);
1989 if (ret) {
1990 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1991 goto err_core_stop;
1992 }
1993 ath11k_hif_irq_enable(ab);
1994 mutex_unlock(&ab->core_lock);
1995
1996 return 0;
1997
1998 err_core_stop:
1999 ath11k_core_stop(ab);
2000 ath11k_mac_destroy(ab);
2001 err_dp_free:
2002 ath11k_dp_free(ab);
2003 mutex_unlock(&ab->core_lock);
2004 err_firmware_stop:
2005 ath11k_qmi_firmware_stop(ab);
2006
2007 return ret;
2008 }
2009
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)2010 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2011 {
2012 int ret;
2013
2014 mutex_lock(&ab->core_lock);
2015 ath11k_thermal_unregister(ab);
2016 ath11k_dp_pdev_free(ab);
2017 ath11k_spectral_deinit(ab);
2018 ath11k_ce_cleanup_pipes(ab);
2019 ath11k_wmi_detach(ab);
2020 ath11k_dp_pdev_reo_cleanup(ab);
2021 mutex_unlock(&ab->core_lock);
2022
2023 ath11k_dp_free(ab);
2024 ath11k_hal_srng_deinit(ab);
2025
2026 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2027
2028 ret = ath11k_hal_srng_init(ab);
2029 if (ret)
2030 return ret;
2031
2032 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
2033
2034 ret = ath11k_core_qmi_firmware_ready(ab);
2035 if (ret)
2036 goto err_hal_srng_deinit;
2037
2038 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
2039
2040 return 0;
2041
2042 err_hal_srng_deinit:
2043 ath11k_hal_srng_deinit(ab);
2044 return ret;
2045 }
2046
ath11k_core_halt(struct ath11k * ar)2047 void ath11k_core_halt(struct ath11k *ar)
2048 {
2049 struct ath11k_base *ab = ar->ab;
2050
2051 lockdep_assert_held(&ar->conf_mutex);
2052
2053 ar->num_created_vdevs = 0;
2054 ar->allocated_vdev_map = 0;
2055
2056 ath11k_mac_scan_finish(ar);
2057 ath11k_mac_peer_cleanup_all(ar);
2058 cancel_delayed_work_sync(&ar->scan.timeout);
2059 cancel_work_sync(&ar->channel_update_work);
2060 cancel_work_sync(&ar->regd_update_work);
2061 cancel_work_sync(&ab->update_11d_work);
2062
2063 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2064 synchronize_rcu();
2065 INIT_LIST_HEAD(&ar->arvifs);
2066 idr_init(&ar->txmgmt_idr);
2067 }
2068
ath11k_update_11d(struct work_struct * work)2069 static void ath11k_update_11d(struct work_struct *work)
2070 {
2071 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2072 struct ath11k *ar;
2073 struct ath11k_pdev *pdev;
2074 int ret, i;
2075
2076 for (i = 0; i < ab->num_radios; i++) {
2077 pdev = &ab->pdevs[i];
2078 ar = pdev->ar;
2079
2080 spin_lock_bh(&ab->base_lock);
2081 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2082 spin_unlock_bh(&ab->base_lock);
2083
2084 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2085 ar->alpha2[0], ar->alpha2[1], i);
2086
2087 ret = ath11k_reg_set_cc(ar);
2088 if (ret)
2089 ath11k_warn(ar->ab,
2090 "pdev id %d failed set current country code: %d\n",
2091 i, ret);
2092 }
2093 }
2094
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2095 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2096 {
2097 struct ath11k *ar;
2098 struct ath11k_pdev *pdev;
2099 int i;
2100
2101 spin_lock_bh(&ab->base_lock);
2102 ab->stats.fw_crash_counter++;
2103 spin_unlock_bh(&ab->base_lock);
2104
2105 for (i = 0; i < ab->num_radios; i++) {
2106 pdev = &ab->pdevs[i];
2107 ar = pdev->ar;
2108 if (!ar || ar->state == ATH11K_STATE_OFF ||
2109 ar->state == ATH11K_STATE_FTM)
2110 continue;
2111
2112 ieee80211_stop_queues(ar->hw);
2113 ath11k_mac_drain_tx(ar);
2114 ar->state_11d = ATH11K_11D_IDLE;
2115 complete(&ar->completed_11d_scan);
2116 complete(&ar->scan.started);
2117 complete_all(&ar->scan.completed);
2118 complete(&ar->scan.on_channel);
2119 complete(&ar->peer_assoc_done);
2120 complete(&ar->peer_delete_done);
2121 complete(&ar->install_key_done);
2122 complete(&ar->vdev_setup_done);
2123 complete(&ar->vdev_delete_done);
2124 complete(&ar->bss_survey_done);
2125 complete(&ar->thermal.wmi_sync);
2126
2127 wake_up(&ar->dp.tx_empty_waitq);
2128 idr_for_each(&ar->txmgmt_idr,
2129 ath11k_mac_tx_mgmt_pending_free, ar);
2130 idr_destroy(&ar->txmgmt_idr);
2131 wake_up(&ar->txmgmt_empty_waitq);
2132
2133 ar->monitor_vdev_id = -1;
2134 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2135 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2136 }
2137
2138 wake_up(&ab->wmi_ab.tx_credits_wq);
2139 wake_up(&ab->peer_mapping_wq);
2140
2141 reinit_completion(&ab->driver_recovery);
2142 }
2143
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2144 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2145 {
2146 struct ath11k *ar;
2147 struct ath11k_pdev *pdev;
2148 int i;
2149
2150 for (i = 0; i < ab->num_radios; i++) {
2151 pdev = &ab->pdevs[i];
2152 ar = pdev->ar;
2153 if (!ar || ar->state == ATH11K_STATE_OFF)
2154 continue;
2155
2156 mutex_lock(&ar->conf_mutex);
2157
2158 switch (ar->state) {
2159 case ATH11K_STATE_ON:
2160 ar->state = ATH11K_STATE_RESTARTING;
2161 ath11k_core_halt(ar);
2162 ieee80211_restart_hw(ar->hw);
2163 break;
2164 case ATH11K_STATE_OFF:
2165 ath11k_warn(ab,
2166 "cannot restart radio %d that hasn't been started\n",
2167 i);
2168 break;
2169 case ATH11K_STATE_RESTARTING:
2170 break;
2171 case ATH11K_STATE_RESTARTED:
2172 ar->state = ATH11K_STATE_WEDGED;
2173 fallthrough;
2174 case ATH11K_STATE_WEDGED:
2175 ath11k_warn(ab,
2176 "device is wedged, will not restart radio %d\n", i);
2177 break;
2178 case ATH11K_STATE_FTM:
2179 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2180 "fw mode reset done radio %d\n", i);
2181 break;
2182 }
2183
2184 mutex_unlock(&ar->conf_mutex);
2185 }
2186 complete(&ab->driver_recovery);
2187 }
2188
ath11k_core_restart(struct work_struct * work)2189 static void ath11k_core_restart(struct work_struct *work)
2190 {
2191 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2192 int ret;
2193
2194 ret = ath11k_core_reconfigure_on_crash(ab);
2195 if (ret) {
2196 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2197 return;
2198 }
2199
2200 if (ab->is_reset)
2201 complete_all(&ab->reconfigure_complete);
2202
2203 if (!ab->is_reset)
2204 ath11k_core_post_reconfigure_recovery(ab);
2205 }
2206
ath11k_core_reset(struct work_struct * work)2207 static void ath11k_core_reset(struct work_struct *work)
2208 {
2209 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2210 int reset_count, fail_cont_count;
2211 long time_left;
2212
2213 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2214 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2215 return;
2216 }
2217
2218 /* Sometimes the recovery will fail and then the next all recovery fail,
2219 * this is to avoid infinite recovery since it can not recovery success.
2220 */
2221 fail_cont_count = atomic_read(&ab->fail_cont_count);
2222
2223 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2224 return;
2225
2226 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2227 time_before(jiffies, ab->reset_fail_timeout))
2228 return;
2229
2230 reset_count = atomic_inc_return(&ab->reset_count);
2231
2232 if (reset_count > 1) {
2233 /* Sometimes it happened another reset worker before the previous one
2234 * completed, then the second reset worker will destroy the previous one,
2235 * thus below is to avoid that.
2236 */
2237 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2238
2239 reinit_completion(&ab->reset_complete);
2240 time_left = wait_for_completion_timeout(&ab->reset_complete,
2241 ATH11K_RESET_TIMEOUT_HZ);
2242
2243 if (time_left) {
2244 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2245 atomic_dec(&ab->reset_count);
2246 return;
2247 }
2248
2249 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2250 /* Record the continuous recovery fail count when recovery failed*/
2251 atomic_inc(&ab->fail_cont_count);
2252 }
2253
2254 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2255
2256 ab->is_reset = true;
2257 atomic_set(&ab->recovery_count, 0);
2258 reinit_completion(&ab->recovery_start);
2259 atomic_set(&ab->recovery_start_count, 0);
2260
2261 ath11k_core_pre_reconfigure_recovery(ab);
2262
2263 reinit_completion(&ab->reconfigure_complete);
2264 ath11k_core_post_reconfigure_recovery(ab);
2265
2266 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2267
2268 time_left = wait_for_completion_timeout(&ab->recovery_start,
2269 ATH11K_RECOVER_START_TIMEOUT_HZ);
2270
2271 ath11k_hif_irq_disable(ab);
2272 ath11k_hif_ce_irq_disable(ab);
2273
2274 ath11k_hif_power_down(ab);
2275 ath11k_hif_power_up(ab);
2276
2277 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2278 }
2279
ath11k_init_hw_params(struct ath11k_base * ab)2280 static int ath11k_init_hw_params(struct ath11k_base *ab)
2281 {
2282 const struct ath11k_hw_params *hw_params = NULL;
2283 int i;
2284
2285 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2286 hw_params = &ath11k_hw_params[i];
2287
2288 if (hw_params->hw_rev == ab->hw_rev)
2289 break;
2290 }
2291
2292 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2293 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2294 return -EINVAL;
2295 }
2296
2297 ab->hw_params = *hw_params;
2298
2299 ath11k_info(ab, "%s\n", ab->hw_params.name);
2300
2301 return 0;
2302 }
2303
ath11k_core_pre_init(struct ath11k_base * ab)2304 int ath11k_core_pre_init(struct ath11k_base *ab)
2305 {
2306 int ret;
2307
2308 ret = ath11k_init_hw_params(ab);
2309 if (ret) {
2310 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2311 return ret;
2312 }
2313
2314 ret = ath11k_fw_pre_init(ab);
2315 if (ret) {
2316 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2317 return ret;
2318 }
2319
2320 return 0;
2321 }
2322 EXPORT_SYMBOL(ath11k_core_pre_init);
2323
ath11k_core_init(struct ath11k_base * ab)2324 int ath11k_core_init(struct ath11k_base *ab)
2325 {
2326 int ret;
2327
2328 ret = ath11k_core_soc_create(ab);
2329 if (ret) {
2330 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2331 return ret;
2332 }
2333
2334 return 0;
2335 }
2336 EXPORT_SYMBOL(ath11k_core_init);
2337
ath11k_core_deinit(struct ath11k_base * ab)2338 void ath11k_core_deinit(struct ath11k_base *ab)
2339 {
2340 mutex_lock(&ab->core_lock);
2341
2342 ath11k_core_pdev_destroy(ab);
2343 ath11k_core_stop(ab);
2344
2345 mutex_unlock(&ab->core_lock);
2346
2347 ath11k_hif_power_down(ab);
2348 ath11k_mac_destroy(ab);
2349 ath11k_core_soc_destroy(ab);
2350 }
2351 EXPORT_SYMBOL(ath11k_core_deinit);
2352
ath11k_core_free(struct ath11k_base * ab)2353 void ath11k_core_free(struct ath11k_base *ab)
2354 {
2355 destroy_workqueue(ab->workqueue_aux);
2356 destroy_workqueue(ab->workqueue);
2357
2358 kfree(ab);
2359 }
2360 EXPORT_SYMBOL(ath11k_core_free);
2361
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2362 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2363 enum ath11k_bus bus)
2364 {
2365 struct ath11k_base *ab;
2366
2367 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2368 if (!ab)
2369 return NULL;
2370
2371 init_completion(&ab->driver_recovery);
2372
2373 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2374 if (!ab->workqueue)
2375 goto err_sc_free;
2376
2377 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2378 if (!ab->workqueue_aux)
2379 goto err_free_wq;
2380
2381 mutex_init(&ab->core_lock);
2382 mutex_init(&ab->tbl_mtx_lock);
2383 spin_lock_init(&ab->base_lock);
2384 mutex_init(&ab->vdev_id_11d_lock);
2385 init_completion(&ab->reset_complete);
2386 init_completion(&ab->reconfigure_complete);
2387 init_completion(&ab->recovery_start);
2388
2389 INIT_LIST_HEAD(&ab->peers);
2390 init_waitqueue_head(&ab->peer_mapping_wq);
2391 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2392 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2393 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2394 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2395 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2396 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2397 init_completion(&ab->htc_suspend);
2398 init_completion(&ab->wow.wakeup_completed);
2399
2400 ab->dev = dev;
2401 ab->hif.bus = bus;
2402
2403 return ab;
2404
2405 err_free_wq:
2406 destroy_workqueue(ab->workqueue);
2407 err_sc_free:
2408 kfree(ab);
2409 return NULL;
2410 }
2411 EXPORT_SYMBOL(ath11k_core_alloc);
2412
2413 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2414 MODULE_LICENSE("Dual BSD/GPL");
2415