1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <[email protected]>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10 #include <linux/bitops.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16
17 #include "realtek.h"
18
19 #define RTL821x_PHYSR 0x11
20 #define RTL821x_PHYSR_DUPLEX BIT(13)
21 #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
22
23 #define RTL821x_INER 0x12
24 #define RTL8211B_INER_INIT 0x6400
25 #define RTL8211E_INER_LINK_STATUS BIT(10)
26 #define RTL8211F_INER_LINK_STATUS BIT(4)
27
28 #define RTL821x_INSR 0x13
29
30 #define RTL821x_EXT_PAGE_SELECT 0x1e
31 #define RTL821x_PAGE_SELECT 0x1f
32
33 #define RTL8211F_PHYCR1 0x18
34 #define RTL8211F_PHYCR2 0x19
35 #define RTL8211F_INSR 0x1d
36
37 #define RTL8211F_LEDCR 0x10
38 #define RTL8211F_LEDCR_MODE BIT(15)
39 #define RTL8211F_LEDCR_ACT_TXRX BIT(4)
40 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
41 #define RTL8211F_LEDCR_LINK_100 BIT(1)
42 #define RTL8211F_LEDCR_LINK_10 BIT(0)
43 #define RTL8211F_LEDCR_MASK GENMASK(4, 0)
44 #define RTL8211F_LEDCR_SHIFT 5
45
46 #define RTL8211F_TX_DELAY BIT(8)
47 #define RTL8211F_RX_DELAY BIT(3)
48
49 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
50 #define RTL8211F_ALDPS_ENABLE BIT(2)
51 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
52
53 #define RTL8211E_CTRL_DELAY BIT(13)
54 #define RTL8211E_TX_DELAY BIT(12)
55 #define RTL8211E_RX_DELAY BIT(11)
56
57 #define RTL8211F_CLKOUT_EN BIT(0)
58
59 #define RTL8201F_ISR 0x1e
60 #define RTL8201F_ISR_ANERR BIT(15)
61 #define RTL8201F_ISR_DUPLEX BIT(13)
62 #define RTL8201F_ISR_LINK BIT(11)
63 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
64 RTL8201F_ISR_DUPLEX | \
65 RTL8201F_ISR_LINK)
66 #define RTL8201F_IER 0x13
67
68 #define RTL822X_VND1_SERDES_OPTION 0x697a
69 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
70 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
71 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
72
73 #define RTL822X_VND1_SERDES_CTRL3 0x7580
74 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
75 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
76 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
77
78 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
79 * is set, they cannot be accessed by C45-over-C22.
80 */
81 #define RTL822X_VND2_GBCR 0xa412
82
83 #define RTL822X_VND2_GANLPAR 0xa414
84
85 #define RTL8366RB_POWER_SAVE 0x15
86 #define RTL8366RB_POWER_SAVE_ON BIT(12)
87
88 #define RTL9000A_GINMR 0x14
89 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
90
91 #define RTL_VND2_PHYSR 0xa434
92 #define RTL_VND2_PHYSR_DUPLEX BIT(3)
93 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
94 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
95 #define RTL_VND2_PHYSR_MASTER BIT(11)
96 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
97
98 #define RTL_GENERIC_PHYID 0x001cc800
99 #define RTL_8211FVD_PHYID 0x001cc878
100 #define RTL_8221B 0x001cc840
101 #define RTL_8221B_VB_CG 0x001cc849
102 #define RTL_8221B_VN_CG 0x001cc84a
103 #define RTL_8251B 0x001cc862
104
105 #define RTL8211F_LED_COUNT 3
106
107 MODULE_DESCRIPTION("Realtek PHY driver");
108 MODULE_AUTHOR("Johnson Leung");
109 MODULE_LICENSE("GPL");
110
111 struct rtl821x_priv {
112 u16 phycr1;
113 u16 phycr2;
114 bool has_phycr2;
115 struct clk *clk;
116 };
117
rtl821x_read_page(struct phy_device * phydev)118 static int rtl821x_read_page(struct phy_device *phydev)
119 {
120 return __phy_read(phydev, RTL821x_PAGE_SELECT);
121 }
122
rtl821x_write_page(struct phy_device * phydev,int page)123 static int rtl821x_write_page(struct phy_device *phydev, int page)
124 {
125 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
126 }
127
rtl821x_probe(struct phy_device * phydev)128 static int rtl821x_probe(struct phy_device *phydev)
129 {
130 struct device *dev = &phydev->mdio.dev;
131 struct rtl821x_priv *priv;
132 u32 phy_id = phydev->drv->phy_id;
133 int ret;
134
135 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
136 if (!priv)
137 return -ENOMEM;
138
139 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
140 if (IS_ERR(priv->clk))
141 return dev_err_probe(dev, PTR_ERR(priv->clk),
142 "failed to get phy clock\n");
143
144 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
145 if (ret < 0)
146 return ret;
147
148 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
149 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
150 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
151
152 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
153 if (priv->has_phycr2) {
154 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
155 if (ret < 0)
156 return ret;
157
158 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
159 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
160 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
161 }
162
163 phydev->priv = priv;
164
165 return 0;
166 }
167
rtl8201_ack_interrupt(struct phy_device * phydev)168 static int rtl8201_ack_interrupt(struct phy_device *phydev)
169 {
170 int err;
171
172 err = phy_read(phydev, RTL8201F_ISR);
173
174 return (err < 0) ? err : 0;
175 }
176
rtl821x_ack_interrupt(struct phy_device * phydev)177 static int rtl821x_ack_interrupt(struct phy_device *phydev)
178 {
179 int err;
180
181 err = phy_read(phydev, RTL821x_INSR);
182
183 return (err < 0) ? err : 0;
184 }
185
rtl8211f_ack_interrupt(struct phy_device * phydev)186 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
187 {
188 int err;
189
190 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
191
192 return (err < 0) ? err : 0;
193 }
194
rtl8201_config_intr(struct phy_device * phydev)195 static int rtl8201_config_intr(struct phy_device *phydev)
196 {
197 u16 val;
198 int err;
199
200 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
201 err = rtl8201_ack_interrupt(phydev);
202 if (err)
203 return err;
204
205 val = BIT(13) | BIT(12) | BIT(11);
206 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
207 } else {
208 val = 0;
209 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
210 if (err)
211 return err;
212
213 err = rtl8201_ack_interrupt(phydev);
214 }
215
216 return err;
217 }
218
rtl8211b_config_intr(struct phy_device * phydev)219 static int rtl8211b_config_intr(struct phy_device *phydev)
220 {
221 int err;
222
223 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
224 err = rtl821x_ack_interrupt(phydev);
225 if (err)
226 return err;
227
228 err = phy_write(phydev, RTL821x_INER,
229 RTL8211B_INER_INIT);
230 } else {
231 err = phy_write(phydev, RTL821x_INER, 0);
232 if (err)
233 return err;
234
235 err = rtl821x_ack_interrupt(phydev);
236 }
237
238 return err;
239 }
240
rtl8211e_config_intr(struct phy_device * phydev)241 static int rtl8211e_config_intr(struct phy_device *phydev)
242 {
243 int err;
244
245 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
246 err = rtl821x_ack_interrupt(phydev);
247 if (err)
248 return err;
249
250 err = phy_write(phydev, RTL821x_INER,
251 RTL8211E_INER_LINK_STATUS);
252 } else {
253 err = phy_write(phydev, RTL821x_INER, 0);
254 if (err)
255 return err;
256
257 err = rtl821x_ack_interrupt(phydev);
258 }
259
260 return err;
261 }
262
rtl8211f_config_intr(struct phy_device * phydev)263 static int rtl8211f_config_intr(struct phy_device *phydev)
264 {
265 u16 val;
266 int err;
267
268 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
269 err = rtl8211f_ack_interrupt(phydev);
270 if (err)
271 return err;
272
273 val = RTL8211F_INER_LINK_STATUS;
274 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
275 } else {
276 val = 0;
277 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
278 if (err)
279 return err;
280
281 err = rtl8211f_ack_interrupt(phydev);
282 }
283
284 return err;
285 }
286
rtl8201_handle_interrupt(struct phy_device * phydev)287 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
288 {
289 int irq_status;
290
291 irq_status = phy_read(phydev, RTL8201F_ISR);
292 if (irq_status < 0) {
293 phy_error(phydev);
294 return IRQ_NONE;
295 }
296
297 if (!(irq_status & RTL8201F_ISR_MASK))
298 return IRQ_NONE;
299
300 phy_trigger_machine(phydev);
301
302 return IRQ_HANDLED;
303 }
304
rtl821x_handle_interrupt(struct phy_device * phydev)305 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
306 {
307 int irq_status, irq_enabled;
308
309 irq_status = phy_read(phydev, RTL821x_INSR);
310 if (irq_status < 0) {
311 phy_error(phydev);
312 return IRQ_NONE;
313 }
314
315 irq_enabled = phy_read(phydev, RTL821x_INER);
316 if (irq_enabled < 0) {
317 phy_error(phydev);
318 return IRQ_NONE;
319 }
320
321 if (!(irq_status & irq_enabled))
322 return IRQ_NONE;
323
324 phy_trigger_machine(phydev);
325
326 return IRQ_HANDLED;
327 }
328
rtl8211f_handle_interrupt(struct phy_device * phydev)329 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
330 {
331 int irq_status;
332
333 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
334 if (irq_status < 0) {
335 phy_error(phydev);
336 return IRQ_NONE;
337 }
338
339 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
340 return IRQ_NONE;
341
342 phy_trigger_machine(phydev);
343
344 return IRQ_HANDLED;
345 }
346
rtl8211_config_aneg(struct phy_device * phydev)347 static int rtl8211_config_aneg(struct phy_device *phydev)
348 {
349 int ret;
350
351 ret = genphy_config_aneg(phydev);
352 if (ret < 0)
353 return ret;
354
355 /* Quirk was copied from vendor driver. Unfortunately it includes no
356 * description of the magic numbers.
357 */
358 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
359 phy_write(phydev, 0x17, 0x2138);
360 phy_write(phydev, 0x0e, 0x0260);
361 } else {
362 phy_write(phydev, 0x17, 0x2108);
363 phy_write(phydev, 0x0e, 0x0000);
364 }
365
366 return 0;
367 }
368
rtl8211c_config_init(struct phy_device * phydev)369 static int rtl8211c_config_init(struct phy_device *phydev)
370 {
371 /* RTL8211C has an issue when operating in Gigabit slave mode */
372 return phy_set_bits(phydev, MII_CTRL1000,
373 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
374 }
375
rtl8211f_config_init(struct phy_device * phydev)376 static int rtl8211f_config_init(struct phy_device *phydev)
377 {
378 struct rtl821x_priv *priv = phydev->priv;
379 struct device *dev = &phydev->mdio.dev;
380 u16 val_txdly, val_rxdly;
381 int ret;
382
383 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
384 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
385 priv->phycr1);
386 if (ret < 0) {
387 dev_err(dev, "aldps mode configuration failed: %pe\n",
388 ERR_PTR(ret));
389 return ret;
390 }
391
392 switch (phydev->interface) {
393 case PHY_INTERFACE_MODE_RGMII:
394 val_txdly = 0;
395 val_rxdly = 0;
396 break;
397
398 case PHY_INTERFACE_MODE_RGMII_RXID:
399 val_txdly = 0;
400 val_rxdly = RTL8211F_RX_DELAY;
401 break;
402
403 case PHY_INTERFACE_MODE_RGMII_TXID:
404 val_txdly = RTL8211F_TX_DELAY;
405 val_rxdly = 0;
406 break;
407
408 case PHY_INTERFACE_MODE_RGMII_ID:
409 val_txdly = RTL8211F_TX_DELAY;
410 val_rxdly = RTL8211F_RX_DELAY;
411 break;
412
413 default: /* the rest of the modes imply leaving delay as is. */
414 return 0;
415 }
416
417 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
418 val_txdly);
419 if (ret < 0) {
420 dev_err(dev, "Failed to update the TX delay register\n");
421 return ret;
422 } else if (ret) {
423 dev_dbg(dev,
424 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
425 val_txdly ? "Enabling" : "Disabling");
426 } else {
427 dev_dbg(dev,
428 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
429 val_txdly ? "enabled" : "disabled");
430 }
431
432 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
433 val_rxdly);
434 if (ret < 0) {
435 dev_err(dev, "Failed to update the RX delay register\n");
436 return ret;
437 } else if (ret) {
438 dev_dbg(dev,
439 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
440 val_rxdly ? "Enabling" : "Disabling");
441 } else {
442 dev_dbg(dev,
443 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
444 val_rxdly ? "enabled" : "disabled");
445 }
446
447 if (priv->has_phycr2) {
448 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
449 RTL8211F_CLKOUT_EN, priv->phycr2);
450 if (ret < 0) {
451 dev_err(dev, "clkout configuration failed: %pe\n",
452 ERR_PTR(ret));
453 return ret;
454 }
455
456 return genphy_soft_reset(phydev);
457 }
458
459 return 0;
460 }
461
rtl821x_suspend(struct phy_device * phydev)462 static int rtl821x_suspend(struct phy_device *phydev)
463 {
464 struct rtl821x_priv *priv = phydev->priv;
465 int ret = 0;
466
467 if (!phydev->wol_enabled) {
468 ret = genphy_suspend(phydev);
469
470 if (ret)
471 return ret;
472
473 clk_disable_unprepare(priv->clk);
474 }
475
476 return ret;
477 }
478
rtl821x_resume(struct phy_device * phydev)479 static int rtl821x_resume(struct phy_device *phydev)
480 {
481 struct rtl821x_priv *priv = phydev->priv;
482 int ret;
483
484 if (!phydev->wol_enabled)
485 clk_prepare_enable(priv->clk);
486
487 ret = genphy_resume(phydev);
488 if (ret < 0)
489 return ret;
490
491 msleep(20);
492
493 return 0;
494 }
495
rtl8211f_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)496 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
497 unsigned long rules)
498 {
499 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
500 BIT(TRIGGER_NETDEV_LINK_100) |
501 BIT(TRIGGER_NETDEV_LINK_1000) |
502 BIT(TRIGGER_NETDEV_RX) |
503 BIT(TRIGGER_NETDEV_TX);
504
505 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
506 * - Link: Configurable subset of 10/100/1000 link rates
507 * - Active: Blink on activity, RX or TX is not differentiated
508 * The Active option has two modes, A and B:
509 * - A: Link and Active indication at configurable, but matching,
510 * subset of 10/100/1000 link rates
511 * - B: Link indication at configurable subset of 10/100/1000 link
512 * rates and Active indication always at all three 10+100+1000
513 * link rates.
514 * This code currently uses mode B only.
515 */
516
517 if (index >= RTL8211F_LED_COUNT)
518 return -EINVAL;
519
520 /* Filter out any other unsupported triggers. */
521 if (rules & ~mask)
522 return -EOPNOTSUPP;
523
524 /* RX and TX are not differentiated, either both are set or not set. */
525 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
526 return -EOPNOTSUPP;
527
528 return 0;
529 }
530
rtl8211f_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)531 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
532 unsigned long *rules)
533 {
534 int val;
535
536 if (index >= RTL8211F_LED_COUNT)
537 return -EINVAL;
538
539 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
540 if (val < 0)
541 return val;
542
543 val >>= RTL8211F_LEDCR_SHIFT * index;
544 val &= RTL8211F_LEDCR_MASK;
545
546 if (val & RTL8211F_LEDCR_LINK_10)
547 set_bit(TRIGGER_NETDEV_LINK_10, rules);
548
549 if (val & RTL8211F_LEDCR_LINK_100)
550 set_bit(TRIGGER_NETDEV_LINK_100, rules);
551
552 if (val & RTL8211F_LEDCR_LINK_1000)
553 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
554
555 if (val & RTL8211F_LEDCR_ACT_TXRX) {
556 set_bit(TRIGGER_NETDEV_RX, rules);
557 set_bit(TRIGGER_NETDEV_TX, rules);
558 }
559
560 return 0;
561 }
562
rtl8211f_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)563 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
564 unsigned long rules)
565 {
566 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
567 u16 reg = 0;
568
569 if (index >= RTL8211F_LED_COUNT)
570 return -EINVAL;
571
572 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
573 reg |= RTL8211F_LEDCR_LINK_10;
574
575 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
576 reg |= RTL8211F_LEDCR_LINK_100;
577
578 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
579 reg |= RTL8211F_LEDCR_LINK_1000;
580
581 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
582 test_bit(TRIGGER_NETDEV_TX, &rules)) {
583 reg |= RTL8211F_LEDCR_ACT_TXRX;
584 }
585
586 reg <<= RTL8211F_LEDCR_SHIFT * index;
587 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
588
589 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
590 }
591
rtl8211e_config_init(struct phy_device * phydev)592 static int rtl8211e_config_init(struct phy_device *phydev)
593 {
594 int ret = 0, oldpage;
595 u16 val;
596
597 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
598 switch (phydev->interface) {
599 case PHY_INTERFACE_MODE_RGMII:
600 val = RTL8211E_CTRL_DELAY | 0;
601 break;
602 case PHY_INTERFACE_MODE_RGMII_ID:
603 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
604 break;
605 case PHY_INTERFACE_MODE_RGMII_RXID:
606 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
607 break;
608 case PHY_INTERFACE_MODE_RGMII_TXID:
609 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
610 break;
611 default: /* the rest of the modes imply leaving delays as is. */
612 return 0;
613 }
614
615 /* According to a sample driver there is a 0x1c config register on the
616 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
617 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
618 * The configuration register definition:
619 * 14 = reserved
620 * 13 = Force Tx RX Delay controlled by bit12 bit11,
621 * 12 = RX Delay, 11 = TX Delay
622 * 10:0 = Test && debug settings reserved by realtek
623 */
624 oldpage = phy_select_page(phydev, 0x7);
625 if (oldpage < 0)
626 goto err_restore_page;
627
628 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
629 if (ret)
630 goto err_restore_page;
631
632 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
633 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
634 val);
635
636 err_restore_page:
637 return phy_restore_page(phydev, oldpage, ret);
638 }
639
rtl8211b_suspend(struct phy_device * phydev)640 static int rtl8211b_suspend(struct phy_device *phydev)
641 {
642 phy_write(phydev, MII_MMD_DATA, BIT(9));
643
644 return genphy_suspend(phydev);
645 }
646
rtl8211b_resume(struct phy_device * phydev)647 static int rtl8211b_resume(struct phy_device *phydev)
648 {
649 phy_write(phydev, MII_MMD_DATA, 0);
650
651 return genphy_resume(phydev);
652 }
653
rtl8366rb_config_init(struct phy_device * phydev)654 static int rtl8366rb_config_init(struct phy_device *phydev)
655 {
656 int ret;
657
658 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
659 RTL8366RB_POWER_SAVE_ON);
660 if (ret) {
661 dev_err(&phydev->mdio.dev,
662 "error enabling power management\n");
663 }
664
665 return ret;
666 }
667
668 /* get actual speed to cover the downshift case */
rtlgen_decode_physr(struct phy_device * phydev,int val)669 static void rtlgen_decode_physr(struct phy_device *phydev, int val)
670 {
671 /* bit 3
672 * 0: Half Duplex
673 * 1: Full Duplex
674 */
675 if (val & RTL_VND2_PHYSR_DUPLEX)
676 phydev->duplex = DUPLEX_FULL;
677 else
678 phydev->duplex = DUPLEX_HALF;
679
680 switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
681 case 0x0000:
682 phydev->speed = SPEED_10;
683 break;
684 case 0x0010:
685 phydev->speed = SPEED_100;
686 break;
687 case 0x0020:
688 phydev->speed = SPEED_1000;
689 break;
690 case 0x0200:
691 phydev->speed = SPEED_10000;
692 break;
693 case 0x0210:
694 phydev->speed = SPEED_2500;
695 break;
696 case 0x0220:
697 phydev->speed = SPEED_5000;
698 break;
699 default:
700 break;
701 }
702
703 /* bit 11
704 * 0: Slave Mode
705 * 1: Master Mode
706 */
707 if (phydev->speed >= 1000) {
708 if (val & RTL_VND2_PHYSR_MASTER)
709 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
710 else
711 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
712 } else {
713 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
714 }
715 }
716
rtlgen_read_status(struct phy_device * phydev)717 static int rtlgen_read_status(struct phy_device *phydev)
718 {
719 int ret, val;
720
721 ret = genphy_read_status(phydev);
722 if (ret < 0)
723 return ret;
724
725 if (!phydev->link)
726 return 0;
727
728 val = phy_read_paged(phydev, 0xa43, 0x12);
729 if (val < 0)
730 return val;
731
732 rtlgen_decode_physr(phydev, val);
733
734 return 0;
735 }
736
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)737 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
738 {
739 int ret;
740
741 if (devnum == MDIO_MMD_VEND2) {
742 rtl821x_write_page(phydev, regnum >> 4);
743 ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
744 rtl821x_write_page(phydev, 0);
745 } else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
746 rtl821x_write_page(phydev, 0xa5c);
747 ret = __phy_read(phydev, 0x12);
748 rtl821x_write_page(phydev, 0);
749 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
750 rtl821x_write_page(phydev, 0xa5d);
751 ret = __phy_read(phydev, 0x10);
752 rtl821x_write_page(phydev, 0);
753 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
754 rtl821x_write_page(phydev, 0xa5d);
755 ret = __phy_read(phydev, 0x11);
756 rtl821x_write_page(phydev, 0);
757 } else {
758 ret = -EOPNOTSUPP;
759 }
760
761 return ret;
762 }
763
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)764 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
765 u16 val)
766 {
767 int ret;
768
769 if (devnum == MDIO_MMD_VEND2) {
770 rtl821x_write_page(phydev, regnum >> 4);
771 ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
772 rtl821x_write_page(phydev, 0);
773 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
774 rtl821x_write_page(phydev, 0xa5d);
775 ret = __phy_write(phydev, 0x10, val);
776 rtl821x_write_page(phydev, 0);
777 } else {
778 ret = -EOPNOTSUPP;
779 }
780
781 return ret;
782 }
783
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)784 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
785 {
786 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
787
788 if (ret != -EOPNOTSUPP)
789 return ret;
790
791 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
792 rtl821x_write_page(phydev, 0xa6e);
793 ret = __phy_read(phydev, 0x16);
794 rtl821x_write_page(phydev, 0);
795 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
796 rtl821x_write_page(phydev, 0xa6d);
797 ret = __phy_read(phydev, 0x12);
798 rtl821x_write_page(phydev, 0);
799 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
800 rtl821x_write_page(phydev, 0xa6d);
801 ret = __phy_read(phydev, 0x10);
802 rtl821x_write_page(phydev, 0);
803 }
804
805 return ret;
806 }
807
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)808 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
809 u16 val)
810 {
811 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
812
813 if (ret != -EOPNOTSUPP)
814 return ret;
815
816 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
817 rtl821x_write_page(phydev, 0xa6d);
818 ret = __phy_write(phydev, 0x12, val);
819 rtl821x_write_page(phydev, 0);
820 }
821
822 return ret;
823 }
824
rtl822x_probe(struct phy_device * phydev)825 static int rtl822x_probe(struct phy_device *phydev)
826 {
827 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) &&
828 phydev->phy_id != RTL_GENERIC_PHYID)
829 return rtl822x_hwmon_init(phydev);
830
831 return 0;
832 }
833
rtl822xb_config_init(struct phy_device * phydev)834 static int rtl822xb_config_init(struct phy_device *phydev)
835 {
836 bool has_2500, has_sgmii;
837 u16 mode;
838 int ret;
839
840 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
841 phydev->host_interfaces) ||
842 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
843
844 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
845 phydev->host_interfaces) ||
846 phydev->interface == PHY_INTERFACE_MODE_SGMII;
847
848 /* fill in possible interfaces */
849 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
850 has_2500);
851 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
852 has_sgmii);
853
854 if (!has_2500 && !has_sgmii)
855 return 0;
856
857 /* determine SerDes option mode */
858 if (has_2500 && !has_sgmii) {
859 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
860 phydev->rate_matching = RATE_MATCH_PAUSE;
861 } else {
862 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
863 phydev->rate_matching = RATE_MATCH_NONE;
864 }
865
866 /* the following sequence with magic numbers sets up the SerDes
867 * option mode
868 */
869 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
870 if (ret < 0)
871 return ret;
872
873 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
874 RTL822X_VND1_SERDES_OPTION,
875 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
876 mode);
877 if (ret < 0)
878 return ret;
879
880 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
881 if (ret < 0)
882 return ret;
883
884 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
885 if (ret < 0)
886 return ret;
887
888 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
889 }
890
rtl822xb_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)891 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
892 phy_interface_t iface)
893 {
894 int val;
895
896 /* Only rate matching at 2500base-x */
897 if (iface != PHY_INTERFACE_MODE_2500BASEX)
898 return RATE_MATCH_NONE;
899
900 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
901 if (val < 0)
902 return val;
903
904 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
905 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
906 return RATE_MATCH_PAUSE;
907
908 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
909 return RATE_MATCH_NONE;
910 }
911
rtl822x_get_features(struct phy_device * phydev)912 static int rtl822x_get_features(struct phy_device *phydev)
913 {
914 int val;
915
916 val = phy_read_paged(phydev, 0xa61, 0x13);
917 if (val < 0)
918 return val;
919
920 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
921 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
922 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
923 phydev->supported, val & MDIO_PMA_SPEED_5G);
924 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
925 phydev->supported, val & MDIO_SPEED_10G);
926
927 return genphy_read_abilities(phydev);
928 }
929
rtl822x_config_aneg(struct phy_device * phydev)930 static int rtl822x_config_aneg(struct phy_device *phydev)
931 {
932 int ret = 0;
933
934 if (phydev->autoneg == AUTONEG_ENABLE) {
935 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
936
937 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
938 MDIO_AN_10GBT_CTRL_ADV2_5G |
939 MDIO_AN_10GBT_CTRL_ADV5G,
940 adv);
941 if (ret < 0)
942 return ret;
943 }
944
945 return __genphy_config_aneg(phydev, ret);
946 }
947
rtl822xb_update_interface(struct phy_device * phydev)948 static void rtl822xb_update_interface(struct phy_device *phydev)
949 {
950 int val;
951
952 if (!phydev->link)
953 return;
954
955 /* Change interface according to serdes mode */
956 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
957 if (val < 0)
958 return;
959
960 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
961 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
962 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
963 break;
964 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
965 phydev->interface = PHY_INTERFACE_MODE_SGMII;
966 break;
967 }
968 }
969
rtl822x_read_status(struct phy_device * phydev)970 static int rtl822x_read_status(struct phy_device *phydev)
971 {
972 int lpadv, ret;
973
974 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
975
976 ret = rtlgen_read_status(phydev);
977 if (ret < 0)
978 return ret;
979
980 if (phydev->autoneg == AUTONEG_DISABLE ||
981 !phydev->autoneg_complete)
982 return 0;
983
984 lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
985 if (lpadv < 0)
986 return lpadv;
987
988 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
989
990 return 0;
991 }
992
rtl822xb_read_status(struct phy_device * phydev)993 static int rtl822xb_read_status(struct phy_device *phydev)
994 {
995 int ret;
996
997 ret = rtl822x_read_status(phydev);
998 if (ret < 0)
999 return ret;
1000
1001 rtl822xb_update_interface(phydev);
1002
1003 return 0;
1004 }
1005
rtl822x_c45_get_features(struct phy_device * phydev)1006 static int rtl822x_c45_get_features(struct phy_device *phydev)
1007 {
1008 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1009 phydev->supported);
1010
1011 return genphy_c45_pma_read_abilities(phydev);
1012 }
1013
rtl822x_c45_config_aneg(struct phy_device * phydev)1014 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1015 {
1016 bool changed = false;
1017 int ret, val;
1018
1019 if (phydev->autoneg == AUTONEG_DISABLE)
1020 return genphy_c45_pma_setup_forced(phydev);
1021
1022 ret = genphy_c45_an_config_aneg(phydev);
1023 if (ret < 0)
1024 return ret;
1025 if (ret > 0)
1026 changed = true;
1027
1028 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1029
1030 /* Vendor register as C45 has no standardized support for 1000BaseT */
1031 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
1032 ADVERTISE_1000FULL, val);
1033 if (ret < 0)
1034 return ret;
1035 if (ret > 0)
1036 changed = true;
1037
1038 return genphy_c45_check_and_restart_aneg(phydev, changed);
1039 }
1040
rtl822x_c45_read_status(struct phy_device * phydev)1041 static int rtl822x_c45_read_status(struct phy_device *phydev)
1042 {
1043 int ret, val;
1044
1045 /* Vendor register as C45 has no standardized support for 1000BaseT */
1046 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1047 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1048 RTL822X_VND2_GANLPAR);
1049 if (val < 0)
1050 return val;
1051 } else {
1052 val = 0;
1053 }
1054 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1055
1056 ret = genphy_c45_read_status(phydev);
1057 if (ret < 0)
1058 return ret;
1059
1060 if (!phydev->link) {
1061 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1062 return 0;
1063 }
1064
1065 /* Read actual speed from vendor register. */
1066 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1067 if (val < 0)
1068 return val;
1069
1070 rtlgen_decode_physr(phydev, val);
1071
1072 return 0;
1073 }
1074
rtl822xb_c45_read_status(struct phy_device * phydev)1075 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1076 {
1077 int ret;
1078
1079 ret = rtl822x_c45_read_status(phydev);
1080 if (ret < 0)
1081 return ret;
1082
1083 rtl822xb_update_interface(phydev);
1084
1085 return 0;
1086 }
1087
rtlgen_supports_2_5gbps(struct phy_device * phydev)1088 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1089 {
1090 int val;
1091
1092 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1093 val = phy_read(phydev, 0x13);
1094 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1095
1096 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1097 }
1098
1099 /* On internal PHY's MMD reads over C22 always return 0.
1100 * Check a MMD register which is known to be non-zero.
1101 */
rtlgen_supports_mmd(struct phy_device * phydev)1102 static bool rtlgen_supports_mmd(struct phy_device *phydev)
1103 {
1104 int val;
1105
1106 phy_lock_mdio_bus(phydev);
1107 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1108 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1109 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1110 val = __phy_read(phydev, MII_MMD_DATA);
1111 phy_unlock_mdio_bus(phydev);
1112
1113 return val > 0;
1114 }
1115
rtlgen_match_phy_device(struct phy_device * phydev)1116 static int rtlgen_match_phy_device(struct phy_device *phydev)
1117 {
1118 return phydev->phy_id == RTL_GENERIC_PHYID &&
1119 !rtlgen_supports_2_5gbps(phydev);
1120 }
1121
rtl8226_match_phy_device(struct phy_device * phydev)1122 static int rtl8226_match_phy_device(struct phy_device *phydev)
1123 {
1124 return phydev->phy_id == RTL_GENERIC_PHYID &&
1125 rtlgen_supports_2_5gbps(phydev) &&
1126 rtlgen_supports_mmd(phydev);
1127 }
1128
rtlgen_is_c45_match(struct phy_device * phydev,unsigned int id,bool is_c45)1129 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1130 bool is_c45)
1131 {
1132 if (phydev->is_c45)
1133 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1134 else
1135 return !is_c45 && (id == phydev->phy_id);
1136 }
1137
rtl8221b_match_phy_device(struct phy_device * phydev)1138 static int rtl8221b_match_phy_device(struct phy_device *phydev)
1139 {
1140 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1141 }
1142
rtl8221b_vb_cg_c22_match_phy_device(struct phy_device * phydev)1143 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1144 {
1145 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1146 }
1147
rtl8221b_vb_cg_c45_match_phy_device(struct phy_device * phydev)1148 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1149 {
1150 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1151 }
1152
rtl8221b_vn_cg_c22_match_phy_device(struct phy_device * phydev)1153 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1154 {
1155 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1156 }
1157
rtl8221b_vn_cg_c45_match_phy_device(struct phy_device * phydev)1158 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1159 {
1160 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1161 }
1162
rtl_internal_nbaset_match_phy_device(struct phy_device * phydev)1163 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
1164 {
1165 if (phydev->is_c45)
1166 return false;
1167
1168 switch (phydev->phy_id) {
1169 case RTL_GENERIC_PHYID:
1170 case RTL_8221B:
1171 case RTL_8251B:
1172 case 0x001cc841:
1173 break;
1174 default:
1175 return false;
1176 }
1177
1178 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1179 }
1180
rtl8251b_c45_match_phy_device(struct phy_device * phydev)1181 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1182 {
1183 return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1184 }
1185
rtlgen_resume(struct phy_device * phydev)1186 static int rtlgen_resume(struct phy_device *phydev)
1187 {
1188 int ret = genphy_resume(phydev);
1189
1190 /* Internal PHY's from RTL8168h up may not be instantly ready */
1191 msleep(20);
1192
1193 return ret;
1194 }
1195
rtlgen_c45_resume(struct phy_device * phydev)1196 static int rtlgen_c45_resume(struct phy_device *phydev)
1197 {
1198 int ret = genphy_c45_pma_resume(phydev);
1199
1200 msleep(20);
1201
1202 return ret;
1203 }
1204
rtl9000a_config_init(struct phy_device * phydev)1205 static int rtl9000a_config_init(struct phy_device *phydev)
1206 {
1207 phydev->autoneg = AUTONEG_DISABLE;
1208 phydev->speed = SPEED_100;
1209 phydev->duplex = DUPLEX_FULL;
1210
1211 return 0;
1212 }
1213
rtl9000a_config_aneg(struct phy_device * phydev)1214 static int rtl9000a_config_aneg(struct phy_device *phydev)
1215 {
1216 int ret;
1217 u16 ctl = 0;
1218
1219 switch (phydev->master_slave_set) {
1220 case MASTER_SLAVE_CFG_MASTER_FORCE:
1221 ctl |= CTL1000_AS_MASTER;
1222 break;
1223 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1224 break;
1225 case MASTER_SLAVE_CFG_UNKNOWN:
1226 case MASTER_SLAVE_CFG_UNSUPPORTED:
1227 return 0;
1228 default:
1229 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1230 return -EOPNOTSUPP;
1231 }
1232
1233 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1234 if (ret == 1)
1235 ret = genphy_soft_reset(phydev);
1236
1237 return ret;
1238 }
1239
rtl9000a_read_status(struct phy_device * phydev)1240 static int rtl9000a_read_status(struct phy_device *phydev)
1241 {
1242 int ret;
1243
1244 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1245 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1246
1247 ret = genphy_update_link(phydev);
1248 if (ret)
1249 return ret;
1250
1251 ret = phy_read(phydev, MII_CTRL1000);
1252 if (ret < 0)
1253 return ret;
1254 if (ret & CTL1000_AS_MASTER)
1255 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1256 else
1257 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1258
1259 ret = phy_read(phydev, MII_STAT1000);
1260 if (ret < 0)
1261 return ret;
1262 if (ret & LPA_1000MSRES)
1263 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1264 else
1265 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1266
1267 return 0;
1268 }
1269
rtl9000a_ack_interrupt(struct phy_device * phydev)1270 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1271 {
1272 int err;
1273
1274 err = phy_read(phydev, RTL8211F_INSR);
1275
1276 return (err < 0) ? err : 0;
1277 }
1278
rtl9000a_config_intr(struct phy_device * phydev)1279 static int rtl9000a_config_intr(struct phy_device *phydev)
1280 {
1281 u16 val;
1282 int err;
1283
1284 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1285 err = rtl9000a_ack_interrupt(phydev);
1286 if (err)
1287 return err;
1288
1289 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1290 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1291 } else {
1292 val = ~0;
1293 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1294 if (err)
1295 return err;
1296
1297 err = rtl9000a_ack_interrupt(phydev);
1298 }
1299
1300 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1301 }
1302
rtl9000a_handle_interrupt(struct phy_device * phydev)1303 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1304 {
1305 int irq_status;
1306
1307 irq_status = phy_read(phydev, RTL8211F_INSR);
1308 if (irq_status < 0) {
1309 phy_error(phydev);
1310 return IRQ_NONE;
1311 }
1312
1313 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1314 return IRQ_NONE;
1315
1316 phy_trigger_machine(phydev);
1317
1318 return IRQ_HANDLED;
1319 }
1320
1321 static struct phy_driver realtek_drvs[] = {
1322 {
1323 PHY_ID_MATCH_EXACT(0x00008201),
1324 .name = "RTL8201CP Ethernet",
1325 .read_page = rtl821x_read_page,
1326 .write_page = rtl821x_write_page,
1327 }, {
1328 PHY_ID_MATCH_EXACT(0x001cc816),
1329 .name = "RTL8201F Fast Ethernet",
1330 .config_intr = &rtl8201_config_intr,
1331 .handle_interrupt = rtl8201_handle_interrupt,
1332 .suspend = genphy_suspend,
1333 .resume = genphy_resume,
1334 .read_page = rtl821x_read_page,
1335 .write_page = rtl821x_write_page,
1336 }, {
1337 PHY_ID_MATCH_MODEL(0x001cc880),
1338 .name = "RTL8208 Fast Ethernet",
1339 .read_mmd = genphy_read_mmd_unsupported,
1340 .write_mmd = genphy_write_mmd_unsupported,
1341 .suspend = genphy_suspend,
1342 .resume = genphy_resume,
1343 .read_page = rtl821x_read_page,
1344 .write_page = rtl821x_write_page,
1345 }, {
1346 PHY_ID_MATCH_EXACT(0x001cc910),
1347 .name = "RTL8211 Gigabit Ethernet",
1348 .config_aneg = rtl8211_config_aneg,
1349 .read_mmd = &genphy_read_mmd_unsupported,
1350 .write_mmd = &genphy_write_mmd_unsupported,
1351 .read_page = rtl821x_read_page,
1352 .write_page = rtl821x_write_page,
1353 }, {
1354 PHY_ID_MATCH_EXACT(0x001cc912),
1355 .name = "RTL8211B Gigabit Ethernet",
1356 .config_intr = &rtl8211b_config_intr,
1357 .handle_interrupt = rtl821x_handle_interrupt,
1358 .read_mmd = &genphy_read_mmd_unsupported,
1359 .write_mmd = &genphy_write_mmd_unsupported,
1360 .suspend = rtl8211b_suspend,
1361 .resume = rtl8211b_resume,
1362 .read_page = rtl821x_read_page,
1363 .write_page = rtl821x_write_page,
1364 }, {
1365 PHY_ID_MATCH_EXACT(0x001cc913),
1366 .name = "RTL8211C Gigabit Ethernet",
1367 .config_init = rtl8211c_config_init,
1368 .read_mmd = &genphy_read_mmd_unsupported,
1369 .write_mmd = &genphy_write_mmd_unsupported,
1370 .read_page = rtl821x_read_page,
1371 .write_page = rtl821x_write_page,
1372 }, {
1373 PHY_ID_MATCH_EXACT(0x001cc914),
1374 .name = "RTL8211DN Gigabit Ethernet",
1375 .config_intr = rtl8211e_config_intr,
1376 .handle_interrupt = rtl821x_handle_interrupt,
1377 .suspend = genphy_suspend,
1378 .resume = genphy_resume,
1379 .read_page = rtl821x_read_page,
1380 .write_page = rtl821x_write_page,
1381 }, {
1382 PHY_ID_MATCH_EXACT(0x001cc915),
1383 .name = "RTL8211E Gigabit Ethernet",
1384 .config_init = &rtl8211e_config_init,
1385 .config_intr = &rtl8211e_config_intr,
1386 .handle_interrupt = rtl821x_handle_interrupt,
1387 .suspend = genphy_suspend,
1388 .resume = genphy_resume,
1389 .read_page = rtl821x_read_page,
1390 .write_page = rtl821x_write_page,
1391 }, {
1392 PHY_ID_MATCH_EXACT(0x001cc916),
1393 .name = "RTL8211F Gigabit Ethernet",
1394 .probe = rtl821x_probe,
1395 .config_init = &rtl8211f_config_init,
1396 .read_status = rtlgen_read_status,
1397 .config_intr = &rtl8211f_config_intr,
1398 .handle_interrupt = rtl8211f_handle_interrupt,
1399 .suspend = rtl821x_suspend,
1400 .resume = rtl821x_resume,
1401 .read_page = rtl821x_read_page,
1402 .write_page = rtl821x_write_page,
1403 .flags = PHY_ALWAYS_CALL_SUSPEND,
1404 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1405 .led_hw_control_get = rtl8211f_led_hw_control_get,
1406 .led_hw_control_set = rtl8211f_led_hw_control_set,
1407 }, {
1408 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1409 .name = "RTL8211F-VD Gigabit Ethernet",
1410 .probe = rtl821x_probe,
1411 .config_init = &rtl8211f_config_init,
1412 .read_status = rtlgen_read_status,
1413 .config_intr = &rtl8211f_config_intr,
1414 .handle_interrupt = rtl8211f_handle_interrupt,
1415 .suspend = rtl821x_suspend,
1416 .resume = rtl821x_resume,
1417 .read_page = rtl821x_read_page,
1418 .write_page = rtl821x_write_page,
1419 .flags = PHY_ALWAYS_CALL_SUSPEND,
1420 }, {
1421 .name = "Generic FE-GE Realtek PHY",
1422 .match_phy_device = rtlgen_match_phy_device,
1423 .read_status = rtlgen_read_status,
1424 .suspend = genphy_suspend,
1425 .resume = rtlgen_resume,
1426 .read_page = rtl821x_read_page,
1427 .write_page = rtl821x_write_page,
1428 .read_mmd = rtlgen_read_mmd,
1429 .write_mmd = rtlgen_write_mmd,
1430 }, {
1431 .name = "RTL8226 2.5Gbps PHY",
1432 .match_phy_device = rtl8226_match_phy_device,
1433 .get_features = rtl822x_get_features,
1434 .config_aneg = rtl822x_config_aneg,
1435 .read_status = rtl822x_read_status,
1436 .suspend = genphy_suspend,
1437 .resume = rtlgen_resume,
1438 .read_page = rtl821x_read_page,
1439 .write_page = rtl821x_write_page,
1440 }, {
1441 .match_phy_device = rtl8221b_match_phy_device,
1442 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1443 .get_features = rtl822x_get_features,
1444 .config_aneg = rtl822x_config_aneg,
1445 .config_init = rtl822xb_config_init,
1446 .get_rate_matching = rtl822xb_get_rate_matching,
1447 .read_status = rtl822xb_read_status,
1448 .suspend = genphy_suspend,
1449 .resume = rtlgen_resume,
1450 .read_page = rtl821x_read_page,
1451 .write_page = rtl821x_write_page,
1452 }, {
1453 PHY_ID_MATCH_EXACT(0x001cc838),
1454 .name = "RTL8226-CG 2.5Gbps PHY",
1455 .get_features = rtl822x_get_features,
1456 .config_aneg = rtl822x_config_aneg,
1457 .read_status = rtl822x_read_status,
1458 .suspend = genphy_suspend,
1459 .resume = rtlgen_resume,
1460 .read_page = rtl821x_read_page,
1461 .write_page = rtl821x_write_page,
1462 }, {
1463 PHY_ID_MATCH_EXACT(0x001cc848),
1464 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1465 .get_features = rtl822x_get_features,
1466 .config_aneg = rtl822x_config_aneg,
1467 .config_init = rtl822xb_config_init,
1468 .get_rate_matching = rtl822xb_get_rate_matching,
1469 .read_status = rtl822xb_read_status,
1470 .suspend = genphy_suspend,
1471 .resume = rtlgen_resume,
1472 .read_page = rtl821x_read_page,
1473 .write_page = rtl821x_write_page,
1474 }, {
1475 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1476 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1477 .probe = rtl822x_probe,
1478 .get_features = rtl822x_get_features,
1479 .config_aneg = rtl822x_config_aneg,
1480 .config_init = rtl822xb_config_init,
1481 .get_rate_matching = rtl822xb_get_rate_matching,
1482 .read_status = rtl822xb_read_status,
1483 .suspend = genphy_suspend,
1484 .resume = rtlgen_resume,
1485 .read_page = rtl821x_read_page,
1486 .write_page = rtl821x_write_page,
1487 }, {
1488 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1489 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1490 .probe = rtl822x_probe,
1491 .config_init = rtl822xb_config_init,
1492 .get_rate_matching = rtl822xb_get_rate_matching,
1493 .get_features = rtl822x_c45_get_features,
1494 .config_aneg = rtl822x_c45_config_aneg,
1495 .read_status = rtl822xb_c45_read_status,
1496 .suspend = genphy_c45_pma_suspend,
1497 .resume = rtlgen_c45_resume,
1498 }, {
1499 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1500 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1501 .probe = rtl822x_probe,
1502 .get_features = rtl822x_get_features,
1503 .config_aneg = rtl822x_config_aneg,
1504 .config_init = rtl822xb_config_init,
1505 .get_rate_matching = rtl822xb_get_rate_matching,
1506 .read_status = rtl822xb_read_status,
1507 .suspend = genphy_suspend,
1508 .resume = rtlgen_resume,
1509 .read_page = rtl821x_read_page,
1510 .write_page = rtl821x_write_page,
1511 }, {
1512 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1513 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1514 .probe = rtl822x_probe,
1515 .config_init = rtl822xb_config_init,
1516 .get_rate_matching = rtl822xb_get_rate_matching,
1517 .get_features = rtl822x_c45_get_features,
1518 .config_aneg = rtl822x_c45_config_aneg,
1519 .read_status = rtl822xb_c45_read_status,
1520 .suspend = genphy_c45_pma_suspend,
1521 .resume = rtlgen_c45_resume,
1522 }, {
1523 .match_phy_device = rtl8251b_c45_match_phy_device,
1524 .name = "RTL8251B 5Gbps PHY",
1525 .probe = rtl822x_probe,
1526 .get_features = rtl822x_get_features,
1527 .config_aneg = rtl822x_config_aneg,
1528 .read_status = rtl822x_read_status,
1529 .suspend = genphy_suspend,
1530 .resume = rtlgen_resume,
1531 .read_page = rtl821x_read_page,
1532 .write_page = rtl821x_write_page,
1533 }, {
1534 .match_phy_device = rtl_internal_nbaset_match_phy_device,
1535 .name = "Realtek Internal NBASE-T PHY",
1536 .flags = PHY_IS_INTERNAL,
1537 .probe = rtl822x_probe,
1538 .get_features = rtl822x_get_features,
1539 .config_aneg = rtl822x_config_aneg,
1540 .read_status = rtl822x_read_status,
1541 .suspend = genphy_suspend,
1542 .resume = rtlgen_resume,
1543 .read_page = rtl821x_read_page,
1544 .write_page = rtl821x_write_page,
1545 .read_mmd = rtl822x_read_mmd,
1546 .write_mmd = rtl822x_write_mmd,
1547 }, {
1548 PHY_ID_MATCH_EXACT(0x001ccad0),
1549 .name = "RTL8224 2.5Gbps PHY",
1550 .get_features = rtl822x_c45_get_features,
1551 .config_aneg = rtl822x_c45_config_aneg,
1552 .read_status = rtl822x_c45_read_status,
1553 .suspend = genphy_c45_pma_suspend,
1554 .resume = rtlgen_c45_resume,
1555 }, {
1556 PHY_ID_MATCH_EXACT(0x001cc961),
1557 .name = "RTL8366RB Gigabit Ethernet",
1558 .config_init = &rtl8366rb_config_init,
1559 /* These interrupts are handled by the irq controller
1560 * embedded inside the RTL8366RB, they get unmasked when the
1561 * irq is requested and ACKed by reading the status register,
1562 * which is done by the irqchip code.
1563 */
1564 .config_intr = genphy_no_config_intr,
1565 .handle_interrupt = genphy_handle_interrupt_no_ack,
1566 .suspend = genphy_suspend,
1567 .resume = genphy_resume,
1568 }, {
1569 PHY_ID_MATCH_EXACT(0x001ccb00),
1570 .name = "RTL9000AA_RTL9000AN Ethernet",
1571 .features = PHY_BASIC_T1_FEATURES,
1572 .config_init = rtl9000a_config_init,
1573 .config_aneg = rtl9000a_config_aneg,
1574 .read_status = rtl9000a_read_status,
1575 .config_intr = rtl9000a_config_intr,
1576 .handle_interrupt = rtl9000a_handle_interrupt,
1577 .suspend = genphy_suspend,
1578 .resume = genphy_resume,
1579 .read_page = rtl821x_read_page,
1580 .write_page = rtl821x_write_page,
1581 }, {
1582 PHY_ID_MATCH_EXACT(0x001cc942),
1583 .name = "RTL8365MB-VC Gigabit Ethernet",
1584 /* Interrupt handling analogous to RTL8366RB */
1585 .config_intr = genphy_no_config_intr,
1586 .handle_interrupt = genphy_handle_interrupt_no_ack,
1587 .suspend = genphy_suspend,
1588 .resume = genphy_resume,
1589 }, {
1590 PHY_ID_MATCH_EXACT(0x001cc960),
1591 .name = "RTL8366S Gigabit Ethernet",
1592 .suspend = genphy_suspend,
1593 .resume = genphy_resume,
1594 .read_mmd = genphy_read_mmd_unsupported,
1595 .write_mmd = genphy_write_mmd_unsupported,
1596 },
1597 };
1598
1599 module_phy_driver(realtek_drvs);
1600
1601 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1602 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1603 { }
1604 };
1605
1606 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1607