1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Driver for the MDIO interface of Microsemi network switches.
4  *
5  * Author: Alexandre Belloni <[email protected]>
6  * Copyright (c) 2017 Microsemi Corporation
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mdio/mdio-mscc-miim.h>
15 #include <linux/mfd/ocelot.h>
16 #include <linux/module.h>
17 #include <linux/of_mdio.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 
24 #define MSCC_MIIM_REG_STATUS		0x0
25 #define		MSCC_MIIM_STATUS_STAT_PENDING	BIT(2)
26 #define		MSCC_MIIM_STATUS_STAT_BUSY	BIT(3)
27 #define MSCC_MIIM_REG_CMD		0x8
28 #define		MSCC_MIIM_CMD_OPR_WRITE		BIT(1)
29 #define		MSCC_MIIM_CMD_OPR_READ		BIT(2)
30 #define		MSCC_MIIM_CMD_WRDATA_SHIFT	4
31 #define		MSCC_MIIM_CMD_REGAD_SHIFT	20
32 #define		MSCC_MIIM_CMD_PHYAD_SHIFT	25
33 #define		MSCC_MIIM_CMD_VLD		BIT(31)
34 #define MSCC_MIIM_REG_DATA		0xC
35 #define		MSCC_MIIM_DATA_ERROR		(BIT(16) | BIT(17))
36 #define MSCC_MIIM_REG_CFG		0x10
37 #define		MSCC_MIIM_CFG_PRESCALE_MASK	GENMASK(7, 0)
38 
39 #define MSCC_PHY_REG_PHY_CFG	0x0
40 #define		PHY_CFG_PHY_ENA		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
41 #define		PHY_CFG_PHY_COMMON_RESET BIT(4)
42 #define		PHY_CFG_PHY_RESET	(BIT(5) | BIT(6) | BIT(7) | BIT(8))
43 #define MSCC_PHY_REG_PHY_STATUS	0x4
44 
45 #define LAN966X_CUPHY_COMMON_CFG	0x0
46 #define		CUPHY_COMMON_CFG_RESET_N	BIT(0)
47 
48 struct mscc_miim_info {
49 	unsigned int phy_reset_offset;
50 	unsigned int phy_reset_bits;
51 };
52 
53 struct mscc_miim_dev {
54 	struct regmap *regs;
55 	int mii_status_offset;
56 	bool ignore_read_errors;
57 	struct regmap *phy_regs;
58 	const struct mscc_miim_info *info;
59 	struct clk *clk;
60 	u32 bus_freq;
61 };
62 
63 /* When high resolution timers aren't built-in: we can't use usleep_range() as
64  * we would sleep way too long. Use udelay() instead.
65  */
66 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
67 ({									  \
68 	if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS))			  \
69 		readx_poll_timeout_atomic(op, addr, val, cond, delay_us,  \
70 					  timeout_us);			  \
71 	readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us);	  \
72 })
73 
mscc_miim_status(struct mii_bus * bus)74 static int mscc_miim_status(struct mii_bus *bus)
75 {
76 	struct mscc_miim_dev *miim = bus->priv;
77 	int val, ret;
78 
79 	ret = regmap_read(miim->regs,
80 			  MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
81 	if (ret < 0) {
82 		WARN_ONCE(1, "mscc miim status read error %d\n", ret);
83 		return ret;
84 	}
85 
86 	return val;
87 }
88 
mscc_miim_wait_ready(struct mii_bus * bus)89 static int mscc_miim_wait_ready(struct mii_bus *bus)
90 {
91 	u32 val;
92 
93 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
94 				       !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
95 				       10000);
96 }
97 
mscc_miim_wait_pending(struct mii_bus * bus)98 static int mscc_miim_wait_pending(struct mii_bus *bus)
99 {
100 	u32 val;
101 
102 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
103 				       !(val & MSCC_MIIM_STATUS_STAT_PENDING),
104 				       50, 10000);
105 }
106 
mscc_miim_read(struct mii_bus * bus,int mii_id,int regnum)107 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
108 {
109 	struct mscc_miim_dev *miim = bus->priv;
110 	u32 val;
111 	int ret;
112 
113 	ret = mscc_miim_wait_pending(bus);
114 	if (ret)
115 		goto out;
116 
117 	ret = regmap_write(miim->regs,
118 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
119 			   MSCC_MIIM_CMD_VLD |
120 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
121 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
122 			   MSCC_MIIM_CMD_OPR_READ);
123 
124 	if (ret < 0) {
125 		WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
126 		goto out;
127 	}
128 
129 	ret = mscc_miim_wait_ready(bus);
130 	if (ret)
131 		goto out;
132 
133 	ret = regmap_read(miim->regs,
134 			  MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
135 	if (ret < 0) {
136 		WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
137 		goto out;
138 	}
139 
140 	if (!miim->ignore_read_errors && !!(val & MSCC_MIIM_DATA_ERROR)) {
141 		ret = -EIO;
142 		goto out;
143 	}
144 
145 	ret = val & 0xFFFF;
146 out:
147 	return ret;
148 }
149 
mscc_miim_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)150 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
151 			   int regnum, u16 value)
152 {
153 	struct mscc_miim_dev *miim = bus->priv;
154 	int ret;
155 
156 	ret = mscc_miim_wait_pending(bus);
157 	if (ret < 0)
158 		goto out;
159 
160 	ret = regmap_write(miim->regs,
161 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
162 			   MSCC_MIIM_CMD_VLD |
163 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
164 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
165 			   (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
166 			   MSCC_MIIM_CMD_OPR_WRITE);
167 
168 	if (ret < 0)
169 		WARN_ONCE(1, "mscc miim write error %d\n", ret);
170 out:
171 	return ret;
172 }
173 
mscc_miim_reset(struct mii_bus * bus)174 static int mscc_miim_reset(struct mii_bus *bus)
175 {
176 	struct mscc_miim_dev *miim = bus->priv;
177 	unsigned int offset, bits;
178 	int ret;
179 
180 	if (!miim->phy_regs)
181 		return 0;
182 
183 	offset = miim->info->phy_reset_offset;
184 	bits = miim->info->phy_reset_bits;
185 
186 	ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
187 	if (ret < 0) {
188 		WARN_ONCE(1, "mscc reset set error %d\n", ret);
189 		return ret;
190 	}
191 
192 	ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
193 	if (ret < 0) {
194 		WARN_ONCE(1, "mscc reset clear error %d\n", ret);
195 		return ret;
196 	}
197 
198 	mdelay(500);
199 
200 	return 0;
201 }
202 
203 static const struct regmap_config mscc_miim_regmap_config = {
204 	.reg_bits	= 32,
205 	.val_bits	= 32,
206 	.reg_stride	= 4,
207 };
208 
209 static const struct regmap_config mscc_miim_phy_regmap_config = {
210 	.reg_bits	= 32,
211 	.val_bits	= 32,
212 	.reg_stride	= 4,
213 	.name		= "phy",
214 };
215 
mscc_miim_setup(struct device * dev,struct mii_bus ** pbus,const char * name,struct regmap * mii_regmap,int status_offset,bool ignore_read_errors)216 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
217 		    struct regmap *mii_regmap, int status_offset,
218 		    bool ignore_read_errors)
219 {
220 	struct mscc_miim_dev *miim;
221 	struct mii_bus *bus;
222 
223 	bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
224 	if (!bus)
225 		return -ENOMEM;
226 
227 	bus->name = name;
228 	bus->read = mscc_miim_read;
229 	bus->write = mscc_miim_write;
230 	bus->reset = mscc_miim_reset;
231 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
232 	bus->parent = dev;
233 
234 	miim = bus->priv;
235 
236 	*pbus = bus;
237 
238 	miim->regs = mii_regmap;
239 	miim->mii_status_offset = status_offset;
240 	miim->ignore_read_errors = ignore_read_errors;
241 
242 	*pbus = bus;
243 
244 	return 0;
245 }
246 EXPORT_SYMBOL(mscc_miim_setup);
247 
mscc_miim_clk_set(struct mii_bus * bus)248 static int mscc_miim_clk_set(struct mii_bus *bus)
249 {
250 	struct mscc_miim_dev *miim = bus->priv;
251 	unsigned long rate;
252 	u32 div;
253 
254 	/* Keep the current settings */
255 	if (!miim->bus_freq)
256 		return 0;
257 
258 	rate = clk_get_rate(miim->clk);
259 
260 	div = DIV_ROUND_UP(rate, 2 * miim->bus_freq) - 1;
261 	if (div == 0 || div & ~MSCC_MIIM_CFG_PRESCALE_MASK) {
262 		dev_err(&bus->dev, "Incorrect MDIO clock frequency\n");
263 		return -EINVAL;
264 	}
265 
266 	return regmap_update_bits(miim->regs, MSCC_MIIM_REG_CFG,
267 				  MSCC_MIIM_CFG_PRESCALE_MASK, div);
268 }
269 
mscc_miim_probe(struct platform_device * pdev)270 static int mscc_miim_probe(struct platform_device *pdev)
271 {
272 	struct device_node *np = pdev->dev.of_node;
273 	struct regmap *mii_regmap, *phy_regmap;
274 	struct device *dev = &pdev->dev;
275 	struct reset_control *reset;
276 	struct mscc_miim_dev *miim;
277 	struct mii_bus *bus;
278 	int ret;
279 
280 	reset = devm_reset_control_get_optional_shared(dev, "switch");
281 	if (IS_ERR(reset))
282 		return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
283 
284 	reset_control_reset(reset);
285 
286 	mii_regmap = ocelot_regmap_from_resource(pdev, 0,
287 						 &mscc_miim_regmap_config);
288 	if (IS_ERR(mii_regmap))
289 		return dev_err_probe(dev, PTR_ERR(mii_regmap),
290 				     "Unable to create MIIM regmap\n");
291 
292 	/* This resource is optional */
293 	phy_regmap = ocelot_regmap_from_resource_optional(pdev, 1,
294 						 &mscc_miim_phy_regmap_config);
295 	if (IS_ERR(phy_regmap))
296 		return dev_err_probe(dev, PTR_ERR(phy_regmap),
297 				     "Unable to create phy register regmap\n");
298 
299 	ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0, false);
300 	if (ret < 0) {
301 		dev_err(dev, "Unable to setup the MDIO bus\n");
302 		return ret;
303 	}
304 
305 	miim = bus->priv;
306 	miim->phy_regs = phy_regmap;
307 
308 	miim->info = device_get_match_data(dev);
309 	if (!miim->info)
310 		return -EINVAL;
311 
312 	miim->clk = devm_clk_get_optional(dev, NULL);
313 	if (IS_ERR(miim->clk))
314 		return PTR_ERR(miim->clk);
315 
316 	of_property_read_u32(np, "clock-frequency", &miim->bus_freq);
317 
318 	if (miim->bus_freq && !miim->clk) {
319 		dev_err(dev, "cannot use clock-frequency without a clock\n");
320 		return -EINVAL;
321 	}
322 
323 	ret = clk_prepare_enable(miim->clk);
324 	if (ret)
325 		return ret;
326 
327 	ret = mscc_miim_clk_set(bus);
328 	if (ret)
329 		goto out_disable_clk;
330 
331 	ret = of_mdiobus_register(bus, np);
332 	if (ret < 0) {
333 		dev_err(dev, "Cannot register MDIO bus (%d)\n", ret);
334 		goto out_disable_clk;
335 	}
336 
337 	platform_set_drvdata(pdev, bus);
338 
339 	return 0;
340 
341 out_disable_clk:
342 	clk_disable_unprepare(miim->clk);
343 	return ret;
344 }
345 
mscc_miim_remove(struct platform_device * pdev)346 static void mscc_miim_remove(struct platform_device *pdev)
347 {
348 	struct mii_bus *bus = platform_get_drvdata(pdev);
349 	struct mscc_miim_dev *miim = bus->priv;
350 
351 	clk_disable_unprepare(miim->clk);
352 	mdiobus_unregister(bus);
353 }
354 
355 static const struct mscc_miim_info mscc_ocelot_miim_info = {
356 	.phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
357 	.phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
358 			  PHY_CFG_PHY_RESET,
359 };
360 
361 static const struct mscc_miim_info microchip_lan966x_miim_info = {
362 	.phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
363 	.phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
364 };
365 
366 static const struct of_device_id mscc_miim_match[] = {
367 	{
368 		.compatible = "mscc,ocelot-miim",
369 		.data = &mscc_ocelot_miim_info
370 	}, {
371 		.compatible = "microchip,lan966x-miim",
372 		.data = &microchip_lan966x_miim_info
373 	},
374 	{ }
375 };
376 MODULE_DEVICE_TABLE(of, mscc_miim_match);
377 
378 static struct platform_driver mscc_miim_driver = {
379 	.probe = mscc_miim_probe,
380 	.remove = mscc_miim_remove,
381 	.driver = {
382 		.name = "mscc-miim",
383 		.of_match_table = mscc_miim_match,
384 	},
385 };
386 
387 module_platform_driver(mscc_miim_driver);
388 
389 MODULE_DESCRIPTION("Microsemi MIIM driver");
390 MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
391 MODULE_LICENSE("Dual MIT/GPL");
392