1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/etherdevice.h>
5 #include <net/ip6_checksum.h>
6 #include <net/page_pool/helpers.h>
7 #include <net/inet_ecn.h>
8 #include <linux/iopoll.h>
9 #include <linux/sctp.h>
10 #include <linux/pci.h>
11 #include <net/tcp.h>
12 #include <net/ip.h>
13
14 #include "wx_type.h"
15 #include "wx_lib.h"
16 #include "wx_hw.h"
17
18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
19 static struct wx_dec_ptype wx_ptype_lookup[256] = {
20 /* L2: mac */
21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
28
29 /* L2: ethertype filter */
30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
31
32 /* L3: ip non-tunnel */
33 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3),
34 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3),
35 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4),
36 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4),
37 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4),
38 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3),
39 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3),
40 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3),
41 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4),
42 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4),
43
44 /* L2: fcoe */
45 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
46 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
47
48 /* IPv4 --> IPv4/IPv6 */
49 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3),
50 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3),
51 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4),
52 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4),
53 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4),
54 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3),
55 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3),
56 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4),
57 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4),
58 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4),
59
60 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */
61 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3),
62 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3),
63 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3),
64 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4),
65 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4),
66 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4),
67 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3),
68 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3),
69 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4),
70 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4),
71 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4),
72
73 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */
74 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3),
75 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3),
76 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3),
77 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4),
78 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4),
79 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4),
80 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3),
81 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3),
82 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4),
83 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4),
84 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4),
85
86 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */
87 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3),
88 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3),
89 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3),
90 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4),
91 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4),
92 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4),
93 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3),
94 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3),
95 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4),
96 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4),
97 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4),
98
99 /* IPv6 --> IPv4/IPv6 */
100 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3),
101 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3),
102 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4),
103 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4),
104 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4),
105 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3),
106 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3),
107 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4),
108 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4),
109 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4),
110
111 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */
112 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3),
113 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3),
114 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3),
115 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4),
116 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4),
117 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4),
118 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3),
119 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3),
120 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4),
121 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4),
122 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4),
123
124 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */
125 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3),
126 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3),
127 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3),
128 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4),
129 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4),
130 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4),
131 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3),
132 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3),
133 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4),
134 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4),
135 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4),
136
137 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */
138 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3),
139 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3),
140 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3),
141 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4),
142 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4),
143 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4),
144 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3),
145 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3),
146 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4),
147 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4),
148 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4),
149 };
150
wx_decode_ptype(const u8 ptype)151 struct wx_dec_ptype wx_decode_ptype(const u8 ptype)
152 {
153 return wx_ptype_lookup[ptype];
154 }
155 EXPORT_SYMBOL(wx_decode_ptype);
156
157 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */
wx_test_staterr(union wx_rx_desc * rx_desc,const u32 stat_err_bits)158 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
159 const u32 stat_err_bits)
160 {
161 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
162 }
163
wx_dma_sync_frag(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer)164 static void wx_dma_sync_frag(struct wx_ring *rx_ring,
165 struct wx_rx_buffer *rx_buffer)
166 {
167 struct sk_buff *skb = rx_buffer->skb;
168 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
169
170 dma_sync_single_range_for_cpu(rx_ring->dev,
171 WX_CB(skb)->dma,
172 skb_frag_off(frag),
173 skb_frag_size(frag),
174 DMA_FROM_DEVICE);
175
176 /* If the page was released, just unmap it. */
177 if (unlikely(WX_CB(skb)->page_released))
178 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
179 }
180
wx_get_rx_buffer(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff ** skb,int * rx_buffer_pgcnt)181 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
182 union wx_rx_desc *rx_desc,
183 struct sk_buff **skb,
184 int *rx_buffer_pgcnt)
185 {
186 struct wx_rx_buffer *rx_buffer;
187 unsigned int size;
188
189 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
190 size = le16_to_cpu(rx_desc->wb.upper.length);
191
192 #if (PAGE_SIZE < 8192)
193 *rx_buffer_pgcnt = page_count(rx_buffer->page);
194 #else
195 *rx_buffer_pgcnt = 0;
196 #endif
197
198 prefetchw(rx_buffer->page);
199 *skb = rx_buffer->skb;
200
201 /* Delay unmapping of the first packet. It carries the header
202 * information, HW may still access the header after the writeback.
203 * Only unmap it when EOP is reached
204 */
205 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
206 if (!*skb)
207 goto skip_sync;
208 } else {
209 if (*skb)
210 wx_dma_sync_frag(rx_ring, rx_buffer);
211 }
212
213 /* we are reusing so sync this buffer for CPU use */
214 dma_sync_single_range_for_cpu(rx_ring->dev,
215 rx_buffer->dma,
216 rx_buffer->page_offset,
217 size,
218 DMA_FROM_DEVICE);
219 skip_sync:
220 return rx_buffer;
221 }
222
wx_put_rx_buffer(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,struct sk_buff * skb,int rx_buffer_pgcnt)223 static void wx_put_rx_buffer(struct wx_ring *rx_ring,
224 struct wx_rx_buffer *rx_buffer,
225 struct sk_buff *skb,
226 int rx_buffer_pgcnt)
227 {
228 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma)
229 /* the page has been released from the ring */
230 WX_CB(skb)->page_released = true;
231
232 /* clear contents of rx_buffer */
233 rx_buffer->page = NULL;
234 rx_buffer->skb = NULL;
235 }
236
wx_build_skb(struct wx_ring * rx_ring,struct wx_rx_buffer * rx_buffer,union wx_rx_desc * rx_desc)237 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
238 struct wx_rx_buffer *rx_buffer,
239 union wx_rx_desc *rx_desc)
240 {
241 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
242 #if (PAGE_SIZE < 8192)
243 unsigned int truesize = WX_RX_BUFSZ;
244 #else
245 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
246 #endif
247 struct sk_buff *skb = rx_buffer->skb;
248
249 if (!skb) {
250 void *page_addr = page_address(rx_buffer->page) +
251 rx_buffer->page_offset;
252
253 /* prefetch first cache line of first page */
254 net_prefetch(page_addr);
255
256 /* allocate a skb to store the frags */
257 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
258 if (unlikely(!skb))
259 return NULL;
260
261 /* we will be copying header into skb->data in
262 * pskb_may_pull so it is in our interest to prefetch
263 * it now to avoid a possible cache miss
264 */
265 prefetchw(skb->data);
266
267 if (size <= WX_RXBUFFER_256) {
268 memcpy(__skb_put(skb, size), page_addr,
269 ALIGN(size, sizeof(long)));
270 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true);
271 return skb;
272 }
273
274 skb_mark_for_recycle(skb);
275
276 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
277 WX_CB(skb)->dma = rx_buffer->dma;
278
279 skb_add_rx_frag(skb, 0, rx_buffer->page,
280 rx_buffer->page_offset,
281 size, truesize);
282 goto out;
283
284 } else {
285 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
286 rx_buffer->page_offset, size, truesize);
287 }
288
289 out:
290 #if (PAGE_SIZE < 8192)
291 /* flip page offset to other buffer */
292 rx_buffer->page_offset ^= truesize;
293 #else
294 /* move offset up to the next cache line */
295 rx_buffer->page_offset += truesize;
296 #endif
297
298 return skb;
299 }
300
wx_alloc_mapped_page(struct wx_ring * rx_ring,struct wx_rx_buffer * bi)301 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
302 struct wx_rx_buffer *bi)
303 {
304 struct page *page = bi->page;
305 dma_addr_t dma;
306
307 /* since we are recycling buffers we should seldom need to alloc */
308 if (likely(page))
309 return true;
310
311 page = page_pool_dev_alloc_pages(rx_ring->page_pool);
312 if (unlikely(!page))
313 return false;
314 dma = page_pool_get_dma_addr(page);
315
316 bi->page_dma = dma;
317 bi->page = page;
318 bi->page_offset = 0;
319
320 return true;
321 }
322
323 /**
324 * wx_alloc_rx_buffers - Replace used receive buffers
325 * @rx_ring: ring to place buffers on
326 * @cleaned_count: number of buffers to replace
327 **/
wx_alloc_rx_buffers(struct wx_ring * rx_ring,u16 cleaned_count)328 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
329 {
330 u16 i = rx_ring->next_to_use;
331 union wx_rx_desc *rx_desc;
332 struct wx_rx_buffer *bi;
333
334 /* nothing to do */
335 if (!cleaned_count)
336 return;
337
338 rx_desc = WX_RX_DESC(rx_ring, i);
339 bi = &rx_ring->rx_buffer_info[i];
340 i -= rx_ring->count;
341
342 do {
343 if (!wx_alloc_mapped_page(rx_ring, bi))
344 break;
345
346 /* sync the buffer for use by the device */
347 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
348 bi->page_offset,
349 WX_RX_BUFSZ,
350 DMA_FROM_DEVICE);
351
352 rx_desc->read.pkt_addr =
353 cpu_to_le64(bi->page_dma + bi->page_offset);
354
355 rx_desc++;
356 bi++;
357 i++;
358 if (unlikely(!i)) {
359 rx_desc = WX_RX_DESC(rx_ring, 0);
360 bi = rx_ring->rx_buffer_info;
361 i -= rx_ring->count;
362 }
363
364 /* clear the status bits for the next_to_use descriptor */
365 rx_desc->wb.upper.status_error = 0;
366
367 cleaned_count--;
368 } while (cleaned_count);
369
370 i += rx_ring->count;
371
372 if (rx_ring->next_to_use != i) {
373 rx_ring->next_to_use = i;
374 /* update next to alloc since we have filled the ring */
375 rx_ring->next_to_alloc = i;
376
377 /* Force memory writes to complete before letting h/w
378 * know there are new descriptors to fetch. (Only
379 * applicable for weak-ordered memory model archs,
380 * such as IA-64).
381 */
382 wmb();
383 writel(i, rx_ring->tail);
384 }
385 }
386
wx_desc_unused(struct wx_ring * ring)387 u16 wx_desc_unused(struct wx_ring *ring)
388 {
389 u16 ntc = ring->next_to_clean;
390 u16 ntu = ring->next_to_use;
391
392 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
393 }
394
395 /**
396 * wx_is_non_eop - process handling of non-EOP buffers
397 * @rx_ring: Rx ring being processed
398 * @rx_desc: Rx descriptor for current buffer
399 * @skb: Current socket buffer containing buffer in progress
400 *
401 * This function updates next to clean. If the buffer is an EOP buffer
402 * this function exits returning false, otherwise it will place the
403 * sk_buff in the next buffer to be chained and return true indicating
404 * that this is in fact a non-EOP buffer.
405 **/
wx_is_non_eop(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)406 static bool wx_is_non_eop(struct wx_ring *rx_ring,
407 union wx_rx_desc *rx_desc,
408 struct sk_buff *skb)
409 {
410 u32 ntc = rx_ring->next_to_clean + 1;
411
412 /* fetch, update, and store next to clean */
413 ntc = (ntc < rx_ring->count) ? ntc : 0;
414 rx_ring->next_to_clean = ntc;
415
416 prefetch(WX_RX_DESC(rx_ring, ntc));
417
418 /* if we are the last buffer then there is nothing else to do */
419 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
420 return false;
421
422 rx_ring->rx_buffer_info[ntc].skb = skb;
423 rx_ring->rx_stats.non_eop_descs++;
424
425 return true;
426 }
427
wx_pull_tail(struct sk_buff * skb)428 static void wx_pull_tail(struct sk_buff *skb)
429 {
430 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
431 unsigned int pull_len;
432 unsigned char *va;
433
434 /* it is valid to use page_address instead of kmap since we are
435 * working with pages allocated out of the lomem pool per
436 * alloc_page(GFP_ATOMIC)
437 */
438 va = skb_frag_address(frag);
439
440 /* we need the header to contain the greater of either ETH_HLEN or
441 * 60 bytes if the skb->len is less than 60 for skb_pad.
442 */
443 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
444
445 /* align pull length to size of long to optimize memcpy performance */
446 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
447
448 /* update all of the pointers */
449 skb_frag_size_sub(frag, pull_len);
450 skb_frag_off_add(frag, pull_len);
451 skb->data_len -= pull_len;
452 skb->tail += pull_len;
453 }
454
455 /**
456 * wx_cleanup_headers - Correct corrupted or empty headers
457 * @rx_ring: rx descriptor ring packet is being transacted on
458 * @rx_desc: pointer to the EOP Rx descriptor
459 * @skb: pointer to current skb being fixed
460 *
461 * Check for corrupted packet headers caused by senders on the local L2
462 * embedded NIC switch not setting up their Tx Descriptors right. These
463 * should be very rare.
464 *
465 * Also address the case where we are pulling data in on pages only
466 * and as such no data is present in the skb header.
467 *
468 * In addition if skb is not at least 60 bytes we need to pad it so that
469 * it is large enough to qualify as a valid Ethernet frame.
470 *
471 * Returns true if an error was encountered and skb was freed.
472 **/
wx_cleanup_headers(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)473 static bool wx_cleanup_headers(struct wx_ring *rx_ring,
474 union wx_rx_desc *rx_desc,
475 struct sk_buff *skb)
476 {
477 struct net_device *netdev = rx_ring->netdev;
478
479 /* verify that the packet does not have any known errors */
480 if (!netdev ||
481 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
482 !(netdev->features & NETIF_F_RXALL))) {
483 dev_kfree_skb_any(skb);
484 return true;
485 }
486
487 /* place header in linear portion of buffer */
488 if (!skb_headlen(skb))
489 wx_pull_tail(skb);
490
491 /* if eth_skb_pad returns an error the skb was freed */
492 if (eth_skb_pad(skb))
493 return true;
494
495 return false;
496 }
497
wx_rx_hash(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)498 static void wx_rx_hash(struct wx_ring *ring,
499 union wx_rx_desc *rx_desc,
500 struct sk_buff *skb)
501 {
502 u16 rss_type;
503
504 if (!(ring->netdev->features & NETIF_F_RXHASH))
505 return;
506
507 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
508 WX_RXD_RSSTYPE_MASK;
509
510 if (!rss_type)
511 return;
512
513 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
514 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
515 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
516 }
517
518 /**
519 * wx_rx_checksum - indicate in skb if hw indicated a good cksum
520 * @ring: structure containing ring specific data
521 * @rx_desc: current Rx descriptor being processed
522 * @skb: skb currently being received and modified
523 **/
wx_rx_checksum(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)524 static void wx_rx_checksum(struct wx_ring *ring,
525 union wx_rx_desc *rx_desc,
526 struct sk_buff *skb)
527 {
528 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc));
529
530 skb_checksum_none_assert(skb);
531 /* Rx csum disabled */
532 if (!(ring->netdev->features & NETIF_F_RXCSUM))
533 return;
534
535 /* if IPv4 header checksum error */
536 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) &&
537 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) ||
538 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) &&
539 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) {
540 ring->rx_stats.csum_err++;
541 return;
542 }
543
544 /* L4 checksum offload flag must set for the below code to work */
545 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS))
546 return;
547
548 /* Hardware can't guarantee csum if IPv6 Dest Header found */
549 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP &&
550 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX))
551 return;
552
553 /* if L4 checksum error */
554 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) {
555 ring->rx_stats.csum_err++;
556 return;
557 }
558
559 /* It must be a TCP or UDP or SCTP packet with a valid checksum */
560 skb->ip_summed = CHECKSUM_UNNECESSARY;
561
562 /* If there is an outer header present that might contain a checksum
563 * we need to bump the checksum level by 1 to reflect the fact that
564 * we are indicating we validated the inner checksum.
565 */
566 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG)
567 __skb_incr_checksum_unnecessary(skb);
568 ring->rx_stats.csum_good_cnt++;
569 }
570
wx_rx_vlan(struct wx_ring * ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)571 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
572 struct sk_buff *skb)
573 {
574 u16 ethertype;
575 u8 idx = 0;
576
577 if ((ring->netdev->features &
578 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) &&
579 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) {
580 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
581 0x1c0) >> 6;
582 ethertype = ring->q_vector->wx->tpid[idx];
583 __vlan_hwaccel_put_tag(skb, htons(ethertype),
584 le16_to_cpu(rx_desc->wb.upper.vlan));
585 }
586 }
587
588 /**
589 * wx_process_skb_fields - Populate skb header fields from Rx descriptor
590 * @rx_ring: rx descriptor ring packet is being transacted on
591 * @rx_desc: pointer to the EOP Rx descriptor
592 * @skb: pointer to current skb being populated
593 *
594 * This function checks the ring, descriptor, and packet information in
595 * order to populate the hash, checksum, protocol, and
596 * other fields within the skb.
597 **/
wx_process_skb_fields(struct wx_ring * rx_ring,union wx_rx_desc * rx_desc,struct sk_buff * skb)598 static void wx_process_skb_fields(struct wx_ring *rx_ring,
599 union wx_rx_desc *rx_desc,
600 struct sk_buff *skb)
601 {
602 wx_rx_hash(rx_ring, rx_desc, skb);
603 wx_rx_checksum(rx_ring, rx_desc, skb);
604 wx_rx_vlan(rx_ring, rx_desc, skb);
605 skb_record_rx_queue(skb, rx_ring->queue_index);
606 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
607 }
608
609 /**
610 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
611 * @q_vector: structure containing interrupt and ring information
612 * @rx_ring: rx descriptor ring to transact packets on
613 * @budget: Total limit on number of packets to process
614 *
615 * This function provides a "bounce buffer" approach to Rx interrupt
616 * processing. The advantage to this is that on systems that have
617 * expensive overhead for IOMMU access this provides a means of avoiding
618 * it by maintaining the mapping of the page to the system.
619 *
620 * Returns amount of work completed.
621 **/
wx_clean_rx_irq(struct wx_q_vector * q_vector,struct wx_ring * rx_ring,int budget)622 static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
623 struct wx_ring *rx_ring,
624 int budget)
625 {
626 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
627 u16 cleaned_count = wx_desc_unused(rx_ring);
628
629 do {
630 struct wx_rx_buffer *rx_buffer;
631 union wx_rx_desc *rx_desc;
632 struct sk_buff *skb;
633 int rx_buffer_pgcnt;
634
635 /* return some buffers to hardware, one at a time is too slow */
636 if (cleaned_count >= WX_RX_BUFFER_WRITE) {
637 wx_alloc_rx_buffers(rx_ring, cleaned_count);
638 cleaned_count = 0;
639 }
640
641 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
642 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
643 break;
644
645 /* This memory barrier is needed to keep us from reading
646 * any other fields out of the rx_desc until we know the
647 * descriptor has been written back
648 */
649 dma_rmb();
650
651 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
652
653 /* retrieve a buffer from the ring */
654 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
655
656 /* exit if we failed to retrieve a buffer */
657 if (!skb) {
658 rx_ring->rx_stats.alloc_rx_buff_failed++;
659 break;
660 }
661
662 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
663 cleaned_count++;
664
665 /* place incomplete frames back on ring for completion */
666 if (wx_is_non_eop(rx_ring, rx_desc, skb))
667 continue;
668
669 /* verify the packet layout is correct */
670 if (wx_cleanup_headers(rx_ring, rx_desc, skb))
671 continue;
672
673 /* probably a little skewed due to removing CRC */
674 total_rx_bytes += skb->len;
675
676 /* populate checksum, timestamp, VLAN, and protocol */
677 wx_process_skb_fields(rx_ring, rx_desc, skb);
678 napi_gro_receive(&q_vector->napi, skb);
679
680 /* update budget accounting */
681 total_rx_packets++;
682 } while (likely(total_rx_packets < budget));
683
684 u64_stats_update_begin(&rx_ring->syncp);
685 rx_ring->stats.packets += total_rx_packets;
686 rx_ring->stats.bytes += total_rx_bytes;
687 u64_stats_update_end(&rx_ring->syncp);
688 q_vector->rx.total_packets += total_rx_packets;
689 q_vector->rx.total_bytes += total_rx_bytes;
690
691 return total_rx_packets;
692 }
693
wx_txring_txq(const struct wx_ring * ring)694 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
695 {
696 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
697 }
698
699 /**
700 * wx_clean_tx_irq - Reclaim resources after transmit completes
701 * @q_vector: structure containing interrupt and ring information
702 * @tx_ring: tx ring to clean
703 * @napi_budget: Used to determine if we are in netpoll
704 **/
wx_clean_tx_irq(struct wx_q_vector * q_vector,struct wx_ring * tx_ring,int napi_budget)705 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
706 struct wx_ring *tx_ring, int napi_budget)
707 {
708 unsigned int budget = q_vector->wx->tx_work_limit;
709 unsigned int total_bytes = 0, total_packets = 0;
710 unsigned int i = tx_ring->next_to_clean;
711 struct wx_tx_buffer *tx_buffer;
712 union wx_tx_desc *tx_desc;
713
714 if (!netif_carrier_ok(tx_ring->netdev))
715 return true;
716
717 tx_buffer = &tx_ring->tx_buffer_info[i];
718 tx_desc = WX_TX_DESC(tx_ring, i);
719 i -= tx_ring->count;
720
721 do {
722 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
723
724 /* if next_to_watch is not set then there is no work pending */
725 if (!eop_desc)
726 break;
727
728 /* prevent any other reads prior to eop_desc */
729 smp_rmb();
730
731 /* if DD is not set pending work has not been completed */
732 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
733 break;
734
735 /* clear next_to_watch to prevent false hangs */
736 tx_buffer->next_to_watch = NULL;
737
738 /* update the statistics for this packet */
739 total_bytes += tx_buffer->bytecount;
740 total_packets += tx_buffer->gso_segs;
741
742 /* free the skb */
743 napi_consume_skb(tx_buffer->skb, napi_budget);
744
745 /* unmap skb header data */
746 dma_unmap_single(tx_ring->dev,
747 dma_unmap_addr(tx_buffer, dma),
748 dma_unmap_len(tx_buffer, len),
749 DMA_TO_DEVICE);
750
751 /* clear tx_buffer data */
752 dma_unmap_len_set(tx_buffer, len, 0);
753
754 /* unmap remaining buffers */
755 while (tx_desc != eop_desc) {
756 tx_buffer++;
757 tx_desc++;
758 i++;
759 if (unlikely(!i)) {
760 i -= tx_ring->count;
761 tx_buffer = tx_ring->tx_buffer_info;
762 tx_desc = WX_TX_DESC(tx_ring, 0);
763 }
764
765 /* unmap any remaining paged data */
766 if (dma_unmap_len(tx_buffer, len)) {
767 dma_unmap_page(tx_ring->dev,
768 dma_unmap_addr(tx_buffer, dma),
769 dma_unmap_len(tx_buffer, len),
770 DMA_TO_DEVICE);
771 dma_unmap_len_set(tx_buffer, len, 0);
772 }
773 }
774
775 /* move us one more past the eop_desc for start of next pkt */
776 tx_buffer++;
777 tx_desc++;
778 i++;
779 if (unlikely(!i)) {
780 i -= tx_ring->count;
781 tx_buffer = tx_ring->tx_buffer_info;
782 tx_desc = WX_TX_DESC(tx_ring, 0);
783 }
784
785 /* issue prefetch for next Tx descriptor */
786 prefetch(tx_desc);
787
788 /* update budget accounting */
789 budget--;
790 } while (likely(budget));
791
792 i += tx_ring->count;
793 tx_ring->next_to_clean = i;
794 u64_stats_update_begin(&tx_ring->syncp);
795 tx_ring->stats.bytes += total_bytes;
796 tx_ring->stats.packets += total_packets;
797 u64_stats_update_end(&tx_ring->syncp);
798 q_vector->tx.total_bytes += total_bytes;
799 q_vector->tx.total_packets += total_packets;
800
801 netdev_tx_completed_queue(wx_txring_txq(tx_ring),
802 total_packets, total_bytes);
803
804 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
805 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
806 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
807 /* Make sure that anybody stopping the queue after this
808 * sees the new next_to_clean.
809 */
810 smp_mb();
811
812 if (__netif_subqueue_stopped(tx_ring->netdev,
813 tx_ring->queue_index) &&
814 netif_running(tx_ring->netdev)) {
815 netif_wake_subqueue(tx_ring->netdev,
816 tx_ring->queue_index);
817 ++tx_ring->tx_stats.restart_queue;
818 }
819 }
820
821 return !!budget;
822 }
823
824 /**
825 * wx_poll - NAPI polling RX/TX cleanup routine
826 * @napi: napi struct with our devices info in it
827 * @budget: amount of work driver is allowed to do this pass, in packets
828 *
829 * This function will clean all queues associated with a q_vector.
830 **/
wx_poll(struct napi_struct * napi,int budget)831 static int wx_poll(struct napi_struct *napi, int budget)
832 {
833 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
834 int per_ring_budget, work_done = 0;
835 struct wx *wx = q_vector->wx;
836 bool clean_complete = true;
837 struct wx_ring *ring;
838
839 wx_for_each_ring(ring, q_vector->tx) {
840 if (!wx_clean_tx_irq(q_vector, ring, budget))
841 clean_complete = false;
842 }
843
844 /* Exit if we are called by netpoll */
845 if (budget <= 0)
846 return budget;
847
848 /* attempt to distribute budget to each queue fairly, but don't allow
849 * the budget to go below 1 because we'll exit polling
850 */
851 if (q_vector->rx.count > 1)
852 per_ring_budget = max(budget / q_vector->rx.count, 1);
853 else
854 per_ring_budget = budget;
855
856 wx_for_each_ring(ring, q_vector->rx) {
857 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
858
859 work_done += cleaned;
860 if (cleaned >= per_ring_budget)
861 clean_complete = false;
862 }
863
864 /* If all work not completed, return budget and keep polling */
865 if (!clean_complete)
866 return budget;
867
868 /* all work done, exit the polling mode */
869 if (likely(napi_complete_done(napi, work_done))) {
870 if (netif_running(wx->netdev))
871 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
872 }
873
874 return min(work_done, budget - 1);
875 }
876
wx_maybe_stop_tx(struct wx_ring * tx_ring,u16 size)877 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
878 {
879 if (likely(wx_desc_unused(tx_ring) >= size))
880 return 0;
881
882 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
883
884 /* For the next check */
885 smp_mb();
886
887 /* We need to check again in a case another CPU has just
888 * made room available.
889 */
890 if (likely(wx_desc_unused(tx_ring) < size))
891 return -EBUSY;
892
893 /* A reprieve! - use start_queue because it doesn't call schedule */
894 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
895 ++tx_ring->tx_stats.restart_queue;
896
897 return 0;
898 }
899
wx_tx_cmd_type(u32 tx_flags)900 static u32 wx_tx_cmd_type(u32 tx_flags)
901 {
902 /* set type for advanced descriptor with frame checksum insertion */
903 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
904
905 /* set HW vlan bit if vlan is present */
906 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE);
907 /* set segmentation enable bits for TSO/FSO */
908 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE);
909 /* set timestamp bit if present */
910 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP);
911 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC);
912
913 return cmd_type;
914 }
915
wx_tx_olinfo_status(union wx_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)916 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc,
917 u32 tx_flags, unsigned int paylen)
918 {
919 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT;
920
921 /* enable L4 checksum for TSO and TX checksum offload */
922 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS);
923 /* enable IPv4 checksum for TSO */
924 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS);
925 /* enable outer IPv4 checksum for TSO */
926 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4,
927 WX_TXD_EIPCS);
928 /* Check Context must be set if Tx switch is enabled, which it
929 * always is for case where virtual functions are running
930 */
931 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC);
932 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC,
933 WX_TXD_IPSEC);
934 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
935 }
936
wx_tx_map(struct wx_ring * tx_ring,struct wx_tx_buffer * first,const u8 hdr_len)937 static void wx_tx_map(struct wx_ring *tx_ring,
938 struct wx_tx_buffer *first,
939 const u8 hdr_len)
940 {
941 struct sk_buff *skb = first->skb;
942 struct wx_tx_buffer *tx_buffer;
943 u32 tx_flags = first->tx_flags;
944 u16 i = tx_ring->next_to_use;
945 unsigned int data_len, size;
946 union wx_tx_desc *tx_desc;
947 skb_frag_t *frag;
948 dma_addr_t dma;
949 u32 cmd_type;
950
951 cmd_type = wx_tx_cmd_type(tx_flags);
952 tx_desc = WX_TX_DESC(tx_ring, i);
953 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
954
955 size = skb_headlen(skb);
956 data_len = skb->data_len;
957 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
958
959 tx_buffer = first;
960
961 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
962 if (dma_mapping_error(tx_ring->dev, dma))
963 goto dma_error;
964
965 /* record length, and DMA address */
966 dma_unmap_len_set(tx_buffer, len, size);
967 dma_unmap_addr_set(tx_buffer, dma, dma);
968
969 tx_desc->read.buffer_addr = cpu_to_le64(dma);
970
971 while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
972 tx_desc->read.cmd_type_len =
973 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
974
975 i++;
976 tx_desc++;
977 if (i == tx_ring->count) {
978 tx_desc = WX_TX_DESC(tx_ring, 0);
979 i = 0;
980 }
981 tx_desc->read.olinfo_status = 0;
982
983 dma += WX_MAX_DATA_PER_TXD;
984 size -= WX_MAX_DATA_PER_TXD;
985
986 tx_desc->read.buffer_addr = cpu_to_le64(dma);
987 }
988
989 if (likely(!data_len))
990 break;
991
992 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
993
994 i++;
995 tx_desc++;
996 if (i == tx_ring->count) {
997 tx_desc = WX_TX_DESC(tx_ring, 0);
998 i = 0;
999 }
1000 tx_desc->read.olinfo_status = 0;
1001
1002 size = skb_frag_size(frag);
1003
1004 data_len -= size;
1005
1006 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1007 DMA_TO_DEVICE);
1008
1009 tx_buffer = &tx_ring->tx_buffer_info[i];
1010 }
1011
1012 /* write last descriptor with RS and EOP bits */
1013 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
1014 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1015
1016 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
1017
1018 skb_tx_timestamp(skb);
1019
1020 /* Force memory writes to complete before letting h/w know there
1021 * are new descriptors to fetch. (Only applicable for weak-ordered
1022 * memory model archs, such as IA-64).
1023 *
1024 * We also need this memory barrier to make certain all of the
1025 * status bits have been updated before next_to_watch is written.
1026 */
1027 wmb();
1028
1029 /* set next_to_watch value indicating a packet is present */
1030 first->next_to_watch = tx_desc;
1031
1032 i++;
1033 if (i == tx_ring->count)
1034 i = 0;
1035
1036 tx_ring->next_to_use = i;
1037
1038 wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
1039
1040 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
1041 writel(i, tx_ring->tail);
1042
1043 return;
1044 dma_error:
1045 dev_err(tx_ring->dev, "TX DMA map failed\n");
1046
1047 /* clear dma mappings for failed tx_buffer_info map */
1048 for (;;) {
1049 tx_buffer = &tx_ring->tx_buffer_info[i];
1050 if (dma_unmap_len(tx_buffer, len))
1051 dma_unmap_page(tx_ring->dev,
1052 dma_unmap_addr(tx_buffer, dma),
1053 dma_unmap_len(tx_buffer, len),
1054 DMA_TO_DEVICE);
1055 dma_unmap_len_set(tx_buffer, len, 0);
1056 if (tx_buffer == first)
1057 break;
1058 if (i == 0)
1059 i += tx_ring->count;
1060 i--;
1061 }
1062
1063 dev_kfree_skb_any(first->skb);
1064 first->skb = NULL;
1065
1066 tx_ring->next_to_use = i;
1067 }
1068
wx_tx_ctxtdesc(struct wx_ring * tx_ring,u32 vlan_macip_lens,u32 fcoe_sof_eof,u32 type_tucmd,u32 mss_l4len_idx)1069 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens,
1070 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1071 {
1072 struct wx_tx_context_desc *context_desc;
1073 u16 i = tx_ring->next_to_use;
1074
1075 context_desc = WX_TX_CTXTDESC(tx_ring, i);
1076 i++;
1077 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1078
1079 /* set bits to identify this as an advanced context descriptor */
1080 type_tucmd |= WX_TXD_DTYP_CTXT;
1081 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1082 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1083 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1084 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
1085 }
1086
1087 union network_header {
1088 struct iphdr *ipv4;
1089 struct ipv6hdr *ipv6;
1090 void *raw;
1091 };
1092
wx_encode_tx_desc_ptype(const struct wx_tx_buffer * first)1093 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first)
1094 {
1095 u8 tun_prot = 0, l4_prot = 0, ptype = 0;
1096 struct sk_buff *skb = first->skb;
1097 unsigned char *exthdr, *l4_hdr;
1098 __be16 frag_off;
1099
1100 if (skb->encapsulation) {
1101 union network_header hdr;
1102
1103 switch (first->protocol) {
1104 case htons(ETH_P_IP):
1105 tun_prot = ip_hdr(skb)->protocol;
1106 ptype = WX_PTYPE_TUN_IPV4;
1107 break;
1108 case htons(ETH_P_IPV6):
1109 l4_hdr = skb_transport_header(skb);
1110 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1111 tun_prot = ipv6_hdr(skb)->nexthdr;
1112 if (l4_hdr != exthdr)
1113 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off);
1114 ptype = WX_PTYPE_TUN_IPV6;
1115 break;
1116 default:
1117 return ptype;
1118 }
1119
1120 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) {
1121 hdr.raw = (void *)inner_ip_hdr(skb);
1122 ptype |= WX_PTYPE_PKT_IPIP;
1123 } else if (tun_prot == IPPROTO_UDP) {
1124 hdr.raw = (void *)inner_ip_hdr(skb);
1125 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1126 skb->inner_protocol != htons(ETH_P_TEB)) {
1127 ptype |= WX_PTYPE_PKT_IG;
1128 } else {
1129 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1130 == htons(ETH_P_8021Q))
1131 ptype |= WX_PTYPE_PKT_IGMV;
1132 else
1133 ptype |= WX_PTYPE_PKT_IGM;
1134 }
1135
1136 } else if (tun_prot == IPPROTO_GRE) {
1137 hdr.raw = (void *)inner_ip_hdr(skb);
1138 if (skb->inner_protocol == htons(ETH_P_IP) ||
1139 skb->inner_protocol == htons(ETH_P_IPV6)) {
1140 ptype |= WX_PTYPE_PKT_IG;
1141 } else {
1142 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1143 == htons(ETH_P_8021Q))
1144 ptype |= WX_PTYPE_PKT_IGMV;
1145 else
1146 ptype |= WX_PTYPE_PKT_IGM;
1147 }
1148 } else {
1149 return ptype;
1150 }
1151
1152 switch (hdr.ipv4->version) {
1153 case IPVERSION:
1154 l4_prot = hdr.ipv4->protocol;
1155 break;
1156 case 6:
1157 l4_hdr = skb_inner_transport_header(skb);
1158 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr);
1159 l4_prot = inner_ipv6_hdr(skb)->nexthdr;
1160 if (l4_hdr != exthdr)
1161 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1162 ptype |= WX_PTYPE_PKT_IPV6;
1163 break;
1164 default:
1165 return ptype;
1166 }
1167 } else {
1168 switch (first->protocol) {
1169 case htons(ETH_P_IP):
1170 l4_prot = ip_hdr(skb)->protocol;
1171 ptype = WX_PTYPE_PKT_IP;
1172 break;
1173 case htons(ETH_P_IPV6):
1174 l4_hdr = skb_transport_header(skb);
1175 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1176 l4_prot = ipv6_hdr(skb)->nexthdr;
1177 if (l4_hdr != exthdr)
1178 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1179 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6;
1180 break;
1181 default:
1182 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC;
1183 }
1184 }
1185 switch (l4_prot) {
1186 case IPPROTO_TCP:
1187 ptype |= WX_PTYPE_TYP_TCP;
1188 break;
1189 case IPPROTO_UDP:
1190 ptype |= WX_PTYPE_TYP_UDP;
1191 break;
1192 case IPPROTO_SCTP:
1193 ptype |= WX_PTYPE_TYP_SCTP;
1194 break;
1195 default:
1196 ptype |= WX_PTYPE_TYP_IP;
1197 break;
1198 }
1199
1200 return ptype;
1201 }
1202
wx_tso(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 * hdr_len,u8 ptype)1203 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1204 u8 *hdr_len, u8 ptype)
1205 {
1206 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1207 struct net_device *netdev = tx_ring->netdev;
1208 u32 l4len, tunhdr_eiplen_tunlen = 0;
1209 struct sk_buff *skb = first->skb;
1210 bool enc = skb->encapsulation;
1211 struct ipv6hdr *ipv6h;
1212 struct tcphdr *tcph;
1213 struct iphdr *iph;
1214 u8 tun_prot = 0;
1215 int err;
1216
1217 if (skb->ip_summed != CHECKSUM_PARTIAL)
1218 return 0;
1219
1220 if (!skb_is_gso(skb))
1221 return 0;
1222
1223 err = skb_cow_head(skb, 0);
1224 if (err < 0)
1225 return err;
1226
1227 /* indicates the inner headers in the skbuff are valid. */
1228 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb);
1229 if (iph->version == 4) {
1230 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1231 iph->tot_len = 0;
1232 iph->check = 0;
1233 tcph->check = ~csum_tcpudp_magic(iph->saddr,
1234 iph->daddr, 0,
1235 IPPROTO_TCP, 0);
1236 first->tx_flags |= WX_TX_FLAGS_TSO |
1237 WX_TX_FLAGS_CSUM |
1238 WX_TX_FLAGS_IPV4 |
1239 WX_TX_FLAGS_CC;
1240 } else if (iph->version == 6 && skb_is_gso_v6(skb)) {
1241 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1242 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1243 ipv6h->payload_len = 0;
1244 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr,
1245 &ipv6h->daddr, 0,
1246 IPPROTO_TCP, 0);
1247 first->tx_flags |= WX_TX_FLAGS_TSO |
1248 WX_TX_FLAGS_CSUM |
1249 WX_TX_FLAGS_CC;
1250 }
1251
1252 /* compute header lengths */
1253 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1254 *hdr_len = enc ? skb_inner_transport_offset(skb) :
1255 skb_transport_offset(skb);
1256 *hdr_len += l4len;
1257
1258 /* update gso size and bytecount with header size */
1259 first->gso_segs = skb_shinfo(skb)->gso_segs;
1260 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1261
1262 /* mss_l4len_id: use 0 as index for TSO */
1263 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT;
1264 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT;
1265
1266 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
1267 if (enc) {
1268 unsigned char *exthdr, *l4_hdr;
1269 __be16 frag_off;
1270
1271 switch (first->protocol) {
1272 case htons(ETH_P_IP):
1273 tun_prot = ip_hdr(skb)->protocol;
1274 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4;
1275 break;
1276 case htons(ETH_P_IPV6):
1277 l4_hdr = skb_transport_header(skb);
1278 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1279 tun_prot = ipv6_hdr(skb)->nexthdr;
1280 if (l4_hdr != exthdr)
1281 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off);
1282 break;
1283 default:
1284 break;
1285 }
1286 switch (tun_prot) {
1287 case IPPROTO_UDP:
1288 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1289 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1290 WX_TXD_OUTER_IPLEN_SHIFT) |
1291 (((skb_inner_mac_header(skb) -
1292 skb_transport_header(skb)) >> 1) <<
1293 WX_TXD_TUNNEL_LEN_SHIFT);
1294 break;
1295 case IPPROTO_GRE:
1296 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1297 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1298 WX_TXD_OUTER_IPLEN_SHIFT) |
1299 (((skb_inner_mac_header(skb) -
1300 skb_transport_header(skb)) >> 1) <<
1301 WX_TXD_TUNNEL_LEN_SHIFT);
1302 break;
1303 case IPPROTO_IPIP:
1304 case IPPROTO_IPV6:
1305 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1306 (char *)ip_hdr(skb)) >> 2) <<
1307 WX_TXD_OUTER_IPLEN_SHIFT;
1308 break;
1309 default:
1310 break;
1311 }
1312 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1;
1313 } else {
1314 vlan_macip_lens = skb_network_header_len(skb) >> 1;
1315 }
1316
1317 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT;
1318 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1319
1320 type_tucmd = ptype << 24;
1321 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1322 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1323 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1324 WX_TX_FLAGS_HW_VLAN,
1325 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1326 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1327 type_tucmd, mss_l4len_idx);
1328
1329 return 1;
1330 }
1331
wx_tx_csum(struct wx_ring * tx_ring,struct wx_tx_buffer * first,u8 ptype)1332 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1333 u8 ptype)
1334 {
1335 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0;
1336 struct net_device *netdev = tx_ring->netdev;
1337 u32 mss_l4len_idx = 0, type_tucmd;
1338 struct sk_buff *skb = first->skb;
1339 u8 tun_prot = 0;
1340
1341 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1342 csum_failed:
1343 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) &&
1344 !(first->tx_flags & WX_TX_FLAGS_CC))
1345 return;
1346 vlan_macip_lens = skb_network_offset(skb) <<
1347 WX_TXD_MACLEN_SHIFT;
1348 } else {
1349 unsigned char *exthdr, *l4_hdr;
1350 __be16 frag_off;
1351 u8 l4_prot = 0;
1352 union {
1353 struct iphdr *ipv4;
1354 struct ipv6hdr *ipv6;
1355 u8 *raw;
1356 } network_hdr;
1357 union {
1358 struct tcphdr *tcphdr;
1359 u8 *raw;
1360 } transport_hdr;
1361
1362 if (skb->encapsulation) {
1363 network_hdr.raw = skb_inner_network_header(skb);
1364 transport_hdr.raw = skb_inner_transport_header(skb);
1365 vlan_macip_lens = skb_network_offset(skb) <<
1366 WX_TXD_MACLEN_SHIFT;
1367 switch (first->protocol) {
1368 case htons(ETH_P_IP):
1369 tun_prot = ip_hdr(skb)->protocol;
1370 break;
1371 case htons(ETH_P_IPV6):
1372 l4_hdr = skb_transport_header(skb);
1373 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr);
1374 tun_prot = ipv6_hdr(skb)->nexthdr;
1375 if (l4_hdr != exthdr)
1376 ipv6_skip_exthdr(skb, exthdr - skb->data,
1377 &tun_prot, &frag_off);
1378 break;
1379 default:
1380 return;
1381 }
1382 switch (tun_prot) {
1383 case IPPROTO_UDP:
1384 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1385 tunhdr_eiplen_tunlen |=
1386 ((skb_network_header_len(skb) >> 2) <<
1387 WX_TXD_OUTER_IPLEN_SHIFT) |
1388 (((skb_inner_mac_header(skb) -
1389 skb_transport_header(skb)) >> 1) <<
1390 WX_TXD_TUNNEL_LEN_SHIFT);
1391 break;
1392 case IPPROTO_GRE:
1393 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1394 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1395 WX_TXD_OUTER_IPLEN_SHIFT) |
1396 (((skb_inner_mac_header(skb) -
1397 skb_transport_header(skb)) >> 1) <<
1398 WX_TXD_TUNNEL_LEN_SHIFT);
1399 break;
1400 case IPPROTO_IPIP:
1401 case IPPROTO_IPV6:
1402 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1403 (char *)ip_hdr(skb)) >> 2) <<
1404 WX_TXD_OUTER_IPLEN_SHIFT;
1405 break;
1406 default:
1407 break;
1408 }
1409
1410 } else {
1411 network_hdr.raw = skb_network_header(skb);
1412 transport_hdr.raw = skb_transport_header(skb);
1413 vlan_macip_lens = skb_network_offset(skb) <<
1414 WX_TXD_MACLEN_SHIFT;
1415 }
1416
1417 switch (network_hdr.ipv4->version) {
1418 case IPVERSION:
1419 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1420 l4_prot = network_hdr.ipv4->protocol;
1421 break;
1422 case 6:
1423 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1424 exthdr = network_hdr.raw + sizeof(struct ipv6hdr);
1425 l4_prot = network_hdr.ipv6->nexthdr;
1426 if (transport_hdr.raw != exthdr)
1427 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off);
1428 break;
1429 default:
1430 break;
1431 }
1432
1433 switch (l4_prot) {
1434 case IPPROTO_TCP:
1435 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
1436 WX_TXD_L4LEN_SHIFT;
1437 break;
1438 case IPPROTO_SCTP:
1439 mss_l4len_idx = sizeof(struct sctphdr) <<
1440 WX_TXD_L4LEN_SHIFT;
1441 break;
1442 case IPPROTO_UDP:
1443 mss_l4len_idx = sizeof(struct udphdr) <<
1444 WX_TXD_L4LEN_SHIFT;
1445 break;
1446 default:
1447 skb_checksum_help(skb);
1448 goto csum_failed;
1449 }
1450
1451 /* update TX checksum flag */
1452 first->tx_flags |= WX_TX_FLAGS_CSUM;
1453 }
1454 first->tx_flags |= WX_TX_FLAGS_CC;
1455 /* vlan_macip_lens: MACLEN, VLAN tag */
1456 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1457
1458 type_tucmd = ptype << 24;
1459 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1460 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1461 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1462 WX_TX_FLAGS_HW_VLAN,
1463 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1464 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1465 type_tucmd, mss_l4len_idx);
1466 }
1467
wx_xmit_frame_ring(struct sk_buff * skb,struct wx_ring * tx_ring)1468 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
1469 struct wx_ring *tx_ring)
1470 {
1471 struct wx *wx = netdev_priv(tx_ring->netdev);
1472 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1473 struct wx_tx_buffer *first;
1474 u8 hdr_len = 0, ptype;
1475 unsigned short f;
1476 u32 tx_flags = 0;
1477 int tso;
1478
1479 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
1480 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
1481 * + 2 desc gap to keep tail from touching head,
1482 * + 1 desc for context descriptor,
1483 * otherwise try next time
1484 */
1485 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1486 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
1487 frags[f]));
1488
1489 if (wx_maybe_stop_tx(tx_ring, count + 3)) {
1490 tx_ring->tx_stats.tx_busy++;
1491 return NETDEV_TX_BUSY;
1492 }
1493
1494 /* record the location of the first descriptor for this packet */
1495 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1496 first->skb = skb;
1497 first->bytecount = skb->len;
1498 first->gso_segs = 1;
1499
1500 /* if we have a HW VLAN tag being added default to the HW one */
1501 if (skb_vlan_tag_present(skb)) {
1502 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT;
1503 tx_flags |= WX_TX_FLAGS_HW_VLAN;
1504 }
1505
1506 /* record initial flags and protocol */
1507 first->tx_flags = tx_flags;
1508 first->protocol = vlan_get_protocol(skb);
1509
1510 ptype = wx_encode_tx_desc_ptype(first);
1511
1512 tso = wx_tso(tx_ring, first, &hdr_len, ptype);
1513 if (tso < 0)
1514 goto out_drop;
1515 else if (!tso)
1516 wx_tx_csum(tx_ring, first, ptype);
1517
1518 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate)
1519 wx->atr(tx_ring, first, ptype);
1520
1521 wx_tx_map(tx_ring, first, hdr_len);
1522
1523 return NETDEV_TX_OK;
1524 out_drop:
1525 dev_kfree_skb_any(first->skb);
1526 first->skb = NULL;
1527
1528 return NETDEV_TX_OK;
1529 }
1530
wx_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1531 netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
1532 struct net_device *netdev)
1533 {
1534 unsigned int r_idx = skb->queue_mapping;
1535 struct wx *wx = netdev_priv(netdev);
1536 struct wx_ring *tx_ring;
1537
1538 if (!netif_carrier_ok(netdev)) {
1539 dev_kfree_skb_any(skb);
1540 return NETDEV_TX_OK;
1541 }
1542
1543 /* The minimum packet size for olinfo paylen is 17 so pad the skb
1544 * in order to meet this minimum size requirement.
1545 */
1546 if (skb_put_padto(skb, 17))
1547 return NETDEV_TX_OK;
1548
1549 if (r_idx >= wx->num_tx_queues)
1550 r_idx = r_idx % wx->num_tx_queues;
1551 tx_ring = wx->tx_ring[r_idx];
1552
1553 return wx_xmit_frame_ring(skb, tx_ring);
1554 }
1555 EXPORT_SYMBOL(wx_xmit_frame);
1556
wx_napi_enable_all(struct wx * wx)1557 void wx_napi_enable_all(struct wx *wx)
1558 {
1559 struct wx_q_vector *q_vector;
1560 int q_idx;
1561
1562 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1563 q_vector = wx->q_vector[q_idx];
1564 napi_enable(&q_vector->napi);
1565 }
1566 }
1567 EXPORT_SYMBOL(wx_napi_enable_all);
1568
wx_napi_disable_all(struct wx * wx)1569 void wx_napi_disable_all(struct wx *wx)
1570 {
1571 struct wx_q_vector *q_vector;
1572 int q_idx;
1573
1574 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1575 q_vector = wx->q_vector[q_idx];
1576 napi_disable(&q_vector->napi);
1577 }
1578 }
1579 EXPORT_SYMBOL(wx_napi_disable_all);
1580
1581 /**
1582 * wx_set_rss_queues: Allocate queues for RSS
1583 * @wx: board private structure to initialize
1584 *
1585 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
1586 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1587 *
1588 **/
wx_set_rss_queues(struct wx * wx)1589 static void wx_set_rss_queues(struct wx *wx)
1590 {
1591 struct wx_ring_feature *f;
1592
1593 /* set mask for 16 queue limit of RSS */
1594 f = &wx->ring_feature[RING_F_RSS];
1595 f->indices = f->limit;
1596
1597 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
1598 goto out;
1599
1600 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
1601
1602 /* Use Flow Director in addition to RSS to ensure the best
1603 * distribution of flows across cores, even when an FDIR flow
1604 * isn't matched.
1605 */
1606 if (f->indices > 1) {
1607 f = &wx->ring_feature[RING_F_FDIR];
1608
1609 f->indices = f->limit;
1610
1611 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
1612 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
1613 }
1614
1615 out:
1616 wx->num_rx_queues = f->indices;
1617 wx->num_tx_queues = f->indices;
1618 }
1619
wx_set_num_queues(struct wx * wx)1620 static void wx_set_num_queues(struct wx *wx)
1621 {
1622 /* Start with base case */
1623 wx->num_rx_queues = 1;
1624 wx->num_tx_queues = 1;
1625 wx->queues_per_pool = 1;
1626
1627 wx_set_rss_queues(wx);
1628 }
1629
1630 /**
1631 * wx_acquire_msix_vectors - acquire MSI-X vectors
1632 * @wx: board private structure
1633 *
1634 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
1635 * return a negative error code if unable to acquire MSI-X vectors for any
1636 * reason.
1637 */
wx_acquire_msix_vectors(struct wx * wx)1638 static int wx_acquire_msix_vectors(struct wx *wx)
1639 {
1640 struct irq_affinity affd = { .pre_vectors = 1 };
1641 int nvecs, i;
1642
1643 /* We start by asking for one vector per queue pair */
1644 nvecs = max(wx->num_rx_queues, wx->num_tx_queues);
1645 nvecs = min_t(int, nvecs, num_online_cpus());
1646 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors);
1647
1648 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry),
1649 GFP_KERNEL);
1650 if (!wx->msix_q_entries)
1651 return -ENOMEM;
1652
1653 /* One for non-queue interrupts */
1654 nvecs += 1;
1655
1656 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry),
1657 GFP_KERNEL);
1658 if (!wx->msix_entry) {
1659 kfree(wx->msix_q_entries);
1660 wx->msix_q_entries = NULL;
1661 return -ENOMEM;
1662 }
1663
1664 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
1665 nvecs,
1666 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
1667 &affd);
1668 if (nvecs < 0) {
1669 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
1670 kfree(wx->msix_q_entries);
1671 wx->msix_q_entries = NULL;
1672 kfree(wx->msix_entry);
1673 wx->msix_entry = NULL;
1674 return nvecs;
1675 }
1676
1677 wx->msix_entry->entry = 0;
1678 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
1679 nvecs -= 1;
1680 for (i = 0; i < nvecs; i++) {
1681 wx->msix_q_entries[i].entry = i;
1682 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1);
1683 }
1684
1685 wx->num_q_vectors = nvecs;
1686
1687 return 0;
1688 }
1689
1690 /**
1691 * wx_set_interrupt_capability - set MSI-X or MSI if supported
1692 * @wx: board private structure to initialize
1693 *
1694 * Attempt to configure the interrupts using the best available
1695 * capabilities of the hardware and the kernel.
1696 **/
wx_set_interrupt_capability(struct wx * wx)1697 static int wx_set_interrupt_capability(struct wx *wx)
1698 {
1699 struct pci_dev *pdev = wx->pdev;
1700 int nvecs, ret;
1701
1702 /* We will try to get MSI-X interrupts first */
1703 ret = wx_acquire_msix_vectors(wx);
1704 if (ret == 0 || (ret == -ENOMEM))
1705 return ret;
1706
1707 /* Disable RSS */
1708 dev_warn(&wx->pdev->dev, "Disabling RSS support\n");
1709 wx->ring_feature[RING_F_RSS].limit = 1;
1710
1711 wx_set_num_queues(wx);
1712
1713 /* minmum one for queue, one for misc*/
1714 nvecs = 1;
1715 nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1716 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX);
1717 if (nvecs == 1) {
1718 if (pdev->msi_enabled)
1719 wx_err(wx, "Fallback to MSI.\n");
1720 else
1721 wx_err(wx, "Fallback to INTx.\n");
1722 } else {
1723 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs);
1724 return nvecs;
1725 }
1726
1727 pdev->irq = pci_irq_vector(pdev, 0);
1728 wx->num_q_vectors = 1;
1729
1730 return 0;
1731 }
1732
1733 /**
1734 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1735 * @wx: board private structure to initialize
1736 *
1737 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1738 *
1739 **/
wx_cache_ring_rss(struct wx * wx)1740 static void wx_cache_ring_rss(struct wx *wx)
1741 {
1742 u16 i;
1743
1744 for (i = 0; i < wx->num_rx_queues; i++)
1745 wx->rx_ring[i]->reg_idx = i;
1746
1747 for (i = 0; i < wx->num_tx_queues; i++)
1748 wx->tx_ring[i]->reg_idx = i;
1749 }
1750
wx_add_ring(struct wx_ring * ring,struct wx_ring_container * head)1751 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1752 {
1753 ring->next = head->ring;
1754 head->ring = ring;
1755 head->count++;
1756 }
1757
1758 /**
1759 * wx_alloc_q_vector - Allocate memory for a single interrupt vector
1760 * @wx: board private structure to initialize
1761 * @v_count: q_vectors allocated on wx, used for ring interleaving
1762 * @v_idx: index of vector in wx struct
1763 * @txr_count: total number of Tx rings to allocate
1764 * @txr_idx: index of first Tx ring to allocate
1765 * @rxr_count: total number of Rx rings to allocate
1766 * @rxr_idx: index of first Rx ring to allocate
1767 *
1768 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1769 **/
wx_alloc_q_vector(struct wx * wx,unsigned int v_count,unsigned int v_idx,unsigned int txr_count,unsigned int txr_idx,unsigned int rxr_count,unsigned int rxr_idx)1770 static int wx_alloc_q_vector(struct wx *wx,
1771 unsigned int v_count, unsigned int v_idx,
1772 unsigned int txr_count, unsigned int txr_idx,
1773 unsigned int rxr_count, unsigned int rxr_idx)
1774 {
1775 struct wx_q_vector *q_vector;
1776 int ring_count, default_itr;
1777 struct wx_ring *ring;
1778
1779 /* note this will allocate space for the ring structure as well! */
1780 ring_count = txr_count + rxr_count;
1781
1782 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1783 GFP_KERNEL);
1784 if (!q_vector)
1785 return -ENOMEM;
1786
1787 /* initialize NAPI */
1788 netif_napi_add(wx->netdev, &q_vector->napi,
1789 wx_poll);
1790
1791 /* tie q_vector and wx together */
1792 wx->q_vector[v_idx] = q_vector;
1793 q_vector->wx = wx;
1794 q_vector->v_idx = v_idx;
1795 if (cpu_online(v_idx))
1796 q_vector->numa_node = cpu_to_node(v_idx);
1797
1798 /* initialize pointer to rings */
1799 ring = q_vector->ring;
1800
1801 if (wx->mac.type == wx_mac_sp)
1802 default_itr = WX_12K_ITR;
1803 else
1804 default_itr = WX_7K_ITR;
1805 /* initialize ITR */
1806 if (txr_count && !rxr_count)
1807 /* tx only vector */
1808 q_vector->itr = wx->tx_itr_setting ?
1809 default_itr : wx->tx_itr_setting;
1810 else
1811 /* rx or rx/tx vector */
1812 q_vector->itr = wx->rx_itr_setting ?
1813 default_itr : wx->rx_itr_setting;
1814
1815 while (txr_count) {
1816 /* assign generic ring traits */
1817 ring->dev = &wx->pdev->dev;
1818 ring->netdev = wx->netdev;
1819
1820 /* configure backlink on ring */
1821 ring->q_vector = q_vector;
1822
1823 /* update q_vector Tx values */
1824 wx_add_ring(ring, &q_vector->tx);
1825
1826 /* apply Tx specific ring traits */
1827 ring->count = wx->tx_ring_count;
1828
1829 ring->queue_index = txr_idx;
1830
1831 /* assign ring to wx */
1832 wx->tx_ring[txr_idx] = ring;
1833
1834 /* update count and index */
1835 txr_count--;
1836 txr_idx += v_count;
1837
1838 /* push pointer to next ring */
1839 ring++;
1840 }
1841
1842 while (rxr_count) {
1843 /* assign generic ring traits */
1844 ring->dev = &wx->pdev->dev;
1845 ring->netdev = wx->netdev;
1846
1847 /* configure backlink on ring */
1848 ring->q_vector = q_vector;
1849
1850 /* update q_vector Rx values */
1851 wx_add_ring(ring, &q_vector->rx);
1852
1853 /* apply Rx specific ring traits */
1854 ring->count = wx->rx_ring_count;
1855 ring->queue_index = rxr_idx;
1856
1857 /* assign ring to wx */
1858 wx->rx_ring[rxr_idx] = ring;
1859
1860 /* update count and index */
1861 rxr_count--;
1862 rxr_idx += v_count;
1863
1864 /* push pointer to next ring */
1865 ring++;
1866 }
1867
1868 return 0;
1869 }
1870
1871 /**
1872 * wx_free_q_vector - Free memory allocated for specific interrupt vector
1873 * @wx: board private structure to initialize
1874 * @v_idx: Index of vector to be freed
1875 *
1876 * This function frees the memory allocated to the q_vector. In addition if
1877 * NAPI is enabled it will delete any references to the NAPI struct prior
1878 * to freeing the q_vector.
1879 **/
wx_free_q_vector(struct wx * wx,int v_idx)1880 static void wx_free_q_vector(struct wx *wx, int v_idx)
1881 {
1882 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1883 struct wx_ring *ring;
1884
1885 wx_for_each_ring(ring, q_vector->tx)
1886 wx->tx_ring[ring->queue_index] = NULL;
1887
1888 wx_for_each_ring(ring, q_vector->rx)
1889 wx->rx_ring[ring->queue_index] = NULL;
1890
1891 wx->q_vector[v_idx] = NULL;
1892 netif_napi_del(&q_vector->napi);
1893 kfree_rcu(q_vector, rcu);
1894 }
1895
1896 /**
1897 * wx_alloc_q_vectors - Allocate memory for interrupt vectors
1898 * @wx: board private structure to initialize
1899 *
1900 * We allocate one q_vector per queue interrupt. If allocation fails we
1901 * return -ENOMEM.
1902 **/
wx_alloc_q_vectors(struct wx * wx)1903 static int wx_alloc_q_vectors(struct wx *wx)
1904 {
1905 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1906 unsigned int rxr_remaining = wx->num_rx_queues;
1907 unsigned int txr_remaining = wx->num_tx_queues;
1908 unsigned int q_vectors = wx->num_q_vectors;
1909 int rqpv, tqpv;
1910 int err;
1911
1912 for (; v_idx < q_vectors; v_idx++) {
1913 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1914 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1915 err = wx_alloc_q_vector(wx, q_vectors, v_idx,
1916 tqpv, txr_idx,
1917 rqpv, rxr_idx);
1918
1919 if (err)
1920 goto err_out;
1921
1922 /* update counts and index */
1923 rxr_remaining -= rqpv;
1924 txr_remaining -= tqpv;
1925 rxr_idx++;
1926 txr_idx++;
1927 }
1928
1929 return 0;
1930
1931 err_out:
1932 wx->num_tx_queues = 0;
1933 wx->num_rx_queues = 0;
1934 wx->num_q_vectors = 0;
1935
1936 while (v_idx--)
1937 wx_free_q_vector(wx, v_idx);
1938
1939 return -ENOMEM;
1940 }
1941
1942 /**
1943 * wx_free_q_vectors - Free memory allocated for interrupt vectors
1944 * @wx: board private structure to initialize
1945 *
1946 * This function frees the memory allocated to the q_vectors. In addition if
1947 * NAPI is enabled it will delete any references to the NAPI struct prior
1948 * to freeing the q_vector.
1949 **/
wx_free_q_vectors(struct wx * wx)1950 static void wx_free_q_vectors(struct wx *wx)
1951 {
1952 int v_idx = wx->num_q_vectors;
1953
1954 wx->num_tx_queues = 0;
1955 wx->num_rx_queues = 0;
1956 wx->num_q_vectors = 0;
1957
1958 while (v_idx--)
1959 wx_free_q_vector(wx, v_idx);
1960 }
1961
wx_reset_interrupt_capability(struct wx * wx)1962 void wx_reset_interrupt_capability(struct wx *wx)
1963 {
1964 struct pci_dev *pdev = wx->pdev;
1965
1966 if (!pdev->msi_enabled && !pdev->msix_enabled)
1967 return;
1968
1969 if (pdev->msix_enabled) {
1970 kfree(wx->msix_q_entries);
1971 wx->msix_q_entries = NULL;
1972 kfree(wx->msix_entry);
1973 wx->msix_entry = NULL;
1974 }
1975 pci_free_irq_vectors(wx->pdev);
1976 }
1977 EXPORT_SYMBOL(wx_reset_interrupt_capability);
1978
1979 /**
1980 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
1981 * @wx: board private structure to clear interrupt scheme on
1982 *
1983 * We go through and clear interrupt specific resources and reset the structure
1984 * to pre-load conditions
1985 **/
wx_clear_interrupt_scheme(struct wx * wx)1986 void wx_clear_interrupt_scheme(struct wx *wx)
1987 {
1988 wx_free_q_vectors(wx);
1989 wx_reset_interrupt_capability(wx);
1990 }
1991 EXPORT_SYMBOL(wx_clear_interrupt_scheme);
1992
wx_init_interrupt_scheme(struct wx * wx)1993 int wx_init_interrupt_scheme(struct wx *wx)
1994 {
1995 int ret;
1996
1997 /* Number of supported queues */
1998 wx_set_num_queues(wx);
1999
2000 /* Set interrupt mode */
2001 ret = wx_set_interrupt_capability(wx);
2002 if (ret) {
2003 wx_err(wx, "Allocate irq vectors for failed.\n");
2004 return ret;
2005 }
2006
2007 /* Allocate memory for queues */
2008 ret = wx_alloc_q_vectors(wx);
2009 if (ret) {
2010 wx_err(wx, "Unable to allocate memory for queue vectors.\n");
2011 wx_reset_interrupt_capability(wx);
2012 return ret;
2013 }
2014
2015 wx_cache_ring_rss(wx);
2016
2017 return 0;
2018 }
2019 EXPORT_SYMBOL(wx_init_interrupt_scheme);
2020
wx_msix_clean_rings(int __always_unused irq,void * data)2021 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
2022 {
2023 struct wx_q_vector *q_vector = data;
2024
2025 /* EIAM disabled interrupts (on this vector) for us */
2026 if (q_vector->rx.ring || q_vector->tx.ring)
2027 napi_schedule_irqoff(&q_vector->napi);
2028
2029 return IRQ_HANDLED;
2030 }
2031 EXPORT_SYMBOL(wx_msix_clean_rings);
2032
wx_free_irq(struct wx * wx)2033 void wx_free_irq(struct wx *wx)
2034 {
2035 struct pci_dev *pdev = wx->pdev;
2036 int vector;
2037
2038 if (!(pdev->msix_enabled)) {
2039 if (!wx->misc_irq_domain)
2040 free_irq(pdev->irq, wx);
2041 return;
2042 }
2043
2044 for (vector = 0; vector < wx->num_q_vectors; vector++) {
2045 struct wx_q_vector *q_vector = wx->q_vector[vector];
2046 struct msix_entry *entry = &wx->msix_q_entries[vector];
2047
2048 /* free only the irqs that were actually requested */
2049 if (!q_vector->rx.ring && !q_vector->tx.ring)
2050 continue;
2051
2052 free_irq(entry->vector, q_vector);
2053 }
2054
2055 if (!wx->misc_irq_domain)
2056 free_irq(wx->msix_entry->vector, wx);
2057 }
2058 EXPORT_SYMBOL(wx_free_irq);
2059
2060 /**
2061 * wx_setup_isb_resources - allocate interrupt status resources
2062 * @wx: board private structure
2063 *
2064 * Return 0 on success, negative on failure
2065 **/
wx_setup_isb_resources(struct wx * wx)2066 int wx_setup_isb_resources(struct wx *wx)
2067 {
2068 struct pci_dev *pdev = wx->pdev;
2069
2070 if (wx->isb_mem)
2071 return 0;
2072
2073 wx->isb_mem = dma_alloc_coherent(&pdev->dev,
2074 sizeof(u32) * 4,
2075 &wx->isb_dma,
2076 GFP_KERNEL);
2077 if (!wx->isb_mem) {
2078 wx_err(wx, "Alloc isb_mem failed\n");
2079 return -ENOMEM;
2080 }
2081
2082 return 0;
2083 }
2084 EXPORT_SYMBOL(wx_setup_isb_resources);
2085
2086 /**
2087 * wx_free_isb_resources - allocate all queues Rx resources
2088 * @wx: board private structure
2089 *
2090 * Return 0 on success, negative on failure
2091 **/
wx_free_isb_resources(struct wx * wx)2092 void wx_free_isb_resources(struct wx *wx)
2093 {
2094 struct pci_dev *pdev = wx->pdev;
2095
2096 dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
2097 wx->isb_mem, wx->isb_dma);
2098 wx->isb_mem = NULL;
2099 }
2100 EXPORT_SYMBOL(wx_free_isb_resources);
2101
wx_misc_isb(struct wx * wx,enum wx_isb_idx idx)2102 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
2103 {
2104 u32 cur_tag = 0;
2105
2106 cur_tag = wx->isb_mem[WX_ISB_HEADER];
2107 wx->isb_tag[idx] = cur_tag;
2108
2109 return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
2110 }
2111 EXPORT_SYMBOL(wx_misc_isb);
2112
2113 /**
2114 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
2115 * @wx: pointer to wx struct
2116 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
2117 * @queue: queue to map the corresponding interrupt to
2118 * @msix_vector: the vector to map to the corresponding queue
2119 *
2120 **/
wx_set_ivar(struct wx * wx,s8 direction,u16 queue,u16 msix_vector)2121 static void wx_set_ivar(struct wx *wx, s8 direction,
2122 u16 queue, u16 msix_vector)
2123 {
2124 u32 ivar, index;
2125
2126 if (direction == -1) {
2127 /* other causes */
2128 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2129 index = 0;
2130 ivar = rd32(wx, WX_PX_MISC_IVAR);
2131 ivar &= ~(0xFF << index);
2132 ivar |= (msix_vector << index);
2133 wr32(wx, WX_PX_MISC_IVAR, ivar);
2134 } else {
2135 /* tx or rx causes */
2136 msix_vector += 1; /* offset for queue vectors */
2137 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2138 index = ((16 * (queue & 1)) + (8 * direction));
2139 ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
2140 ivar &= ~(0xFF << index);
2141 ivar |= (msix_vector << index);
2142 wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
2143 }
2144 }
2145
2146 /**
2147 * wx_write_eitr - write EITR register in hardware specific way
2148 * @q_vector: structure containing interrupt and ring information
2149 *
2150 * This function is made to be called by ethtool and by the driver
2151 * when it needs to update EITR registers at runtime. Hardware
2152 * specific quirks/differences are taken care of here.
2153 */
wx_write_eitr(struct wx_q_vector * q_vector)2154 void wx_write_eitr(struct wx_q_vector *q_vector)
2155 {
2156 struct wx *wx = q_vector->wx;
2157 int v_idx = q_vector->v_idx;
2158 u32 itr_reg;
2159
2160 if (wx->mac.type == wx_mac_sp)
2161 itr_reg = q_vector->itr & WX_SP_MAX_EITR;
2162 else
2163 itr_reg = q_vector->itr & WX_EM_MAX_EITR;
2164
2165 itr_reg |= WX_PX_ITR_CNT_WDIS;
2166
2167 wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg);
2168 }
2169
2170 /**
2171 * wx_configure_vectors - Configure vectors for hardware
2172 * @wx: board private structure
2173 *
2174 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx
2175 * interrupts.
2176 **/
wx_configure_vectors(struct wx * wx)2177 void wx_configure_vectors(struct wx *wx)
2178 {
2179 struct pci_dev *pdev = wx->pdev;
2180 u32 eitrsel = 0;
2181 u16 v_idx;
2182
2183 if (pdev->msix_enabled) {
2184 /* Populate MSIX to EITR Select */
2185 wr32(wx, WX_PX_ITRSEL, eitrsel);
2186 /* use EIAM to auto-mask when MSI-X interrupt is asserted
2187 * this saves a register write for every interrupt
2188 */
2189 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
2190 } else {
2191 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2192 * specifically only auto mask tx and rx interrupts.
2193 */
2194 wr32(wx, WX_PX_GPIE, 0);
2195 }
2196
2197 /* Populate the IVAR table and set the ITR values to the
2198 * corresponding register.
2199 */
2200 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
2201 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2202 struct wx_ring *ring;
2203
2204 wx_for_each_ring(ring, q_vector->rx)
2205 wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
2206
2207 wx_for_each_ring(ring, q_vector->tx)
2208 wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
2209
2210 wx_write_eitr(q_vector);
2211 }
2212
2213 wx_set_ivar(wx, -1, 0, 0);
2214 if (pdev->msix_enabled)
2215 wr32(wx, WX_PX_ITR(0), 1950);
2216 }
2217 EXPORT_SYMBOL(wx_configure_vectors);
2218
2219 /**
2220 * wx_clean_rx_ring - Free Rx Buffers per Queue
2221 * @rx_ring: ring to free buffers from
2222 **/
wx_clean_rx_ring(struct wx_ring * rx_ring)2223 static void wx_clean_rx_ring(struct wx_ring *rx_ring)
2224 {
2225 struct wx_rx_buffer *rx_buffer;
2226 u16 i = rx_ring->next_to_clean;
2227
2228 rx_buffer = &rx_ring->rx_buffer_info[i];
2229
2230 /* Free all the Rx ring sk_buffs */
2231 while (i != rx_ring->next_to_alloc) {
2232 if (rx_buffer->skb) {
2233 struct sk_buff *skb = rx_buffer->skb;
2234
2235 if (WX_CB(skb)->page_released)
2236 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2237
2238 dev_kfree_skb(skb);
2239 }
2240
2241 /* Invalidate cache lines that may have been written to by
2242 * device so that we avoid corrupting memory.
2243 */
2244 dma_sync_single_range_for_cpu(rx_ring->dev,
2245 rx_buffer->dma,
2246 rx_buffer->page_offset,
2247 WX_RX_BUFSZ,
2248 DMA_FROM_DEVICE);
2249
2250 /* free resources associated with mapping */
2251 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2252
2253 i++;
2254 rx_buffer++;
2255 if (i == rx_ring->count) {
2256 i = 0;
2257 rx_buffer = rx_ring->rx_buffer_info;
2258 }
2259 }
2260
2261 rx_ring->next_to_alloc = 0;
2262 rx_ring->next_to_clean = 0;
2263 rx_ring->next_to_use = 0;
2264 }
2265
2266 /**
2267 * wx_clean_all_rx_rings - Free Rx Buffers for all queues
2268 * @wx: board private structure
2269 **/
wx_clean_all_rx_rings(struct wx * wx)2270 void wx_clean_all_rx_rings(struct wx *wx)
2271 {
2272 int i;
2273
2274 for (i = 0; i < wx->num_rx_queues; i++)
2275 wx_clean_rx_ring(wx->rx_ring[i]);
2276 }
2277 EXPORT_SYMBOL(wx_clean_all_rx_rings);
2278
2279 /**
2280 * wx_free_rx_resources - Free Rx Resources
2281 * @rx_ring: ring to clean the resources from
2282 *
2283 * Free all receive software resources
2284 **/
wx_free_rx_resources(struct wx_ring * rx_ring)2285 static void wx_free_rx_resources(struct wx_ring *rx_ring)
2286 {
2287 wx_clean_rx_ring(rx_ring);
2288 kvfree(rx_ring->rx_buffer_info);
2289 rx_ring->rx_buffer_info = NULL;
2290
2291 /* if not set, then don't free */
2292 if (!rx_ring->desc)
2293 return;
2294
2295 dma_free_coherent(rx_ring->dev, rx_ring->size,
2296 rx_ring->desc, rx_ring->dma);
2297
2298 rx_ring->desc = NULL;
2299
2300 if (rx_ring->page_pool) {
2301 page_pool_destroy(rx_ring->page_pool);
2302 rx_ring->page_pool = NULL;
2303 }
2304 }
2305
2306 /**
2307 * wx_free_all_rx_resources - Free Rx Resources for All Queues
2308 * @wx: pointer to hardware structure
2309 *
2310 * Free all receive software resources
2311 **/
wx_free_all_rx_resources(struct wx * wx)2312 static void wx_free_all_rx_resources(struct wx *wx)
2313 {
2314 int i;
2315
2316 for (i = 0; i < wx->num_rx_queues; i++)
2317 wx_free_rx_resources(wx->rx_ring[i]);
2318 }
2319
2320 /**
2321 * wx_clean_tx_ring - Free Tx Buffers
2322 * @tx_ring: ring to be cleaned
2323 **/
wx_clean_tx_ring(struct wx_ring * tx_ring)2324 static void wx_clean_tx_ring(struct wx_ring *tx_ring)
2325 {
2326 struct wx_tx_buffer *tx_buffer;
2327 u16 i = tx_ring->next_to_clean;
2328
2329 tx_buffer = &tx_ring->tx_buffer_info[i];
2330
2331 while (i != tx_ring->next_to_use) {
2332 union wx_tx_desc *eop_desc, *tx_desc;
2333
2334 /* Free all the Tx ring sk_buffs */
2335 dev_kfree_skb_any(tx_buffer->skb);
2336
2337 /* unmap skb header data */
2338 dma_unmap_single(tx_ring->dev,
2339 dma_unmap_addr(tx_buffer, dma),
2340 dma_unmap_len(tx_buffer, len),
2341 DMA_TO_DEVICE);
2342
2343 /* check for eop_desc to determine the end of the packet */
2344 eop_desc = tx_buffer->next_to_watch;
2345 tx_desc = WX_TX_DESC(tx_ring, i);
2346
2347 /* unmap remaining buffers */
2348 while (tx_desc != eop_desc) {
2349 tx_buffer++;
2350 tx_desc++;
2351 i++;
2352 if (unlikely(i == tx_ring->count)) {
2353 i = 0;
2354 tx_buffer = tx_ring->tx_buffer_info;
2355 tx_desc = WX_TX_DESC(tx_ring, 0);
2356 }
2357
2358 /* unmap any remaining paged data */
2359 if (dma_unmap_len(tx_buffer, len))
2360 dma_unmap_page(tx_ring->dev,
2361 dma_unmap_addr(tx_buffer, dma),
2362 dma_unmap_len(tx_buffer, len),
2363 DMA_TO_DEVICE);
2364 }
2365
2366 /* move us one more past the eop_desc for start of next pkt */
2367 tx_buffer++;
2368 i++;
2369 if (unlikely(i == tx_ring->count)) {
2370 i = 0;
2371 tx_buffer = tx_ring->tx_buffer_info;
2372 }
2373 }
2374
2375 netdev_tx_reset_queue(wx_txring_txq(tx_ring));
2376
2377 /* reset next_to_use and next_to_clean */
2378 tx_ring->next_to_use = 0;
2379 tx_ring->next_to_clean = 0;
2380 }
2381
2382 /**
2383 * wx_clean_all_tx_rings - Free Tx Buffers for all queues
2384 * @wx: board private structure
2385 **/
wx_clean_all_tx_rings(struct wx * wx)2386 void wx_clean_all_tx_rings(struct wx *wx)
2387 {
2388 int i;
2389
2390 for (i = 0; i < wx->num_tx_queues; i++)
2391 wx_clean_tx_ring(wx->tx_ring[i]);
2392 }
2393 EXPORT_SYMBOL(wx_clean_all_tx_rings);
2394
2395 /**
2396 * wx_free_tx_resources - Free Tx Resources per Queue
2397 * @tx_ring: Tx descriptor ring for a specific queue
2398 *
2399 * Free all transmit software resources
2400 **/
wx_free_tx_resources(struct wx_ring * tx_ring)2401 static void wx_free_tx_resources(struct wx_ring *tx_ring)
2402 {
2403 wx_clean_tx_ring(tx_ring);
2404 kvfree(tx_ring->tx_buffer_info);
2405 tx_ring->tx_buffer_info = NULL;
2406
2407 /* if not set, then don't free */
2408 if (!tx_ring->desc)
2409 return;
2410
2411 dma_free_coherent(tx_ring->dev, tx_ring->size,
2412 tx_ring->desc, tx_ring->dma);
2413 tx_ring->desc = NULL;
2414 }
2415
2416 /**
2417 * wx_free_all_tx_resources - Free Tx Resources for All Queues
2418 * @wx: pointer to hardware structure
2419 *
2420 * Free all transmit software resources
2421 **/
wx_free_all_tx_resources(struct wx * wx)2422 static void wx_free_all_tx_resources(struct wx *wx)
2423 {
2424 int i;
2425
2426 for (i = 0; i < wx->num_tx_queues; i++)
2427 wx_free_tx_resources(wx->tx_ring[i]);
2428 }
2429
wx_free_resources(struct wx * wx)2430 void wx_free_resources(struct wx *wx)
2431 {
2432 wx_free_all_rx_resources(wx);
2433 wx_free_all_tx_resources(wx);
2434 }
2435 EXPORT_SYMBOL(wx_free_resources);
2436
wx_alloc_page_pool(struct wx_ring * rx_ring)2437 static int wx_alloc_page_pool(struct wx_ring *rx_ring)
2438 {
2439 int ret = 0;
2440
2441 struct page_pool_params pp_params = {
2442 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
2443 .order = 0,
2444 .pool_size = rx_ring->size,
2445 .nid = dev_to_node(rx_ring->dev),
2446 .dev = rx_ring->dev,
2447 .dma_dir = DMA_FROM_DEVICE,
2448 .offset = 0,
2449 .max_len = PAGE_SIZE,
2450 };
2451
2452 rx_ring->page_pool = page_pool_create(&pp_params);
2453 if (IS_ERR(rx_ring->page_pool)) {
2454 ret = PTR_ERR(rx_ring->page_pool);
2455 rx_ring->page_pool = NULL;
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * wx_setup_rx_resources - allocate Rx resources (Descriptors)
2463 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2464 *
2465 * Returns 0 on success, negative on failure
2466 **/
wx_setup_rx_resources(struct wx_ring * rx_ring)2467 static int wx_setup_rx_resources(struct wx_ring *rx_ring)
2468 {
2469 struct device *dev = rx_ring->dev;
2470 int orig_node = dev_to_node(dev);
2471 int numa_node = NUMA_NO_NODE;
2472 int size, ret;
2473
2474 size = sizeof(struct wx_rx_buffer) * rx_ring->count;
2475
2476 if (rx_ring->q_vector)
2477 numa_node = rx_ring->q_vector->numa_node;
2478
2479 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2480 if (!rx_ring->rx_buffer_info)
2481 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
2482 if (!rx_ring->rx_buffer_info)
2483 goto err;
2484
2485 /* Round up to nearest 4K */
2486 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
2487 rx_ring->size = ALIGN(rx_ring->size, 4096);
2488
2489 set_dev_node(dev, numa_node);
2490 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2491 &rx_ring->dma, GFP_KERNEL);
2492 if (!rx_ring->desc) {
2493 set_dev_node(dev, orig_node);
2494 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2495 &rx_ring->dma, GFP_KERNEL);
2496 }
2497
2498 if (!rx_ring->desc)
2499 goto err;
2500
2501 rx_ring->next_to_clean = 0;
2502 rx_ring->next_to_use = 0;
2503
2504 ret = wx_alloc_page_pool(rx_ring);
2505 if (ret < 0) {
2506 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
2507 goto err_desc;
2508 }
2509
2510 return 0;
2511
2512 err_desc:
2513 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2514 err:
2515 kvfree(rx_ring->rx_buffer_info);
2516 rx_ring->rx_buffer_info = NULL;
2517 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2518 return -ENOMEM;
2519 }
2520
2521 /**
2522 * wx_setup_all_rx_resources - allocate all queues Rx resources
2523 * @wx: pointer to hardware structure
2524 *
2525 * If this function returns with an error, then it's possible one or
2526 * more of the rings is populated (while the rest are not). It is the
2527 * callers duty to clean those orphaned rings.
2528 *
2529 * Return 0 on success, negative on failure
2530 **/
wx_setup_all_rx_resources(struct wx * wx)2531 static int wx_setup_all_rx_resources(struct wx *wx)
2532 {
2533 int i, err = 0;
2534
2535 for (i = 0; i < wx->num_rx_queues; i++) {
2536 err = wx_setup_rx_resources(wx->rx_ring[i]);
2537 if (!err)
2538 continue;
2539
2540 wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
2541 goto err_setup_rx;
2542 }
2543
2544 return 0;
2545 err_setup_rx:
2546 /* rewind the index freeing the rings as we go */
2547 while (i--)
2548 wx_free_rx_resources(wx->rx_ring[i]);
2549 return err;
2550 }
2551
2552 /**
2553 * wx_setup_tx_resources - allocate Tx resources (Descriptors)
2554 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2555 *
2556 * Return 0 on success, negative on failure
2557 **/
wx_setup_tx_resources(struct wx_ring * tx_ring)2558 static int wx_setup_tx_resources(struct wx_ring *tx_ring)
2559 {
2560 struct device *dev = tx_ring->dev;
2561 int orig_node = dev_to_node(dev);
2562 int numa_node = NUMA_NO_NODE;
2563 int size;
2564
2565 size = sizeof(struct wx_tx_buffer) * tx_ring->count;
2566
2567 if (tx_ring->q_vector)
2568 numa_node = tx_ring->q_vector->numa_node;
2569
2570 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2571 if (!tx_ring->tx_buffer_info)
2572 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
2573 if (!tx_ring->tx_buffer_info)
2574 goto err;
2575
2576 /* round up to nearest 4K */
2577 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
2578 tx_ring->size = ALIGN(tx_ring->size, 4096);
2579
2580 set_dev_node(dev, numa_node);
2581 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2582 &tx_ring->dma, GFP_KERNEL);
2583 if (!tx_ring->desc) {
2584 set_dev_node(dev, orig_node);
2585 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2586 &tx_ring->dma, GFP_KERNEL);
2587 }
2588
2589 if (!tx_ring->desc)
2590 goto err;
2591
2592 tx_ring->next_to_use = 0;
2593 tx_ring->next_to_clean = 0;
2594
2595 return 0;
2596
2597 err:
2598 kvfree(tx_ring->tx_buffer_info);
2599 tx_ring->tx_buffer_info = NULL;
2600 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2601 return -ENOMEM;
2602 }
2603
2604 /**
2605 * wx_setup_all_tx_resources - allocate all queues Tx resources
2606 * @wx: pointer to private structure
2607 *
2608 * If this function returns with an error, then it's possible one or
2609 * more of the rings is populated (while the rest are not). It is the
2610 * callers duty to clean those orphaned rings.
2611 *
2612 * Return 0 on success, negative on failure
2613 **/
wx_setup_all_tx_resources(struct wx * wx)2614 static int wx_setup_all_tx_resources(struct wx *wx)
2615 {
2616 int i, err = 0;
2617
2618 for (i = 0; i < wx->num_tx_queues; i++) {
2619 err = wx_setup_tx_resources(wx->tx_ring[i]);
2620 if (!err)
2621 continue;
2622
2623 wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
2624 goto err_setup_tx;
2625 }
2626
2627 return 0;
2628 err_setup_tx:
2629 /* rewind the index freeing the rings as we go */
2630 while (i--)
2631 wx_free_tx_resources(wx->tx_ring[i]);
2632 return err;
2633 }
2634
wx_setup_resources(struct wx * wx)2635 int wx_setup_resources(struct wx *wx)
2636 {
2637 int err;
2638
2639 /* allocate transmit descriptors */
2640 err = wx_setup_all_tx_resources(wx);
2641 if (err)
2642 return err;
2643
2644 /* allocate receive descriptors */
2645 err = wx_setup_all_rx_resources(wx);
2646 if (err)
2647 goto err_free_tx;
2648
2649 err = wx_setup_isb_resources(wx);
2650 if (err)
2651 goto err_free_rx;
2652
2653 return 0;
2654
2655 err_free_rx:
2656 wx_free_all_rx_resources(wx);
2657 err_free_tx:
2658 wx_free_all_tx_resources(wx);
2659
2660 return err;
2661 }
2662 EXPORT_SYMBOL(wx_setup_resources);
2663
2664 /**
2665 * wx_get_stats64 - Get System Network Statistics
2666 * @netdev: network interface device structure
2667 * @stats: storage space for 64bit statistics
2668 */
wx_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2669 void wx_get_stats64(struct net_device *netdev,
2670 struct rtnl_link_stats64 *stats)
2671 {
2672 struct wx *wx = netdev_priv(netdev);
2673 struct wx_hw_stats *hwstats;
2674 int i;
2675
2676 wx_update_stats(wx);
2677
2678 rcu_read_lock();
2679 for (i = 0; i < wx->num_rx_queues; i++) {
2680 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
2681 u64 bytes, packets;
2682 unsigned int start;
2683
2684 if (ring) {
2685 do {
2686 start = u64_stats_fetch_begin(&ring->syncp);
2687 packets = ring->stats.packets;
2688 bytes = ring->stats.bytes;
2689 } while (u64_stats_fetch_retry(&ring->syncp, start));
2690 stats->rx_packets += packets;
2691 stats->rx_bytes += bytes;
2692 }
2693 }
2694
2695 for (i = 0; i < wx->num_tx_queues; i++) {
2696 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
2697 u64 bytes, packets;
2698 unsigned int start;
2699
2700 if (ring) {
2701 do {
2702 start = u64_stats_fetch_begin(&ring->syncp);
2703 packets = ring->stats.packets;
2704 bytes = ring->stats.bytes;
2705 } while (u64_stats_fetch_retry(&ring->syncp,
2706 start));
2707 stats->tx_packets += packets;
2708 stats->tx_bytes += bytes;
2709 }
2710 }
2711
2712 rcu_read_unlock();
2713
2714 hwstats = &wx->stats;
2715 stats->rx_errors = hwstats->crcerrs + hwstats->rlec;
2716 stats->multicast = hwstats->qmprc;
2717 stats->rx_length_errors = hwstats->rlec;
2718 stats->rx_crc_errors = hwstats->crcerrs;
2719 }
2720 EXPORT_SYMBOL(wx_get_stats64);
2721
wx_set_features(struct net_device * netdev,netdev_features_t features)2722 int wx_set_features(struct net_device *netdev, netdev_features_t features)
2723 {
2724 netdev_features_t changed = netdev->features ^ features;
2725 struct wx *wx = netdev_priv(netdev);
2726 bool need_reset = false;
2727
2728 if (features & NETIF_F_RXHASH) {
2729 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,
2730 WX_RDB_RA_CTL_RSS_EN);
2731 wx->rss_enabled = true;
2732 } else {
2733 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);
2734 wx->rss_enabled = false;
2735 }
2736
2737 netdev->features = features;
2738
2739 if (wx->mac.type == wx_mac_sp && changed & NETIF_F_HW_VLAN_CTAG_RX)
2740 wx->do_reset(netdev);
2741 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER))
2742 wx_set_rx_mode(netdev);
2743
2744 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
2745 return 0;
2746
2747 /* Check if Flow Director n-tuple support was enabled or disabled. If
2748 * the state changed, we need to reset.
2749 */
2750 switch (features & NETIF_F_NTUPLE) {
2751 case NETIF_F_NTUPLE:
2752 /* turn off ATR, enable perfect filters and reset */
2753 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags)))
2754 need_reset = true;
2755
2756 clear_bit(WX_FLAG_FDIR_HASH, wx->flags);
2757 break;
2758 default:
2759 /* turn off perfect filters, enable ATR and reset */
2760 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags))
2761 need_reset = true;
2762
2763 /* We cannot enable ATR if RSS is disabled */
2764 if (wx->ring_feature[RING_F_RSS].limit <= 1)
2765 break;
2766
2767 set_bit(WX_FLAG_FDIR_HASH, wx->flags);
2768 break;
2769 }
2770
2771 if (need_reset)
2772 wx->do_reset(netdev);
2773
2774 return 0;
2775 }
2776 EXPORT_SYMBOL(wx_set_features);
2777
2778 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \
2779 NETIF_F_HW_VLAN_STAG_RX)
2780
2781 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \
2782 NETIF_F_HW_VLAN_STAG_TX)
2783
2784 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
2785 NETIF_F_HW_VLAN_STAG_FILTER)
2786
wx_fix_features(struct net_device * netdev,netdev_features_t features)2787 netdev_features_t wx_fix_features(struct net_device *netdev,
2788 netdev_features_t features)
2789 {
2790 netdev_features_t changed = netdev->features ^ features;
2791 struct wx *wx = netdev_priv(netdev);
2792
2793 if (changed & NETIF_VLAN_STRIPPING_FEATURES) {
2794 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES &&
2795 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) {
2796 features &= ~NETIF_VLAN_STRIPPING_FEATURES;
2797 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES;
2798 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off.");
2799 }
2800 }
2801
2802 if (changed & NETIF_VLAN_INSERTION_FEATURES) {
2803 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES &&
2804 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) {
2805 features &= ~NETIF_VLAN_INSERTION_FEATURES;
2806 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES;
2807 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off.");
2808 }
2809 }
2810
2811 if (changed & NETIF_VLAN_FILTERING_FEATURES) {
2812 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES &&
2813 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) {
2814 features &= ~NETIF_VLAN_FILTERING_FEATURES;
2815 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES;
2816 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off.");
2817 }
2818 }
2819
2820 return features;
2821 }
2822 EXPORT_SYMBOL(wx_fix_features);
2823
wx_set_ring(struct wx * wx,u32 new_tx_count,u32 new_rx_count,struct wx_ring * temp_ring)2824 void wx_set_ring(struct wx *wx, u32 new_tx_count,
2825 u32 new_rx_count, struct wx_ring *temp_ring)
2826 {
2827 int i, err = 0;
2828
2829 /* Setup new Tx resources and free the old Tx resources in that order.
2830 * We can then assign the new resources to the rings via a memcpy.
2831 * The advantage to this approach is that we are guaranteed to still
2832 * have resources even in the case of an allocation failure.
2833 */
2834 if (new_tx_count != wx->tx_ring_count) {
2835 for (i = 0; i < wx->num_tx_queues; i++) {
2836 memcpy(&temp_ring[i], wx->tx_ring[i],
2837 sizeof(struct wx_ring));
2838
2839 temp_ring[i].count = new_tx_count;
2840 err = wx_setup_tx_resources(&temp_ring[i]);
2841 if (err) {
2842 wx_err(wx, "setup new tx resources failed, keep using the old config\n");
2843 while (i) {
2844 i--;
2845 wx_free_tx_resources(&temp_ring[i]);
2846 }
2847 return;
2848 }
2849 }
2850
2851 for (i = 0; i < wx->num_tx_queues; i++) {
2852 wx_free_tx_resources(wx->tx_ring[i]);
2853
2854 memcpy(wx->tx_ring[i], &temp_ring[i],
2855 sizeof(struct wx_ring));
2856 }
2857
2858 wx->tx_ring_count = new_tx_count;
2859 }
2860
2861 /* Repeat the process for the Rx rings if needed */
2862 if (new_rx_count != wx->rx_ring_count) {
2863 for (i = 0; i < wx->num_rx_queues; i++) {
2864 memcpy(&temp_ring[i], wx->rx_ring[i],
2865 sizeof(struct wx_ring));
2866
2867 temp_ring[i].count = new_rx_count;
2868 err = wx_setup_rx_resources(&temp_ring[i]);
2869 if (err) {
2870 wx_err(wx, "setup new rx resources failed, keep using the old config\n");
2871 while (i) {
2872 i--;
2873 wx_free_rx_resources(&temp_ring[i]);
2874 }
2875 return;
2876 }
2877 }
2878
2879 for (i = 0; i < wx->num_rx_queues; i++) {
2880 wx_free_rx_resources(wx->rx_ring[i]);
2881 memcpy(wx->rx_ring[i], &temp_ring[i],
2882 sizeof(struct wx_ring));
2883 }
2884
2885 wx->rx_ring_count = new_rx_count;
2886 }
2887 }
2888 EXPORT_SYMBOL(wx_set_ring);
2889
2890 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers.");
2891 MODULE_LICENSE("GPL");
2892