1 /* SPDX-License-Identifier: GPL-2.0+ 2 * Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200. 8 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 */ 10 11 #ifndef _SPARX5_MAIN_REGS_H_ 12 #define _SPARX5_MAIN_REGS_H_ 13 14 #include <linux/bitfield.h> 15 #include <linux/types.h> 16 #include <linux/bug.h> 17 18 #include "sparx5_regs.h" 19 20 enum sparx5_target { 21 TARGET_ANA_AC = 1, 22 TARGET_ANA_ACL = 2, 23 TARGET_ANA_AC_POL = 4, 24 TARGET_ANA_AC_SDLB = 5, 25 TARGET_ANA_CL = 6, 26 TARGET_ANA_L2 = 7, 27 TARGET_ANA_L3 = 8, 28 TARGET_ASM = 9, 29 TARGET_CLKGEN = 11, 30 TARGET_CPU = 12, 31 TARGET_DEV10G = 17, 32 TARGET_DEV25G = 29, 33 TARGET_DEV2G5 = 37, 34 TARGET_DEV5G = 102, 35 TARGET_DSM = 115, 36 TARGET_EACL = 116, 37 TARGET_FDMA = 117, 38 TARGET_GCB = 118, 39 TARGET_HSCH = 119, 40 TARGET_HSIO_WRAP = 120, 41 TARGET_LRN = 122, 42 TARGET_PCEP = 129, 43 TARGET_PCS10G_BR = 132, 44 TARGET_PCS25G_BR = 144, 45 TARGET_PCS5G_BR = 160, 46 TARGET_PORT_CONF = 173, 47 TARGET_PTP = 174, 48 TARGET_QFWD = 175, 49 TARGET_QRES = 176, 50 TARGET_QS = 177, 51 TARGET_QSYS = 178, 52 TARGET_REW = 179, 53 TARGET_VCAP_ES0 = 323, 54 TARGET_VCAP_ES2 = 324, 55 TARGET_VCAP_SUPER = 326, 56 TARGET_VOP = 327, 57 TARGET_XQS = 331, 58 TARGET_DEVRGMII = 392, 59 NUM_TARGETS = 517 60 }; 61 62 /* sparx5_main.c 63 * 64 * This is used by the register macros to access chip differences (if any) in: 65 * target size, register address, register count, group address, group count, 66 * group size, field position and field size. 67 */ 68 extern const struct sparx5_regs *regs; 69 70 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 71 #define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 72 #define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 73 74 #define __REG(...) __VA_ARGS__ 75 76 /* ANA_AC:RAM_CTRL:RAM_INIT */ 77 #define ANA_AC_RAM_INIT \ 78 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\ 79 0, 1, 4) 80 81 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 82 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ 83 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 84 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ 85 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 86 87 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) 88 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 89 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 90 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 91 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 92 93 /* ANA_AC:PS_COMMON:OWN_UPSID */ 94 #define ANA_AC_OWN_UPSID(r) \ 95 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\ 96 52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4) 97 98 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 99 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ 100 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 101 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 102 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 103 104 /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ 105 #define ANA_AC_PROBE_CFG(g) \ 106 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 107 32, 0, 0, 1, 4) 108 109 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) 110 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ 111 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 112 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ 113 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 114 115 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) 116 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ 117 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 118 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ 119 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 120 121 #define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) 122 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ 123 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) 124 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ 125 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) 126 127 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) 128 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ 129 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 130 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ 131 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 132 133 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) 134 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ 135 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 136 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ 137 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 138 139 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) 140 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ 141 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 142 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ 143 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 144 145 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ 146 #define ANA_AC_PROBE_PORT_CFG(g) \ 147 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 148 32, 8, 0, 1, 4) 149 150 /* SPARX5 ONLY */ 151 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ 152 #define ANA_AC_PROBE_PORT_CFG1(g) \ 153 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 154 32, 12, 0, 1, 4) 155 156 /* SPARX5 ONLY */ 157 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ 158 #define ANA_AC_PROBE_PORT_CFG2(g) \ 159 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 160 32, 16, 0, 1, 4) 161 162 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) 163 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ 164 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 165 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ 166 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 167 168 /* ANA_AC:SRC:SRC_CFG */ 169 #define ANA_AC_SRC_CFG(g) \ 170 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 171 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4) 172 173 /* SPARX5 ONLY */ 174 /* ANA_AC:SRC:SRC_CFG1 */ 175 #define ANA_AC_SRC_CFG1(g) \ 176 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 177 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4) 178 179 /* SPARX5 ONLY */ 180 /* ANA_AC:SRC:SRC_CFG2 */ 181 #define ANA_AC_SRC_CFG2(g) \ 182 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 183 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4) 184 185 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 186 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ 187 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 188 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 189 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 190 191 /* ANA_AC:PGID:PGID_CFG */ 192 #define ANA_AC_PGID_CFG(g) \ 193 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 194 regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4) 195 196 /* SPARX5 ONLY */ 197 /* ANA_AC:PGID:PGID_CFG1 */ 198 #define ANA_AC_PGID_CFG1(g) \ 199 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 200 regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4) 201 202 /* SPARX5 ONLY */ 203 /* ANA_AC:PGID:PGID_CFG2 */ 204 #define ANA_AC_PGID_CFG2(g) \ 205 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 206 regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4) 207 208 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 209 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ 210 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 211 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 212 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 213 214 /* ANA_AC:PGID:PGID_MISC_CFG */ 215 #define ANA_AC_PGID_MISC_CFG(g) \ 216 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 217 regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4) 218 219 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 220 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ 221 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 222 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ 223 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 224 225 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) 226 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ 227 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 228 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ 229 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 230 231 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) 232 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ 233 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 234 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 235 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 236 237 /* ANA_AC:TSN_SF:TSN_SF */ 238 #define ANA_AC_TSN_SF \ 239 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \ 240 0, 1, 4) 241 242 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) 243 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ 244 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 245 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ 246 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 247 248 #define ANA_AC_TSN_SF_PORT_NUM\ 249 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0) 250 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ 251 spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x) 252 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ 253 spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x) 254 255 /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 256 #define ANA_AC_TSN_SF_CFG(g) \ 257 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \ 258 regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4) 259 260 #define ANA_AC_TSN_SF_CFG_TSN_SGID\ 261 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16) 262 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ 263 spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 264 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ 265 spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 266 267 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) 268 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ 269 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 270 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\ 271 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 272 273 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1) 274 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\ 275 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 276 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\ 277 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 278 279 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE BIT(0) 280 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\ 281 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 282 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ 283 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 284 285 /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 286 #define ANA_AC_TSN_SF_STATUS \ 287 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \ 288 16, 0, 0, 1, 4) 289 290 #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) 291 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ 292 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 293 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\ 294 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 295 296 #define ANA_AC_TSN_SF_STATUS_DLB_DROP BIT(11) 297 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\ 298 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 299 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ 300 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 301 302 #define ANA_AC_TSN_SF_STATUS_TSN_SFID\ 303 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1) 304 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ 305 spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 306 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ 307 spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 308 309 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) 310 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ 311 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 312 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ 313 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 314 315 /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 316 #define ANA_AC_SG_ACCESS_CTRL \ 317 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 318 0, 0, 1, 4) 319 320 #define ANA_AC_SG_ACCESS_CTRL_SGID\ 321 GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0) 322 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ 323 spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x) 324 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ 325 spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x) 326 327 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) 328 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ 329 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 330 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ 331 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 332 333 /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 334 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ 335 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 336 8, 0, 1, 4) 337 338 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) 339 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ 340 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 341 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\ 342 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 343 344 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31) 345 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\ 346 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 347 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ 348 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 349 350 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 351 #define ANA_AC_SG_CONFIG_REG_1 \ 352 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 353 48, 0, 1, 4) 354 355 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 356 #define ANA_AC_SG_CONFIG_REG_2 \ 357 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 358 52, 0, 1, 4) 359 360 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 361 #define ANA_AC_SG_CONFIG_REG_3 \ 362 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 363 56, 0, 1, 4) 364 365 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) 366 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ 367 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 368 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\ 369 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 370 371 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16) 372 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\ 373 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 374 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\ 375 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 376 377 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) 378 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\ 379 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 380 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\ 381 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 382 383 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21) 384 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\ 385 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 386 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\ 387 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 388 389 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) 390 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\ 391 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 392 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\ 393 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 394 395 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA BIT(26) 396 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\ 397 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 398 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\ 399 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 400 401 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX BIT(27) 402 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\ 403 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 404 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\ 405 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 406 407 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28) 408 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\ 409 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 410 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\ 411 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 412 413 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED BIT(29) 414 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\ 415 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 416 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ 417 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 418 419 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 420 #define ANA_AC_SG_CONFIG_REG_4 \ 421 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 422 60, 0, 1, 4) 423 424 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 425 #define ANA_AC_SG_CONFIG_REG_5 \ 426 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 427 64, 0, 1, 4) 428 429 /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 430 #define ANA_AC_SG_GCL_GS_CONFIG(r) \ 431 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 432 0, r, 4, 4) 433 434 #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) 435 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ 436 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 437 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\ 438 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 439 440 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) 441 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\ 442 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 443 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ 444 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 445 446 /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 447 #define ANA_AC_SG_GCL_TI_CONFIG(r) \ 448 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 449 16, r, 4, 4) 450 451 /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 452 #define ANA_AC_SG_GCL_OCT_CONFIG(r) \ 453 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 454 32, r, 4, 4) 455 456 /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 457 #define ANA_AC_SG_STATUS_REG_1 \ 458 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 459 0, 0, 1, 4) 460 461 /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 462 #define ANA_AC_SG_STATUS_REG_2 \ 463 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 464 4, 0, 1, 4) 465 466 /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 467 #define ANA_AC_SG_STATUS_REG_3 \ 468 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 469 8, 0, 1, 4) 470 471 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) 472 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ 473 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 474 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\ 475 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 476 477 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE BIT(16) 478 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\ 479 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 480 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\ 481 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 482 483 #define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20) 484 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\ 485 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x) 486 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\ 487 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x) 488 489 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) 490 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\ 491 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 492 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\ 493 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 494 495 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25) 496 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\ 497 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 498 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ 499 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 500 501 /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 502 #define ANA_AC_SG_STATUS_REG_4 \ 503 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 504 12, 0, 1, 4) 505 506 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 507 #define ANA_AC_PORT_SGE_CFG(r) \ 508 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 509 0, 1, 20, 0, r, 4, 4) 510 511 #define ANA_AC_PORT_SGE_CFG_MASK\ 512 GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0) 513 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 514 spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x) 515 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 516 spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x) 517 518 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 519 #define ANA_AC_STAT_RESET \ 520 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 521 0, 1, 20, 16, 0, 1, 4) 522 523 #define ANA_AC_STAT_RESET_RESET BIT(0) 524 #define ANA_AC_STAT_RESET_RESET_SET(x)\ 525 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) 526 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 527 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 528 529 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 530 #define ANA_AC_PORT_STAT_CFG(g, r) \ 531 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 532 regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4) 533 534 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 535 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ 536 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 537 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ 538 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 539 540 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) 541 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ 542 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 543 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ 544 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 545 546 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) 547 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ 548 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 549 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 550 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 551 552 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 553 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ 554 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 555 regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4) 556 557 /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ 558 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) \ 559 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 560 0, 1, 24, 0, r, 2, 4) 561 562 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) 563 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ 564 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 565 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ 566 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 567 568 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ 569 #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) \ 570 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 571 0, 1, 24, 8, r, 2, 4) 572 573 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) 574 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ 575 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 576 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ 577 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 578 579 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ 580 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) \ 581 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 582 0, 1, 24, 16, r, 2, 4) 583 584 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) 585 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ 586 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 587 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ 588 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 589 590 /* ANA_ACL:COMMON:VCAP_S2_CFG */ 591 #define ANA_ACL_VCAP_S2_CFG(r) \ 592 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 593 0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4) 594 595 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 596 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ 597 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 598 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ 599 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 600 601 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26) 602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ 603 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 604 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ 605 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 606 607 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24) 608 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ 609 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 610 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ 611 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 612 613 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22) 614 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ 615 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 616 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ 617 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 618 619 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20) 620 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ 621 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 622 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ 623 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 624 625 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18) 626 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ 627 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 628 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ 629 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 630 631 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16) 632 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ 633 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 634 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ 635 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 636 637 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14) 638 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ 639 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 640 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ 641 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 642 643 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12) 644 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ 645 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 646 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ 647 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 648 649 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10) 650 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ 651 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 652 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ 653 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 654 655 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8) 656 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ 657 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 658 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ 659 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 660 661 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6) 662 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ 663 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 664 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ 665 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 666 667 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4) 668 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ 669 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 670 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ 671 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 672 673 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0) 674 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ 675 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 676 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 677 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 678 679 /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 680 #define ANA_ACL_SWAP_IP_CTRL \ 681 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 682 412, 0, 1, 4) 683 684 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 685 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ 686 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 687 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ 688 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 689 690 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10) 691 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ 692 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 693 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ 694 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 695 696 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2) 697 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ 698 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 699 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ 700 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 701 702 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1) 703 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ 704 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 705 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ 706 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 707 708 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0) 709 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ 710 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 711 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 712 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 713 714 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 715 #define ANA_ACL_VCAP_S2_RLEG_STAT(r) \ 716 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 717 424, r, 4, 4) 718 719 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 720 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ 721 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 722 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ 723 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 724 725 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0) 726 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ 727 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 728 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 729 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 730 731 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 732 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG \ 733 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 734 440, 0, 1, 4) 735 736 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 737 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ 738 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 739 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ 740 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 741 742 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4) 743 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ 744 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 745 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ 746 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 747 748 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0) 749 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ 750 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 751 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 752 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 753 754 /* ANA_ACL:COMMON:OWN_UPSID */ 755 #define ANA_ACL_OWN_UPSID(r) \ 756 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 757 580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4) 758 759 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 760 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ 761 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 762 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 763 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 764 765 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 766 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ 767 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \ 768 regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4) 769 770 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 771 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ 772 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 773 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ 774 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 775 776 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12) 777 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ 778 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 779 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ 780 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 781 782 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10) 783 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ 784 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 785 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ 786 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 787 788 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8) 789 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ 790 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 791 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ 792 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 793 794 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6) 795 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ 796 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 797 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ 798 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 799 800 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3) 801 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ 802 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 803 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ 804 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 805 806 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1) 807 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ 808 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 809 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ 810 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 811 812 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0) 813 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 814 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 815 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 816 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 817 818 /* ANA_ACL:CNT_A:CNT_A */ 819 #define ANA_ACL_CNT_A(g) \ 820 __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \ 821 0, 1, 4) 822 823 /* ANA_ACL:CNT_B:CNT_B */ 824 #define ANA_ACL_CNT_B(g) \ 825 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \ 826 regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4) 827 828 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 829 #define ANA_ACL_SEC_LOOKUP_STICKY(r) \ 830 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \ 831 0, r, 4, 4) 832 833 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 834 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ 835 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 836 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ 837 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 838 839 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16) 840 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ 841 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 842 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ 843 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 844 845 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15) 846 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ 847 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 848 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ 849 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 850 851 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14) 852 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ 853 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 854 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ 855 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 856 857 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13) 858 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ 859 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 860 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ 861 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 862 863 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12) 864 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ 865 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 866 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ 867 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 868 869 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11) 870 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ 871 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 872 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ 873 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 874 875 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10) 876 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 877 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 878 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 879 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 880 881 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9) 882 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 883 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 884 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 885 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 886 887 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8) 888 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ 889 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 890 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ 891 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 892 893 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 894 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 895 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 896 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 897 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 898 899 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6) 900 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 901 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 902 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 903 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 904 905 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5) 906 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 907 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 908 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 909 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 910 911 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4) 912 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 913 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 914 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 915 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 916 917 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3) 918 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 919 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 920 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 921 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 922 923 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2) 924 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ 925 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 926 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ 927 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 928 929 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1) 930 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ 931 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 932 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ 933 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 934 935 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 936 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 937 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 938 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 939 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 940 941 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 942 #define ANA_AC_POL_POL_UPD_INT_CFG \ 943 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \ 944 0, 1, 1160, 1148, 0, 1, 4) 945 946 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 947 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ 948 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 949 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 950 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 951 952 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 953 #define ANA_AC_POL_BDLB_DLB_CTRL \ 954 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \ 955 0, 1, 8, 0, 0, 1, 4) 956 957 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 958 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 959 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 960 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 961 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 962 963 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 964 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 965 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 966 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 967 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 968 969 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) 970 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ 971 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 972 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ 973 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 974 975 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 976 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 977 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 978 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 979 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 980 981 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 982 #define ANA_AC_POL_SLB_DLB_CTRL \ 983 __REG(TARGET_ANA_AC_POL, 0, 1, \ 984 regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4) 985 986 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 987 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 988 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 989 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 990 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 991 992 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 993 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 994 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 995 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 996 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 997 998 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) 999 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ 1000 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 1001 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ 1002 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 1003 1004 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 1005 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 1006 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 1007 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 1008 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 1009 1010 /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 1011 #define ANA_AC_SDLB_XLB_START(g) \ 1012 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1013 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4) 1014 1015 #define ANA_AC_SDLB_XLB_START_LBSET_START\ 1016 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0) 1017 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ 1018 spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1019 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ 1020 spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1021 1022 /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 1023 #define ANA_AC_SDLB_PUP_INTERVAL(g) \ 1024 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1025 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4) 1026 1027 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) 1028 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ 1029 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 1030 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ 1031 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 1032 1033 /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 1034 #define ANA_AC_SDLB_PUP_CTRL(g) \ 1035 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1036 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4) 1037 1038 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) 1039 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ 1040 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 1041 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\ 1042 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 1043 1044 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA BIT(24) 1045 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\ 1046 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 1047 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ 1048 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 1049 1050 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 1051 #define ANA_AC_SDLB_LBGRP_MISC(g) \ 1052 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1053 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4) 1054 1055 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\ 1056 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8) 1057 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ 1058 spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1059 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ 1060 spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1061 1062 /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 1063 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ 1064 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1065 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4) 1066 1067 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) 1068 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ 1069 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 1070 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ 1071 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 1072 1073 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 1074 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ 1075 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1076 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4) 1077 1078 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) 1079 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ 1080 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 1081 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\ 1082 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 1083 1084 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1) 1085 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\ 1086 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1087 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ 1088 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1089 1090 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\ 1091 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16) 1092 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ 1093 spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1094 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ 1095 spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1096 1097 /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 1098 #define ANA_AC_SDLB_PUP_TOKENS(g, r) \ 1099 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1100 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4) 1101 1102 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) 1103 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ 1104 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1105 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ 1106 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1107 1108 /* ANA_AC_SDLB:LBSET_TBL:THRES */ 1109 #define ANA_AC_SDLB_THRES(g, r) \ 1110 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1111 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4) 1112 1113 #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) 1114 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ 1115 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x) 1116 #define ANA_AC_SDLB_THRES_THRES_GET(x)\ 1117 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x) 1118 1119 #define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16) 1120 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\ 1121 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x) 1122 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ 1123 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) 1124 1125 /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 1126 #define ANA_AC_SDLB_XLB_NEXT(g) \ 1127 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1128 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4) 1129 1130 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\ 1131 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0) 1132 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ 1133 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1134 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ 1135 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1136 1137 #define ANA_AC_SDLB_XLB_NEXT_LBGRP\ 1138 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24) 1139 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ 1140 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1141 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ 1142 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1143 1144 /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 1145 #define ANA_AC_SDLB_INH_CTRL(g, r) \ 1146 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1147 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4) 1148 1149 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) 1150 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ 1151 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1152 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\ 1153 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1154 1155 #define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20) 1156 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\ 1157 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1158 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\ 1159 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1160 1161 #define ANA_AC_SDLB_INH_CTRL_INH_LB BIT(24) 1162 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\ 1163 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1164 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ 1165 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1166 1167 /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 1168 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ 1169 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1170 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4) 1171 1172 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\ 1173 GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0) 1174 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ 1175 spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1176 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ 1177 spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1178 1179 /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 1180 #define ANA_AC_SDLB_DLB_MISC(g) \ 1181 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1182 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4) 1183 1184 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) 1185 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ 1186 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1187 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\ 1188 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1189 1190 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6) 1191 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\ 1192 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1193 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\ 1194 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1195 1196 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8) 1197 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\ 1198 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1199 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ 1200 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1201 1202 /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 1203 #define ANA_AC_SDLB_DLB_CFG(g) \ 1204 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1205 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4) 1206 1207 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) 1208 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ 1209 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1210 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\ 1211 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1212 1213 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9) 1214 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\ 1215 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1216 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\ 1217 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1218 1219 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS BIT(8) 1220 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\ 1221 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1222 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\ 1223 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1224 1225 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS BIT(7) 1226 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\ 1227 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1228 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\ 1229 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1230 1231 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5) 1232 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\ 1233 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1234 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\ 1235 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1236 1237 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3) 1238 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\ 1239 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1240 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\ 1241 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1242 1243 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE BIT(2) 1244 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\ 1245 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1246 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\ 1247 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1248 1249 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0) 1250 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\ 1251 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1252 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ 1253 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1254 1255 /* ANA_CL:PORT:FILTER_CTRL */ 1256 #define ANA_CL_FILTER_CTRL(g) \ 1257 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1258 regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4) 1259 1260 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 1261 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ 1262 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1263 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ 1264 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1265 1266 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) 1267 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ 1268 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1269 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ 1270 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1271 1272 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) 1273 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ 1274 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1275 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 1276 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1277 1278 /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1279 #define ANA_CL_VLAN_FILTER_CTRL(g, r) \ 1280 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1281 regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4) 1282 1283 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 1284 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ 1285 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1286 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ 1287 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1288 1289 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) 1290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ 1291 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1292 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ 1293 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1294 1295 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) 1296 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ 1297 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1298 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ 1299 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1300 1301 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) 1302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ 1303 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1304 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ 1305 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1306 1307 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) 1308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ 1309 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1310 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ 1311 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1312 1313 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) 1314 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ 1315 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1316 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ 1317 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1318 1319 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) 1320 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ 1321 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1322 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ 1323 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1324 1325 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) 1326 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ 1327 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1328 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ 1329 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1330 1331 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) 1332 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ 1333 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1334 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ 1335 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1336 1337 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) 1338 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ 1339 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1340 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ 1341 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1342 1343 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) 1344 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ 1345 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1346 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 1347 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1348 1349 /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1350 #define ANA_CL_ETAG_FILTER_CTRL(g) \ 1351 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1352 regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4) 1353 1354 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 1355 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ 1356 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1357 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ 1358 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1359 1360 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) 1361 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ 1362 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1363 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 1364 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1365 1366 /* ANA_CL:PORT:VLAN_CTRL */ 1367 #define ANA_CL_VLAN_CTRL(g) \ 1368 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1369 regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4) 1370 1371 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 1372 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ 1373 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1374 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ 1375 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1376 1377 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) 1378 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ 1379 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1380 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ 1381 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1382 1383 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) 1384 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ 1385 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1386 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ 1387 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1388 1389 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) 1390 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ 1391 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1392 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ 1393 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1394 1395 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) 1396 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ 1397 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1398 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ 1399 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1400 1401 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) 1402 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ 1403 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1404 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ 1405 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1406 1407 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) 1408 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ 1409 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1410 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ 1411 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1412 1413 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) 1414 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ 1415 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1416 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ 1417 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1418 1419 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) 1420 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ 1421 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1422 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ 1423 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1424 1425 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) 1426 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ 1427 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1428 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ 1429 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1430 1431 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) 1432 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ 1433 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) 1434 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 1435 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 1436 1437 /* ANA_CL:PORT:VLAN_CTRL_2 */ 1438 #define ANA_CL_VLAN_CTRL_2(g) \ 1439 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1440 regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4) 1441 1442 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 1443 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ 1444 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1445 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 1446 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1447 1448 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1449 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ 1450 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1451 regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4) 1452 1453 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 1454 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ 1455 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1456 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ 1457 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1458 1459 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0) 1460 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ 1461 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1462 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 1463 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1464 1465 /* ANA_CL:PORT:QOS_CFG */ 1466 #define ANA_CL_QOS_CFG(g) \ 1467 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1468 regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4) 1469 1470 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 1471 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ 1472 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1473 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ 1474 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1475 1476 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14) 1477 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ 1478 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1479 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ 1480 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1481 1482 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12) 1483 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ 1484 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1485 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ 1486 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1487 1488 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11) 1489 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ 1490 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1491 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ 1492 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1493 1494 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10) 1495 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ 1496 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1497 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ 1498 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1499 1500 #define ANA_CL_QOS_CFG_KEEP_ENA BIT(9) 1501 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ 1502 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x) 1503 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ 1504 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x) 1505 1506 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8) 1507 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ 1508 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1509 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ 1510 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1511 1512 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7) 1513 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ 1514 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1515 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ 1516 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1517 1518 #define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6) 1519 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ 1520 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1521 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ 1522 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1523 1524 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5) 1525 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ 1526 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1527 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ 1528 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1529 1530 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3) 1531 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ 1532 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1533 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ 1534 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1535 1536 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0) 1537 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ 1538 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1539 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 1540 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1541 1542 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1543 #define ANA_CL_CAPTURE_BPDU_CFG(g) \ 1544 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1545 regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4) 1546 1547 /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1548 #define ANA_CL_ADV_CL_CFG_2(g, r) \ 1549 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1550 regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4) 1551 1552 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) 1553 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ 1554 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1555 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\ 1556 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1557 1558 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA BIT(0) 1559 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\ 1560 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1561 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ 1562 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1563 1564 /* ANA_CL:PORT:ADV_CL_CFG */ 1565 #define ANA_CL_ADV_CL_CFG(g, r) \ 1566 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1567 regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4) 1568 1569 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) 1570 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ 1571 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1572 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\ 1573 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1574 1575 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21) 1576 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\ 1577 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1578 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\ 1579 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1580 1581 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16) 1582 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\ 1583 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1584 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\ 1585 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1586 1587 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11) 1588 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\ 1589 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1590 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\ 1591 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1592 1593 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6) 1594 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\ 1595 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1596 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\ 1597 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1598 1599 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1) 1600 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\ 1601 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1602 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\ 1603 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1604 1605 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA BIT(0) 1606 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\ 1607 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1608 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ 1609 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1610 1611 /* ANA_CL:COMMON:OWN_UPSID */ 1612 #define ANA_CL_OWN_UPSID(r) \ 1613 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\ 1614 r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4) 1615 1616 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1617 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ 1618 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1619 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 1620 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1621 1622 /* ANA_CL:COMMON:DSCP_CFG */ 1623 #define ANA_CL_DSCP_CFG(r) \ 1624 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1625 256, r, 64, 4) 1626 1627 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 1628 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ 1629 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1630 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ 1631 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1632 1633 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4) 1634 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ 1635 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1636 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ 1637 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1638 1639 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2) 1640 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ 1641 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1642 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ 1643 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1644 1645 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1) 1646 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 1647 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1648 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 1649 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1650 1651 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0) 1652 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 1653 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1654 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 1655 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1656 1657 /* ANA_CL:COMMON:QOS_MAP_CFG */ 1658 #define ANA_CL_QOS_MAP_CFG(r) \ 1659 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1660 512, r, 32, 4) 1661 1662 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) 1663 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ 1664 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1665 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ 1666 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1667 1668 /* ANA_L2:COMMON:FWD_CFG */ 1669 #define ANA_L2_FWD_CFG \ 1670 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1671 regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4) 1672 1673 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) 1674 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ 1675 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1676 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\ 1677 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1678 1679 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA BIT(18) 1680 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\ 1681 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1682 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\ 1683 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1684 1685 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA BIT(17) 1686 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\ 1687 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1688 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\ 1689 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1690 1691 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA BIT(16) 1692 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\ 1693 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1694 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\ 1695 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1696 1697 #define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8) 1698 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\ 1699 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1700 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\ 1701 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1702 1703 #define ANA_L2_FWD_CFG_LOOPBACK_ENA BIT(7) 1704 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\ 1705 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1706 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\ 1707 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1708 1709 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) 1710 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\ 1711 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1712 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\ 1713 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1714 1715 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL BIT(4) 1716 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\ 1717 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1718 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\ 1719 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1720 1721 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA BIT(3) 1722 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\ 1723 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1724 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\ 1725 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1726 1727 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA BIT(2) 1728 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\ 1729 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1730 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\ 1731 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1732 1733 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1) 1734 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\ 1735 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1736 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\ 1737 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1738 1739 #define ANA_L2_FWD_CFG_FWD_ENA BIT(0) 1740 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\ 1741 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x) 1742 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ 1743 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) 1744 1745 /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1746 #define ANA_L2_AUTO_LRN_CFG \ 1747 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1748 regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4) 1749 1750 /* SPARX5 ONLY */ 1751 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1752 #define ANA_L2_AUTO_LRN_CFG1 \ 1753 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1754 regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4) 1755 1756 /* SPARX5 ONLY */ 1757 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1758 #define ANA_L2_AUTO_LRN_CFG2 \ 1759 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1760 regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4) 1761 1762 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 1763 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ 1764 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1765 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 1766 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1767 1768 /* ANA_L2:COMMON:OWN_UPSID */ 1769 #define ANA_L2_OWN_UPSID(r) \ 1770 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1771 regs->gsize[GW_ANA_L2_COMMON], 672, r, \ 1772 regs->rcnt[RC_ANA_L2_OWN_UPSID], 4) 1773 1774 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1775 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ 1776 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1777 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 1778 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1779 1780 /* ANA_L2:ISDX:DLB_CFG */ 1781 #define ANA_L2_DLB_CFG(g) \ 1782 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \ 1783 0, 1, 4) 1784 1785 #define ANA_L2_DLB_CFG_DLB_IDX\ 1786 GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0) 1787 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ 1788 spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x) 1789 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ 1790 spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x) 1791 1792 /* ANA_L2:ISDX:TSN_CFG */ 1793 #define ANA_L2_TSN_CFG(g) \ 1794 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \ 1795 0, 1, 4) 1796 1797 #define ANA_L2_TSN_CFG_TSN_SFID\ 1798 GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0) 1799 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ 1800 spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x) 1801 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ 1802 spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x) 1803 1804 /* ANA_L3:COMMON:VLAN_CTRL */ 1805 #define ANA_L3_VLAN_CTRL \ 1806 __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\ 1807 0, 1, 4) 1808 1809 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 1810 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ 1811 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1812 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 1813 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1814 1815 /* ANA_L3:VLAN:VLAN_CFG */ 1816 #define ANA_L3_VLAN_CFG(g) \ 1817 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \ 1818 1, 4) 1819 1820 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 1821 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ 1822 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1823 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ 1824 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1825 1826 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) 1827 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ 1828 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) 1829 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ 1830 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) 1831 1832 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) 1833 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ 1834 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1835 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ 1836 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1837 1838 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) 1839 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ 1840 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1841 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ 1842 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1843 1844 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) 1845 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ 1846 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1847 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ 1848 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1849 1850 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) 1851 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ 1852 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1853 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ 1854 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1855 1856 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) 1857 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ 1858 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1859 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ 1860 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1861 1862 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) 1863 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ 1864 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1865 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ 1866 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1867 1868 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) 1869 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ 1870 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1871 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 1872 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1873 1874 /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1875 #define ANA_L3_VLAN_MASK_CFG(g) \ 1876 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\ 1877 1, 4) 1878 1879 /* SPARX5 ONLY */ 1880 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1881 #define ANA_L3_VLAN_MASK_CFG1(g) \ 1882 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\ 1883 1, 4) 1884 1885 /* SPARX5 ONLY */ 1886 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1887 #define ANA_L3_VLAN_MASK_CFG2(g) \ 1888 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\ 1889 1, 4) 1890 1891 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 1892 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ 1893 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1894 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 1895 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1896 1897 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1898 #define ASM_RX_IN_BYTES_CNT(g) \ 1899 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1900 0, 0, 1, 4) 1901 1902 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1903 #define ASM_RX_SYMBOL_ERR_CNT(g) \ 1904 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1905 4, 0, 1, 4) 1906 1907 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1908 #define ASM_RX_PAUSE_CNT(g) \ 1909 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1910 8, 0, 1, 4) 1911 1912 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1913 #define ASM_RX_UNSUP_OPCODE_CNT(g) \ 1914 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1915 12, 0, 1, 4) 1916 1917 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1918 #define ASM_RX_OK_BYTES_CNT(g) \ 1919 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1920 16, 0, 1, 4) 1921 1922 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1923 #define ASM_RX_BAD_BYTES_CNT(g) \ 1924 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1925 20, 0, 1, 4) 1926 1927 /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1928 #define ASM_RX_UC_CNT(g) \ 1929 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1930 24, 0, 1, 4) 1931 1932 /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1933 #define ASM_RX_MC_CNT(g) \ 1934 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1935 28, 0, 1, 4) 1936 1937 /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1938 #define ASM_RX_BC_CNT(g) \ 1939 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1940 32, 0, 1, 4) 1941 1942 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1943 #define ASM_RX_CRC_ERR_CNT(g) \ 1944 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1945 36, 0, 1, 4) 1946 1947 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1948 #define ASM_RX_UNDERSIZE_CNT(g) \ 1949 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1950 40, 0, 1, 4) 1951 1952 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1953 #define ASM_RX_FRAGMENTS_CNT(g) \ 1954 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1955 44, 0, 1, 4) 1956 1957 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1958 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ 1959 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1960 48, 0, 1, 4) 1961 1962 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1963 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 1964 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1965 52, 0, 1, 4) 1966 1967 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1968 #define ASM_RX_OVERSIZE_CNT(g) \ 1969 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1970 56, 0, 1, 4) 1971 1972 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1973 #define ASM_RX_JABBERS_CNT(g) \ 1974 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1975 60, 0, 1, 4) 1976 1977 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1978 #define ASM_RX_SIZE64_CNT(g) \ 1979 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1980 64, 0, 1, 4) 1981 1982 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1983 #define ASM_RX_SIZE65TO127_CNT(g) \ 1984 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1985 68, 0, 1, 4) 1986 1987 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1988 #define ASM_RX_SIZE128TO255_CNT(g) \ 1989 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1990 72, 0, 1, 4) 1991 1992 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1993 #define ASM_RX_SIZE256TO511_CNT(g) \ 1994 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1995 76, 0, 1, 4) 1996 1997 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1998 #define ASM_RX_SIZE512TO1023_CNT(g) \ 1999 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2000 80, 0, 1, 4) 2001 2002 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 2003 #define ASM_RX_SIZE1024TO1518_CNT(g) \ 2004 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2005 84, 0, 1, 4) 2006 2007 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 2008 #define ASM_RX_SIZE1519TOMAX_CNT(g) \ 2009 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2010 88, 0, 1, 4) 2011 2012 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 2013 #define ASM_RX_IPG_SHRINK_CNT(g) \ 2014 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2015 92, 0, 1, 4) 2016 2017 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 2018 #define ASM_TX_OUT_BYTES_CNT(g) \ 2019 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2020 96, 0, 1, 4) 2021 2022 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 2023 #define ASM_TX_PAUSE_CNT(g) \ 2024 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2025 100, 0, 1, 4) 2026 2027 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 2028 #define ASM_TX_OK_BYTES_CNT(g) \ 2029 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2030 104, 0, 1, 4) 2031 2032 /* ASM:DEV_STATISTICS:TX_UC_CNT */ 2033 #define ASM_TX_UC_CNT(g) \ 2034 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2035 108, 0, 1, 4) 2036 2037 /* ASM:DEV_STATISTICS:TX_MC_CNT */ 2038 #define ASM_TX_MC_CNT(g) \ 2039 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2040 112, 0, 1, 4) 2041 2042 /* ASM:DEV_STATISTICS:TX_BC_CNT */ 2043 #define ASM_TX_BC_CNT(g) \ 2044 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2045 116, 0, 1, 4) 2046 2047 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 2048 #define ASM_TX_SIZE64_CNT(g) \ 2049 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2050 120, 0, 1, 4) 2051 2052 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 2053 #define ASM_TX_SIZE65TO127_CNT(g) \ 2054 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2055 124, 0, 1, 4) 2056 2057 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 2058 #define ASM_TX_SIZE128TO255_CNT(g) \ 2059 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2060 128, 0, 1, 4) 2061 2062 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 2063 #define ASM_TX_SIZE256TO511_CNT(g) \ 2064 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2065 132, 0, 1, 4) 2066 2067 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 2068 #define ASM_TX_SIZE512TO1023_CNT(g) \ 2069 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2070 136, 0, 1, 4) 2071 2072 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 2073 #define ASM_TX_SIZE1024TO1518_CNT(g) \ 2074 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2075 140, 0, 1, 4) 2076 2077 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 2078 #define ASM_TX_SIZE1519TOMAX_CNT(g) \ 2079 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2080 144, 0, 1, 4) 2081 2082 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 2083 #define ASM_RX_ALIGNMENT_LOST_CNT(g) \ 2084 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2085 148, 0, 1, 4) 2086 2087 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 2088 #define ASM_RX_TAGGED_FRMS_CNT(g) \ 2089 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2090 152, 0, 1, 4) 2091 2092 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 2093 #define ASM_RX_UNTAGGED_FRMS_CNT(g) \ 2094 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2095 156, 0, 1, 4) 2096 2097 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 2098 #define ASM_TX_TAGGED_FRMS_CNT(g) \ 2099 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2100 160, 0, 1, 4) 2101 2102 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 2103 #define ASM_TX_UNTAGGED_FRMS_CNT(g) \ 2104 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2105 164, 0, 1, 4) 2106 2107 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 2108 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ 2109 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2110 168, 0, 1, 4) 2111 2112 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 2113 #define ASM_PMAC_RX_PAUSE_CNT(g) \ 2114 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2115 172, 0, 1, 4) 2116 2117 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 2118 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ 2119 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2120 176, 0, 1, 4) 2121 2122 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 2123 #define ASM_PMAC_RX_OK_BYTES_CNT(g) \ 2124 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2125 180, 0, 1, 4) 2126 2127 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 2128 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ 2129 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2130 184, 0, 1, 4) 2131 2132 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 2133 #define ASM_PMAC_RX_UC_CNT(g) \ 2134 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2135 188, 0, 1, 4) 2136 2137 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 2138 #define ASM_PMAC_RX_MC_CNT(g) \ 2139 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2140 192, 0, 1, 4) 2141 2142 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 2143 #define ASM_PMAC_RX_BC_CNT(g) \ 2144 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2145 196, 0, 1, 4) 2146 2147 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 2148 #define ASM_PMAC_RX_CRC_ERR_CNT(g) \ 2149 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2150 200, 0, 1, 4) 2151 2152 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 2153 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ 2154 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2155 204, 0, 1, 4) 2156 2157 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 2158 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ 2159 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2160 208, 0, 1, 4) 2161 2162 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 2163 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ 2164 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2165 212, 0, 1, 4) 2166 2167 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2168 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 2169 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2170 216, 0, 1, 4) 2171 2172 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 2173 #define ASM_PMAC_RX_OVERSIZE_CNT(g) \ 2174 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2175 220, 0, 1, 4) 2176 2177 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 2178 #define ASM_PMAC_RX_JABBERS_CNT(g) \ 2179 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2180 224, 0, 1, 4) 2181 2182 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 2183 #define ASM_PMAC_RX_SIZE64_CNT(g) \ 2184 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2185 228, 0, 1, 4) 2186 2187 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 2188 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ 2189 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2190 232, 0, 1, 4) 2191 2192 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 2193 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ 2194 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2195 236, 0, 1, 4) 2196 2197 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 2198 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ 2199 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2200 240, 0, 1, 4) 2201 2202 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 2203 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ 2204 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2205 244, 0, 1, 4) 2206 2207 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 2208 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ 2209 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2210 248, 0, 1, 4) 2211 2212 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 2213 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ 2214 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2215 252, 0, 1, 4) 2216 2217 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 2218 #define ASM_PMAC_TX_PAUSE_CNT(g) \ 2219 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2220 256, 0, 1, 4) 2221 2222 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 2223 #define ASM_PMAC_TX_OK_BYTES_CNT(g) \ 2224 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2225 260, 0, 1, 4) 2226 2227 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 2228 #define ASM_PMAC_TX_UC_CNT(g) \ 2229 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2230 264, 0, 1, 4) 2231 2232 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 2233 #define ASM_PMAC_TX_MC_CNT(g) \ 2234 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2235 268, 0, 1, 4) 2236 2237 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 2238 #define ASM_PMAC_TX_BC_CNT(g) \ 2239 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2240 272, 0, 1, 4) 2241 2242 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 2243 #define ASM_PMAC_TX_SIZE64_CNT(g) \ 2244 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2245 276, 0, 1, 4) 2246 2247 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 2248 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ 2249 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2250 280, 0, 1, 4) 2251 2252 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 2253 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ 2254 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2255 284, 0, 1, 4) 2256 2257 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 2258 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ 2259 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2260 288, 0, 1, 4) 2261 2262 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 2263 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ 2264 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2265 292, 0, 1, 4) 2266 2267 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 2268 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ 2269 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2270 296, 0, 1, 4) 2271 2272 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 2273 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ 2274 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2275 300, 0, 1, 4) 2276 2277 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 2278 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ 2279 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2280 304, 0, 1, 4) 2281 2282 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 2283 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ 2284 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2285 308, 0, 1, 4) 2286 2287 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 2288 #define ASM_MM_RX_SMD_ERR_CNT(g) \ 2289 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2290 312, 0, 1, 4) 2291 2292 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 2293 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ 2294 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2295 316, 0, 1, 4) 2296 2297 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 2298 #define ASM_MM_RX_MERGE_FRAG_CNT(g) \ 2299 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2300 320, 0, 1, 4) 2301 2302 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 2303 #define ASM_MM_TX_PFRAGMENT_CNT(g) \ 2304 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2305 324, 0, 1, 4) 2306 2307 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 2308 #define ASM_TX_MULTI_COLL_CNT(g) \ 2309 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2310 328, 0, 1, 4) 2311 2312 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 2313 #define ASM_TX_LATE_COLL_CNT(g) \ 2314 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2315 332, 0, 1, 4) 2316 2317 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 2318 #define ASM_TX_XCOLL_CNT(g) \ 2319 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2320 336, 0, 1, 4) 2321 2322 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 2323 #define ASM_TX_DEFER_CNT(g) \ 2324 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2325 340, 0, 1, 4) 2326 2327 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 2328 #define ASM_TX_XDEFER_CNT(g) \ 2329 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2330 344, 0, 1, 4) 2331 2332 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 2333 #define ASM_TX_BACKOFF1_CNT(g) \ 2334 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2335 348, 0, 1, 4) 2336 2337 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 2338 #define ASM_TX_CSENSE_CNT(g) \ 2339 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2340 352, 0, 1, 4) 2341 2342 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 2343 #define ASM_RX_IN_BYTES_MSB_CNT(g) \ 2344 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2345 356, 0, 1, 4) 2346 2347 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 2348 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 2349 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2350 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 2351 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2352 2353 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 2354 #define ASM_RX_OK_BYTES_MSB_CNT(g) \ 2355 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2356 360, 0, 1, 4) 2357 2358 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2359 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 2360 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2361 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 2362 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2363 2364 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 2365 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ 2366 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2367 364, 0, 1, 4) 2368 2369 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2370 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 2371 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2372 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 2373 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2374 2375 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 2376 #define ASM_RX_BAD_BYTES_MSB_CNT(g) \ 2377 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2378 368, 0, 1, 4) 2379 2380 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2381 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2382 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2383 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2384 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2385 2386 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 2387 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ 2388 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2389 372, 0, 1, 4) 2390 2391 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2392 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2393 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2394 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2395 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2396 2397 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 2398 #define ASM_TX_OUT_BYTES_MSB_CNT(g) \ 2399 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2400 376, 0, 1, 4) 2401 2402 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 2403 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 2404 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2405 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 2406 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2407 2408 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 2409 #define ASM_TX_OK_BYTES_MSB_CNT(g) \ 2410 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2411 380, 0, 1, 4) 2412 2413 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2414 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 2415 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2416 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 2417 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2418 2419 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 2420 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ 2421 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2422 384, 0, 1, 4) 2423 2424 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2425 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 2426 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2427 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 2428 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2429 2430 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 2431 #define ASM_RX_SYNC_LOST_ERR_CNT(g) \ 2432 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2433 388, 0, 1, 4) 2434 2435 /* ASM:CFG:STAT_CFG */ 2436 #define ASM_STAT_CFG \ 2437 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2438 regs->gsize[GW_ASM_CFG], 0, 0, 1, 4) 2439 2440 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 2441 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ 2442 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2443 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 2444 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2445 2446 /* ASM:CFG:PORT_CFG */ 2447 #define ASM_PORT_CFG(r) \ 2448 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2449 regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4) 2450 2451 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 2452 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ 2453 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) 2454 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ 2455 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) 2456 2457 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) 2458 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ 2459 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2460 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ 2461 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2462 2463 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) 2464 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ 2465 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2466 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ 2467 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2468 2469 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) 2470 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ 2471 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2472 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ 2473 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2474 2475 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) 2476 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ 2477 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2478 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ 2479 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2480 2481 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) 2482 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ 2483 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) 2484 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ 2485 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) 2486 2487 #define ASM_PORT_CFG_PAD_ENA BIT(6) 2488 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ 2489 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) 2490 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ 2491 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) 2492 2493 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) 2494 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ 2495 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2496 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ 2497 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2498 2499 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) 2500 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ 2501 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2502 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ 2503 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2504 2505 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) 2506 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ 2507 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2508 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ 2509 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2510 2511 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) 2512 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ 2513 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) 2514 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 2515 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 2516 2517 /* ASM:RAM_CTRL:RAM_INIT */ 2518 #define ASM_RAM_INIT \ 2519 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 2520 4) 2521 2522 #define ASM_RAM_INIT_RAM_INIT BIT(1) 2523 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ 2524 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) 2525 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ 2526 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) 2527 2528 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) 2529 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 2530 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2531 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2532 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2533 2534 /* SPARX5 ONLY */ 2535 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2536 #define CLKGEN_LCPLL1_CORE_CLK_CFG \ 2537 __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2538 2539 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 2540 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ 2541 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2542 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ 2543 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2544 2545 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) 2546 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ 2547 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2548 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ 2549 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2550 2551 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) 2552 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ 2553 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2554 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ 2555 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2556 2557 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) 2558 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ 2559 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2560 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ 2561 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2562 2563 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) 2564 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ 2565 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2566 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ 2567 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2568 2569 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) 2570 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ 2571 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2572 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 2573 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2574 2575 /* CPU:CPU_REGS:PROC_CTRL */ 2576 #define CPU_PROC_CTRL \ 2577 __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \ 2578 regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4) 2579 2580 #define CPU_PROC_CTRL_AARCH64_MODE_ENA\ 2581 BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA]) 2582 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 2583 spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2584 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 2585 spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2586 2587 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\ 2588 BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS]) 2589 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 2590 spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2591 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 2592 spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2593 2594 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\ 2595 BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS]) 2596 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 2597 spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2598 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 2599 spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2600 2601 #define CPU_PROC_CTRL_BE_EXCEP_MODE\ 2602 BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE]) 2603 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 2604 spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2605 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 2606 spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2607 2608 #define CPU_PROC_CTRL_VINITHI\ 2609 BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI]) 2610 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 2611 spx5_field_prep(CPU_PROC_CTRL_VINITHI, x) 2612 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 2613 spx5_field_get(CPU_PROC_CTRL_VINITHI, x) 2614 2615 #define CPU_PROC_CTRL_CFGTE\ 2616 BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE]) 2617 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 2618 spx5_field_prep(CPU_PROC_CTRL_CFGTE, x) 2619 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 2620 spx5_field_get(CPU_PROC_CTRL_CFGTE, x) 2621 2622 #define CPU_PROC_CTRL_CP15S_DISABLE\ 2623 BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE]) 2624 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 2625 spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x) 2626 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 2627 spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x) 2628 2629 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\ 2630 BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE]) 2631 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 2632 spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2633 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 2634 spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2635 2636 /* SPARX5 ONLY */ 2637 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 2638 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 2639 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2640 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 2641 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2642 2643 /* SPARX5 ONLY */ 2644 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 2645 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 2646 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 2647 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 2648 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 2649 2650 /* SPARX5 ONLY */ 2651 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 2652 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 2653 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 2654 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 2655 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 2656 2657 #define CPU_PROC_CTRL_L2_FLUSH_REQ\ 2658 BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ]) 2659 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 2660 spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2661 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 2662 spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2663 2664 /* SPARX5 ONLY */ 2665 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 2666 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 2667 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 2668 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 2669 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 2670 2671 /* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 2672 #define DEV2G5_PHAD_CTRL(t, g) \ 2673 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ 2674 regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) 2675 2676 #define DEV2G5_PHAD_CTRL_PHAD_ENA\ 2677 BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) 2678 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ 2679 spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) 2680 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ 2681 spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) 2682 2683 /* LAN969X ONLY */ 2684 #define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) 2685 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ 2686 FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) 2687 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ 2688 FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) 2689 2690 /* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 2691 #define DEV2G5_PHAD_CTRL(t, g) \ 2692 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ 2693 regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) 2694 2695 #define DEV2G5_PHAD_CTRL_PHAD_ENA\ 2696 BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) 2697 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ 2698 spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) 2699 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ 2700 spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) 2701 2702 /* LAN969X ONLY */ 2703 #define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) 2704 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ 2705 FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) 2706 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ 2707 FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) 2708 2709 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2710 #define DEV10G_MAC_ENA_CFG(t) \ 2711 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ 2712 4) 2713 2714 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 2715 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2716 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2717 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2718 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2719 2720 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) 2721 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2722 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2723 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2724 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2725 2726 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2727 #define DEV10G_MAC_MAXLEN_CFG(t) \ 2728 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \ 2729 4) 2730 2731 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2732 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2733 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2734 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2735 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2736 2737 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2738 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2739 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2740 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2741 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2742 2743 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2744 #define DEV10G_MAC_NUM_TAGS_CFG(t) \ 2745 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \ 2746 4) 2747 2748 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 2749 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ 2750 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2751 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 2752 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2753 2754 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2755 #define DEV10G_MAC_TAGS_CFG(t, r) \ 2756 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \ 2757 4) 2758 2759 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2760 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2761 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2762 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2763 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2764 2765 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) 2766 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ 2767 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2768 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 2769 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2770 2771 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2772 #define DEV10G_MAC_ADV_CHK_CFG(t) \ 2773 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \ 2774 4) 2775 2776 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2777 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2778 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2779 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2780 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2781 2782 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2783 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2784 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2785 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2786 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2787 2788 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2789 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2790 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2791 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2792 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2793 2794 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2795 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2796 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2797 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2798 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2799 2800 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2801 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2802 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2803 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2804 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2805 2806 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2807 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2808 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2809 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2810 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2811 2812 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2813 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2814 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2815 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2816 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2817 2818 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2819 #define DEV10G_MAC_TX_MONITOR_STICKY(t) \ 2820 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \ 2821 4) 2822 2823 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 2824 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ 2825 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2826 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ 2827 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2828 2829 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) 2830 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ 2831 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2832 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ 2833 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2834 2835 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) 2836 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ 2837 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2838 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ 2839 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2840 2841 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) 2842 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ 2843 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2844 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ 2845 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2846 2847 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) 2848 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ 2849 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2850 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 2851 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2852 2853 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2854 #define DEV10G_DEV_RST_CTRL(t) \ 2855 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\ 2856 4) 2857 2858 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2859 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2860 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2861 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2862 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2863 2864 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2865 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2866 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2867 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2868 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2869 2870 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2871 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2872 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2873 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2874 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2875 2876 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2877 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2878 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2879 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2880 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2881 2882 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2883 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2884 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2885 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2886 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2887 2888 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2889 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2890 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2891 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2892 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2893 2894 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2895 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2896 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2897 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2898 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2899 2900 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2901 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2902 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2903 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2904 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2905 2906 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2907 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2908 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2909 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2910 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2911 2912 /* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ 2913 #define DEV10G_PTP_STAMPER_CFG(t) \ 2914 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \ 2915 1, 4) 2916 2917 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2918 #define DEV10G_PCS25G_CFG(t) \ 2919 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ 2920 4) 2921 2922 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 2923 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2924 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2925 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2926 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2927 2928 /* SPARX5 ONLY */ 2929 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2930 #define DEV25G_MAC_ENA_CFG(t) \ 2931 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2932 2933 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 2934 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2935 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2936 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2937 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2938 2939 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) 2940 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2941 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2942 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2943 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2944 2945 /* SPARX5 ONLY */ 2946 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2947 #define DEV25G_MAC_MAXLEN_CFG(t) \ 2948 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2949 2950 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2951 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2952 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2953 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2954 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2955 2956 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2957 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2958 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2959 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2960 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2961 2962 /* SPARX5 ONLY */ 2963 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2964 #define DEV25G_MAC_ADV_CHK_CFG(t) \ 2965 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2966 2967 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2968 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2969 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2970 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2971 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2972 2973 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2974 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2975 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2976 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2977 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2978 2979 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2980 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2981 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2982 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2983 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2984 2985 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2986 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2987 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2988 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2989 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2990 2991 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2992 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2993 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2994 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2995 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2996 2997 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2998 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2999 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3000 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 3001 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3002 3003 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 3004 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 3005 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3006 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3007 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3008 3009 /* SPARX5 ONLY */ 3010 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3011 #define DEV25G_DEV_RST_CTRL(t) \ 3012 __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 3013 3014 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 3015 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 3016 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3017 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 3018 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3019 3020 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 3021 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 3022 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3023 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 3024 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3025 3026 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 3027 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 3028 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3029 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 3030 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3031 3032 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 3033 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 3034 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3035 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 3036 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3037 3038 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 3039 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 3040 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 3041 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 3042 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 3043 3044 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3045 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3046 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 3047 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3048 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 3049 3050 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3051 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3052 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 3053 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3054 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 3055 3056 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3057 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3058 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 3059 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3060 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 3061 3062 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3063 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3064 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 3065 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3066 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 3067 3068 /* SPARX5 ONLY */ 3069 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 3070 #define DEV25G_PCS25G_CFG(t) \ 3071 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 3072 3073 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 3074 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 3075 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 3076 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 3077 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 3078 3079 /* SPARX5 ONLY */ 3080 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 3081 #define DEV25G_PCS25G_SD_CFG(t) \ 3082 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 3083 3084 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 3085 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ 3086 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 3087 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ 3088 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 3089 3090 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) 3091 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ 3092 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) 3093 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ 3094 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) 3095 3096 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) 3097 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ 3098 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 3099 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 3100 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 3101 3102 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3103 #define DEV2G5_DEV_RST_CTRL(t) \ 3104 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \ 3105 4) 3106 3107 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 3108 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 3109 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3110 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 3111 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3112 3113 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 3114 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 3115 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 3116 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 3117 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 3118 3119 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) 3120 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ 3121 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 3122 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ 3123 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 3124 3125 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) 3126 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ 3127 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 3128 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ 3129 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 3130 3131 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3132 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3133 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 3134 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3135 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 3136 3137 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3138 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3139 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 3140 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3141 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 3142 3143 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3144 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3145 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 3146 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3147 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 3148 3149 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3150 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3151 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 3152 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3153 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 3154 3155 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3156 #define DEV2G5_MAC_ENA_CFG(t) \ 3157 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \ 3158 4) 3159 3160 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 3161 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ 3162 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 3163 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ 3164 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 3165 3166 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) 3167 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ 3168 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 3169 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 3170 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 3171 3172 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 3173 #define DEV2G5_MAC_MODE_CFG(t) \ 3174 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \ 3175 4) 3176 3177 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 3178 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ 3179 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 3180 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ 3181 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 3182 3183 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 3184 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 3185 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 3186 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 3187 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 3188 3189 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) 3190 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ 3191 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 3192 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 3193 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 3194 3195 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3196 #define DEV2G5_MAC_MAXLEN_CFG(t) \ 3197 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \ 3198 4) 3199 3200 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3201 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3202 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 3203 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3204 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 3205 3206 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 3207 #define DEV2G5_MAC_TAGS_CFG(t) \ 3208 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\ 3209 4) 3210 3211 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 3212 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ 3213 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 3214 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ 3215 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 3216 3217 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 3218 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 3219 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 3220 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 3221 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 3222 3223 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 3224 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ 3225 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 3226 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ 3227 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 3228 3229 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 3230 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 3231 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 3232 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 3233 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 3234 3235 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 3236 #define DEV2G5_MAC_TAGS_CFG2(t) \ 3237 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\ 3238 4) 3239 3240 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 3241 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ 3242 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 3243 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ 3244 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 3245 3246 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) 3247 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ 3248 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 3249 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 3250 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 3251 3252 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3253 #define DEV2G5_MAC_ADV_CHK_CFG(t) \ 3254 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\ 3255 4) 3256 3257 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 3258 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ 3259 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 3260 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 3261 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 3262 3263 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 3264 #define DEV2G5_MAC_IFG_CFG(t) \ 3265 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\ 3266 4) 3267 3268 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 3269 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ 3270 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 3271 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ 3272 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 3273 3274 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 3275 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ 3276 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 3277 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ 3278 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 3279 3280 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 3281 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ 3282 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 3283 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ 3284 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 3285 3286 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 3287 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ 3288 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 3289 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 3290 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 3291 3292 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 3293 #define DEV2G5_MAC_HDX_CFG(t) \ 3294 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\ 3295 4) 3296 3297 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 3298 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ 3299 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 3300 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ 3301 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 3302 3303 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) 3304 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ 3305 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) 3306 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ 3307 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) 3308 3309 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) 3310 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 3311 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3312 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 3313 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3314 3315 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) 3316 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ 3317 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3318 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ 3319 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3320 3321 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) 3322 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ 3323 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3324 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 3325 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3326 3327 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 3328 #define DEV2G5_PCS1G_CFG(t) \ 3329 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \ 3330 4) 3331 3332 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 3333 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ 3334 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3335 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ 3336 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3337 3338 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) 3339 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ 3340 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3341 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ 3342 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3343 3344 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) 3345 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ 3346 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3347 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 3348 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3349 3350 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 3351 #define DEV2G5_PCS1G_MODE_CFG(t) \ 3352 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \ 3353 4) 3354 3355 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 3356 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ 3357 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3358 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ 3359 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3360 3361 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 3362 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 3363 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3364 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 3365 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3366 3367 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 3368 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 3369 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3370 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 3371 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3372 3373 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 3374 #define DEV2G5_PCS1G_SD_CFG(t) \ 3375 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \ 3376 4) 3377 3378 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 3379 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ 3380 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3381 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ 3382 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3383 3384 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) 3385 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ 3386 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3387 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ 3388 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3389 3390 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) 3391 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ 3392 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3393 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 3394 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3395 3396 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 3397 #define DEV2G5_PCS1G_ANEG_CFG(t) \ 3398 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\ 3399 4) 3400 3401 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 3402 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 3403 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3404 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 3405 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3406 3407 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 3408 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 3409 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3410 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 3411 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3412 3413 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) 3414 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ 3415 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3416 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ 3417 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3418 3419 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) 3420 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ 3421 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3422 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 3423 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3424 3425 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 3426 #define DEV2G5_PCS1G_LB_CFG(t) \ 3427 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\ 3428 4) 3429 3430 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 3431 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ 3432 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3433 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ 3434 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3435 3436 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) 3437 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ 3438 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3439 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ 3440 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3441 3442 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) 3443 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ 3444 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3445 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 3446 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3447 3448 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 3449 #define DEV2G5_PCS1G_ANEG_STATUS(t) \ 3450 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\ 3451 4) 3452 3453 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 3454 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ 3455 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3456 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ 3457 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3458 3459 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) 3460 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ 3461 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3462 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ 3463 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3464 3465 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) 3466 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ 3467 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3468 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ 3469 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3470 3471 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 3472 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 3473 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3474 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 3475 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3476 3477 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 3478 #define DEV2G5_PCS1G_LINK_STATUS(t) \ 3479 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\ 3480 4) 3481 3482 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 3483 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ 3484 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3485 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ 3486 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3487 3488 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) 3489 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ 3490 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3491 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ 3492 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3493 3494 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 3495 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 3496 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3497 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 3498 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3499 3500 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 3501 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 3502 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3503 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 3504 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3505 3506 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 3507 #define DEV2G5_PCS1G_STICKY(t) \ 3508 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\ 3509 4) 3510 3511 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 3512 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 3513 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3514 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 3515 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3516 3517 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) 3518 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ 3519 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3520 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 3521 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3522 3523 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 3524 #define DEV2G5_PCS_FX100_CFG(t) \ 3525 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \ 3526 4) 3527 3528 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 3529 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ 3530 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3531 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ 3532 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3533 3534 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) 3535 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ 3536 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3537 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ 3538 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3539 3540 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) 3541 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ 3542 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3543 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ 3544 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3545 3546 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) 3547 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ 3548 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3549 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ 3550 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3551 3552 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) 3553 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ 3554 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3555 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ 3556 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3557 3558 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) 3559 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ 3560 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3561 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ 3562 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3563 3564 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) 3565 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ 3566 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3567 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ 3568 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3569 3570 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) 3571 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ 3572 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3573 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ 3574 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3575 3576 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) 3577 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ 3578 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3579 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ 3580 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3581 3582 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) 3583 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ 3584 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3585 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ 3586 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3587 3588 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) 3589 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ 3590 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3591 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ 3592 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3593 3594 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) 3595 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ 3596 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3597 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ 3598 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3599 3600 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) 3601 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ 3602 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3603 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 3604 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3605 3606 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3607 #define DEV2G5_PCS_FX100_STATUS(t) \ 3608 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \ 3609 4) 3610 3611 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 3612 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ 3613 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3614 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ 3615 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3616 3617 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) 3618 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ 3619 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3620 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ 3621 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3622 3623 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) 3624 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ 3625 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3626 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ 3627 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3628 3629 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) 3630 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ 3631 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3632 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ 3633 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3634 3635 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) 3636 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ 3637 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3638 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ 3639 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3640 3641 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) 3642 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ 3643 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3644 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ 3645 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3646 3647 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) 3648 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ 3649 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3650 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ 3651 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3652 3653 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) 3654 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ 3655 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3656 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 3657 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3658 3659 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3660 #define DEV5G_MAC_ENA_CFG(t) \ 3661 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4) 3662 3663 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 3664 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ 3665 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3666 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ 3667 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3668 3669 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) 3670 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ 3671 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3672 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 3673 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3674 3675 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3676 #define DEV5G_MAC_MAXLEN_CFG(t) \ 3677 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4) 3678 3679 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 3680 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 3681 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3682 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 3683 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3684 3685 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3686 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3687 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3688 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3689 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3690 3691 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3692 #define DEV5G_MAC_ADV_CHK_CFG(t) \ 3693 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \ 3694 4) 3695 3696 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 3697 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 3698 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3699 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 3700 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3701 3702 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 3703 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 3704 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3705 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 3706 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3707 3708 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 3709 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 3710 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3711 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 3712 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3713 3714 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 3715 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 3716 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3717 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 3718 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3719 3720 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 3721 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 3722 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3723 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 3724 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3725 3726 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 3727 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 3728 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3729 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 3730 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3731 3732 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 3733 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 3734 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3735 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3736 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3737 3738 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3739 #define DEV5G_RX_SYMBOL_ERR_CNT(t) \ 3740 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \ 3741 4) 3742 3743 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3744 #define DEV5G_RX_PAUSE_CNT(t) \ 3745 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \ 3746 4) 3747 3748 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3749 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) \ 3750 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \ 3751 4) 3752 3753 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3754 #define DEV5G_RX_UC_CNT(t) \ 3755 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \ 3756 4) 3757 3758 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3759 #define DEV5G_RX_MC_CNT(t) \ 3760 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \ 3761 4) 3762 3763 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3764 #define DEV5G_RX_BC_CNT(t) \ 3765 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \ 3766 4) 3767 3768 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3769 #define DEV5G_RX_CRC_ERR_CNT(t) \ 3770 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \ 3771 4) 3772 3773 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3774 #define DEV5G_RX_UNDERSIZE_CNT(t) \ 3775 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \ 3776 4) 3777 3778 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3779 #define DEV5G_RX_FRAGMENTS_CNT(t) \ 3780 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \ 3781 4) 3782 3783 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3784 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3785 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \ 3786 4) 3787 3788 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3789 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3790 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \ 3791 4) 3792 3793 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3794 #define DEV5G_RX_OVERSIZE_CNT(t) \ 3795 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \ 3796 4) 3797 3798 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3799 #define DEV5G_RX_JABBERS_CNT(t) \ 3800 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \ 3801 4) 3802 3803 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3804 #define DEV5G_RX_SIZE64_CNT(t) \ 3805 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \ 3806 4) 3807 3808 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3809 #define DEV5G_RX_SIZE65TO127_CNT(t) \ 3810 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \ 3811 4) 3812 3813 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3814 #define DEV5G_RX_SIZE128TO255_CNT(t) \ 3815 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \ 3816 4) 3817 3818 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3819 #define DEV5G_RX_SIZE256TO511_CNT(t) \ 3820 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \ 3821 4) 3822 3823 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3824 #define DEV5G_RX_SIZE512TO1023_CNT(t) \ 3825 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \ 3826 4) 3827 3828 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3829 #define DEV5G_RX_SIZE1024TO1518_CNT(t) \ 3830 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \ 3831 4) 3832 3833 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3834 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) \ 3835 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \ 3836 4) 3837 3838 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3839 #define DEV5G_RX_IPG_SHRINK_CNT(t) \ 3840 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \ 3841 4) 3842 3843 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3844 #define DEV5G_TX_PAUSE_CNT(t) \ 3845 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \ 3846 4) 3847 3848 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3849 #define DEV5G_TX_UC_CNT(t) \ 3850 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \ 3851 4) 3852 3853 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3854 #define DEV5G_TX_MC_CNT(t) \ 3855 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \ 3856 4) 3857 3858 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3859 #define DEV5G_TX_BC_CNT(t) \ 3860 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \ 3861 4) 3862 3863 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3864 #define DEV5G_TX_SIZE64_CNT(t) \ 3865 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\ 3866 4) 3867 3868 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3869 #define DEV5G_TX_SIZE65TO127_CNT(t) \ 3870 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\ 3871 4) 3872 3873 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3874 #define DEV5G_TX_SIZE128TO255_CNT(t) \ 3875 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\ 3876 4) 3877 3878 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3879 #define DEV5G_TX_SIZE256TO511_CNT(t) \ 3880 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\ 3881 4) 3882 3883 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3884 #define DEV5G_TX_SIZE512TO1023_CNT(t) \ 3885 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\ 3886 4) 3887 3888 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3889 #define DEV5G_TX_SIZE1024TO1518_CNT(t) \ 3890 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\ 3891 4) 3892 3893 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3894 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) \ 3895 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\ 3896 4) 3897 3898 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3899 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) \ 3900 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\ 3901 4) 3902 3903 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3904 #define DEV5G_RX_TAGGED_FRMS_CNT(t) \ 3905 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\ 3906 4) 3907 3908 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3909 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) \ 3910 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\ 3911 4) 3912 3913 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3914 #define DEV5G_TX_TAGGED_FRMS_CNT(t) \ 3915 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\ 3916 4) 3917 3918 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3919 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) \ 3920 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\ 3921 4) 3922 3923 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3924 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) \ 3925 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\ 3926 4) 3927 3928 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3929 #define DEV5G_PMAC_RX_PAUSE_CNT(t) \ 3930 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\ 3931 4) 3932 3933 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3934 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) \ 3935 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\ 3936 4) 3937 3938 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3939 #define DEV5G_PMAC_RX_UC_CNT(t) \ 3940 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\ 3941 4) 3942 3943 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3944 #define DEV5G_PMAC_RX_MC_CNT(t) \ 3945 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\ 3946 4) 3947 3948 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3949 #define DEV5G_PMAC_RX_BC_CNT(t) \ 3950 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\ 3951 4) 3952 3953 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3954 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) \ 3955 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\ 3956 4) 3957 3958 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3959 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) \ 3960 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\ 3961 4) 3962 3963 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3964 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) \ 3965 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\ 3966 4) 3967 3968 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3969 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3970 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\ 3971 4) 3972 3973 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3974 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3975 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\ 3976 4) 3977 3978 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3979 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) \ 3980 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\ 3981 4) 3982 3983 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3984 #define DEV5G_PMAC_RX_JABBERS_CNT(t) \ 3985 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\ 3986 4) 3987 3988 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3989 #define DEV5G_PMAC_RX_SIZE64_CNT(t) \ 3990 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\ 3991 4) 3992 3993 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3994 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) \ 3995 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\ 3996 4) 3997 3998 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3999 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) \ 4000 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\ 4001 4) 4002 4003 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 4004 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) \ 4005 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\ 4006 4) 4007 4008 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 4009 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) \ 4010 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\ 4011 4) 4012 4013 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 4014 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) \ 4015 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\ 4016 4) 4017 4018 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 4019 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) \ 4020 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\ 4021 4) 4022 4023 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 4024 #define DEV5G_PMAC_TX_PAUSE_CNT(t) \ 4025 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\ 4026 4) 4027 4028 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 4029 #define DEV5G_PMAC_TX_UC_CNT(t) \ 4030 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\ 4031 4) 4032 4033 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 4034 #define DEV5G_PMAC_TX_MC_CNT(t) \ 4035 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\ 4036 4) 4037 4038 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 4039 #define DEV5G_PMAC_TX_BC_CNT(t) \ 4040 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\ 4041 4) 4042 4043 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 4044 #define DEV5G_PMAC_TX_SIZE64_CNT(t) \ 4045 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\ 4046 4) 4047 4048 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 4049 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) \ 4050 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\ 4051 4) 4052 4053 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 4054 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) \ 4055 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\ 4056 4) 4057 4058 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 4059 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) \ 4060 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\ 4061 4) 4062 4063 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 4064 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) \ 4065 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\ 4066 4) 4067 4068 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 4069 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) \ 4070 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\ 4071 4) 4072 4073 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 4074 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) \ 4075 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\ 4076 4) 4077 4078 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 4079 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) \ 4080 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\ 4081 4) 4082 4083 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 4084 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) \ 4085 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\ 4086 4) 4087 4088 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 4089 #define DEV5G_MM_RX_SMD_ERR_CNT(t) \ 4090 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\ 4091 4) 4092 4093 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 4094 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) \ 4095 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\ 4096 4) 4097 4098 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 4099 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) \ 4100 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\ 4101 4) 4102 4103 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 4104 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) \ 4105 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\ 4106 4) 4107 4108 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 4109 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) \ 4110 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\ 4111 4) 4112 4113 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 4114 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) \ 4115 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\ 4116 4) 4117 4118 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 4119 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) \ 4120 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\ 4121 4) 4122 4123 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 4124 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) \ 4125 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\ 4126 4) 4127 4128 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 4129 #define DEV5G_RX_IN_BYTES_CNT(t) \ 4130 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \ 4131 4) 4132 4133 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 4134 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) \ 4135 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \ 4136 4) 4137 4138 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 4139 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 4140 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 4141 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 4142 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 4143 4144 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 4145 #define DEV5G_RX_OK_BYTES_CNT(t) \ 4146 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \ 4147 4) 4148 4149 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 4150 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) \ 4151 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \ 4152 4) 4153 4154 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4155 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 4156 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 4157 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 4158 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 4159 4160 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 4161 #define DEV5G_RX_BAD_BYTES_CNT(t) \ 4162 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \ 4163 4) 4164 4165 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 4166 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) \ 4167 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \ 4168 4) 4169 4170 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4171 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 4172 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 4173 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4174 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 4175 4176 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 4177 #define DEV5G_TX_OUT_BYTES_CNT(t) \ 4178 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \ 4179 4) 4180 4181 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 4182 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) \ 4183 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \ 4184 4) 4185 4186 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 4187 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 4188 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 4189 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 4190 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 4191 4192 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 4193 #define DEV5G_TX_OK_BYTES_CNT(t) \ 4194 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \ 4195 4) 4196 4197 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 4198 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) \ 4199 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \ 4200 4) 4201 4202 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4203 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 4204 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 4205 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 4206 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 4207 4208 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 4209 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) \ 4210 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \ 4211 4) 4212 4213 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 4214 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) \ 4215 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \ 4216 4) 4217 4218 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4219 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 4220 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 4221 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 4222 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 4223 4224 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 4225 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) \ 4226 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \ 4227 4) 4228 4229 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 4230 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) \ 4231 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \ 4232 4) 4233 4234 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4235 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 4236 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 4237 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4238 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 4239 4240 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 4241 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) \ 4242 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \ 4243 4) 4244 4245 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 4246 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) \ 4247 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \ 4248 4) 4249 4250 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4251 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 4252 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 4253 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 4254 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 4255 4256 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 4257 #define DEV5G_DEV_RST_CTRL(t) \ 4258 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \ 4259 4) 4260 4261 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 4262 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 4263 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 4264 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 4265 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 4266 4267 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 4268 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 4269 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 4270 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 4271 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 4272 4273 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 4274 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 4275 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 4276 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 4277 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 4278 4279 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 4280 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 4281 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 4282 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 4283 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 4284 4285 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 4286 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 4287 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 4288 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 4289 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 4290 4291 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 4292 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 4293 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 4294 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 4295 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 4296 4297 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 4298 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 4299 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 4300 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 4301 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 4302 4303 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 4304 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 4305 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 4306 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 4307 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 4308 4309 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 4310 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 4311 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 4312 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 4313 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 4314 4315 /* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ 4316 #define DEV5G_PTP_STAMPER_CFG(t) \ 4317 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \ 4318 4) 4319 4320 /* DSM:RAM_CTRL:RAM_INIT */ 4321 #define DSM_RAM_INIT \ 4322 __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 4323 4324 #define DSM_RAM_INIT_RAM_INIT BIT(1) 4325 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ 4326 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) 4327 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ 4328 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) 4329 4330 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) 4331 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 4332 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) 4333 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4334 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 4335 4336 /* DSM:CFG:BUF_CFG */ 4337 #define DSM_BUF_CFG(r) \ 4338 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \ 4339 regs->rcnt[RC_DSM_BUF_CFG], 4) 4340 4341 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 4342 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ 4343 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) 4344 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ 4345 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) 4346 4347 #define DSM_BUF_CFG_AGING_ENA BIT(12) 4348 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ 4349 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) 4350 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ 4351 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) 4352 4353 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) 4354 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ 4355 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 4356 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ 4357 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 4358 4359 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) 4360 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ 4361 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 4362 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 4363 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 4364 4365 /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 4366 #define DSM_DEV_TX_STOP_WM_CFG(r) \ 4367 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \ 4368 regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4) 4369 4370 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 4371 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ 4372 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 4373 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ 4374 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 4375 4376 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8) 4377 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ 4378 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 4379 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ 4380 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 4381 4382 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1) 4383 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ 4384 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 4385 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ 4386 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 4387 4388 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0) 4389 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ 4390 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 4391 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 4392 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 4393 4394 /* DSM:CFG:RX_PAUSE_CFG */ 4395 #define DSM_RX_PAUSE_CFG(r) \ 4396 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \ 4397 regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4) 4398 4399 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 4400 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ 4401 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 4402 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ 4403 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 4404 4405 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0) 4406 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ 4407 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 4408 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 4409 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 4410 4411 /* DSM:CFG:MAC_CFG */ 4412 #define DSM_MAC_CFG(r) \ 4413 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \ 4414 regs->rcnt[RC_DSM_MAC_CFG], 4) 4415 4416 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 4417 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ 4418 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x) 4419 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ 4420 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x) 4421 4422 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2) 4423 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ 4424 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4425 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ 4426 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4427 4428 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1) 4429 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ 4430 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4431 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ 4432 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4433 4434 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0) 4435 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ 4436 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4437 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 4438 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4439 4440 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 4441 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) \ 4442 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \ 4443 regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4) 4444 4445 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 4446 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ 4447 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4448 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 4449 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4450 4451 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 4452 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) \ 4453 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \ 4454 regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4) 4455 4456 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 4457 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ 4458 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4459 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 4460 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4461 4462 /* DSM:CFG:TAXI_CAL_CFG */ 4463 #define DSM_TAXI_CAL_CFG(r) \ 4464 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \ 4465 regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4) 4466 4467 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 4468 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ 4469 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4470 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ 4471 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4472 4473 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9) 4474 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ 4475 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4476 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ 4477 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4478 4479 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5) 4480 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ 4481 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4482 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ 4483 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4484 4485 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1) 4486 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ 4487 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4488 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ 4489 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4490 4491 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0) 4492 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ 4493 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4494 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 4495 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4496 4497 /* LAN969X ONLY */ 4498 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23) 4499 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\ 4500 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) 4501 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\ 4502 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) 4503 4504 /* LAN969X ONLY */ 4505 #define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22) 4506 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\ 4507 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) 4508 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\ 4509 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) 4510 4511 /* LAN969X ONLY */ 4512 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21) 4513 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\ 4514 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) 4515 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\ 4516 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) 4517 4518 /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 4519 #define EACL_VCAP_ES2_KEY_SEL(g, r) \ 4520 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ 4521 g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4) 4522 4523 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) 4524 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ 4525 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4526 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\ 4527 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4528 4529 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2) 4530 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\ 4531 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4532 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\ 4533 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4534 4535 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1) 4536 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 4537 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4538 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 4539 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4540 4541 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA BIT(0) 4542 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\ 4543 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4544 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ 4545 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4546 4547 /* EACL:CNT_TBL:ES2_CNT */ 4548 #define EACL_ES2_CNT(g) \ 4549 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \ 4550 regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4) 4551 4552 /* EACL:POL_CFG:POL_EACL_CFG */ 4553 #define EACL_POL_EACL_CFG \ 4554 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \ 4555 0, 1, 4) 4556 4557 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 4558 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ 4559 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4560 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ 4561 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4562 4563 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4) 4564 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ 4565 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4566 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ 4567 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4568 4569 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3) 4570 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ 4571 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4572 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ 4573 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4574 4575 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2) 4576 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ 4577 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4578 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ 4579 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4580 4581 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1) 4582 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ 4583 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4584 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ 4585 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4586 4587 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0) 4588 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ 4589 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4590 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 4591 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4592 4593 /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 4594 #define EACL_SEC_LOOKUP_STICKY(r) \ 4595 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \ 4596 r, 2, 4) 4597 4598 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 4599 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 4600 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4601 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 4602 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4603 4604 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6) 4605 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 4606 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4607 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 4608 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4609 4610 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5) 4611 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 4612 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4613 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 4614 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4615 4616 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4) 4617 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 4618 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4619 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 4620 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4621 4622 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3) 4623 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 4624 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4625 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 4626 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4627 4628 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2) 4629 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 4630 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4631 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 4632 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4633 4634 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1) 4635 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 4636 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4637 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 4638 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4639 4640 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 4641 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 4642 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4643 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 4644 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4645 4646 /* EACL:RAM_CTRL:RAM_INIT */ 4647 #define EACL_RAM_INIT \ 4648 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \ 4649 1, 4) 4650 4651 #define EACL_RAM_INIT_RAM_INIT BIT(1) 4652 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ 4653 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x) 4654 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ 4655 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x) 4656 4657 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0) 4658 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 4659 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4660 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4661 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4662 4663 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 4664 #define FDMA_CH_ACTIVATE \ 4665 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \ 4666 4) 4667 4668 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 4669 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 4670 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4671 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 4672 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4673 4674 /* FDMA:FDMA:FDMA_CH_RELOAD */ 4675 #define FDMA_CH_RELOAD \ 4676 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \ 4677 4) 4678 4679 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 4680 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 4681 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 4682 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 4683 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 4684 4685 /* FDMA:FDMA:FDMA_CH_DISABLE */ 4686 #define FDMA_CH_DISABLE \ 4687 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \ 4688 4) 4689 4690 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 4691 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 4692 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 4693 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 4694 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 4695 4696 /* FDMA:FDMA:FDMA_DCB_LLP */ 4697 #define FDMA_DCB_LLP(r) \ 4698 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \ 4699 4) 4700 4701 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 4702 #define FDMA_DCB_LLP1(r) \ 4703 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \ 4704 4) 4705 4706 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 4707 #define FDMA_DCB_LLP_PREV(r) \ 4708 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\ 4709 4) 4710 4711 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 4712 #define FDMA_DCB_LLP_PREV1(r) \ 4713 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\ 4714 4) 4715 4716 /* FDMA:FDMA:FDMA_CH_CFG */ 4717 #define FDMA_CH_CFG(r) \ 4718 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\ 4719 4) 4720 4721 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE\ 4722 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE]) 4723 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 4724 spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4725 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 4726 spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4727 4728 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\ 4729 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY]) 4730 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 4731 spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4732 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 4733 spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4734 4735 #define FDMA_CH_CFG_CH_INJ_PORT\ 4736 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT]) 4737 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 4738 spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x) 4739 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 4740 spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x) 4741 4742 #define FDMA_CH_CFG_CH_DCB_DB_CNT\ 4743 GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1) 4744 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 4745 spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4746 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 4747 spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4748 4749 #define FDMA_CH_CFG_CH_MEM BIT(0) 4750 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 4751 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 4752 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 4753 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 4754 4755 /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 4756 #define FDMA_CH_TRANSLATE(r) \ 4757 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\ 4758 4) 4759 4760 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 4761 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ 4762 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x) 4763 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 4764 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 4765 4766 /* FDMA:FDMA:FDMA_XTR_CFG */ 4767 #define FDMA_XTR_CFG \ 4768 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\ 4769 4) 4770 4771 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 4772 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ 4773 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4774 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ 4775 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4776 4777 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0) 4778 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ 4779 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4780 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 4781 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4782 4783 /* FDMA:FDMA:FDMA_PORT_CTRL */ 4784 #define FDMA_PORT_CTRL(r) \ 4785 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\ 4786 4) 4787 4788 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 4789 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 4790 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 4791 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 4792 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 4793 4794 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3) 4795 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ 4796 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4797 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ 4798 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4799 4800 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 4801 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 4802 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 4803 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 4804 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 4805 4806 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1) 4807 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ 4808 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4809 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ 4810 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4811 4812 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0) 4813 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ 4814 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4815 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 4816 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4817 4818 /* FDMA:FDMA:FDMA_INTR_DCB */ 4819 #define FDMA_INTR_DCB \ 4820 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\ 4821 4) 4822 4823 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 4824 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ 4825 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x) 4826 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 4827 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 4828 4829 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 4830 #define FDMA_INTR_DCB_ENA \ 4831 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\ 4832 4) 4833 4834 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 4835 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ 4836 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4837 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 4838 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4839 4840 /* FDMA:FDMA:FDMA_INTR_DB */ 4841 #define FDMA_INTR_DB \ 4842 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\ 4843 4) 4844 4845 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 4846 #define FDMA_INTR_DB_INTR_DB_SET(x)\ 4847 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x) 4848 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 4849 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 4850 4851 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 4852 #define FDMA_INTR_DB_ENA \ 4853 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\ 4854 4) 4855 4856 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 4857 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 4858 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4859 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 4860 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4861 4862 /* FDMA:FDMA:FDMA_INTR_ERR */ 4863 #define FDMA_INTR_ERR \ 4864 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\ 4865 4) 4866 4867 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 4868 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ 4869 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4870 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ 4871 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4872 4873 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0) 4874 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ 4875 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x) 4876 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 4877 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 4878 4879 /* FDMA:FDMA:FDMA_ERRORS */ 4880 #define FDMA_ERRORS \ 4881 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\ 4882 4) 4883 4884 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 4885 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ 4886 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x) 4887 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ 4888 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x) 4889 4890 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28) 4891 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ 4892 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x) 4893 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ 4894 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x) 4895 4896 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26) 4897 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ 4898 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4899 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ 4900 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4901 4902 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24) 4903 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ 4904 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4905 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ 4906 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4907 4908 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16) 4909 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ 4910 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x) 4911 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ 4912 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x) 4913 4914 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10) 4915 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ 4916 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x) 4917 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ 4918 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x) 4919 4920 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8) 4921 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ 4922 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4923 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ 4924 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4925 4926 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0) 4927 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ 4928 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x) 4929 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 4930 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 4931 4932 /* FDMA:FDMA:FDMA_ERRORS_2 */ 4933 #define FDMA_ERRORS_2 \ 4934 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\ 4935 4) 4936 4937 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 4938 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ 4939 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4940 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 4941 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4942 4943 /* FDMA:FDMA:FDMA_CTRL */ 4944 #define FDMA_CTRL \ 4945 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\ 4946 4) 4947 4948 #define FDMA_CTRL_NRESET BIT(0) 4949 #define FDMA_CTRL_NRESET_SET(x)\ 4950 FIELD_PREP(FDMA_CTRL_NRESET, x) 4951 #define FDMA_CTRL_NRESET_GET(x)\ 4952 FIELD_GET(FDMA_CTRL_NRESET, x) 4953 4954 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4955 #define GCB_CHIP_ID \ 4956 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \ 4957 1, 4) 4958 4959 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 4960 #define GCB_CHIP_ID_REV_ID_SET(x)\ 4961 FIELD_PREP(GCB_CHIP_ID_REV_ID, x) 4962 #define GCB_CHIP_ID_REV_ID_GET(x)\ 4963 FIELD_GET(GCB_CHIP_ID_REV_ID, x) 4964 4965 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12) 4966 #define GCB_CHIP_ID_PART_ID_SET(x)\ 4967 FIELD_PREP(GCB_CHIP_ID_PART_ID, x) 4968 #define GCB_CHIP_ID_PART_ID_GET(x)\ 4969 FIELD_GET(GCB_CHIP_ID_PART_ID, x) 4970 4971 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1) 4972 #define GCB_CHIP_ID_MFG_ID_SET(x)\ 4973 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x) 4974 #define GCB_CHIP_ID_MFG_ID_GET(x)\ 4975 FIELD_GET(GCB_CHIP_ID_MFG_ID, x) 4976 4977 #define GCB_CHIP_ID_ONE BIT(0) 4978 #define GCB_CHIP_ID_ONE_SET(x)\ 4979 FIELD_PREP(GCB_CHIP_ID_ONE, x) 4980 #define GCB_CHIP_ID_ONE_GET(x)\ 4981 FIELD_GET(GCB_CHIP_ID_ONE, x) 4982 4983 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4984 #define GCB_SOFT_RST \ 4985 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 4986 regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4) 4987 4988 /* SPARX5 ONLY */ 4989 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 4990 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 4991 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4992 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ 4993 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4994 4995 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1) 4996 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ 4997 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x) 4998 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ 4999 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x) 5000 5001 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0) 5002 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ 5003 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x) 5004 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 5005 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 5006 5007 /* SPARX5 ONLY */ 5008 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 5009 #define GCB_HW_SGPIO_SD_CFG \ 5010 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \ 5011 1, 4) 5012 5013 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 5014 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ 5015 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 5016 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ 5017 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 5018 5019 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0) 5020 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ 5021 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 5022 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 5023 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 5024 5025 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 5026 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) \ 5027 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 5028 regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r, \ 5029 regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4) 5030 5031 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\ 5032 GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0) 5033 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 5034 spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 5035 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 5036 spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 5037 5038 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 5039 #define GCB_SIO_CLOCK(g) \ 5040 __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \ 5041 regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4) 5042 5043 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 5044 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ 5045 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 5046 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ 5047 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 5048 5049 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0) 5050 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ 5051 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 5052 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 5053 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 5054 5055 /* HSCH:HSCH_CFG:CIR_CFG */ 5056 #define HSCH_CIR_CFG(g) \ 5057 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \ 5058 1, 4) 5059 5060 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 5061 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ 5062 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x) 5063 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ 5064 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x) 5065 5066 #define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0) 5067 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ 5068 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x) 5069 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 5070 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 5071 5072 /* HSCH:HSCH_CFG:EIR_CFG */ 5073 #define HSCH_EIR_CFG(g) \ 5074 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \ 5075 1, 4) 5076 5077 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 5078 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ 5079 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x) 5080 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ 5081 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x) 5082 5083 #define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0) 5084 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ 5085 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x) 5086 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 5087 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 5088 5089 /* HSCH:HSCH_CFG:SE_CFG */ 5090 #define HSCH_SE_CFG(g) \ 5091 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \ 5092 1, 4) 5093 5094 #define HSCH_SE_CFG_SE_DWRR_CNT\ 5095 GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6) 5096 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 5097 spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x) 5098 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 5099 spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x) 5100 5101 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 5102 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ 5103 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x) 5104 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ 5105 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x) 5106 5107 #define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3) 5108 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ 5109 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x) 5110 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ 5111 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x) 5112 5113 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1) 5114 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ 5115 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 5116 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ 5117 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 5118 5119 #define HSCH_SE_CFG_SE_STOP BIT(0) 5120 #define HSCH_SE_CFG_SE_STOP_SET(x)\ 5121 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x) 5122 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 5123 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 5124 5125 /* HSCH:HSCH_CFG:SE_CONNECT */ 5126 #define HSCH_SE_CONNECT(g) \ 5127 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\ 5128 1, 4) 5129 5130 #define HSCH_SE_CONNECT_SE_LEAK_LINK\ 5131 GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0) 5132 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 5133 spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5134 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 5135 spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5136 5137 /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 5138 #define HSCH_SE_DLB_SENSE(g) \ 5139 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\ 5140 1, 4) 5141 5142 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 5143 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ 5144 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 5145 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 5146 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 5147 5148 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\ 5149 GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3) 5150 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 5151 spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5152 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 5153 spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5154 5155 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 5156 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ 5157 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 5158 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ 5159 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 5160 5161 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1) 5162 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ 5163 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 5164 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ 5165 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 5166 5167 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 5168 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ 5169 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 5170 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 5171 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 5172 5173 /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 5174 #define HSCH_DWRR_ENTRY(g) \ 5175 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \ 5176 regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4) 5177 5178 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 5179 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ 5180 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) 5181 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ 5182 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) 5183 5184 #define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) 5185 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ 5186 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 5187 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 5188 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 5189 5190 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 5191 #define HSCH_HSCH_CFG_CFG \ 5192 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 5193 284, 0, 1, 4) 5194 5195 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\ 5196 GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14) 5197 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 5198 spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5199 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 5200 spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5201 5202 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 5203 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ 5204 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 5205 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ 5206 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 5207 5208 #define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0) 5209 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ 5210 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 5211 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 5212 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 5213 5214 /* SPARX5 ONLY */ 5215 /* HSCH:HSCH_MISC:SYS_CLK_PER */ 5216 #define HSCH_SYS_CLK_PER \ 5217 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 5218 640, 0, 1, 4) 5219 5220 #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) 5221 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ 5222 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x) 5223 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ 5224 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) 5225 5226 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 5227 #define HSCH_HSCH_TIMER_CFG(g, r) \ 5228 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 5229 32, 0, r, 4, 4) 5230 5231 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 5232 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ 5233 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 5234 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 5235 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 5236 5237 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 5238 #define HSCH_HSCH_LEAK_CFG(g, r) \ 5239 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 5240 32, 16, r, 4, 4) 5241 5242 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\ 5243 GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1) 5244 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 5245 spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5246 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 5247 spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5248 5249 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 5250 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ 5251 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 5252 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 5253 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 5254 5255 /* HSCH:SYSTEM:FLUSH_CTRL */ 5256 #define HSCH_FLUSH_CTRL \ 5257 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \ 5258 1, 4) 5259 5260 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 5261 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ 5262 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 5263 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ 5264 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 5265 5266 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26) 5267 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ 5268 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 5269 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ 5270 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 5271 5272 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25) 5273 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ 5274 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x) 5275 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 5276 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 5277 5278 #define HSCH_FLUSH_CTRL_FLUSH_PORT\ 5279 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18) 5280 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 5281 spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5282 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 5283 spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5284 5285 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 5286 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ 5287 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 5288 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ 5289 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 5290 5291 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16) 5292 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ 5293 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x) 5294 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 5295 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 5296 5297 #define HSCH_FLUSH_CTRL_FLUSH_HIER\ 5298 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0) 5299 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 5300 spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5301 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 5302 spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5303 5304 /* HSCH:SYSTEM:PORT_MODE */ 5305 #define HSCH_PORT_MODE(r) \ 5306 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \ 5307 regs->rcnt[RC_HSCH_PORT_MODE], 4) 5308 5309 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 5310 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ 5311 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x) 5312 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ 5313 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x) 5314 5315 #define HSCH_PORT_MODE_AGE_DIS BIT(3) 5316 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ 5317 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x) 5318 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ 5319 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x) 5320 5321 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2) 5322 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ 5323 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x) 5324 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ 5325 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x) 5326 5327 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1) 5328 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ 5329 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 5330 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ 5331 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 5332 5333 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0) 5334 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ 5335 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 5336 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 5337 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 5338 5339 /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 5340 #define HSCH_OUTB_SHARE_ENA(r) \ 5341 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \ 5342 r, 5, 4) 5343 5344 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 5345 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ 5346 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 5347 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 5348 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 5349 5350 /* HSCH:MMGT:RESET_CFG */ 5351 #define HSCH_RESET_CFG \ 5352 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \ 5353 4) 5354 5355 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 5356 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ 5357 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x) 5358 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 5359 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 5360 5361 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 5362 #define HSCH_TAS_STATEMACHINE_CFG \ 5363 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \ 5364 regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4) 5365 5366 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 5367 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ 5368 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 5369 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 5370 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 5371 5372 /* LAN969X ONLY */ 5373 /* HSIOWRAP:XMII_CFG:XMII_CFG */ 5374 #define HSIO_WRAP_XMII_CFG(g) \ 5375 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4) 5376 5377 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1) 5378 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\ 5379 FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) 5380 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\ 5381 FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) 5382 5383 /* LAN969X ONLY */ 5384 /* HSIOWRAP:XMII_CFG:RGMII_CFG */ 5385 #define HSIO_WRAP_RGMII_CFG(g) \ 5386 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4) 5387 5388 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2) 5389 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\ 5390 FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) 5391 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\ 5392 FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) 5393 5394 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1) 5395 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\ 5396 FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) 5397 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\ 5398 FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) 5399 5400 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST BIT(0) 5401 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\ 5402 FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) 5403 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\ 5404 FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) 5405 5406 /* LAN969X ONLY */ 5407 /* HSIOWRAP:XMII_CFG:DLL_CFG */ 5408 #define HSIO_WRAP_DLL_CFG(g, r) \ 5409 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4) 5410 5411 #define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19) 5412 #define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\ 5413 FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x) 5414 #define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\ 5415 FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x) 5416 5417 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18) 5418 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\ 5419 FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) 5420 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\ 5421 FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) 5422 5423 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15) 5424 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\ 5425 FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) 5426 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\ 5427 FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) 5428 5429 #define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0) 5430 #define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\ 5431 FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x) 5432 #define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\ 5433 FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x) 5434 5435 /* LRN:COMMON:COMMON_ACCESS_CTRL */ 5436 #define LRN_COMMON_ACCESS_CTRL \ 5437 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 5438 5439 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 5440 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ 5441 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 5442 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ 5443 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 5444 5445 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19) 5446 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ 5447 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 5448 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 5449 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 5450 5451 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\ 5452 GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5) 5453 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 5454 spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5455 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 5456 spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5457 5458 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 5459 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ 5460 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 5461 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ 5462 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 5463 5464 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0) 5465 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ 5466 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 5467 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 5468 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 5469 5470 /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 5471 #define LRN_MAC_ACCESS_CFG_0 \ 5472 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 5473 5474 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 5475 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ 5476 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 5477 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ 5478 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 5479 5480 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0) 5481 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ 5482 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 5483 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 5484 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 5485 5486 /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 5487 #define LRN_MAC_ACCESS_CFG_1 \ 5488 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 5489 5490 /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 5491 #define LRN_MAC_ACCESS_CFG_2 \ 5492 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 5493 5494 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 5495 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ 5496 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 5497 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ 5498 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 5499 5500 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27) 5501 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ 5502 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 5503 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ 5504 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 5505 5506 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24) 5507 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ 5508 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 5509 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ 5510 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 5511 5512 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23) 5513 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ 5514 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 5515 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ 5516 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 5517 5518 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22) 5519 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ 5520 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 5521 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ 5522 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 5523 5524 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21) 5525 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ 5526 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 5527 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ 5528 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 5529 5530 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19) 5531 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ 5532 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 5533 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ 5534 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 5535 5536 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17) 5537 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ 5538 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 5539 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ 5540 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 5541 5542 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16) 5543 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ 5544 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 5545 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ 5546 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 5547 5548 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15) 5549 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ 5550 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 5551 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ 5552 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 5553 5554 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12) 5555 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ 5556 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 5557 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ 5558 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 5559 5560 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0) 5561 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ 5562 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 5563 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 5564 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 5565 5566 /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 5567 #define LRN_MAC_ACCESS_CFG_3 \ 5568 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 5569 5570 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\ 5571 GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0) 5572 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 5573 spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5574 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 5575 spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5576 5577 /* LRN:COMMON:SCAN_NEXT_CFG */ 5578 #define LRN_SCAN_NEXT_CFG \ 5579 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 5580 5581 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 5582 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ 5583 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5584 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ 5585 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5586 5587 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17) 5588 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ 5589 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5590 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ 5591 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5592 5593 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15) 5594 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ 5595 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5596 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ 5597 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5598 5599 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14) 5600 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ 5601 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5602 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ 5603 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5604 5605 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13) 5606 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ 5607 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5608 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ 5609 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5610 5611 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12) 5612 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ 5613 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5614 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ 5615 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5616 5617 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11) 5618 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ 5619 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5620 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ 5621 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5622 5623 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10) 5624 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ 5625 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5626 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ 5627 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5628 5629 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9) 5630 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ 5631 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5632 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ 5633 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5634 5635 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8) 5636 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ 5637 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5638 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ 5639 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5640 5641 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7) 5642 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ 5643 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5644 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ 5645 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5646 5647 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3) 5648 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ 5649 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5650 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ 5651 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5652 5653 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2) 5654 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ 5655 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5656 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ 5657 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5658 5659 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1) 5660 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ 5661 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5662 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ 5663 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5664 5665 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0) 5666 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ 5667 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5668 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 5669 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5670 5671 /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 5672 #define LRN_SCAN_NEXT_CFG_1 \ 5673 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 5674 5675 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 5676 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ 5677 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5678 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ 5679 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5680 5681 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0) 5682 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ 5683 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5684 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 5685 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5686 5687 /* LRN:COMMON:AUTOAGE_CFG */ 5688 #define LRN_AUTOAGE_CFG(r) \ 5689 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 5690 5691 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 5692 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ 5693 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5694 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ 5695 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5696 5697 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0) 5698 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ 5699 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5700 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 5701 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5702 5703 /* LRN:COMMON:AUTOAGE_CFG_1 */ 5704 #define LRN_AUTOAGE_CFG_1 \ 5705 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 5706 5707 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 5708 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ 5709 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5710 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ 5711 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5712 5713 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15) 5714 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ 5715 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5716 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ 5717 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5718 5719 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7) 5720 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ 5721 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5722 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ 5723 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5724 5725 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6) 5726 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ 5727 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5728 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ 5729 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5730 5731 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2) 5732 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ 5733 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5734 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ 5735 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5736 5737 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1) 5738 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ 5739 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5740 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ 5741 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5742 5743 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0) 5744 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ 5745 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5746 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 5747 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5748 5749 /* LRN:COMMON:AUTOAGE_CFG_2 */ 5750 #define LRN_AUTOAGE_CFG_2 \ 5751 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 5752 5753 #define LRN_AUTOAGE_CFG_2_NEXT_ROW\ 5754 GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4) 5755 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 5756 spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5757 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 5758 spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5759 5760 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 5761 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ 5762 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5763 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 5764 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5765 5766 /* SPARX5 ONLY */ 5767 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 5768 #define PCEP_RCTRL_2_OUT_0 \ 5769 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 5770 5771 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 5772 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ 5773 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5774 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ 5775 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5776 5777 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8) 5778 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ 5779 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x) 5780 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ 5781 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x) 5782 5783 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16) 5784 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ 5785 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5786 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ 5787 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5788 5789 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19) 5790 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ 5791 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5792 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ 5793 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5794 5795 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20) 5796 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ 5797 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x) 5798 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ 5799 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x) 5800 5801 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22) 5802 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ 5803 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5804 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ 5805 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5806 5807 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23) 5808 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ 5809 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5810 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ 5811 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5812 5813 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28) 5814 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ 5815 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5816 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ 5817 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5818 5819 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29) 5820 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ 5821 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5822 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ 5823 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5824 5825 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31) 5826 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ 5827 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5828 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 5829 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5830 5831 /* SPARX5 ONLY */ 5832 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 5833 #define PCEP_ADDR_LWR_OUT_0 \ 5834 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 5835 5836 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 5837 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ 5838 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5839 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ 5840 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5841 5842 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16) 5843 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ 5844 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5845 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 5846 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5847 5848 /* SPARX5 ONLY */ 5849 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 5850 #define PCEP_ADDR_UPR_OUT_0 \ 5851 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 5852 5853 /* SPARX5 ONLY */ 5854 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5855 #define PCEP_ADDR_LIM_OUT_0 \ 5856 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 5857 5858 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 5859 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ 5860 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5861 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ 5862 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5863 5864 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16) 5865 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ 5866 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5867 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 5868 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5869 5870 /* SPARX5 ONLY */ 5871 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 5872 #define PCEP_ADDR_LWR_TGT_OUT_0 \ 5873 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 5874 5875 /* SPARX5 ONLY */ 5876 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 5877 #define PCEP_ADDR_UPR_TGT_OUT_0 \ 5878 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 5879 5880 /* SPARX5 ONLY */ 5881 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5882 #define PCEP_ADDR_UPR_LIM_OUT_0 \ 5883 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 5884 5885 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 5886 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ 5887 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5888 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ 5889 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5890 5891 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2) 5892 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ 5893 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5894 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 5895 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5896 5897 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5898 #define PCS10G_BR_PCS_CFG(t) \ 5899 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \ 5900 0, 1, 4) 5901 5902 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 5903 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5904 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5905 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5906 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5907 5908 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5909 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5910 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5911 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5912 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5913 5914 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5915 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5916 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5917 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5918 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5919 5920 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5921 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5922 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5923 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5924 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5925 5926 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5927 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5928 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5929 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5930 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5931 5932 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5933 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5934 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5935 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5936 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5937 5938 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5939 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5940 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5941 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5942 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5943 5944 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5945 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5946 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5947 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5948 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5949 5950 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5951 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5952 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5953 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5954 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5955 5956 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5957 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5958 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5959 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5960 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5961 5962 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5963 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5964 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5965 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5966 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5967 5968 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5969 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5970 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5971 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5972 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5973 5974 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5975 #define PCS10G_BR_PCS_SD_CFG(t) \ 5976 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \ 5977 0, 1, 4) 5978 5979 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5980 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5981 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5982 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5983 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5984 5985 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4) 5986 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5987 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5988 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5989 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5990 5991 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5992 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5993 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5994 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5995 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5996 5997 /* SPARX5 ONLY */ 5998 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5999 #define PCS25G_BR_PCS_CFG(t) \ 6000 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 6001 6002 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 6003 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ 6004 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x) 6005 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ 6006 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x) 6007 6008 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 6009 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 6010 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 6011 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 6012 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 6013 6014 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 6015 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 6016 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 6017 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 6018 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 6019 6020 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 6021 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 6022 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 6023 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 6024 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 6025 6026 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15) 6027 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 6028 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 6029 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 6030 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 6031 6032 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 6033 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 6034 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 6035 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 6036 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 6037 6038 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 6039 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 6040 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 6041 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 6042 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 6043 6044 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 6045 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 6046 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6047 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 6048 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6049 6050 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 6051 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 6052 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 6053 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 6054 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 6055 6056 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 6057 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 6058 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6059 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 6060 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6061 6062 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 6063 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 6064 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 6065 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 6066 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 6067 6068 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 6069 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 6070 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6071 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 6072 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6073 6074 /* SPARX5 ONLY */ 6075 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 6076 #define PCS25G_BR_PCS_SD_CFG(t) \ 6077 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 6078 6079 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 6080 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 6081 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 6082 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 6083 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 6084 6085 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4) 6086 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 6087 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 6088 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 6089 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 6090 6091 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0) 6092 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 6093 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 6094 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 6095 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 6096 6097 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 6098 #define PCS5G_BR_PCS_CFG(t) \ 6099 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \ 6100 1, 4) 6101 6102 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 6103 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ 6104 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x) 6105 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ 6106 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x) 6107 6108 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 6109 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 6110 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 6111 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 6112 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 6113 6114 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 6115 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 6116 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 6117 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 6118 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 6119 6120 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 6121 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 6122 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 6123 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 6124 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 6125 6126 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15) 6127 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 6128 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 6129 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 6130 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 6131 6132 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 6133 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 6134 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 6135 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 6136 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 6137 6138 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 6139 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 6140 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 6141 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 6142 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 6143 6144 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 6145 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 6146 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6147 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 6148 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6149 6150 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 6151 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 6152 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 6153 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 6154 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 6155 6156 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 6157 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 6158 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6159 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 6160 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6161 6162 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 6163 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 6164 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 6165 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 6166 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 6167 6168 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 6169 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 6170 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6171 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 6172 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6173 6174 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 6175 #define PCS5G_BR_PCS_SD_CFG(t) \ 6176 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \ 6177 1, 4) 6178 6179 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 6180 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 6181 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 6182 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 6183 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 6184 6185 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4) 6186 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 6187 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 6188 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 6189 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 6190 6191 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0) 6192 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 6193 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 6194 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 6195 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 6196 6197 /* PORT_CONF:HW_CFG:DEV5G_MODES */ 6198 #define PORT_CONF_DEV5G_MODES \ 6199 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 6200 6201 /* SPARX5 ONLY */ 6202 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 6203 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 6204 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6205 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 6206 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6207 6208 /* SPARX5 ONLY */ 6209 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 6210 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 6211 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6212 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 6213 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6214 6215 /* SPARX5 ONLY */ 6216 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 6217 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 6218 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6219 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 6220 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6221 6222 /* SPARX5 ONLY */ 6223 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 6224 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 6225 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6226 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 6227 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6228 6229 /* SPARX5 ONLY */ 6230 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 6231 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 6232 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6233 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 6234 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6235 6236 /* SPARX5 ONLY */ 6237 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 6238 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 6239 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6240 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 6241 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6242 6243 /* SPARX5 ONLY */ 6244 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 6245 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 6246 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6247 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 6248 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6249 6250 /* SPARX5 ONLY */ 6251 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 6252 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 6253 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6254 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 6255 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6256 6257 /* SPARX5 ONLY */ 6258 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 6259 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 6260 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 6261 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ 6262 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 6263 6264 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9) 6265 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ 6266 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 6267 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 6268 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 6269 6270 /* SPARX5 ONLY */ 6271 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 6272 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 6273 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6274 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 6275 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6276 6277 /* SPARX5 ONLY */ 6278 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 6279 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 6280 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6281 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 6282 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6283 6284 /* SPARX5 ONLY */ 6285 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 6286 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 6287 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6288 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 6289 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6290 6291 /* PORT_CONF:HW_CFG:DEV10G_MODES */ 6292 #define PORT_CONF_DEV10G_MODES \ 6293 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 6294 6295 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 6296 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ 6297 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 6298 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 6299 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 6300 6301 /* SPARX5 ONLY */ 6302 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 6303 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 6304 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6305 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 6306 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6307 6308 /* SPARX5 ONLY */ 6309 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 6310 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 6311 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6312 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 6313 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6314 6315 /* SPARX5 ONLY */ 6316 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 6317 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 6318 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6319 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 6320 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6321 6322 /* SPARX5 ONLY */ 6323 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 6324 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 6325 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6326 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 6327 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6328 6329 /* SPARX5 ONLY */ 6330 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 6331 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 6332 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6333 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 6334 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6335 6336 /* SPARX5 ONLY */ 6337 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 6338 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 6339 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6340 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 6341 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6342 6343 /* SPARX5 ONLY */ 6344 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 6345 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 6346 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6347 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 6348 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6349 6350 /* SPARX5 ONLY */ 6351 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 6352 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 6353 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6354 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 6355 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6356 6357 /* SPARX5 ONLY */ 6358 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 6359 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 6360 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6361 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 6362 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6363 6364 /* SPARX5 ONLY */ 6365 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 6366 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 6367 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6368 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 6369 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6370 6371 /* SPARX5 ONLY */ 6372 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 6373 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 6374 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6375 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 6376 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6377 6378 /* SPARX5 ONLY */ 6379 /* PORT_CONF:HW_CFG:DEV25G_MODES */ 6380 #define PORT_CONF_DEV25G_MODES \ 6381 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 6382 6383 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 6384 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ 6385 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 6386 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ 6387 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 6388 6389 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1) 6390 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ 6391 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 6392 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ 6393 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 6394 6395 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2) 6396 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ 6397 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 6398 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ 6399 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 6400 6401 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3) 6402 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ 6403 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 6404 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ 6405 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 6406 6407 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4) 6408 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ 6409 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 6410 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ 6411 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 6412 6413 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5) 6414 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ 6415 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 6416 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ 6417 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 6418 6419 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6) 6420 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ 6421 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 6422 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ 6423 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 6424 6425 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7) 6426 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ 6427 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 6428 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 6429 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 6430 6431 /* PORT_CONF:HW_CFG:QSGMII_ENA */ 6432 #define PORT_CONF_QSGMII_ENA \ 6433 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 6434 6435 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 6436 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ 6437 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 6438 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ 6439 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 6440 6441 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1) 6442 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ 6443 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 6444 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ 6445 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 6446 6447 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2) 6448 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ 6449 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 6450 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ 6451 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 6452 6453 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3) 6454 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ 6455 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 6456 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ 6457 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 6458 6459 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4) 6460 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ 6461 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 6462 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ 6463 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 6464 6465 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5) 6466 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ 6467 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 6468 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 6469 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 6470 6471 /* SPARX5 ONLY */ 6472 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 6473 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 6474 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6475 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 6476 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6477 6478 /* SPARX5 ONLY */ 6479 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 6480 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 6481 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6482 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 6483 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6484 6485 /* SPARX5 ONLY */ 6486 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 6487 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 6488 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6489 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 6490 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6491 6492 /* SPARX5 ONLY */ 6493 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 6494 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 6495 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6496 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 6497 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6498 6499 /* SPARX5 ONLY */ 6500 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 6501 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 6502 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6503 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 6504 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6505 6506 /* SPARX5 ONLY */ 6507 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 6508 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 6509 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6510 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 6511 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6512 6513 /* SPARX5 ONLY */ 6514 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 6515 #define PORT_CONF_USGMII_CFG(g) \ 6516 __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 6517 6518 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 6519 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ 6520 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 6521 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ 6522 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 6523 6524 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8) 6525 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ 6526 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 6527 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ 6528 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 6529 6530 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7) 6531 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ 6532 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 6533 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ 6534 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 6535 6536 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6) 6537 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ 6538 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 6539 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ 6540 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 6541 6542 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5) 6543 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ 6544 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 6545 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ 6546 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 6547 6548 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4) 6549 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ 6550 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 6551 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ 6552 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 6553 6554 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1) 6555 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ 6556 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 6557 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 6558 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 6559 6560 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 6561 #define PTP_PTP_PIN_INTR \ 6562 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\ 6563 4) 6564 6565 #define PTP_PTP_PIN_INTR_INTR_PTP\ 6566 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0) 6567 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 6568 spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x) 6569 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 6570 spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x) 6571 6572 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 6573 #define PTP_PTP_PIN_INTR_ENA \ 6574 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\ 6575 4) 6576 6577 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\ 6578 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0) 6579 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 6580 spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6581 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 6582 spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6583 6584 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 6585 #define PTP_PTP_INTR_IDENT \ 6586 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\ 6587 4) 6588 6589 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\ 6590 GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0) 6591 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 6592 spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6593 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 6594 spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6595 6596 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 6597 #define PTP_PTP_DOM_CFG \ 6598 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \ 6599 1, 4) 6600 6601 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 6602 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ 6603 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x) 6604 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ 6605 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x) 6606 6607 #define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6) 6608 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ 6609 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x) 6610 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ 6611 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x) 6612 6613 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3) 6614 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ 6615 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 6616 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ 6617 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 6618 6619 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0) 6620 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ 6621 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 6622 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 6623 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 6624 6625 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 6626 #define PTP_CLK_PER_CFG(g, r) \ 6627 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6628 0, r, 2, 4) 6629 6630 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 6631 #define PTP_PTP_CUR_NSEC(g) \ 6632 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6633 8, 0, 1, 4) 6634 6635 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 6636 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ 6637 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6638 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 6639 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6640 6641 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 6642 #define PTP_PTP_CUR_NSEC_FRAC(g) \ 6643 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6644 12, 0, 1, 4) 6645 6646 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 6647 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ 6648 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6649 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 6650 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6651 6652 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 6653 #define PTP_PTP_CUR_SEC_LSB(g) \ 6654 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6655 16, 0, 1, 4) 6656 6657 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 6658 #define PTP_PTP_CUR_SEC_MSB(g) \ 6659 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6660 20, 0, 1, 4) 6661 6662 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 6663 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ 6664 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6665 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 6666 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6667 6668 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 6669 #define PTP_NTP_CUR_NSEC(g) \ 6670 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6671 24, 0, 1, 4) 6672 6673 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 6674 #define PTP_PTP_PIN_CFG(g) \ 6675 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\ 6676 4) 6677 6678 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\ 6679 GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION]) 6680 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 6681 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6682 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 6683 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6684 6685 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\ 6686 GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC]) 6687 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 6688 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6689 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 6690 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6691 6692 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\ 6693 BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL]) 6694 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 6695 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6696 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 6697 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6698 6699 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\ 6700 GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21) 6701 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 6702 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6703 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 6704 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6705 6706 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 6707 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ 6708 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6709 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ 6710 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6711 6712 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16) 6713 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ 6714 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6715 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ 6716 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6717 6718 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14) 6719 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ 6720 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6721 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ 6722 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6723 6724 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13) 6725 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ 6726 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6727 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ 6728 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6729 6730 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0) 6731 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ 6732 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6733 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 6734 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6735 6736 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 6737 #define PTP_PTP_TOD_SEC_MSB(g) \ 6738 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\ 6739 4) 6740 6741 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 6742 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ 6743 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6744 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 6745 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6746 6747 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 6748 #define PTP_PTP_TOD_SEC_LSB(g) \ 6749 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\ 6750 4) 6751 6752 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 6753 #define PTP_PTP_TOD_NSEC(g) \ 6754 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \ 6755 1, 4) 6756 6757 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 6758 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ 6759 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6760 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 6761 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6762 6763 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 6764 #define PTP_PTP_TOD_NSEC_FRAC(g) \ 6765 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \ 6766 1, 4) 6767 6768 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 6769 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ 6770 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6771 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 6772 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6773 6774 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 6775 #define PTP_NTP_NSEC(g) \ 6776 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \ 6777 1, 4) 6778 6779 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 6780 #define PTP_PIN_WF_HIGH_PERIOD(g) \ 6781 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \ 6782 1, 4) 6783 6784 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 6785 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ 6786 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6787 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 6788 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6789 6790 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 6791 #define PTP_PIN_WF_LOW_PERIOD(g) \ 6792 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \ 6793 1, 4) 6794 6795 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 6796 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ 6797 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6798 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 6799 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6800 6801 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 6802 #define PTP_PIN_IOBOUNCH_DELAY(g) \ 6803 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \ 6804 1, 4) 6805 6806 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 6807 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ 6808 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6809 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ 6810 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6811 6812 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0) 6813 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ 6814 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6815 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 6816 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6817 6818 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 6819 #define PTP_PHAD_CTRL(g) \ 6820 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6821 regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6822 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) 6823 6824 #define PTP_PHAD_CTRL_PHAD_ENA\ 6825 BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA]) 6826 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 6827 spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x) 6828 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 6829 spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x) 6830 6831 #define PTP_PHAD_CTRL_PHAD_FAILED\ 6832 BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED]) 6833 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 6834 spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x) 6835 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 6836 spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x) 6837 6838 /* SPARX5 ONLY */ 6839 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 6840 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 6841 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) 6842 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ 6843 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x) 6844 6845 #define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0) 6846 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ 6847 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x) 6848 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 6849 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 6850 6851 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 6852 #define PTP_PHAD_CYC_STAT(g) \ 6853 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6854 regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6855 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) 6856 6857 /* LAN969X ONLY */ 6858 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 6859 #define PTP_TWOSTEP_CTRL \ 6860 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4) 6861 6862 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 6863 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 6864 FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6865 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 6866 FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6867 6868 #define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 6869 #define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 6870 FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x) 6871 #define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 6872 FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x) 6873 6874 #define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 6875 #define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 6876 FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x) 6877 #define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 6878 FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x) 6879 6880 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 6881 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 6882 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 6883 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 6884 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 6885 6886 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 6887 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 6888 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6889 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 6890 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6891 6892 #define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 6893 #define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 6894 FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6895 #define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 6896 FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6897 6898 /* LAN969X ONLY */ 6899 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */ 6900 #define PTP_TWOSTEP_STAMP_NSEC \ 6901 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4) 6902 6903 #define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0) 6904 #define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\ 6905 FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x) 6906 #define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\ 6907 FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x) 6908 6909 /* LAN969X ONLY */ 6910 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */ 6911 #define PTP_TWOSTEP_STAMP_SUBNS \ 6912 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4) 6913 6914 #define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0) 6915 #define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\ 6916 FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x) 6917 #define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\ 6918 FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x) 6919 6920 /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 6921 #define QFWD_SWITCH_PORT_MODE(r) \ 6922 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ 6923 regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4) 6924 6925 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 6926 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ 6927 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6928 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ 6929 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6930 6931 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10) 6932 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ 6933 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6934 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ 6935 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6936 6937 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6) 6938 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ 6939 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6940 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ 6941 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6942 6943 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5) 6944 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 6945 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6946 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 6947 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6948 6949 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4) 6950 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ 6951 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6952 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ 6953 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6954 6955 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3) 6956 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ 6957 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6958 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ 6959 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6960 6961 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2) 6962 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ 6963 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6964 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ 6965 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6966 6967 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1) 6968 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ 6969 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6970 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ 6971 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6972 6973 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0) 6974 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ 6975 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6976 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 6977 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6978 6979 /* QFWD:SYSTEM:FRAME_COPY_CFG */ 6980 #define QFWD_FRAME_COPY_CFG(r) \ 6981 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) 6982 6983 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\ 6984 GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6) 6985 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ 6986 spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6987 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ 6988 spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6989 6990 /* QRES:RES_CTRL:RES_CFG */ 6991 #define QRES_RES_CFG(g) \ 6992 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 6993 6994 #define QRES_RES_CFG_WM_HIGH\ 6995 GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0) 6996 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 6997 spx5_field_prep(QRES_RES_CFG_WM_HIGH, x) 6998 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 6999 spx5_field_get(QRES_RES_CFG_WM_HIGH, x) 7000 7001 /* QRES:RES_CTRL:RES_STAT */ 7002 #define QRES_RES_STAT(g) \ 7003 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 7004 7005 #define QRES_RES_STAT_MAXUSE\ 7006 GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0) 7007 #define QRES_RES_STAT_MAXUSE_SET(x)\ 7008 spx5_field_prep(QRES_RES_STAT_MAXUSE, x) 7009 #define QRES_RES_STAT_MAXUSE_GET(x)\ 7010 spx5_field_get(QRES_RES_STAT_MAXUSE, x) 7011 7012 /* QRES:RES_CTRL:RES_STAT_CUR */ 7013 #define QRES_RES_STAT_CUR(g) \ 7014 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 7015 7016 #define QRES_RES_STAT_CUR_INUSE\ 7017 GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0) 7018 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 7019 spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x) 7020 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 7021 spx5_field_get(QRES_RES_STAT_CUR_INUSE, x) 7022 7023 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 7024 #define QS_XTR_GRP_CFG(r) \ 7025 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 7026 7027 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 7028 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 7029 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 7030 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 7031 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 7032 7033 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 7034 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ 7035 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 7036 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ 7037 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 7038 7039 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 7040 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 7041 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 7042 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 7043 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 7044 7045 /* DEVCPU_QS:XTR:XTR_RD */ 7046 #define QS_XTR_RD(r) \ 7047 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 7048 7049 /* DEVCPU_QS:XTR:XTR_FLUSH */ 7050 #define QS_XTR_FLUSH \ 7051 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 7052 7053 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 7054 #define QS_XTR_FLUSH_FLUSH_SET(x)\ 7055 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x) 7056 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 7057 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 7058 7059 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 7060 #define QS_XTR_DATA_PRESENT \ 7061 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 7062 7063 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 7064 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ 7065 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 7066 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 7067 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 7068 7069 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 7070 #define QS_INJ_GRP_CFG(r) \ 7071 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 7072 7073 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 7074 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 7075 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 7076 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 7077 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 7078 7079 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 7080 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 7081 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 7082 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 7083 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 7084 7085 /* DEVCPU_QS:INJ:INJ_WR */ 7086 #define QS_INJ_WR(r) \ 7087 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 7088 7089 /* DEVCPU_QS:INJ:INJ_CTRL */ 7090 #define QS_INJ_CTRL(r) \ 7091 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 7092 7093 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 7094 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 7095 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 7096 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 7097 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 7098 7099 #define QS_INJ_CTRL_ABORT BIT(20) 7100 #define QS_INJ_CTRL_ABORT_SET(x)\ 7101 FIELD_PREP(QS_INJ_CTRL_ABORT, x) 7102 #define QS_INJ_CTRL_ABORT_GET(x)\ 7103 FIELD_GET(QS_INJ_CTRL_ABORT, x) 7104 7105 #define QS_INJ_CTRL_EOF BIT(19) 7106 #define QS_INJ_CTRL_EOF_SET(x)\ 7107 FIELD_PREP(QS_INJ_CTRL_EOF, x) 7108 #define QS_INJ_CTRL_EOF_GET(x)\ 7109 FIELD_GET(QS_INJ_CTRL_EOF, x) 7110 7111 #define QS_INJ_CTRL_SOF BIT(18) 7112 #define QS_INJ_CTRL_SOF_SET(x)\ 7113 FIELD_PREP(QS_INJ_CTRL_SOF, x) 7114 #define QS_INJ_CTRL_SOF_GET(x)\ 7115 FIELD_GET(QS_INJ_CTRL_SOF, x) 7116 7117 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 7118 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 7119 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 7120 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 7121 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 7122 7123 /* DEVCPU_QS:INJ:INJ_STATUS */ 7124 #define QS_INJ_STATUS \ 7125 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 7126 7127 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 7128 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 7129 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 7130 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 7131 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 7132 7133 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 7134 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 7135 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 7136 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 7137 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 7138 7139 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0) 7140 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ 7141 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 7142 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 7143 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 7144 7145 /* QSYS:PAUSE_CFG:PAUSE_CFG */ 7146 #define QSYS_PAUSE_CFG(r) \ 7147 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \ 7148 r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4) 7149 7150 #define QSYS_PAUSE_CFG_PAUSE_START\ 7151 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14) 7152 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 7153 spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x) 7154 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 7155 spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x) 7156 7157 #define QSYS_PAUSE_CFG_PAUSE_STOP\ 7158 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2) 7159 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 7160 spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x) 7161 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 7162 spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x) 7163 7164 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 7165 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 7166 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x) 7167 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 7168 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x) 7169 7170 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0) 7171 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ 7172 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 7173 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 7174 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 7175 7176 /* QSYS:PAUSE_CFG:ATOP */ 7177 #define QSYS_ATOP(r) \ 7178 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 7179 284, r, regs->rcnt[RC_QSYS_ATOP], 4) 7180 7181 #define QSYS_ATOP_ATOP\ 7182 GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0) 7183 #define QSYS_ATOP_ATOP_SET(x)\ 7184 spx5_field_prep(QSYS_ATOP_ATOP, x) 7185 #define QSYS_ATOP_ATOP_GET(x)\ 7186 spx5_field_get(QSYS_ATOP_ATOP, x) 7187 7188 /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 7189 #define QSYS_FWD_PRESSURE(r) \ 7190 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 7191 564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4) 7192 7193 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 7194 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ 7195 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 7196 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ 7197 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 7198 7199 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0) 7200 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ 7201 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 7202 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 7203 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 7204 7205 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 7206 #define QSYS_ATOP_TOT_CFG \ 7207 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 7208 844, 0, 1, 4) 7209 7210 #define QSYS_ATOP_TOT_CFG_ATOP_TOT\ 7211 GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0) 7212 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 7213 spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7214 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 7215 spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7216 7217 /* QSYS:CALCFG:CAL_AUTO */ 7218 #define QSYS_CAL_AUTO(r) \ 7219 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \ 7220 regs->rcnt[RC_QSYS_CAL_AUTO], 4) 7221 7222 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 7223 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ 7224 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x) 7225 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 7226 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 7227 7228 /* QSYS:CALCFG:CAL_CTRL */ 7229 #define QSYS_CAL_CTRL \ 7230 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \ 7231 1, 4) 7232 7233 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 7234 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ 7235 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x) 7236 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ 7237 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x) 7238 7239 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1) 7240 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ 7241 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 7242 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ 7243 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 7244 7245 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0) 7246 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ 7247 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 7248 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 7249 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 7250 7251 /* QSYS:RAM_CTRL:RAM_INIT */ 7252 #define QSYS_RAM_INIT \ 7253 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \ 7254 1, 4) 7255 7256 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 7257 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ 7258 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x) 7259 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ 7260 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x) 7261 7262 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 7263 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7264 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 7265 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7266 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 7267 7268 /* REW:COMMON:OWN_UPSID */ 7269 #define REW_OWN_UPSID(r) \ 7270 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \ 7271 regs->rcnt[RC_REW_OWN_UPSID], 4) 7272 7273 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 7274 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ 7275 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x) 7276 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 7277 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 7278 7279 /* REW:COMMON:RTAG_ETAG_CTRL */ 7280 #define REW_RTAG_ETAG_CTRL(r) \ 7281 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\ 7282 regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4) 7283 7284 #define REW_RTAG_ETAG_CTRL_IPE_TBL\ 7285 GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3) 7286 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ 7287 spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7288 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ 7289 spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7290 7291 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) 7292 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ 7293 FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 7294 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\ 7295 FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 7296 7297 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG BIT(0) 7298 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\ 7299 FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 7300 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ 7301 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 7302 7303 /* REW:COMMON:ES0_CTRL */ 7304 #define REW_ES0_CTRL \ 7305 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\ 7306 1, 4) 7307 7308 #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) 7309 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ 7310 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 7311 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\ 7312 FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 7313 7314 #define REW_ES0_CTRL_ES0_BY_RLEG BIT(4) 7315 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\ 7316 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x) 7317 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\ 7318 FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x) 7319 7320 #define REW_ES0_CTRL_ES0_DPORT_ENA BIT(3) 7321 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\ 7322 FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x) 7323 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\ 7324 FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x) 7325 7326 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG BIT(2) 7327 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\ 7328 FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 7329 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\ 7330 FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 7331 7332 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1) 7333 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\ 7334 FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 7335 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\ 7336 FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 7337 7338 #define REW_ES0_CTRL_ES0_LU_ENA BIT(0) 7339 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\ 7340 FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x) 7341 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ 7342 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) 7343 7344 /* REW:PORT:PORT_VLAN_CFG */ 7345 #define REW_PORT_VLAN_CFG(g) \ 7346 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7347 regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4) 7348 7349 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 7350 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ 7351 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x) 7352 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ 7353 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x) 7354 7355 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12) 7356 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ 7357 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x) 7358 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ 7359 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x) 7360 7361 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 7362 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 7363 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 7364 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 7365 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 7366 7367 /* REW:PORT:PCP_MAP_DE0 */ 7368 #define REW_PCP_MAP_DE0(g, r) \ 7369 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7370 regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4) 7371 7372 #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) 7373 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ 7374 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x) 7375 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ 7376 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) 7377 7378 /* REW:PORT:PCP_MAP_DE1 */ 7379 #define REW_PCP_MAP_DE1(g, r) \ 7380 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7381 regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4) 7382 7383 #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) 7384 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ 7385 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x) 7386 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ 7387 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) 7388 7389 /* REW:PORT:DEI_MAP_DE0 */ 7390 #define REW_DEI_MAP_DE0(g, r) \ 7391 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7392 regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4) 7393 7394 #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) 7395 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ 7396 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x) 7397 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ 7398 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) 7399 7400 /* REW:PORT:DEI_MAP_DE1 */ 7401 #define REW_DEI_MAP_DE1(g, r) \ 7402 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7403 regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4) 7404 7405 #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) 7406 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ 7407 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x) 7408 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ 7409 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) 7410 7411 /* REW:PORT:TAG_CTRL */ 7412 #define REW_TAG_CTRL(g) \ 7413 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7414 regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4) 7415 7416 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 7417 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ 7418 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 7419 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ 7420 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 7421 7422 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11) 7423 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ 7424 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x) 7425 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ 7426 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x) 7427 7428 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8) 7429 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ 7430 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x) 7431 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ 7432 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x) 7433 7434 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6) 7435 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ 7436 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x) 7437 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ 7438 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x) 7439 7440 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3) 7441 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ 7442 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x) 7443 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ 7444 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x) 7445 7446 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0) 7447 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ 7448 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x) 7449 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 7450 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 7451 7452 /* REW:PORT:DSCP_MAP */ 7453 #define REW_DSCP_MAP(g) \ 7454 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7455 regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4) 7456 7457 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) 7458 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ 7459 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 7460 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\ 7461 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 7462 7463 #define REW_DSCP_MAP_DSCP_REMAP_ENA BIT(0) 7464 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\ 7465 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 7466 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ 7467 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 7468 7469 /* SPARX5 ONLY */ 7470 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 7471 #define REW_PTP_TWOSTEP_CTRL \ 7472 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 7473 7474 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 7475 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 7476 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 7477 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 7478 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 7479 7480 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 7481 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 7482 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 7483 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 7484 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 7485 7486 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 7487 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 7488 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 7489 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 7490 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 7491 7492 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 7493 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 7494 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 7495 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 7496 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 7497 7498 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 7499 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 7500 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 7501 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 7502 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 7503 7504 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 7505 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 7506 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 7507 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 7508 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 7509 7510 /* SPARX5 ONLY */ 7511 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 7512 #define REW_PTP_TWOSTEP_STAMP \ 7513 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 7514 7515 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 7516 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 7517 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 7518 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 7519 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 7520 7521 /* SPARX5 ONLY */ 7522 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 7523 #define REW_PTP_TWOSTEP_STAMP_SUBNS \ 7524 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 7525 7526 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 7527 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ 7528 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 7529 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 7530 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 7531 7532 /* SPARX5 ONLY */ 7533 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 7534 #define REW_PTP_RSRV_NOT_ZERO \ 7535 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 7536 7537 /* SPARX5 ONLY */ 7538 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 7539 #define REW_PTP_RSRV_NOT_ZERO1 \ 7540 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 7541 7542 /* SPARX5 ONLY */ 7543 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 7544 #define REW_PTP_RSRV_NOT_ZERO2 \ 7545 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 7546 7547 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 7548 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ 7549 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 7550 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 7551 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 7552 7553 /* SPARX5 ONLY */ 7554 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 7555 #define REW_PTP_GEN_STAMP_FMT(r) \ 7556 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 7557 7558 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 7559 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ 7560 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 7561 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ 7562 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 7563 7564 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0) 7565 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ 7566 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 7567 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 7568 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 7569 7570 /* REW:RAM_CTRL:RAM_INIT */ 7571 #define REW_RAM_INIT \ 7572 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 7573 4) 7574 7575 #define REW_RAM_INIT_RAM_INIT BIT(1) 7576 #define REW_RAM_INIT_RAM_INIT_SET(x)\ 7577 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x) 7578 #define REW_RAM_INIT_RAM_INIT_GET(x)\ 7579 FIELD_GET(REW_RAM_INIT_RAM_INIT, x) 7580 7581 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0) 7582 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7583 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x) 7584 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7585 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 7586 7587 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7588 #define VCAP_ES0_CTRL \ 7589 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7590 7591 #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) 7592 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ 7593 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x) 7594 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\ 7595 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x) 7596 7597 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS BIT(21) 7598 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7599 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 7600 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7601 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 7602 7603 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS BIT(20) 7604 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7605 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 7606 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7607 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 7608 7609 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS BIT(19) 7610 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\ 7611 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 7612 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\ 7613 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 7614 7615 #define VCAP_ES0_CTRL_UPDATE_ADDR GENMASK(18, 3) 7616 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\ 7617 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x) 7618 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\ 7619 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x) 7620 7621 #define VCAP_ES0_CTRL_UPDATE_SHOT BIT(2) 7622 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\ 7623 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x) 7624 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\ 7625 FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x) 7626 7627 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1) 7628 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\ 7629 FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x) 7630 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\ 7631 FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x) 7632 7633 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN BIT(0) 7634 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7635 FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 7636 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7637 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 7638 7639 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ 7640 #define VCAP_ES0_CFG \ 7641 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7642 7643 #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) 7644 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ 7645 FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x) 7646 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\ 7647 FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x) 7648 7649 #define VCAP_ES0_CFG_MV_SIZE GENMASK(15, 0) 7650 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\ 7651 FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x) 7652 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ 7653 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) 7654 7655 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7656 #define VCAP_ES0_VCAP_ENTRY_DAT(r) \ 7657 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7658 7659 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7660 #define VCAP_ES0_VCAP_MASK_DAT(r) \ 7661 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7662 7663 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7664 #define VCAP_ES0_VCAP_ACTION_DAT(r) \ 7665 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7666 7667 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7668 #define VCAP_ES0_VCAP_CNT_DAT(r) \ 7669 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7670 7671 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7672 #define VCAP_ES0_VCAP_CNT_FW_DAT \ 7673 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7674 7675 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7676 #define VCAP_ES0_VCAP_TG_DAT \ 7677 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7678 7679 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7680 #define VCAP_ES0_IDX \ 7681 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7682 7683 #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) 7684 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ 7685 FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x) 7686 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ 7687 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) 7688 7689 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7690 #define VCAP_ES0_MAP \ 7691 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7692 7693 #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) 7694 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ 7695 FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x) 7696 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ 7697 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) 7698 7699 /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ 7700 #define VCAP_ES0_VCAP_STICKY \ 7701 __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7702 7703 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7704 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 7705 FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7706 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7707 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7708 7709 /* VCAP_ES0:VCAP_CONST:VCAP_VER */ 7710 #define VCAP_ES0_VCAP_VER \ 7711 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7712 7713 /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ 7714 #define VCAP_ES0_ENTRY_WIDTH \ 7715 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7716 7717 /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ 7718 #define VCAP_ES0_ENTRY_CNT \ 7719 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7720 7721 /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ 7722 #define VCAP_ES0_ENTRY_SWCNT \ 7723 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7724 7725 /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ 7726 #define VCAP_ES0_ENTRY_TG_WIDTH \ 7727 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7728 7729 /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ 7730 #define VCAP_ES0_ACTION_DEF_CNT \ 7731 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7732 7733 /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ 7734 #define VCAP_ES0_ACTION_WIDTH \ 7735 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7736 7737 /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ 7738 #define VCAP_ES0_CNT_WIDTH \ 7739 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7740 7741 /* VCAP_ES0:VCAP_CONST:CORE_CNT */ 7742 #define VCAP_ES0_CORE_CNT \ 7743 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7744 7745 /* VCAP_ES0:VCAP_CONST:IF_CNT */ 7746 #define VCAP_ES0_IF_CNT \ 7747 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7748 7749 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7750 #define VCAP_ES2_CTRL \ 7751 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7752 7753 #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) 7754 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ 7755 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x) 7756 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\ 7757 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x) 7758 7759 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS BIT(21) 7760 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7761 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7762 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7763 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7764 7765 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS BIT(20) 7766 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7767 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7768 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7769 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7770 7771 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS BIT(19) 7772 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\ 7773 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7774 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\ 7775 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7776 7777 #define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3) 7778 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\ 7779 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7780 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\ 7781 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7782 7783 #define VCAP_ES2_CTRL_UPDATE_SHOT BIT(2) 7784 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\ 7785 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7786 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\ 7787 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7788 7789 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1) 7790 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\ 7791 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7792 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\ 7793 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7794 7795 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN BIT(0) 7796 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7797 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7798 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7799 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7800 7801 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 7802 #define VCAP_ES2_CFG \ 7803 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7804 7805 #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) 7806 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ 7807 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x) 7808 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\ 7809 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x) 7810 7811 #define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0) 7812 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\ 7813 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x) 7814 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ 7815 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) 7816 7817 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7818 #define VCAP_ES2_VCAP_ENTRY_DAT(r) \ 7819 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7820 7821 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7822 #define VCAP_ES2_VCAP_MASK_DAT(r) \ 7823 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7824 7825 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7826 #define VCAP_ES2_VCAP_ACTION_DAT(r) \ 7827 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7828 7829 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7830 #define VCAP_ES2_VCAP_CNT_DAT(r) \ 7831 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7832 7833 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7834 #define VCAP_ES2_VCAP_CNT_FW_DAT \ 7835 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7836 7837 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7838 #define VCAP_ES2_VCAP_TG_DAT \ 7839 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7840 7841 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7842 #define VCAP_ES2_IDX \ 7843 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7844 7845 #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) 7846 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ 7847 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x) 7848 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ 7849 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) 7850 7851 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7852 #define VCAP_ES2_MAP \ 7853 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7854 7855 #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) 7856 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ 7857 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x) 7858 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ 7859 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) 7860 7861 /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 7862 #define VCAP_ES2_VCAP_STICKY \ 7863 __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7864 7865 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7866 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 7867 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7868 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7869 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7870 7871 /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 7872 #define VCAP_ES2_VCAP_VER \ 7873 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7874 7875 /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 7876 #define VCAP_ES2_ENTRY_WIDTH \ 7877 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7878 7879 /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 7880 #define VCAP_ES2_ENTRY_CNT \ 7881 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7882 7883 /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 7884 #define VCAP_ES2_ENTRY_SWCNT \ 7885 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7886 7887 /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 7888 #define VCAP_ES2_ENTRY_TG_WIDTH \ 7889 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7890 7891 /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 7892 #define VCAP_ES2_ACTION_DEF_CNT \ 7893 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7894 7895 /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 7896 #define VCAP_ES2_ACTION_WIDTH \ 7897 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7898 7899 /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 7900 #define VCAP_ES2_CNT_WIDTH \ 7901 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7902 7903 /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 7904 #define VCAP_ES2_CORE_CNT \ 7905 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7906 7907 /* VCAP_ES2:VCAP_CONST:IF_CNT */ 7908 #define VCAP_ES2_IF_CNT \ 7909 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7910 7911 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7912 #define VCAP_SUPER_CTRL \ 7913 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7914 7915 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 7916 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ 7917 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7918 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ 7919 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7920 7921 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21) 7922 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7923 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7924 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7925 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7926 7927 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20) 7928 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7929 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7930 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7931 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7932 7933 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19) 7934 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ 7935 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7936 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ 7937 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7938 7939 #define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3) 7940 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ 7941 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7942 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ 7943 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7944 7945 #define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2) 7946 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ 7947 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7948 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ 7949 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7950 7951 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1) 7952 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ 7953 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7954 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ 7955 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7956 7957 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0) 7958 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7959 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7960 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7961 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7962 7963 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 7964 #define VCAP_SUPER_CFG \ 7965 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7966 7967 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 7968 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ 7969 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x) 7970 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ 7971 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x) 7972 7973 #define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0) 7974 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ 7975 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x) 7976 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 7977 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 7978 7979 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7980 #define VCAP_SUPER_VCAP_ENTRY_DAT(r) \ 7981 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7982 7983 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7984 #define VCAP_SUPER_VCAP_MASK_DAT(r) \ 7985 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7986 7987 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7988 #define VCAP_SUPER_VCAP_ACTION_DAT(r) \ 7989 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7990 7991 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7992 #define VCAP_SUPER_VCAP_CNT_DAT(r) \ 7993 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7994 7995 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7996 #define VCAP_SUPER_VCAP_CNT_FW_DAT \ 7997 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7998 7999 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 8000 #define VCAP_SUPER_VCAP_TG_DAT \ 8001 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 8002 8003 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 8004 #define VCAP_SUPER_IDX \ 8005 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 8006 8007 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 8008 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ 8009 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x) 8010 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 8011 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 8012 8013 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 8014 #define VCAP_SUPER_MAP \ 8015 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 8016 8017 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 8018 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ 8019 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x) 8020 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 8021 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 8022 8023 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 8024 #define VCAP_SUPER_VCAP_VER \ 8025 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 8026 8027 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 8028 #define VCAP_SUPER_ENTRY_WIDTH \ 8029 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 8030 8031 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 8032 #define VCAP_SUPER_ENTRY_CNT \ 8033 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 8034 8035 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 8036 #define VCAP_SUPER_ENTRY_SWCNT \ 8037 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 8038 8039 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 8040 #define VCAP_SUPER_ENTRY_TG_WIDTH \ 8041 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 8042 8043 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 8044 #define VCAP_SUPER_ACTION_DEF_CNT \ 8045 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 8046 8047 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 8048 #define VCAP_SUPER_ACTION_WIDTH \ 8049 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 8050 8051 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 8052 #define VCAP_SUPER_CNT_WIDTH \ 8053 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 8054 8055 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 8056 #define VCAP_SUPER_CORE_CNT \ 8057 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 8058 8059 /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 8060 #define VCAP_SUPER_IF_CNT \ 8061 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 8062 8063 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 8064 #define VCAP_SUPER_RAM_INIT \ 8065 __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 8066 8067 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 8068 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ 8069 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 8070 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ 8071 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 8072 8073 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0) 8074 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 8075 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 8076 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 8077 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 8078 8079 /* VOP:RAM_CTRL:RAM_INIT */ 8080 #define VOP_RAM_INIT \ 8081 __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 8082 4) 8083 8084 #define VOP_RAM_INIT_RAM_INIT BIT(1) 8085 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ 8086 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x) 8087 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ 8088 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x) 8089 8090 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0) 8091 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 8092 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x) 8093 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 8094 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 8095 8096 /* XQS:SYSTEM:STAT_CFG */ 8097 #define XQS_STAT_CFG \ 8098 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \ 8099 1, 4) 8100 8101 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 8102 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ 8103 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 8104 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 8105 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 8106 8107 #define XQS_STAT_CFG_STAT_VIEW\ 8108 GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5) 8109 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 8110 spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x) 8111 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 8112 spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x) 8113 8114 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 8115 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ 8116 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 8117 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ 8118 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 8119 8120 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0) 8121 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ 8122 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x) 8123 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 8124 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 8125 8126 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 8127 #define XQS_QLIMIT_SHR_TOP_CFG(g) \ 8128 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\ 8129 1, 4) 8130 8131 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\ 8132 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0) 8133 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 8134 spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 8135 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 8136 spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 8137 8138 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 8139 #define XQS_QLIMIT_SHR_ATOP_CFG(g) \ 8140 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\ 8141 1, 4) 8142 8143 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\ 8144 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0) 8145 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 8146 spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 8147 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 8148 spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 8149 8150 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 8151 #define XQS_QLIMIT_SHR_CTOP_CFG(g) \ 8152 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\ 8153 1, 4) 8154 8155 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\ 8156 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0) 8157 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 8158 spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 8159 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 8160 spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 8161 8162 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 8163 #define XQS_QLIMIT_SHR_QLIM_CFG(g) \ 8164 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \ 8165 0, 1, 4) 8166 8167 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\ 8168 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0) 8169 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 8170 spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 8171 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 8172 spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 8173 8174 /* XQS:STAT:CNT */ 8175 #define XQS_CNT(g) \ 8176 __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 8177 8178 /* LAN969X ONLY */ 8179 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 8180 #define DEVRGMII_DEV_RST_CTRL(t) \ 8181 __REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4) 8182 8183 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 8184 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 8185 FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) 8186 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 8187 FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) 8188 8189 /* LAN969X ONLY */ 8190 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 8191 #define DEVRGMII_MAC_ENA_CFG(t) \ 8192 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4) 8193 8194 #define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4) 8195 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\ 8196 FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) 8197 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\ 8198 FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) 8199 8200 #define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0) 8201 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\ 8202 FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) 8203 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\ 8204 FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) 8205 8206 /* LAN969X ONLY */ 8207 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 8208 #define DEVRGMII_MAC_TAGS_CFG(t) \ 8209 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4) 8210 8211 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 8212 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\ 8213 FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) 8214 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\ 8215 FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) 8216 8217 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 8218 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 8219 FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 8220 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 8221 FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 8222 8223 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 8224 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\ 8225 FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) 8226 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\ 8227 FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) 8228 8229 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 8230 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 8231 FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 8232 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 8233 FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 8234 8235 /* LAN969X ONLY */ 8236 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 8237 #define DEVRGMII_MAC_IFG_CFG(t) \ 8238 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4) 8239 8240 #define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 8241 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\ 8242 FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) 8243 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\ 8244 FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) 8245 8246 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 8247 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\ 8248 FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) 8249 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\ 8250 FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) 8251 8252 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 8253 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\ 8254 FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) 8255 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\ 8256 FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) 8257 8258 #endif /* _SPARX5_MAIN_REGS_H_ */ 8259