1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_TXHEADER_H 5 #define _MLXSW_TXHEADER_H 6 7 /* tx_hdr_version 8 * Tx header version. 9 * Must be set to 1. 10 */ 11 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 12 13 /* tx_hdr_ctl 14 * Packet control type. 15 * 0 - Ethernet control (e.g. EMADs, LACP) 16 * 1 - Ethernet data 17 */ 18 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 19 20 /* tx_hdr_proto 21 * Packet protocol type. Must be set to 1 (Ethernet). 22 */ 23 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 24 25 /* tx_hdr_rx_is_router 26 * Packet is sent from the router. Valid for data packets only. 27 */ 28 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 29 30 /* tx_hdr_fid_valid 31 * Indicates if the 'fid' field is valid and should be used for 32 * forwarding lookup. Valid for data packets only. 33 */ 34 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 35 36 /* tx_hdr_swid 37 * Switch partition ID. Must be set to 0. 38 */ 39 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 40 41 /* tx_hdr_control_tclass 42 * Indicates if the packet should use the control TClass and not one 43 * of the data TClasses. 44 */ 45 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 46 47 /* tx_hdr_port_mid 48 * Destination local port for unicast packets. 49 * Destination multicast ID for multicast packets. 50 * 51 * Control packets are directed to a specific egress port, while data 52 * packets are transmitted through the CPU port (0) into the switch partition, 53 * where forwarding rules are applied. 54 */ 55 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 56 57 /* tx_hdr_fid 58 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 59 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 60 * Valid for data packets only. 61 */ 62 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16); 63 64 /* tx_hdr_type 65 * 0 - Data packets 66 * 6 - Control packets 67 */ 68 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 69 70 #define MLXSW_TXHDR_LEN 0x10 71 #define MLXSW_TXHDR_VERSION_0 0 72 #define MLXSW_TXHDR_VERSION_1 1 73 74 enum { 75 MLXSW_TXHDR_ETH_CTL, 76 MLXSW_TXHDR_ETH_DATA, 77 }; 78 79 #define MLXSW_TXHDR_PROTO_ETH 1 80 81 enum { 82 MLXSW_TXHDR_ETCLASS_0, 83 MLXSW_TXHDR_ETCLASS_1, 84 MLXSW_TXHDR_ETCLASS_2, 85 MLXSW_TXHDR_ETCLASS_3, 86 MLXSW_TXHDR_ETCLASS_4, 87 MLXSW_TXHDR_ETCLASS_5, 88 MLXSW_TXHDR_ETCLASS_6, 89 MLXSW_TXHDR_ETCLASS_7, 90 }; 91 92 enum { 93 MLXSW_TXHDR_RDQ_OTHER, 94 MLXSW_TXHDR_RDQ_EMAD = 0x1f, 95 }; 96 97 #define MLXSW_TXHDR_CTCLASS3 0 98 #define MLXSW_TXHDR_CPU_SIG 0 99 #define MLXSW_TXHDR_SIG 0xE0E0 100 #define MLXSW_TXHDR_STCLASS_NONE 0 101 102 enum { 103 MLXSW_TXHDR_NOT_EMAD, 104 MLXSW_TXHDR_EMAD, 105 }; 106 107 enum { 108 MLXSW_TXHDR_TYPE_DATA, 109 MLXSW_TXHDR_TYPE_CONTROL = 6, 110 }; 111 112 #endif 113