1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <[email protected]>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 if (WARN_ON(!dev->caps.hca[cap_type]))
372 /* this cap_type must be added to mlx5_hca_caps_alloc() */
373 return -EINVAL;
374
375 memset(in, 0, sizeof(in));
376 out = kzalloc(out_sz, GFP_KERNEL);
377 if (!out)
378 return -ENOMEM;
379
380 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
381 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
382 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
383 if (err) {
384 mlx5_core_warn(dev,
385 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
386 cap_type, cap_mode, err);
387 goto query_ex;
388 }
389
390 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
391
392 switch (cap_mode) {
393 case HCA_CAP_OPMOD_GET_MAX:
394 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 case HCA_CAP_OPMOD_GET_CUR:
398 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
399 MLX5_UN_SZ_BYTES(hca_cap_union));
400 break;
401 default:
402 mlx5_core_warn(dev,
403 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
404 cap_type, cap_mode);
405 err = -EINVAL;
406 break;
407 }
408 query_ex:
409 kfree(out);
410 return err;
411 }
412
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)413 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
414 {
415 int ret;
416
417 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
418 if (ret)
419 return ret;
420 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
421 }
422
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)423 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
424 {
425 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
426 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
427 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
428 }
429
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)430 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
431 {
432 void *set_hca_cap;
433 int req_endianness;
434 int err;
435
436 if (!MLX5_CAP_GEN(dev, atomic))
437 return 0;
438
439 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
440 if (err)
441 return err;
442
443 req_endianness =
444 MLX5_CAP_ATOMIC(dev,
445 supported_atomic_req_8B_endianness_mode_1);
446
447 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
448 return 0;
449
450 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
451
452 /* Set requestor to host endianness */
453 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
454 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
455
456 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
457 }
458
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)459 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
460 {
461 bool do_set = false, mem_page_fault = false;
462 void *set_hca_cap;
463 int err;
464
465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
466 !MLX5_CAP_GEN(dev, pg))
467 return 0;
468
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
470 if (err)
471 return err;
472
473 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
474 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
475 MLX5_ST_SZ_BYTES(odp_cap));
476
477 /* For best performance, enable memory scheme ODP only when
478 * it has page prefetch enabled.
479 */
480 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) &&
481 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) {
482 mem_page_fault = true;
483 do_set = true;
484 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
485 goto set;
486 }
487
488 #define ODP_CAP_SET_MAX(dev, field) \
489 do { \
490 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
491 if (_res) { \
492 do_set = true; \
493 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
494 } \
495 } while (0)
496
497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive);
498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive);
499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive);
500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send);
501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive);
502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write);
503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read);
504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic);
505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive);
506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send);
507 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive);
508 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write);
509 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read);
510 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic);
511
512 set:
513 if (do_set)
514 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
515
516 mlx5_core_dbg(dev, "Using ODP %s scheme\n",
517 mem_page_fault ? "memory" : "transport");
518 return err;
519 }
520
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)521 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
522 {
523 struct devlink *devlink = priv_to_devlink(dev);
524 union devlink_param_value val;
525 int err;
526
527 err = devl_param_driverinit_value_get(devlink,
528 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
529 &val);
530 if (!err)
531 return val.vu32;
532 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
533 return err;
534 }
535
mlx5_is_roce_on(struct mlx5_core_dev * dev)536 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
537 {
538 struct devlink *devlink = priv_to_devlink(dev);
539 union devlink_param_value val;
540 int err;
541
542 err = devl_param_driverinit_value_get(devlink,
543 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
544 &val);
545
546 if (!err)
547 return val.vbool;
548
549 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
550 return MLX5_CAP_GEN(dev, roce);
551 }
552 EXPORT_SYMBOL(mlx5_is_roce_on);
553
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)554 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
555 {
556 void *set_hca_cap;
557 int err;
558
559 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
560 return 0;
561
562 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
563 if (err)
564 return err;
565
566 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
567 !(dev->priv.sw_vhca_id > 0))
568 return 0;
569
570 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
571 capability);
572 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
573 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
574 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
575
576 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
577 }
578
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)579 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
580 {
581 struct mlx5_profile *prof = &dev->profile;
582 void *set_hca_cap;
583 int max_uc_list;
584 int err;
585
586 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
587 if (err)
588 return err;
589
590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
591 capability);
592 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
593 MLX5_ST_SZ_BYTES(cmd_hca_cap));
594
595 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
596 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
597 128);
598 /* we limit the size of the pkey table to 128 entries for now */
599 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
600 to_fw_pkey_sz(dev, 128));
601
602 /* Check log_max_qp from HCA caps to set in current profile */
603 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
604 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
605 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
606 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
607 prof->log_max_qp,
608 MLX5_CAP_GEN_MAX(dev, log_max_qp));
609 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
610 }
611 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
612 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
613 prof->log_max_qp);
614
615 /* disable cmdif checksum */
616 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
617
618 /* Enable 4K UAR only when HCA supports it and page size is bigger
619 * than 4K.
620 */
621 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
622 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
623
624 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
625
626 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
627 MLX5_SET(cmd_hca_cap,
628 set_hca_cap,
629 cache_line_128byte,
630 cache_line_size() >= 128 ? 1 : 0);
631
632 if (MLX5_CAP_GEN_MAX(dev, dct))
633 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
634
635 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
636 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
637 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
638 MLX5_SET(cmd_hca_cap, set_hca_cap,
639 pci_sync_for_fw_update_with_driver_unload, 1);
640 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
641 MLX5_SET(cmd_hca_cap, set_hca_cap,
642 pcie_reset_using_hotreset_method, 1);
643
644 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
645 MLX5_SET(cmd_hca_cap,
646 set_hca_cap,
647 num_vhca_ports,
648 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
649
650 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
651 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
652
653 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
654 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
655
656 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
657
658 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
659 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
660 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
661
662 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
663 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
664 mlx5_is_roce_on(dev));
665
666 max_uc_list = max_uc_list_get_devlink_param(dev);
667 if (max_uc_list > 0)
668 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
669 ilog2(max_uc_list));
670
671 /* enable absolute native port num */
672 if (MLX5_CAP_GEN_MAX(dev, abs_native_port_num))
673 MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1);
674
675 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
676 }
677
678 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
679 * boot process.
680 * In case RoCE cap is writable in FW and user/devlink requested to change the
681 * cap, we are yet to query the final state of the above cap.
682 * Hence, the need for this function.
683 *
684 * Returns
685 * True:
686 * 1) RoCE cap is read only in FW and already disabled
687 * OR:
688 * 2) RoCE cap is writable in FW and user/devlink requested it off.
689 *
690 * In any other case, return False.
691 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)692 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
693 {
694 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
695 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
696 }
697
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)698 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
699 {
700 void *set_hca_cap;
701 int err;
702
703 if (is_roce_fw_disabled(dev))
704 return 0;
705
706 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
707 if (err)
708 return err;
709
710 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
711 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
712 return 0;
713
714 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
715 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
716 MLX5_ST_SZ_BYTES(roce_cap));
717 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
718
719 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
720 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
721
722 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
723 return err;
724 }
725
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)726 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
727 void *set_ctx)
728 {
729 void *set_hca_cap;
730 int err;
731
732 if (!MLX5_CAP_GEN(dev, port_selection_cap))
733 return 0;
734
735 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
736 if (err)
737 return err;
738
739 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
740 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
741 return 0;
742
743 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
744 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
745 MLX5_ST_SZ_BYTES(port_selection_cap));
746 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
747
748 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
749
750 return err;
751 }
752
set_hca_cap(struct mlx5_core_dev * dev)753 static int set_hca_cap(struct mlx5_core_dev *dev)
754 {
755 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
756 void *set_ctx;
757 int err;
758
759 set_ctx = kzalloc(set_sz, GFP_KERNEL);
760 if (!set_ctx)
761 return -ENOMEM;
762
763 err = handle_hca_cap(dev, set_ctx);
764 if (err) {
765 mlx5_core_err(dev, "handle_hca_cap failed\n");
766 goto out;
767 }
768
769 memset(set_ctx, 0, set_sz);
770 err = handle_hca_cap_atomic(dev, set_ctx);
771 if (err) {
772 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
773 goto out;
774 }
775
776 memset(set_ctx, 0, set_sz);
777 err = handle_hca_cap_odp(dev, set_ctx);
778 if (err) {
779 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
780 goto out;
781 }
782
783 memset(set_ctx, 0, set_sz);
784 err = handle_hca_cap_roce(dev, set_ctx);
785 if (err) {
786 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
787 goto out;
788 }
789
790 memset(set_ctx, 0, set_sz);
791 err = handle_hca_cap_2(dev, set_ctx);
792 if (err) {
793 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
794 goto out;
795 }
796
797 memset(set_ctx, 0, set_sz);
798 err = handle_hca_cap_port_selection(dev, set_ctx);
799 if (err) {
800 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
801 goto out;
802 }
803
804 out:
805 kfree(set_ctx);
806 return err;
807 }
808
set_hca_ctrl(struct mlx5_core_dev * dev)809 static int set_hca_ctrl(struct mlx5_core_dev *dev)
810 {
811 struct mlx5_reg_host_endianness he_in;
812 struct mlx5_reg_host_endianness he_out;
813 int err;
814
815 if (!mlx5_core_is_pf(dev))
816 return 0;
817
818 memset(&he_in, 0, sizeof(he_in));
819 he_in.he = MLX5_SET_HOST_ENDIANNESS;
820 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
821 &he_out, sizeof(he_out),
822 MLX5_REG_HOST_ENDIANNESS, 0, 1);
823 return err;
824 }
825
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)826 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
827 {
828 int ret = 0;
829
830 /* Disable local_lb by default */
831 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
832 ret = mlx5_nic_vport_update_local_lb(dev, false);
833
834 return ret;
835 }
836
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)837 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
838 {
839 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
840
841 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
842 MLX5_SET(enable_hca_in, in, function_id, func_id);
843 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
844 dev->caps.embedded_cpu);
845 return mlx5_cmd_exec_in(dev, enable_hca, in);
846 }
847
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)848 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
849 {
850 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
851
852 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
853 MLX5_SET(disable_hca_in, in, function_id, func_id);
854 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
855 dev->caps.embedded_cpu);
856 return mlx5_cmd_exec_in(dev, disable_hca, in);
857 }
858
mlx5_core_set_issi(struct mlx5_core_dev * dev)859 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
860 {
861 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
862 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
863 u32 sup_issi;
864 int err;
865
866 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
867 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
868 if (err) {
869 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
870 u8 status = MLX5_GET(query_issi_out, query_out, status);
871
872 if (!status || syndrome == MLX5_DRIVER_SYND) {
873 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
874 err, status, syndrome);
875 return err;
876 }
877
878 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
879 dev->issi = 0;
880 return 0;
881 }
882
883 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
884
885 if (sup_issi & (1 << 1)) {
886 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
887
888 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
889 MLX5_SET(set_issi_in, set_in, current_issi, 1);
890 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
891 if (err) {
892 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
893 err);
894 return err;
895 }
896
897 dev->issi = 1;
898
899 return 0;
900 } else if (sup_issi & (1 << 0) || !sup_issi) {
901 return 0;
902 }
903
904 return -EOPNOTSUPP;
905 }
906
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)907 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
908 const struct pci_device_id *id)
909 {
910 int err = 0;
911
912 mutex_init(&dev->pci_status_mutex);
913 pci_set_drvdata(dev->pdev, dev);
914
915 dev->bar_addr = pci_resource_start(pdev, 0);
916
917 err = mlx5_pci_enable_device(dev);
918 if (err) {
919 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
920 return err;
921 }
922
923 err = request_bar(pdev);
924 if (err) {
925 mlx5_core_err(dev, "error requesting BARs, aborting\n");
926 goto err_disable;
927 }
928
929 pci_set_master(pdev);
930
931 err = set_dma_caps(pdev);
932 if (err) {
933 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
934 goto err_clr_master;
935 }
936
937 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
938 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
939 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
940 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
941
942 dev->iseg_base = dev->bar_addr;
943 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
944 if (!dev->iseg) {
945 err = -ENOMEM;
946 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
947 goto err_clr_master;
948 }
949
950 mlx5_pci_vsc_init(dev);
951
952 pci_enable_ptm(pdev, NULL);
953
954 return 0;
955
956 err_clr_master:
957 release_bar(dev->pdev);
958 err_disable:
959 mlx5_pci_disable_device(dev);
960 return err;
961 }
962
mlx5_pci_close(struct mlx5_core_dev * dev)963 static void mlx5_pci_close(struct mlx5_core_dev *dev)
964 {
965 /* health work might still be active, and it needs pci bar in
966 * order to know the NIC state. Therefore, drain the health WQ
967 * before removing the pci bars
968 */
969 mlx5_drain_health_wq(dev);
970 pci_disable_ptm(dev->pdev);
971 iounmap(dev->iseg);
972 release_bar(dev->pdev);
973 mlx5_pci_disable_device(dev);
974 }
975
mlx5_register_hca_devcom_comp(struct mlx5_core_dev * dev)976 static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev)
977 {
978 /* This component is use to sync adding core_dev to lag_dev and to sync
979 * changes of mlx5_adev_devices between LAG layer and other layers.
980 */
981 if (!mlx5_lag_is_supported(dev))
982 return;
983
984 dev->priv.hca_devcom_comp =
985 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS,
986 mlx5_query_nic_system_image_guid(dev),
987 NULL, dev);
988 if (IS_ERR(dev->priv.hca_devcom_comp))
989 mlx5_core_err(dev, "Failed to register devcom HCA component\n");
990 }
991
mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev * dev)992 static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev)
993 {
994 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp);
995 }
996
mlx5_init_once(struct mlx5_core_dev * dev)997 static int mlx5_init_once(struct mlx5_core_dev *dev)
998 {
999 int err;
1000
1001 dev->priv.devc = mlx5_devcom_register_device(dev);
1002 if (IS_ERR(dev->priv.devc))
1003 mlx5_core_warn(dev, "failed to register devcom device %ld\n",
1004 PTR_ERR(dev->priv.devc));
1005 mlx5_register_hca_devcom_comp(dev);
1006
1007 err = mlx5_query_board_id(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "query board id failed\n");
1010 goto err_devcom;
1011 }
1012
1013 err = mlx5_irq_table_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to initialize irq table\n");
1016 goto err_devcom;
1017 }
1018
1019 err = mlx5_eq_table_init(dev);
1020 if (err) {
1021 mlx5_core_err(dev, "failed to initialize eq\n");
1022 goto err_irq_cleanup;
1023 }
1024
1025 err = mlx5_events_init(dev);
1026 if (err) {
1027 mlx5_core_err(dev, "failed to initialize events\n");
1028 goto err_eq_cleanup;
1029 }
1030
1031 err = mlx5_fw_reset_init(dev);
1032 if (err) {
1033 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1034 goto err_events_cleanup;
1035 }
1036
1037 mlx5_cq_debugfs_init(dev);
1038
1039 mlx5_init_reserved_gids(dev);
1040
1041 mlx5_init_clock(dev);
1042
1043 dev->vxlan = mlx5_vxlan_create(dev);
1044 dev->geneve = mlx5_geneve_create(dev);
1045
1046 err = mlx5_init_rl_table(dev);
1047 if (err) {
1048 mlx5_core_err(dev, "Failed to init rate limiting\n");
1049 goto err_tables_cleanup;
1050 }
1051
1052 err = mlx5_mpfs_init(dev);
1053 if (err) {
1054 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1055 goto err_rl_cleanup;
1056 }
1057
1058 err = mlx5_sriov_init(dev);
1059 if (err) {
1060 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1061 goto err_mpfs_cleanup;
1062 }
1063
1064 err = mlx5_eswitch_init(dev);
1065 if (err) {
1066 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1067 goto err_sriov_cleanup;
1068 }
1069
1070 err = mlx5_fpga_init(dev);
1071 if (err) {
1072 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1073 goto err_eswitch_cleanup;
1074 }
1075
1076 err = mlx5_vhca_event_init(dev);
1077 if (err) {
1078 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1079 goto err_fpga_cleanup;
1080 }
1081
1082 err = mlx5_sf_hw_table_init(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1085 goto err_sf_hw_table_cleanup;
1086 }
1087
1088 err = mlx5_sf_table_init(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1091 goto err_sf_table_cleanup;
1092 }
1093
1094 err = mlx5_fs_core_alloc(dev);
1095 if (err) {
1096 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1097 goto err_fs;
1098 }
1099
1100 dev->dm = mlx5_dm_create(dev);
1101 if (IS_ERR(dev->dm))
1102 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
1103
1104 dev->tracer = mlx5_fw_tracer_create(dev);
1105 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1106 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1107
1108 return 0;
1109
1110 err_fs:
1111 mlx5_sf_table_cleanup(dev);
1112 err_sf_table_cleanup:
1113 mlx5_sf_hw_table_cleanup(dev);
1114 err_sf_hw_table_cleanup:
1115 mlx5_vhca_event_cleanup(dev);
1116 err_fpga_cleanup:
1117 mlx5_fpga_cleanup(dev);
1118 err_eswitch_cleanup:
1119 mlx5_eswitch_cleanup(dev->priv.eswitch);
1120 err_sriov_cleanup:
1121 mlx5_sriov_cleanup(dev);
1122 err_mpfs_cleanup:
1123 mlx5_mpfs_cleanup(dev);
1124 err_rl_cleanup:
1125 mlx5_cleanup_rl_table(dev);
1126 err_tables_cleanup:
1127 mlx5_geneve_destroy(dev->geneve);
1128 mlx5_vxlan_destroy(dev->vxlan);
1129 mlx5_cleanup_clock(dev);
1130 mlx5_cleanup_reserved_gids(dev);
1131 mlx5_cq_debugfs_cleanup(dev);
1132 mlx5_fw_reset_cleanup(dev);
1133 err_events_cleanup:
1134 mlx5_events_cleanup(dev);
1135 err_eq_cleanup:
1136 mlx5_eq_table_cleanup(dev);
1137 err_irq_cleanup:
1138 mlx5_irq_table_cleanup(dev);
1139 err_devcom:
1140 mlx5_unregister_hca_devcom_comp(dev);
1141 mlx5_devcom_unregister_device(dev->priv.devc);
1142
1143 return err;
1144 }
1145
mlx5_cleanup_once(struct mlx5_core_dev * dev)1146 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1147 {
1148 mlx5_rsc_dump_destroy(dev);
1149 mlx5_hv_vhca_destroy(dev->hv_vhca);
1150 mlx5_fw_tracer_destroy(dev->tracer);
1151 mlx5_dm_cleanup(dev);
1152 mlx5_fs_core_free(dev);
1153 mlx5_sf_table_cleanup(dev);
1154 mlx5_sf_hw_table_cleanup(dev);
1155 mlx5_vhca_event_cleanup(dev);
1156 mlx5_fpga_cleanup(dev);
1157 mlx5_eswitch_cleanup(dev->priv.eswitch);
1158 mlx5_sriov_cleanup(dev);
1159 mlx5_mpfs_cleanup(dev);
1160 mlx5_cleanup_rl_table(dev);
1161 mlx5_geneve_destroy(dev->geneve);
1162 mlx5_vxlan_destroy(dev->vxlan);
1163 mlx5_cleanup_clock(dev);
1164 mlx5_cleanup_reserved_gids(dev);
1165 mlx5_cq_debugfs_cleanup(dev);
1166 mlx5_fw_reset_cleanup(dev);
1167 mlx5_events_cleanup(dev);
1168 mlx5_eq_table_cleanup(dev);
1169 mlx5_irq_table_cleanup(dev);
1170 mlx5_unregister_hca_devcom_comp(dev);
1171 mlx5_devcom_unregister_device(dev->priv.devc);
1172 }
1173
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1174 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1175 {
1176 int err;
1177
1178 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1179 fw_rev_min(dev), fw_rev_sub(dev));
1180
1181 /* Only PFs hold the relevant PCIe information for this query */
1182 if (mlx5_core_is_pf(dev))
1183 pcie_print_link_status(dev->pdev);
1184
1185 /* wait for firmware to accept initialization segments configurations
1186 */
1187 err = wait_fw_init(dev, timeout,
1188 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1189 "pre-initializing");
1190 if (err)
1191 return err;
1192
1193 err = mlx5_cmd_enable(dev);
1194 if (err) {
1195 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1196 return err;
1197 }
1198
1199 mlx5_tout_query_iseg(dev);
1200
1201 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1202 if (err)
1203 goto err_cmd_cleanup;
1204
1205 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1206 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1207
1208 err = mlx5_core_enable_hca(dev, 0);
1209 if (err) {
1210 mlx5_core_err(dev, "enable hca failed\n");
1211 goto err_cmd_cleanup;
1212 }
1213
1214 mlx5_start_health_poll(dev);
1215
1216 err = mlx5_core_set_issi(dev);
1217 if (err) {
1218 mlx5_core_err(dev, "failed to set issi\n");
1219 goto stop_health_poll;
1220 }
1221
1222 err = mlx5_satisfy_startup_pages(dev, 1);
1223 if (err) {
1224 mlx5_core_err(dev, "failed to allocate boot pages\n");
1225 goto stop_health_poll;
1226 }
1227
1228 err = mlx5_tout_query_dtor(dev);
1229 if (err) {
1230 mlx5_core_err(dev, "failed to read dtor\n");
1231 goto reclaim_boot_pages;
1232 }
1233
1234 return 0;
1235
1236 reclaim_boot_pages:
1237 mlx5_reclaim_startup_pages(dev);
1238 stop_health_poll:
1239 mlx5_stop_health_poll(dev, boot);
1240 mlx5_core_disable_hca(dev, 0);
1241 err_cmd_cleanup:
1242 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1243 mlx5_cmd_disable(dev);
1244
1245 return err;
1246 }
1247
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1248 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1249 {
1250 mlx5_reclaim_startup_pages(dev);
1251 mlx5_stop_health_poll(dev, boot);
1252 mlx5_core_disable_hca(dev, 0);
1253 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1254 mlx5_cmd_disable(dev);
1255 }
1256
mlx5_function_open(struct mlx5_core_dev * dev)1257 static int mlx5_function_open(struct mlx5_core_dev *dev)
1258 {
1259 int err;
1260
1261 err = set_hca_ctrl(dev);
1262 if (err) {
1263 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1264 return err;
1265 }
1266
1267 err = set_hca_cap(dev);
1268 if (err) {
1269 mlx5_core_err(dev, "set_hca_cap failed\n");
1270 return err;
1271 }
1272
1273 err = mlx5_satisfy_startup_pages(dev, 0);
1274 if (err) {
1275 mlx5_core_err(dev, "failed to allocate init pages\n");
1276 return err;
1277 }
1278
1279 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1280 if (err) {
1281 mlx5_core_err(dev, "init hca failed\n");
1282 return err;
1283 }
1284
1285 mlx5_set_driver_version(dev);
1286
1287 err = mlx5_query_hca_caps(dev);
1288 if (err) {
1289 mlx5_core_err(dev, "query hca failed\n");
1290 return err;
1291 }
1292 mlx5_start_health_fw_log_up(dev);
1293 return 0;
1294 }
1295
mlx5_function_close(struct mlx5_core_dev * dev)1296 static int mlx5_function_close(struct mlx5_core_dev *dev)
1297 {
1298 int err;
1299
1300 err = mlx5_cmd_teardown_hca(dev);
1301 if (err) {
1302 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1303 return err;
1304 }
1305
1306 return 0;
1307 }
1308
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1309 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1310 {
1311 int err;
1312
1313 err = mlx5_function_enable(dev, boot, timeout);
1314 if (err)
1315 return err;
1316
1317 err = mlx5_function_open(dev);
1318 if (err)
1319 mlx5_function_disable(dev, boot);
1320 return err;
1321 }
1322
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1323 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1324 {
1325 int err = mlx5_function_close(dev);
1326
1327 if (!err)
1328 mlx5_function_disable(dev, boot);
1329 else
1330 mlx5_stop_health_poll(dev, boot);
1331
1332 return err;
1333 }
1334
mlx5_load(struct mlx5_core_dev * dev)1335 static int mlx5_load(struct mlx5_core_dev *dev)
1336 {
1337 int err;
1338
1339 dev->priv.uar = mlx5_get_uars_page(dev);
1340 if (IS_ERR(dev->priv.uar)) {
1341 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1342 err = PTR_ERR(dev->priv.uar);
1343 return err;
1344 }
1345
1346 mlx5_events_start(dev);
1347 mlx5_pagealloc_start(dev);
1348
1349 err = mlx5_irq_table_create(dev);
1350 if (err) {
1351 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1352 goto err_irq_table;
1353 }
1354
1355 err = mlx5_eq_table_create(dev);
1356 if (err) {
1357 mlx5_core_err(dev, "Failed to create EQs\n");
1358 goto err_eq_table;
1359 }
1360
1361 err = mlx5_fw_tracer_init(dev->tracer);
1362 if (err) {
1363 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1364 mlx5_fw_tracer_destroy(dev->tracer);
1365 dev->tracer = NULL;
1366 }
1367
1368 mlx5_fw_reset_events_start(dev);
1369 mlx5_hv_vhca_init(dev->hv_vhca);
1370
1371 err = mlx5_rsc_dump_init(dev);
1372 if (err) {
1373 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1374 mlx5_rsc_dump_destroy(dev);
1375 dev->rsc_dump = NULL;
1376 }
1377
1378 err = mlx5_fpga_device_start(dev);
1379 if (err) {
1380 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1381 goto err_fpga_start;
1382 }
1383
1384 err = mlx5_fs_core_init(dev);
1385 if (err) {
1386 mlx5_core_err(dev, "Failed to init flow steering\n");
1387 goto err_fs;
1388 }
1389
1390 err = mlx5_core_set_hca_defaults(dev);
1391 if (err) {
1392 mlx5_core_err(dev, "Failed to set hca defaults\n");
1393 goto err_set_hca;
1394 }
1395
1396 mlx5_vhca_event_start(dev);
1397
1398 err = mlx5_sf_hw_table_create(dev);
1399 if (err) {
1400 mlx5_core_err(dev, "sf table create failed %d\n", err);
1401 goto err_vhca;
1402 }
1403
1404 err = mlx5_ec_init(dev);
1405 if (err) {
1406 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1407 goto err_ec;
1408 }
1409
1410 mlx5_lag_add_mdev(dev);
1411 err = mlx5_sriov_attach(dev);
1412 if (err) {
1413 mlx5_core_err(dev, "sriov init failed %d\n", err);
1414 goto err_sriov;
1415 }
1416
1417 mlx5_sf_dev_table_create(dev);
1418
1419 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1420 if (err)
1421 goto err_traps_reg;
1422
1423 return 0;
1424
1425 err_traps_reg:
1426 mlx5_sf_dev_table_destroy(dev);
1427 mlx5_sriov_detach(dev);
1428 err_sriov:
1429 mlx5_lag_remove_mdev(dev);
1430 mlx5_ec_cleanup(dev);
1431 err_ec:
1432 mlx5_sf_hw_table_destroy(dev);
1433 err_vhca:
1434 mlx5_vhca_event_stop(dev);
1435 err_set_hca:
1436 mlx5_fs_core_cleanup(dev);
1437 err_fs:
1438 mlx5_fpga_device_stop(dev);
1439 err_fpga_start:
1440 mlx5_rsc_dump_cleanup(dev);
1441 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1442 mlx5_fw_reset_events_stop(dev);
1443 mlx5_fw_tracer_cleanup(dev->tracer);
1444 mlx5_eq_table_destroy(dev);
1445 err_eq_table:
1446 mlx5_irq_table_destroy(dev);
1447 err_irq_table:
1448 mlx5_pagealloc_stop(dev);
1449 mlx5_events_stop(dev);
1450 mlx5_put_uars_page(dev, dev->priv.uar);
1451 return err;
1452 }
1453
mlx5_unload(struct mlx5_core_dev * dev)1454 static void mlx5_unload(struct mlx5_core_dev *dev)
1455 {
1456 mlx5_eswitch_disable(dev->priv.eswitch);
1457 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1458 mlx5_sf_dev_table_destroy(dev);
1459 mlx5_sriov_detach(dev);
1460 mlx5_lag_remove_mdev(dev);
1461 mlx5_ec_cleanup(dev);
1462 mlx5_sf_hw_table_destroy(dev);
1463 mlx5_vhca_event_stop(dev);
1464 mlx5_fs_core_cleanup(dev);
1465 mlx5_fpga_device_stop(dev);
1466 mlx5_rsc_dump_cleanup(dev);
1467 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1468 mlx5_fw_reset_events_stop(dev);
1469 mlx5_fw_tracer_cleanup(dev->tracer);
1470 mlx5_eq_table_destroy(dev);
1471 mlx5_irq_table_destroy(dev);
1472 mlx5_pagealloc_stop(dev);
1473 mlx5_events_stop(dev);
1474 mlx5_put_uars_page(dev, dev->priv.uar);
1475 }
1476
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1477 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1478 {
1479 bool light_probe = mlx5_dev_is_lightweight(dev);
1480 int err = 0;
1481
1482 mutex_lock(&dev->intf_state_mutex);
1483 dev->state = MLX5_DEVICE_STATE_UP;
1484
1485 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1486 if (err)
1487 goto err_function;
1488
1489 err = mlx5_init_once(dev);
1490 if (err) {
1491 mlx5_core_err(dev, "sw objs init failed\n");
1492 goto function_teardown;
1493 }
1494
1495 /* In case of light_probe, mlx5_devlink is already registered.
1496 * Hence, don't register devlink again.
1497 */
1498 if (!light_probe) {
1499 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1500 if (err)
1501 goto err_devlink_params_reg;
1502 }
1503
1504 err = mlx5_load(dev);
1505 if (err)
1506 goto err_load;
1507
1508 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1509
1510 err = mlx5_register_device(dev);
1511 if (err)
1512 goto err_register;
1513
1514 err = mlx5_crdump_enable(dev);
1515 if (err)
1516 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1517
1518 err = mlx5_hwmon_dev_register(dev);
1519 if (err)
1520 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1521
1522 mutex_unlock(&dev->intf_state_mutex);
1523 return 0;
1524
1525 err_register:
1526 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1527 mlx5_unload(dev);
1528 err_load:
1529 if (!light_probe)
1530 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1531 err_devlink_params_reg:
1532 mlx5_cleanup_once(dev);
1533 function_teardown:
1534 mlx5_function_teardown(dev, true);
1535 err_function:
1536 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1537 mutex_unlock(&dev->intf_state_mutex);
1538 return err;
1539 }
1540
mlx5_init_one(struct mlx5_core_dev * dev)1541 int mlx5_init_one(struct mlx5_core_dev *dev)
1542 {
1543 struct devlink *devlink = priv_to_devlink(dev);
1544 int err;
1545
1546 devl_lock(devlink);
1547 devl_register(devlink);
1548 err = mlx5_init_one_devl_locked(dev);
1549 if (err)
1550 devl_unregister(devlink);
1551 devl_unlock(devlink);
1552 return err;
1553 }
1554
mlx5_uninit_one(struct mlx5_core_dev * dev)1555 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1556 {
1557 struct devlink *devlink = priv_to_devlink(dev);
1558
1559 devl_lock(devlink);
1560 mutex_lock(&dev->intf_state_mutex);
1561
1562 mlx5_hwmon_dev_unregister(dev);
1563 mlx5_crdump_disable(dev);
1564 mlx5_unregister_device(dev);
1565
1566 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1567 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1568 __func__);
1569 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1570 mlx5_cleanup_once(dev);
1571 goto out;
1572 }
1573
1574 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1575 mlx5_unload(dev);
1576 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1577 mlx5_cleanup_once(dev);
1578 mlx5_function_teardown(dev, true);
1579 out:
1580 mutex_unlock(&dev->intf_state_mutex);
1581 devl_unregister(devlink);
1582 devl_unlock(devlink);
1583 }
1584
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1585 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1586 {
1587 int err = 0;
1588 u64 timeout;
1589
1590 devl_assert_locked(priv_to_devlink(dev));
1591 mutex_lock(&dev->intf_state_mutex);
1592 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1593 mlx5_core_warn(dev, "interface is up, NOP\n");
1594 goto out;
1595 }
1596 /* remove any previous indication of internal error */
1597 dev->state = MLX5_DEVICE_STATE_UP;
1598
1599 if (recovery)
1600 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1601 else
1602 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1603 err = mlx5_function_setup(dev, false, timeout);
1604 if (err)
1605 goto err_function;
1606
1607 err = mlx5_load(dev);
1608 if (err)
1609 goto err_load;
1610
1611 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1612
1613 err = mlx5_attach_device(dev);
1614 if (err)
1615 goto err_attach;
1616
1617 mutex_unlock(&dev->intf_state_mutex);
1618 return 0;
1619
1620 err_attach:
1621 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1622 mlx5_unload(dev);
1623 err_load:
1624 mlx5_function_teardown(dev, false);
1625 err_function:
1626 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1627 out:
1628 mutex_unlock(&dev->intf_state_mutex);
1629 return err;
1630 }
1631
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1632 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1633 {
1634 struct devlink *devlink = priv_to_devlink(dev);
1635 int ret;
1636
1637 devl_lock(devlink);
1638 ret = mlx5_load_one_devl_locked(dev, recovery);
1639 devl_unlock(devlink);
1640 return ret;
1641 }
1642
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1643 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1644 {
1645 devl_assert_locked(priv_to_devlink(dev));
1646 mutex_lock(&dev->intf_state_mutex);
1647
1648 mlx5_detach_device(dev, suspend);
1649
1650 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1651 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1652 __func__);
1653 goto out;
1654 }
1655
1656 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1657 mlx5_unload(dev);
1658 mlx5_function_teardown(dev, false);
1659 out:
1660 mutex_unlock(&dev->intf_state_mutex);
1661 }
1662
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1663 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1664 {
1665 struct devlink *devlink = priv_to_devlink(dev);
1666
1667 devl_lock(devlink);
1668 mlx5_unload_one_devl_locked(dev, suspend);
1669 devl_unlock(devlink);
1670 }
1671
1672 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1673 * A full query of hca_caps will be done when the device will reload.
1674 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1675 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1676 {
1677 int err;
1678
1679 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1680 if (err)
1681 return err;
1682
1683 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1684 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1685 HCA_CAP_OPMOD_GET_CUR);
1686 if (err)
1687 return err;
1688 }
1689
1690 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1691 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1692 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1693 HCA_CAP_OPMOD_GET_CUR);
1694 if (err)
1695 return err;
1696 }
1697
1698 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1699 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1700 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1701 HCA_CAP_OPMOD_GET_CUR);
1702 if (err)
1703 return err;
1704 }
1705
1706 return 0;
1707 }
1708
mlx5_init_one_light(struct mlx5_core_dev * dev)1709 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1710 {
1711 struct devlink *devlink = priv_to_devlink(dev);
1712 int err;
1713
1714 devl_lock(devlink);
1715 devl_register(devlink);
1716 dev->state = MLX5_DEVICE_STATE_UP;
1717 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1718 if (err) {
1719 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1720 goto out;
1721 }
1722
1723 err = mlx5_query_hca_caps_light(dev);
1724 if (err) {
1725 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1726 goto query_hca_caps_err;
1727 }
1728
1729 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1730 if (err) {
1731 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1732 goto query_hca_caps_err;
1733 }
1734
1735 devl_unlock(devlink);
1736 return 0;
1737
1738 query_hca_caps_err:
1739 mlx5_function_disable(dev, true);
1740 out:
1741 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1742 devl_unregister(devlink);
1743 devl_unlock(devlink);
1744 return err;
1745 }
1746
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1747 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1748 {
1749 struct devlink *devlink = priv_to_devlink(dev);
1750
1751 devl_lock(devlink);
1752 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1753 devl_unregister(devlink);
1754 devl_unlock(devlink);
1755 if (dev->state != MLX5_DEVICE_STATE_UP)
1756 return;
1757 mlx5_function_disable(dev, true);
1758 }
1759
1760 /* xxx_light() function are used in order to configure the device without full
1761 * init (light init). e.g.: There isn't a point in reload a device to light state.
1762 * Hence, mlx5_load_one_light() isn't needed.
1763 */
1764
mlx5_unload_one_light(struct mlx5_core_dev * dev)1765 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1766 {
1767 if (dev->state != MLX5_DEVICE_STATE_UP)
1768 return;
1769 mlx5_function_disable(dev, false);
1770 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1771 }
1772
1773 static const int types[] = {
1774 MLX5_CAP_GENERAL,
1775 MLX5_CAP_GENERAL_2,
1776 MLX5_CAP_ETHERNET_OFFLOADS,
1777 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1778 MLX5_CAP_ODP,
1779 MLX5_CAP_ATOMIC,
1780 MLX5_CAP_ROCE,
1781 MLX5_CAP_IPOIB_OFFLOADS,
1782 MLX5_CAP_FLOW_TABLE,
1783 MLX5_CAP_ESWITCH_FLOW_TABLE,
1784 MLX5_CAP_ESWITCH,
1785 MLX5_CAP_QOS,
1786 MLX5_CAP_DEBUG,
1787 MLX5_CAP_DEV_MEM,
1788 MLX5_CAP_DEV_EVENT,
1789 MLX5_CAP_TLS,
1790 MLX5_CAP_VDPA_EMULATION,
1791 MLX5_CAP_IPSEC,
1792 MLX5_CAP_PORT_SELECTION,
1793 MLX5_CAP_MACSEC,
1794 MLX5_CAP_ADV_VIRTUALIZATION,
1795 MLX5_CAP_CRYPTO,
1796 MLX5_CAP_SHAMPO,
1797 };
1798
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1799 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1800 {
1801 int type;
1802 int i;
1803
1804 for (i = 0; i < ARRAY_SIZE(types); i++) {
1805 type = types[i];
1806 kfree(dev->caps.hca[type]);
1807 }
1808 }
1809
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1810 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1811 {
1812 struct mlx5_hca_cap *cap;
1813 int type;
1814 int i;
1815
1816 for (i = 0; i < ARRAY_SIZE(types); i++) {
1817 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1818 if (!cap)
1819 goto err;
1820 type = types[i];
1821 dev->caps.hca[type] = cap;
1822 }
1823
1824 return 0;
1825
1826 err:
1827 mlx5_hca_caps_free(dev);
1828 return -ENOMEM;
1829 }
1830
vhca_id_show(struct seq_file * file,void * priv)1831 static int vhca_id_show(struct seq_file *file, void *priv)
1832 {
1833 struct mlx5_core_dev *dev = file->private;
1834
1835 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1836 return 0;
1837 }
1838
1839 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1840
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1841 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1842 {
1843 struct mlx5_priv *priv = &dev->priv;
1844 int err;
1845
1846 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1847 lockdep_register_key(&dev->lock_key);
1848 mutex_init(&dev->intf_state_mutex);
1849 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1850 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1851 mutex_init(&dev->wc_state_lock);
1852
1853 mutex_init(&priv->bfregs.reg_head.lock);
1854 mutex_init(&priv->bfregs.wc_head.lock);
1855 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1856 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1857
1858 mutex_init(&priv->alloc_mutex);
1859 mutex_init(&priv->pgdir_mutex);
1860 INIT_LIST_HEAD(&priv->pgdir_list);
1861
1862 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1863 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1864 mlx5_debugfs_root);
1865 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1866 INIT_LIST_HEAD(&priv->traps);
1867
1868 err = mlx5_cmd_init(dev);
1869 if (err) {
1870 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1871 goto err_cmd_init;
1872 }
1873
1874 err = mlx5_tout_init(dev);
1875 if (err) {
1876 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1877 goto err_timeout_init;
1878 }
1879
1880 err = mlx5_health_init(dev);
1881 if (err)
1882 goto err_health_init;
1883
1884 err = mlx5_pagealloc_init(dev);
1885 if (err)
1886 goto err_pagealloc_init;
1887
1888 err = mlx5_adev_init(dev);
1889 if (err)
1890 goto err_adev_init;
1891
1892 err = mlx5_hca_caps_alloc(dev);
1893 if (err)
1894 goto err_hca_caps;
1895
1896 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1897 * unique id per function which uses mlx5_core.
1898 * Those values are supplied to FW as part of the init HCA command to
1899 * be used by both driver and FW when it's applicable.
1900 */
1901 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1902 MAX_SW_VHCA_ID,
1903 GFP_KERNEL);
1904 if (dev->priv.sw_vhca_id < 0)
1905 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1906 dev->priv.sw_vhca_id);
1907
1908 return 0;
1909
1910 err_hca_caps:
1911 mlx5_adev_cleanup(dev);
1912 err_adev_init:
1913 mlx5_pagealloc_cleanup(dev);
1914 err_pagealloc_init:
1915 mlx5_health_cleanup(dev);
1916 err_health_init:
1917 mlx5_tout_cleanup(dev);
1918 err_timeout_init:
1919 mlx5_cmd_cleanup(dev);
1920 err_cmd_init:
1921 debugfs_remove(dev->priv.dbg.dbg_root);
1922 mutex_destroy(&priv->pgdir_mutex);
1923 mutex_destroy(&priv->alloc_mutex);
1924 mutex_destroy(&priv->bfregs.wc_head.lock);
1925 mutex_destroy(&priv->bfregs.reg_head.lock);
1926 mutex_destroy(&dev->intf_state_mutex);
1927 lockdep_unregister_key(&dev->lock_key);
1928 return err;
1929 }
1930
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1931 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1932 {
1933 struct mlx5_priv *priv = &dev->priv;
1934
1935 if (priv->sw_vhca_id > 0)
1936 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1937
1938 mlx5_hca_caps_free(dev);
1939 mlx5_adev_cleanup(dev);
1940 mlx5_pagealloc_cleanup(dev);
1941 mlx5_health_cleanup(dev);
1942 mlx5_tout_cleanup(dev);
1943 mlx5_cmd_cleanup(dev);
1944 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1945 mutex_destroy(&priv->pgdir_mutex);
1946 mutex_destroy(&priv->alloc_mutex);
1947 mutex_destroy(&priv->bfregs.wc_head.lock);
1948 mutex_destroy(&priv->bfregs.reg_head.lock);
1949 mutex_destroy(&dev->wc_state_lock);
1950 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1951 mutex_destroy(&dev->intf_state_mutex);
1952 lockdep_unregister_key(&dev->lock_key);
1953 }
1954
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1955 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1956 {
1957 struct mlx5_core_dev *dev;
1958 struct devlink *devlink;
1959 int err;
1960
1961 devlink = mlx5_devlink_alloc(&pdev->dev);
1962 if (!devlink) {
1963 dev_err(&pdev->dev, "devlink alloc failed\n");
1964 return -ENOMEM;
1965 }
1966
1967 dev = devlink_priv(devlink);
1968 dev->device = &pdev->dev;
1969 dev->pdev = pdev;
1970
1971 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1972 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1973
1974 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1975 if (dev->priv.adev_idx < 0) {
1976 err = dev->priv.adev_idx;
1977 goto adev_init_err;
1978 }
1979
1980 err = mlx5_mdev_init(dev, prof_sel);
1981 if (err)
1982 goto mdev_init_err;
1983
1984 err = mlx5_pci_init(dev, pdev, id);
1985 if (err) {
1986 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1987 err);
1988 goto pci_init_err;
1989 }
1990
1991 err = mlx5_init_one(dev);
1992 if (err) {
1993 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1994 err);
1995 goto err_init_one;
1996 }
1997
1998 pci_save_state(pdev);
1999 return 0;
2000
2001 err_init_one:
2002 mlx5_pci_close(dev);
2003 pci_init_err:
2004 mlx5_mdev_uninit(dev);
2005 mdev_init_err:
2006 mlx5_adev_idx_free(dev->priv.adev_idx);
2007 adev_init_err:
2008 mlx5_devlink_free(devlink);
2009
2010 return err;
2011 }
2012
remove_one(struct pci_dev * pdev)2013 static void remove_one(struct pci_dev *pdev)
2014 {
2015 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2016 struct devlink *devlink = priv_to_devlink(dev);
2017
2018 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2019 mlx5_drain_fw_reset(dev);
2020 mlx5_drain_health_wq(dev);
2021 mlx5_sriov_disable(pdev, false);
2022 mlx5_uninit_one(dev);
2023 mlx5_pci_close(dev);
2024 mlx5_mdev_uninit(dev);
2025 mlx5_adev_idx_free(dev->priv.adev_idx);
2026 mlx5_devlink_free(devlink);
2027 }
2028
2029 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2030 struct mlx5_core_dev *__dev = (dev); \
2031 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2032 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2033 __dev->pci_status, ##__VA_ARGS__); \
2034 })
2035
result2str(enum pci_ers_result result)2036 static const char *result2str(enum pci_ers_result result)
2037 {
2038 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2039 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2040 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2041 "unknown";
2042 }
2043
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2044 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2045 pci_channel_state_t state)
2046 {
2047 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2048 enum pci_ers_result res;
2049
2050 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2051
2052 mlx5_enter_error_state(dev, false);
2053 mlx5_error_sw_reset(dev);
2054 mlx5_unload_one(dev, false);
2055 mlx5_drain_health_wq(dev);
2056 mlx5_pci_disable_device(dev);
2057
2058 res = state == pci_channel_io_perm_failure ?
2059 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2060
2061 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2062 __func__, dev->state, dev->pci_status, res, result2str(res));
2063 return res;
2064 }
2065
2066 /* wait for the device to show vital signs by waiting
2067 * for the health counter to start counting.
2068 */
wait_vital(struct pci_dev * pdev)2069 static int wait_vital(struct pci_dev *pdev)
2070 {
2071 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2072 struct mlx5_core_health *health = &dev->priv.health;
2073 const int niter = 100;
2074 u32 last_count = 0;
2075 u32 count;
2076 int i;
2077
2078 for (i = 0; i < niter; i++) {
2079 count = ioread32be(health->health_counter);
2080 if (count && count != 0xffffffff) {
2081 if (last_count && last_count != count) {
2082 mlx5_core_info(dev,
2083 "wait vital counter value 0x%x after %d iterations\n",
2084 count, i);
2085 return 0;
2086 }
2087 last_count = count;
2088 }
2089 msleep(50);
2090 }
2091
2092 return -ETIMEDOUT;
2093 }
2094
mlx5_pci_slot_reset(struct pci_dev * pdev)2095 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2096 {
2097 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2098 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2099 int err;
2100
2101 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2102 __func__, dev->state, dev->pci_status);
2103
2104 err = mlx5_pci_enable_device(dev);
2105 if (err) {
2106 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2107 __func__, err);
2108 goto out;
2109 }
2110
2111 pci_set_master(pdev);
2112 pci_restore_state(pdev);
2113 pci_save_state(pdev);
2114
2115 err = wait_vital(pdev);
2116 if (err) {
2117 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2118 __func__, err);
2119 goto out;
2120 }
2121
2122 res = PCI_ERS_RESULT_RECOVERED;
2123 out:
2124 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2125 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2126 return res;
2127 }
2128
mlx5_pci_resume(struct pci_dev * pdev)2129 static void mlx5_pci_resume(struct pci_dev *pdev)
2130 {
2131 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2132 int err;
2133
2134 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2135
2136 err = mlx5_load_one(dev, false);
2137
2138 if (!err)
2139 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2140 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2141
2142 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2143 !err ? "recovered" : "Failed");
2144 }
2145
2146 static const struct pci_error_handlers mlx5_err_handler = {
2147 .error_detected = mlx5_pci_err_detected,
2148 .slot_reset = mlx5_pci_slot_reset,
2149 .resume = mlx5_pci_resume
2150 };
2151
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2152 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2153 {
2154 bool fast_teardown = false, force_teardown = false;
2155 int ret = 1;
2156
2157 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2158 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2159
2160 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2161 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2162
2163 if (!fast_teardown && !force_teardown)
2164 return -EOPNOTSUPP;
2165
2166 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2167 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2168 return -EAGAIN;
2169 }
2170
2171 /* Panic tear down fw command will stop the PCI bus communication
2172 * with the HCA, so the health poll is no longer needed.
2173 */
2174 mlx5_stop_health_poll(dev, false);
2175
2176 ret = mlx5_cmd_fast_teardown_hca(dev);
2177 if (!ret)
2178 goto succeed;
2179
2180 ret = mlx5_cmd_force_teardown_hca(dev);
2181 if (!ret)
2182 goto succeed;
2183
2184 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2185 mlx5_start_health_poll(dev);
2186 return ret;
2187
2188 succeed:
2189 mlx5_enter_error_state(dev, true);
2190
2191 /* Some platforms requiring freeing the IRQ's in the shutdown
2192 * flow. If they aren't freed they can't be allocated after
2193 * kexec. There is no need to cleanup the mlx5_core software
2194 * contexts.
2195 */
2196 mlx5_core_eq_free_irqs(dev);
2197
2198 return 0;
2199 }
2200
shutdown(struct pci_dev * pdev)2201 static void shutdown(struct pci_dev *pdev)
2202 {
2203 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2204 int err;
2205
2206 mlx5_core_info(dev, "Shutdown was called\n");
2207 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2208 mlx5_drain_health_wq(dev);
2209 err = mlx5_try_fast_unload(dev);
2210 if (err)
2211 mlx5_unload_one(dev, false);
2212 mlx5_pci_disable_device(dev);
2213 }
2214
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2215 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2216 {
2217 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2218
2219 mlx5_unload_one(dev, true);
2220
2221 return 0;
2222 }
2223
mlx5_resume(struct pci_dev * pdev)2224 static int mlx5_resume(struct pci_dev *pdev)
2225 {
2226 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2227
2228 return mlx5_load_one(dev, false);
2229 }
2230
2231 static const struct pci_device_id mlx5_core_pci_table[] = {
2232 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2233 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2234 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2235 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2236 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2237 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2238 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2239 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2240 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2241 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2242 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2243 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2244 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2245 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2246 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2247 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2248 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2249 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2250 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2251 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2252 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2253 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2254 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2255 { 0, }
2256 };
2257
2258 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2259
mlx5_disable_device(struct mlx5_core_dev * dev)2260 void mlx5_disable_device(struct mlx5_core_dev *dev)
2261 {
2262 mlx5_error_sw_reset(dev);
2263 mlx5_unload_one_devl_locked(dev, false);
2264 }
2265
mlx5_recover_device(struct mlx5_core_dev * dev)2266 int mlx5_recover_device(struct mlx5_core_dev *dev)
2267 {
2268 if (!mlx5_core_is_sf(dev)) {
2269 mlx5_pci_disable_device(dev);
2270 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2271 return -EIO;
2272 }
2273
2274 return mlx5_load_one_devl_locked(dev, true);
2275 }
2276
2277 static struct pci_driver mlx5_core_driver = {
2278 .name = KBUILD_MODNAME,
2279 .id_table = mlx5_core_pci_table,
2280 .probe = probe_one,
2281 .remove = remove_one,
2282 .suspend = mlx5_suspend,
2283 .resume = mlx5_resume,
2284 .shutdown = shutdown,
2285 .err_handler = &mlx5_err_handler,
2286 .sriov_configure = mlx5_core_sriov_configure,
2287 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2288 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2289 };
2290
2291 /**
2292 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2293 * mlx5_core is its driver.
2294 * @pdev: The associated PCI device.
2295 *
2296 * Upon return the interface state lock stay held to let caller uses it safely.
2297 * Caller must ensure to use the returned mlx5 device for a narrow window
2298 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2299 *
2300 * Return: Pointer to the associated mlx5_core_dev or NULL.
2301 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2302 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2303 {
2304 struct mlx5_core_dev *mdev;
2305
2306 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2307 if (IS_ERR(mdev))
2308 return NULL;
2309
2310 mutex_lock(&mdev->intf_state_mutex);
2311 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2312 mutex_unlock(&mdev->intf_state_mutex);
2313 return NULL;
2314 }
2315
2316 return mdev;
2317 }
2318 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2319
2320 /**
2321 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2322 * @mdev: The mlx5 core device.
2323 *
2324 * Upon return the interface state lock is unlocked and caller should not
2325 * access the mdev any more.
2326 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2327 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2328 {
2329 mutex_unlock(&mdev->intf_state_mutex);
2330 }
2331 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2332
mlx5_core_verify_params(void)2333 static void mlx5_core_verify_params(void)
2334 {
2335 if (prof_sel >= ARRAY_SIZE(profile)) {
2336 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2337 prof_sel,
2338 ARRAY_SIZE(profile) - 1,
2339 MLX5_DEFAULT_PROF);
2340 prof_sel = MLX5_DEFAULT_PROF;
2341 }
2342 }
2343
mlx5_init(void)2344 static int __init mlx5_init(void)
2345 {
2346 int err;
2347
2348 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2349 "mlx5_core name not in sync with kernel module name");
2350
2351 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2352
2353 mlx5_core_verify_params();
2354 mlx5_register_debugfs();
2355
2356 err = mlx5e_init();
2357 if (err)
2358 goto err_debug;
2359
2360 err = mlx5_sf_driver_register();
2361 if (err)
2362 goto err_sf;
2363
2364 err = pci_register_driver(&mlx5_core_driver);
2365 if (err)
2366 goto err_pci;
2367
2368 return 0;
2369
2370 err_pci:
2371 mlx5_sf_driver_unregister();
2372 err_sf:
2373 mlx5e_cleanup();
2374 err_debug:
2375 mlx5_unregister_debugfs();
2376 return err;
2377 }
2378
mlx5_cleanup(void)2379 static void __exit mlx5_cleanup(void)
2380 {
2381 pci_unregister_driver(&mlx5_core_driver);
2382 mlx5_sf_driver_unregister();
2383 mlx5e_cleanup();
2384 mlx5_unregister_debugfs();
2385 }
2386
2387 module_init(mlx5_init);
2388 module_exit(mlx5_cleanup);
2389