1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 #define MBOX_DOWN_MSG 1
20 #define MBOX_UP_MSG 2
21
22 /* AF/PF: PF initiated, PF/VF VF initiated */
23 #define MBOX_DOWN_RX_START 0
24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27 /* AF/PF: AF initiated, PF/VF PF initiated */
28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29 #define MBOX_UP_RX_SIZE SZ_1K
30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31 #define MBOX_UP_TX_SIZE SZ_1K
32
33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34 # error "incorrect mailbox area sizes"
35 #endif
36
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
40
41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
42
43 /* Mailbox directions */
44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
52
53 struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
55 void *hwbase;
56 spinlock_t mbox_lock;
57 u16 msg_size; /* Total msg size to be sent */
58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
59 u16 num_msgs; /* No of msgs sent or waiting for response */
60 u16 msgs_acked; /* No of msgs for which response is received */
61 };
62
63 struct otx2_mbox {
64 struct pci_dev *pdev;
65 void *hwbase; /* Mbox region advertised by HW */
66 void *reg_base;/* CSR base for this dev */
67 u64 trigger; /* Trigger mbox notification */
68 u16 tr_shift; /* Mbox trigger shift */
69 u64 rx_start; /* Offset of Rx region in mbox memory */
70 u64 tx_start; /* Offset of Tx region in mbox memory */
71 u16 rx_size; /* Size of Rx region */
72 u16 tx_size; /* Size of Tx region */
73 u16 ndevs; /* The number of peers */
74 struct otx2_mbox_dev *dev;
75 };
76
77 /* Header which precedes all mbox messages */
78 struct mbox_hdr {
79 u64 msg_size; /* Total msgs size embedded */
80 u16 num_msgs; /* No of msgs embedded */
81 };
82
83 /* Header which precedes every msg and is also part of it */
84 struct mbox_msghdr {
85 u16 pcifunc; /* Who's sending this msg */
86 u16 id; /* Mbox message ID */
87 #define OTX2_MBOX_REQ_SIG (0xdead)
88 #define OTX2_MBOX_RSP_SIG (0xbeef)
89 u16 sig; /* Signature, for validating corrupted msgs */
90 #define OTX2_MBOX_VERSION (0x000a)
91 u16 ver; /* Version of msg's structure for this ID */
92 u16 next_msgoff; /* Offset of next msg within mailbox region */
93 int rc; /* Msg process'ed response code */
94 };
95
96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
98 void otx2_mbox_destroy(struct otx2_mbox *mbox);
99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
100 struct pci_dev *pdev, void __force *reg_base,
101 int direction, int ndevs);
102
103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
104 struct pci_dev *pdev, void __force *reg_base,
105 int direction, int ndevs, unsigned long *bmap);
106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
111 int size, int size_rsp);
112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
113 struct mbox_msghdr *msg);
114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
116 u16 pcifunc, u16 id);
117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
118 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
120 int devid, int size)
121 {
122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
123 }
124
125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
126
127 /* Mailbox message types */
128 #define MBOX_MSG_MASK 0xFFFF
129 #define MBOX_MSG_INVALID 0xFFFE
130 #define MBOX_MSG_MAX 0xFFFF
131
132 #define MBOX_MESSAGES \
133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
142 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
143 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
144 msg_rsp) \
145 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
146 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
147 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
148 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
149 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
150 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
151 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
152 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
153 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
154 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
155 cgx_mac_addr_set_or_get) \
156 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
157 cgx_mac_addr_set_or_get) \
158 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
159 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
160 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
161 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
162 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
163 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
164 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
165 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
166 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
167 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
168 cgx_pause_frm_cfg) \
169 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
170 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
171 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
172 cgx_mac_addr_add_rsp) \
173 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
174 msg_rsp) \
175 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
176 cgx_max_dmac_entries_get_rsp) \
177 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
178 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
179 cgx_set_link_mode_rsp) \
180 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
181 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
182 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
183 cgx_features_info_msg) \
184 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
185 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
186 msg_rsp) \
187 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
188 cgx_mac_addr_update_rsp) \
189 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
190 cgx_pfc_rsp) \
191 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
192 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
193 npa_lf_alloc_req, npa_lf_alloc_rsp) \
194 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
195 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
196 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
197 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
198 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
199 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
200 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
201 msg_rsp) \
202 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
203 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
204 cpt_rd_wr_reg_msg) \
205 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
206 cpt_inline_ipsec_cfg_msg, msg_rsp) \
207 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
208 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
209 msg_rsp) \
210 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
211 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
212 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
213 cpt_flt_eng_info_rsp) \
214 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
215 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
216 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
217 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
218 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
219 npc_mcam_alloc_entry_rsp) \
220 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
221 npc_mcam_free_entry_req, msg_rsp) \
222 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
223 npc_mcam_write_entry_req, msg_rsp) \
224 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
225 npc_mcam_ena_dis_entry_req, msg_rsp) \
226 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
227 npc_mcam_ena_dis_entry_req, msg_rsp) \
228 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
229 npc_mcam_shift_entry_rsp) \
230 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
231 npc_mcam_alloc_counter_req, \
232 npc_mcam_alloc_counter_rsp) \
233 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
234 npc_mcam_oper_counter_req, msg_rsp) \
235 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
236 npc_mcam_unmap_counter_req, msg_rsp) \
237 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
238 npc_mcam_oper_counter_req, msg_rsp) \
239 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
240 npc_mcam_oper_counter_req, \
241 npc_mcam_oper_counter_rsp) \
242 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
243 npc_mcam_alloc_and_write_entry_req, \
244 npc_mcam_alloc_and_write_entry_rsp) \
245 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
246 msg_req, npc_get_kex_cfg_rsp) \
247 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
248 npc_install_flow_req, npc_install_flow_rsp) \
249 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
250 npc_delete_flow_req, npc_delete_flow_rsp) \
251 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
252 npc_mcam_read_entry_req, \
253 npc_mcam_read_entry_rsp) \
254 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
255 npc_set_pkind, msg_rsp) \
256 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
257 msg_req, npc_mcam_read_base_rule_rsp) \
258 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
259 npc_mcam_get_stats_req, \
260 npc_mcam_get_stats_rsp) \
261 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
262 npc_get_field_hash_info_req, \
263 npc_get_field_hash_info_rsp) \
264 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
265 npc_get_field_status_req, \
266 npc_get_field_status_rsp) \
267 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
268 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
269 nix_lf_alloc_req, nix_lf_alloc_rsp) \
270 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
271 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
272 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
273 hwctx_disable_req, msg_rsp) \
274 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
275 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
276 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
277 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
278 nix_txschq_config) \
279 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
280 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
281 nix_vtag_config_rsp) \
282 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
283 nix_rss_flowkey_cfg, \
284 nix_rss_flowkey_cfg_rsp) \
285 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
286 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
287 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
288 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
289 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
290 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
291 nix_mark_format_cfg, \
292 nix_mark_format_cfg_rsp) \
293 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
294 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
295 nix_lso_format_cfg, \
296 nix_lso_format_cfg_rsp) \
297 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
298 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
299 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
300 nix_bp_cfg_rsp) \
301 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
302 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
303 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
304 nix_inline_ipsec_cfg, msg_rsp) \
305 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
306 nix_inline_ipsec_lf_cfg, msg_rsp) \
307 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
308 nix_cn10k_aq_enq_rsp) \
309 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
310 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
311 nix_bandprof_alloc_rsp) \
312 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
313 msg_rsp) \
314 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
315 nix_bandprof_get_hwinfo_rsp) \
316 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
317 nix_bp_cfg_rsp) \
318 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
319 msg_rsp) \
320 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
321 msg_req, nix_inline_ipsec_cfg) \
322 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
323 nix_mcast_grp_create_rsp) \
324 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
325 msg_rsp) \
326 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
327 nix_mcast_grp_update_req, \
328 nix_mcast_grp_update_rsp) \
329 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \
330 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
331 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
332 mcs_alloc_rsrc_rsp) \
333 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
334 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
335 msg_rsp) \
336 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
337 msg_rsp) \
338 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
339 msg_rsp) \
340 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
341 msg_rsp) \
342 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
343 msg_rsp) \
344 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
345 msg_rsp) \
346 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
347 msg_rsp) \
348 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
349 msg_rsp) \
350 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
351 msg_rsp) \
352 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
353 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
354 mcs_flowid_stats) \
355 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
356 mcs_secy_stats) \
357 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
358 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
359 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
360 mcs_port_stats) \
361 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
362 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
363 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
364 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
365 msg_rsp) \
366 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
367 mcs_alloc_ctrl_pkt_rule_req, \
368 mcs_alloc_ctrl_pkt_rule_rsp) \
369 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
370 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
371 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
372 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
373 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
374 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
375 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
376 mcs_port_cfg_get_rsp) \
377 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
378 mcs_custom_tag_cfg_get_req, \
379 mcs_custom_tag_cfg_get_rsp)
380
381 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
382 #define MBOX_UP_CGX_MESSAGES \
383 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
384
385 #define MBOX_UP_CPT_MESSAGES \
386 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
387
388 #define MBOX_UP_MCS_MESSAGES \
389 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
390
391 #define MBOX_UP_REP_MESSAGES \
392 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
393
394 enum {
395 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
396 MBOX_MESSAGES
397 MBOX_UP_CGX_MESSAGES
398 MBOX_UP_CPT_MESSAGES
399 MBOX_UP_MCS_MESSAGES
400 MBOX_UP_REP_MESSAGES
401 #undef M
402 };
403
404 /* Mailbox message formats */
405
406 #define RVU_DEFAULT_PF_FUNC 0xFFFF
407
408 /* Generic request msg used for those mbox messages which
409 * don't send any data in the request.
410 */
411 struct msg_req {
412 struct mbox_msghdr hdr;
413 };
414
415 /* Generic response msg used an ack or response for those mbox
416 * messages which don't have a specific rsp msg format.
417 */
418 struct msg_rsp {
419 struct mbox_msghdr hdr;
420 };
421
422 /* RVU mailbox error codes
423 * Range 256 - 300.
424 */
425 enum rvu_af_status {
426 RVU_INVALID_VF_ID = -256,
427 };
428
429 struct ready_msg_rsp {
430 struct mbox_msghdr hdr;
431 u16 sclk_freq; /* SCLK frequency (in MHz) */
432 u16 rclk_freq; /* RCLK frequency (in MHz) */
433 };
434
435 /* Structure for requesting resource provisioning.
436 * 'modify' flag to be used when either requesting more
437 * or to detach partial of a certain resource type.
438 * Rest of the fields specify how many of what type to
439 * be attached.
440 * To request LFs from two blocks of same type this mailbox
441 * can be sent twice as below:
442 * struct rsrc_attach *attach;
443 * .. Allocate memory for message ..
444 * attach->cptlfs = 3; <3 LFs from CPT0>
445 * .. Send message ..
446 * .. Allocate memory for message ..
447 * attach->modify = 1;
448 * attach->cpt_blkaddr = BLKADDR_CPT1;
449 * attach->cptlfs = 2; <2 LFs from CPT1>
450 * .. Send message ..
451 */
452 struct rsrc_attach {
453 struct mbox_msghdr hdr;
454 u8 modify:1;
455 u8 npalf:1;
456 u8 nixlf:1;
457 u16 sso;
458 u16 ssow;
459 u16 timlfs;
460 u16 cptlfs;
461 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
462 };
463
464 /* Structure for relinquishing resources.
465 * 'partial' flag to be used when relinquishing all resources
466 * but only of a certain type. If not set, all resources of all
467 * types provisioned to the RVU function will be detached.
468 */
469 struct rsrc_detach {
470 struct mbox_msghdr hdr;
471 u8 partial:1;
472 u8 npalf:1;
473 u8 nixlf:1;
474 u8 sso:1;
475 u8 ssow:1;
476 u8 timlfs:1;
477 u8 cptlfs:1;
478 };
479
480 /* Number of resources available to the caller.
481 * In reply to MBOX_MSG_FREE_RSRC_CNT.
482 */
483 struct free_rsrcs_rsp {
484 struct mbox_msghdr hdr;
485 u16 schq[NIX_TXSCH_LVL_CNT];
486 u16 sso;
487 u16 tim;
488 u16 ssow;
489 u16 cpt;
490 u8 npa;
491 u8 nix;
492 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
493 u8 nix1;
494 u8 cpt1;
495 u8 ree0;
496 u8 ree1;
497 };
498
499 #define MSIX_VECTOR_INVALID 0xFFFF
500 #define MAX_RVU_BLKLF_CNT 256
501
502 struct msix_offset_rsp {
503 struct mbox_msghdr hdr;
504 u16 npa_msixoff;
505 u16 nix_msixoff;
506 u16 sso;
507 u16 ssow;
508 u16 timlfs;
509 u16 cptlfs;
510 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
511 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
512 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
513 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
514 u16 cpt1_lfs;
515 u16 ree0_lfs;
516 u16 ree1_lfs;
517 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
518 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
519 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
520 };
521
522 struct get_hw_cap_rsp {
523 struct mbox_msghdr hdr;
524 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
525 u8 nix_shaping; /* Is shaping and coloring supported */
526 u8 npc_hash_extract; /* Is hash extract supported */
527 };
528
529 /* CGX mbox message formats */
530
531 struct cgx_stats_rsp {
532 struct mbox_msghdr hdr;
533 #define CGX_RX_STATS_COUNT 9
534 #define CGX_TX_STATS_COUNT 18
535 u64 rx_stats[CGX_RX_STATS_COUNT];
536 u64 tx_stats[CGX_TX_STATS_COUNT];
537 };
538
539 struct cgx_fec_stats_rsp {
540 struct mbox_msghdr hdr;
541 u64 fec_corr_blks;
542 u64 fec_uncorr_blks;
543 };
544 /* Structure for requesting the operation for
545 * setting/getting mac address in the CGX interface
546 */
547 struct cgx_mac_addr_set_or_get {
548 struct mbox_msghdr hdr;
549 u8 mac_addr[ETH_ALEN];
550 u32 index;
551 };
552
553 /* Structure for requesting the operation to
554 * add DMAC filter entry into CGX interface
555 */
556 struct cgx_mac_addr_add_req {
557 struct mbox_msghdr hdr;
558 u8 mac_addr[ETH_ALEN];
559 };
560
561 /* Structure for response against the operation to
562 * add DMAC filter entry into CGX interface
563 */
564 struct cgx_mac_addr_add_rsp {
565 struct mbox_msghdr hdr;
566 u32 index;
567 };
568
569 /* Structure for requesting the operation to
570 * delete DMAC filter entry from CGX interface
571 */
572 struct cgx_mac_addr_del_req {
573 struct mbox_msghdr hdr;
574 u32 index;
575 };
576
577 /* Structure for response against the operation to
578 * get maximum supported DMAC filter entries
579 */
580 struct cgx_max_dmac_entries_get_rsp {
581 struct mbox_msghdr hdr;
582 u32 max_dmac_filters;
583 };
584
585 struct cgx_link_user_info {
586 uint64_t link_up:1;
587 uint64_t full_duplex:1;
588 uint64_t lmac_type_id:4;
589 uint64_t speed:20; /* speed in Mbps */
590 uint64_t an:1; /* AN supported or not */
591 uint64_t fec:2; /* FEC type if enabled else 0 */
592 #define LMACTYPE_STR_LEN 16
593 char lmac_type[LMACTYPE_STR_LEN];
594 };
595
596 struct cgx_link_info_msg {
597 struct mbox_msghdr hdr;
598 struct cgx_link_user_info link_info;
599 };
600
601 struct cgx_pause_frm_cfg {
602 struct mbox_msghdr hdr;
603 u8 set;
604 /* set = 1 if the request is to config pause frames */
605 /* set = 0 if the request is to fetch pause frames config */
606 u8 rx_pause;
607 u8 tx_pause;
608 };
609
610 enum fec_type {
611 OTX2_FEC_NONE,
612 OTX2_FEC_BASER,
613 OTX2_FEC_RS,
614 OTX2_FEC_STATS_CNT = 2,
615 OTX2_FEC_OFF,
616 };
617
618 struct fec_mode {
619 struct mbox_msghdr hdr;
620 int fec;
621 };
622
623 struct sfp_eeprom_s {
624 #define SFP_EEPROM_SIZE 256
625 u16 sff_id;
626 u8 buf[SFP_EEPROM_SIZE];
627 u64 reserved;
628 };
629
630 struct phy_s {
631 struct {
632 u64 can_change_mod_type:1;
633 u64 mod_type:1;
634 u64 has_fec_stats:1;
635 } misc;
636 struct fec_stats_s {
637 u32 rsfec_corr_cws;
638 u32 rsfec_uncorr_cws;
639 u32 brfec_corr_blks;
640 u32 brfec_uncorr_blks;
641 } fec_stats;
642 };
643
644 struct cgx_lmac_fwdata_s {
645 u16 rw_valid;
646 u64 supported_fec;
647 u64 supported_an;
648 u64 supported_link_modes;
649 /* only applicable if AN is supported */
650 u64 advertised_fec;
651 u64 advertised_link_modes;
652 /* Only applicable if SFP/QSFP slot is present */
653 struct sfp_eeprom_s sfp_eeprom;
654 struct phy_s phy;
655 #define LMAC_FWDATA_RESERVED_MEM 1021
656 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
657 };
658
659 struct cgx_fw_data {
660 struct mbox_msghdr hdr;
661 struct cgx_lmac_fwdata_s fwdata;
662 };
663
664 struct cgx_set_link_mode_args {
665 u32 speed;
666 u8 duplex;
667 u8 an;
668 u8 ports;
669 u64 mode;
670 };
671
672 struct cgx_set_link_mode_req {
673 #define AUTONEG_UNKNOWN 0xff
674 struct mbox_msghdr hdr;
675 struct cgx_set_link_mode_args args;
676 };
677
678 struct cgx_set_link_mode_rsp {
679 struct mbox_msghdr hdr;
680 int status;
681 };
682
683 struct cgx_mac_addr_reset_req {
684 struct mbox_msghdr hdr;
685 u32 index;
686 };
687
688 struct cgx_mac_addr_update_req {
689 struct mbox_msghdr hdr;
690 u8 mac_addr[ETH_ALEN];
691 u32 index;
692 };
693
694 struct cgx_mac_addr_update_rsp {
695 struct mbox_msghdr hdr;
696 u32 index;
697 };
698
699 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
700 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
701 /* flow control from physical link higig2 messages */
702 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
703 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
704 #define RVU_MAC_VERSION BIT_ULL(4)
705 #define RVU_MAC_CGX BIT_ULL(5)
706 #define RVU_MAC_RPM BIT_ULL(6)
707
708 struct cgx_features_info_msg {
709 struct mbox_msghdr hdr;
710 u64 lmac_features;
711 };
712
713 struct rpm_stats_rsp {
714 struct mbox_msghdr hdr;
715 #define RPM_RX_STATS_COUNT 43
716 #define RPM_TX_STATS_COUNT 34
717 u64 rx_stats[RPM_RX_STATS_COUNT];
718 u64 tx_stats[RPM_TX_STATS_COUNT];
719 };
720
721 struct cgx_pfc_cfg {
722 struct mbox_msghdr hdr;
723 u8 rx_pause;
724 u8 tx_pause;
725 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
726 };
727
728 struct cgx_pfc_rsp {
729 struct mbox_msghdr hdr;
730 u8 rx_pause;
731 u8 tx_pause;
732 };
733
734 /* NPA mbox message formats */
735
736 struct npc_set_pkind {
737 struct mbox_msghdr hdr;
738 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
739 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
740 u64 mode;
741 #define PKIND_TX BIT_ULL(0)
742 #define PKIND_RX BIT_ULL(1)
743 u8 dir;
744 u8 pkind; /* valid only in case custom flag */
745 u8 var_len_off; /* Offset of custom header length field.
746 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
747 */
748 u8 var_len_off_mask; /* Mask for length with in offset */
749 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
750 };
751
752 /* NPA mbox message formats */
753
754 /* NPA mailbox error codes
755 * Range 301 - 400.
756 */
757 enum npa_af_status {
758 NPA_AF_ERR_PARAM = -301,
759 NPA_AF_ERR_AQ_FULL = -302,
760 NPA_AF_ERR_AQ_ENQUEUE = -303,
761 NPA_AF_ERR_AF_LF_INVALID = -304,
762 NPA_AF_ERR_AF_LF_ALLOC = -305,
763 NPA_AF_ERR_LF_RESET = -306,
764 };
765
766 /* For NPA LF context alloc and init */
767 struct npa_lf_alloc_req {
768 struct mbox_msghdr hdr;
769 int node;
770 int aura_sz; /* No of auras */
771 u32 nr_pools; /* No of pools */
772 u64 way_mask;
773 };
774
775 struct npa_lf_alloc_rsp {
776 struct mbox_msghdr hdr;
777 u32 stack_pg_ptrs; /* No of ptrs per stack page */
778 u32 stack_pg_bytes; /* Size of stack page */
779 u16 qints; /* NPA_AF_CONST::QINTS */
780 u8 cache_lines; /*BATCH ALLOC DMA */
781 };
782
783 /* NPA AQ enqueue msg */
784 struct npa_aq_enq_req {
785 struct mbox_msghdr hdr;
786 u32 aura_id;
787 u8 ctype;
788 u8 op;
789 union {
790 /* Valid when op == WRITE/INIT and ctype == AURA.
791 * LF fills the pool_id in aura.pool_addr. AF will translate
792 * the pool_id to pool context pointer.
793 */
794 struct npa_aura_s aura;
795 /* Valid when op == WRITE/INIT and ctype == POOL */
796 struct npa_pool_s pool;
797 };
798 /* Mask data when op == WRITE (1=write, 0=don't write) */
799 union {
800 /* Valid when op == WRITE and ctype == AURA */
801 struct npa_aura_s aura_mask;
802 /* Valid when op == WRITE and ctype == POOL */
803 struct npa_pool_s pool_mask;
804 };
805 };
806
807 struct npa_aq_enq_rsp {
808 struct mbox_msghdr hdr;
809 union {
810 /* Valid when op == READ and ctype == AURA */
811 struct npa_aura_s aura;
812 /* Valid when op == READ and ctype == POOL */
813 struct npa_pool_s pool;
814 };
815 };
816
817 /* Disable all contexts of type 'ctype' */
818 struct hwctx_disable_req {
819 struct mbox_msghdr hdr;
820 u8 ctype;
821 };
822
823 /* NIX mbox message formats */
824
825 /* NIX mailbox error codes
826 * Range 401 - 500.
827 */
828 enum nix_af_status {
829 NIX_AF_ERR_PARAM = -401,
830 NIX_AF_ERR_AQ_FULL = -402,
831 NIX_AF_ERR_AQ_ENQUEUE = -403,
832 NIX_AF_ERR_AF_LF_INVALID = -404,
833 NIX_AF_ERR_AF_LF_ALLOC = -405,
834 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
835 NIX_AF_ERR_TLX_INVALID = -407,
836 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
837 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
838 NIX_AF_ERR_FRS_INVALID = -410,
839 NIX_AF_ERR_RX_LINK_INVALID = -411,
840 NIX_AF_INVAL_TXSCHQ_CFG = -412,
841 NIX_AF_SMQ_FLUSH_FAILED = -413,
842 NIX_AF_ERR_LF_RESET = -414,
843 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
844 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
845 NIX_AF_ERR_MARK_CFG_FAIL = -417,
846 NIX_AF_ERR_LSO_CFG_FAIL = -418,
847 NIX_AF_INVAL_NPA_PF_FUNC = -419,
848 NIX_AF_INVAL_SSO_PF_FUNC = -420,
849 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
850 NIX_AF_ERR_RX_VTAG_INUSE = -422,
851 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
852 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
853 NIX_AF_ERR_INVALID_NIXBLK = -425,
854 NIX_AF_ERR_INVALID_BANDPROF = -426,
855 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
856 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
857 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
858 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
859 NIX_AF_ERR_LINK_CREDITS = -431,
860 NIX_AF_ERR_INVALID_BPID = -434,
861 NIX_AF_ERR_INVALID_BPID_REQ = -435,
862 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
863 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
864 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
865 };
866
867 /* For NIX RX vtag action */
868 enum nix_rx_vtag0_type {
869 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
870 NIX_AF_LFX_RX_VTAG_TYPE1,
871 NIX_AF_LFX_RX_VTAG_TYPE2,
872 NIX_AF_LFX_RX_VTAG_TYPE3,
873 NIX_AF_LFX_RX_VTAG_TYPE4,
874 NIX_AF_LFX_RX_VTAG_TYPE5,
875 NIX_AF_LFX_RX_VTAG_TYPE6,
876 NIX_AF_LFX_RX_VTAG_TYPE7,
877 };
878
879 /* For NIX LF context alloc and init */
880 struct nix_lf_alloc_req {
881 struct mbox_msghdr hdr;
882 int node;
883 u32 rq_cnt; /* No of receive queues */
884 u32 sq_cnt; /* No of send queues */
885 u32 cq_cnt; /* No of completion queues */
886 u8 xqe_sz;
887 u16 rss_sz;
888 u8 rss_grps;
889 u16 npa_func;
890 u16 sso_func;
891 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
892 u64 way_mask;
893 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
894 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
895 u64 flags;
896 };
897
898 struct nix_lf_alloc_rsp {
899 struct mbox_msghdr hdr;
900 u16 sqb_size;
901 u16 rx_chan_base;
902 u16 tx_chan_base;
903 u8 rx_chan_cnt; /* total number of RX channels */
904 u8 tx_chan_cnt; /* total number of TX channels */
905 u8 lso_tsov4_idx;
906 u8 lso_tsov6_idx;
907 u8 mac_addr[ETH_ALEN];
908 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
909 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
910 u16 cints; /* NIX_AF_CONST2::CINTS */
911 u16 qints; /* NIX_AF_CONST2::QINTS */
912 u8 cgx_links; /* No. of CGX links present in HW */
913 u8 lbk_links; /* No. of LBK links present in HW */
914 u8 sdp_links; /* No. of SDP links present in HW */
915 u8 tx_link; /* Transmit channel link number */
916 };
917
918 struct nix_lf_free_req {
919 struct mbox_msghdr hdr;
920 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
921 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
922 u64 flags;
923 };
924
925 /* CN10K NIX AQ enqueue msg */
926 struct nix_cn10k_aq_enq_req {
927 struct mbox_msghdr hdr;
928 u32 qidx;
929 u8 ctype;
930 u8 op;
931 union {
932 struct nix_cn10k_rq_ctx_s rq;
933 struct nix_cn10k_sq_ctx_s sq;
934 struct nix_cq_ctx_s cq;
935 struct nix_rsse_s rss;
936 struct nix_rx_mce_s mce;
937 struct nix_bandprof_s prof;
938 };
939 union {
940 struct nix_cn10k_rq_ctx_s rq_mask;
941 struct nix_cn10k_sq_ctx_s sq_mask;
942 struct nix_cq_ctx_s cq_mask;
943 struct nix_rsse_s rss_mask;
944 struct nix_rx_mce_s mce_mask;
945 struct nix_bandprof_s prof_mask;
946 };
947 };
948
949 struct nix_cn10k_aq_enq_rsp {
950 struct mbox_msghdr hdr;
951 union {
952 struct nix_cn10k_rq_ctx_s rq;
953 struct nix_cn10k_sq_ctx_s sq;
954 struct nix_cq_ctx_s cq;
955 struct nix_rsse_s rss;
956 struct nix_rx_mce_s mce;
957 struct nix_bandprof_s prof;
958 };
959 };
960
961 /* NIX AQ enqueue msg */
962 struct nix_aq_enq_req {
963 struct mbox_msghdr hdr;
964 u32 qidx;
965 u8 ctype;
966 u8 op;
967 union {
968 struct nix_rq_ctx_s rq;
969 struct nix_sq_ctx_s sq;
970 struct nix_cq_ctx_s cq;
971 struct nix_rsse_s rss;
972 struct nix_rx_mce_s mce;
973 struct nix_bandprof_s prof;
974 };
975 union {
976 struct nix_rq_ctx_s rq_mask;
977 struct nix_sq_ctx_s sq_mask;
978 struct nix_cq_ctx_s cq_mask;
979 struct nix_rsse_s rss_mask;
980 struct nix_rx_mce_s mce_mask;
981 struct nix_bandprof_s prof_mask;
982 };
983 };
984
985 struct nix_aq_enq_rsp {
986 struct mbox_msghdr hdr;
987 union {
988 struct nix_rq_ctx_s rq;
989 struct nix_sq_ctx_s sq;
990 struct nix_cq_ctx_s cq;
991 struct nix_rsse_s rss;
992 struct nix_rx_mce_s mce;
993 struct nix_bandprof_s prof;
994 };
995 };
996
997 /* Tx scheduler/shaper mailbox messages */
998
999 #define MAX_TXSCHQ_PER_FUNC 128
1000
1001 struct nix_txsch_alloc_req {
1002 struct mbox_msghdr hdr;
1003 /* Scheduler queue count request at each level */
1004 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
1005 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
1006 };
1007
1008 struct nix_txsch_alloc_rsp {
1009 struct mbox_msghdr hdr;
1010 /* Scheduler queue count allocated at each level */
1011 u16 schq_contig[NIX_TXSCH_LVL_CNT];
1012 u16 schq[NIX_TXSCH_LVL_CNT];
1013 /* Scheduler queue list allocated at each level */
1014 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1015 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1016 u8 aggr_level; /* Traffic aggregation scheduler level */
1017 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
1018 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1019 };
1020
1021 struct nix_txsch_free_req {
1022 struct mbox_msghdr hdr;
1023 #define TXSCHQ_FREE_ALL BIT_ULL(0)
1024 u16 flags;
1025 /* Scheduler queue level to be freed */
1026 u16 schq_lvl;
1027 /* List of scheduler queues to be freed */
1028 u16 schq;
1029 };
1030
1031 struct nix_txschq_config {
1032 struct mbox_msghdr hdr;
1033 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1034 u8 read;
1035 #define TXSCHQ_IDX_SHIFT 16
1036 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1037 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1038 u8 num_regs;
1039 #define MAX_REGS_PER_MBOX_MSG 20
1040 u64 reg[MAX_REGS_PER_MBOX_MSG];
1041 u64 regval[MAX_REGS_PER_MBOX_MSG];
1042 /* All 0's => overwrite with new value */
1043 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1044 };
1045
1046 struct nix_vtag_config {
1047 struct mbox_msghdr hdr;
1048 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1049 u8 vtag_size;
1050 /* cfg_type is '0' for tx vlan cfg
1051 * cfg_type is '1' for rx vlan cfg
1052 */
1053 u8 cfg_type;
1054 union {
1055 /* valid when cfg_type is '0' */
1056 struct {
1057 u64 vtag0;
1058 u64 vtag1;
1059
1060 /* cfg_vtag0 & cfg_vtag1 fields are valid
1061 * when free_vtag0 & free_vtag1 are '0's.
1062 */
1063 /* cfg_vtag0 = 1 to configure vtag0 */
1064 u8 cfg_vtag0 :1;
1065 /* cfg_vtag1 = 1 to configure vtag1 */
1066 u8 cfg_vtag1 :1;
1067
1068 /* vtag0_idx & vtag1_idx are only valid when
1069 * both cfg_vtag0 & cfg_vtag1 are '0's,
1070 * these fields are used along with free_vtag0
1071 * & free_vtag1 to free the nix lf's tx_vlan
1072 * configuration.
1073 *
1074 * Denotes the indices of tx_vtag def registers
1075 * that needs to be cleared and freed.
1076 */
1077 int vtag0_idx;
1078 int vtag1_idx;
1079
1080 /* free_vtag0 & free_vtag1 fields are valid
1081 * when cfg_vtag0 & cfg_vtag1 are '0's.
1082 */
1083 /* free_vtag0 = 1 clears vtag0 configuration
1084 * vtag0_idx denotes the index to be cleared.
1085 */
1086 u8 free_vtag0 :1;
1087 /* free_vtag1 = 1 clears vtag1 configuration
1088 * vtag1_idx denotes the index to be cleared.
1089 */
1090 u8 free_vtag1 :1;
1091 } tx;
1092
1093 /* valid when cfg_type is '1' */
1094 struct {
1095 /* rx vtag type index, valid values are in 0..7 range */
1096 u8 vtag_type;
1097 /* rx vtag strip */
1098 u8 strip_vtag :1;
1099 /* rx vtag capture */
1100 u8 capture_vtag :1;
1101 } rx;
1102 };
1103 };
1104
1105 struct nix_vtag_config_rsp {
1106 struct mbox_msghdr hdr;
1107 int vtag0_idx;
1108 int vtag1_idx;
1109 /* Indices of tx_vtag def registers used to configure
1110 * tx vtag0 & vtag1 headers, these indices are valid
1111 * when nix_vtag_config mbox requested for vtag0 and/
1112 * or vtag1 configuration.
1113 */
1114 };
1115
1116 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1117
1118 struct nix_rss_flowkey_cfg {
1119 struct mbox_msghdr hdr;
1120 int mcam_index; /* MCAM entry index to modify */
1121 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1122 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1123 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1124 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1125 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1126 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1127 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1128 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1129 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1130 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1131 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1132 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1133 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1134 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1135 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1136 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1137 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1138 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1139 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1140 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1141 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1142 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1143 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1144 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1145 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1146 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1147 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1148 u32 flowkey_cfg; /* Flowkey types selected */
1149 u8 group; /* RSS context or group */
1150 };
1151
1152 struct nix_rss_flowkey_cfg_rsp {
1153 struct mbox_msghdr hdr;
1154 u8 alg_idx; /* Selected algo index */
1155 };
1156
1157 struct nix_set_mac_addr {
1158 struct mbox_msghdr hdr;
1159 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1160 };
1161
1162 struct nix_get_mac_addr_rsp {
1163 struct mbox_msghdr hdr;
1164 u8 mac_addr[ETH_ALEN];
1165 };
1166
1167 struct nix_mark_format_cfg {
1168 struct mbox_msghdr hdr;
1169 u8 offset;
1170 u8 y_mask;
1171 u8 y_val;
1172 u8 r_mask;
1173 u8 r_val;
1174 };
1175
1176 struct nix_mark_format_cfg_rsp {
1177 struct mbox_msghdr hdr;
1178 u8 mark_format_idx;
1179 };
1180
1181 struct nix_rx_mode {
1182 struct mbox_msghdr hdr;
1183 #define NIX_RX_MODE_UCAST BIT(0)
1184 #define NIX_RX_MODE_PROMISC BIT(1)
1185 #define NIX_RX_MODE_ALLMULTI BIT(2)
1186 #define NIX_RX_MODE_USE_MCE BIT(3)
1187 u16 mode;
1188 };
1189
1190 struct nix_rx_cfg {
1191 struct mbox_msghdr hdr;
1192 #define NIX_RX_OL3_VERIFY BIT(0)
1193 #define NIX_RX_OL4_VERIFY BIT(1)
1194 #define NIX_RX_DROP_RE BIT(2)
1195 u8 len_verify; /* Outer L3/L4 len check */
1196 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1197 u8 csum_verify; /* Outer L4 checksum verification */
1198 };
1199
1200 struct nix_frs_cfg {
1201 struct mbox_msghdr hdr;
1202 u8 update_smq; /* Update SMQ's min/max lens */
1203 u8 update_minlen; /* Set minlen also */
1204 u8 sdp_link; /* Set SDP RX link */
1205 u16 maxlen;
1206 u16 minlen;
1207 };
1208
1209 struct nix_lso_format_cfg {
1210 struct mbox_msghdr hdr;
1211 u64 field_mask;
1212 #define NIX_LSO_FIELD_MAX 8
1213 u64 fields[NIX_LSO_FIELD_MAX];
1214 };
1215
1216 struct nix_lso_format_cfg_rsp {
1217 struct mbox_msghdr hdr;
1218 u8 lso_format_idx;
1219 };
1220
1221 struct nix_bp_cfg_req {
1222 struct mbox_msghdr hdr;
1223 u16 chan_base; /* Starting channel number */
1224 u8 chan_cnt; /* Number of channels */
1225 u8 bpid_per_chan;
1226 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1227 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1228 };
1229
1230 /* Maximum channels any single NIX interface can have */
1231 #define NIX_MAX_BPID_CHAN 256
1232 struct nix_bp_cfg_rsp {
1233 struct mbox_msghdr hdr;
1234 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1235 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1236 };
1237
1238 struct nix_mcast_grp_create_req {
1239 struct mbox_msghdr hdr;
1240 #define NIX_MCAST_INGRESS 0
1241 #define NIX_MCAST_EGRESS 1
1242 u8 dir;
1243 u8 reserved[11];
1244 /* Reserving few bytes for future requirement */
1245 };
1246
1247 struct nix_mcast_grp_create_rsp {
1248 struct mbox_msghdr hdr;
1249 /* This mcast_grp_idx should be passed during MCAM
1250 * write entry for multicast. AF will identify the
1251 * corresponding multicast table index associated
1252 * with the group id and program the same to MCAM entry.
1253 * This group id is also needed during group delete
1254 * and update request.
1255 */
1256 u32 mcast_grp_idx;
1257 };
1258
1259 struct nix_mcast_grp_destroy_req {
1260 struct mbox_msghdr hdr;
1261 /* Group id returned by nix_mcast_grp_create_rsp */
1262 u32 mcast_grp_idx;
1263 /* If AF is requesting for destroy, then set
1264 * it to '1'. Otherwise keep it to '0'
1265 */
1266 u8 is_af;
1267 };
1268
1269 struct nix_mcast_grp_update_req {
1270 struct mbox_msghdr hdr;
1271 /* Group id returned by nix_mcast_grp_create_rsp */
1272 u32 mcast_grp_idx;
1273 /* Number of multicast/mirror entries requested */
1274 u32 num_mce_entry;
1275 #define NIX_MCE_ENTRY_MAX 64
1276 #define NIX_RX_RQ 0
1277 #define NIX_RX_RSS 1
1278 /* Receive queue or RSS index within pf_func */
1279 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1280 /* pcifunc is required for both ingress and egress multicast */
1281 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1282 /* channel is required for egress multicast */
1283 u16 channel[NIX_MCE_ENTRY_MAX];
1284 #define NIX_MCAST_OP_ADD_ENTRY 0
1285 #define NIX_MCAST_OP_DEL_ENTRY 1
1286 /* Destination type. 0:Receive queue, 1:RSS*/
1287 u8 dest_type[NIX_MCE_ENTRY_MAX];
1288 u8 op;
1289 /* If AF is requesting for update, then set
1290 * it to '1'. Otherwise keep it to '0'
1291 */
1292 u8 is_af;
1293 };
1294
1295 struct nix_mcast_grp_update_rsp {
1296 struct mbox_msghdr hdr;
1297 u32 mce_start_index;
1298 };
1299
1300 /* Global NIX inline IPSec configuration */
1301 struct nix_inline_ipsec_cfg {
1302 struct mbox_msghdr hdr;
1303 u32 cpt_credit;
1304 struct {
1305 u8 egrp;
1306 u16 opcode;
1307 u16 param1;
1308 u16 param2;
1309 } gen_cfg;
1310 struct {
1311 u16 cpt_pf_func;
1312 u8 cpt_slot;
1313 } inst_qsel;
1314 u8 enable;
1315 u16 bpid;
1316 u32 credit_th;
1317 };
1318
1319 /* Per NIX LF inline IPSec configuration */
1320 struct nix_inline_ipsec_lf_cfg {
1321 struct mbox_msghdr hdr;
1322 u64 sa_base_addr;
1323 struct {
1324 u32 tag_const;
1325 u16 lenm1_max;
1326 u8 sa_pow2_size;
1327 u8 tt;
1328 } ipsec_cfg0;
1329 struct {
1330 u32 sa_idx_max;
1331 u8 sa_idx_w;
1332 } ipsec_cfg1;
1333 u8 enable;
1334 };
1335
1336 struct nix_hw_info {
1337 struct mbox_msghdr hdr;
1338 u16 rsvs16;
1339 u16 max_mtu;
1340 u16 min_mtu;
1341 u32 rpm_dwrr_mtu;
1342 u32 sdp_dwrr_mtu;
1343 u32 lbk_dwrr_mtu;
1344 u32 rsvd32[1];
1345 u64 rsvd[15]; /* Add reserved fields for future expansion */
1346 };
1347
1348 struct nix_bandprof_alloc_req {
1349 struct mbox_msghdr hdr;
1350 /* Count of profiles needed per layer */
1351 u16 prof_count[BAND_PROF_NUM_LAYERS];
1352 };
1353
1354 struct nix_bandprof_alloc_rsp {
1355 struct mbox_msghdr hdr;
1356 u16 prof_count[BAND_PROF_NUM_LAYERS];
1357
1358 /* There is no need to allocate morethan 1 bandwidth profile
1359 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1360 * profiles to 64 per PF_FUNC.
1361 */
1362 #define MAX_BANDPROF_PER_PFFUNC 64
1363 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1364 };
1365
1366 struct nix_bandprof_free_req {
1367 struct mbox_msghdr hdr;
1368 u8 free_all;
1369 u16 prof_count[BAND_PROF_NUM_LAYERS];
1370 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1371 };
1372
1373 struct nix_bandprof_get_hwinfo_rsp {
1374 struct mbox_msghdr hdr;
1375 u16 prof_count[BAND_PROF_NUM_LAYERS];
1376 u32 policer_timeunit;
1377 };
1378
1379 struct nix_stats_req {
1380 struct mbox_msghdr hdr;
1381 u8 reset;
1382 u16 pcifunc;
1383 u64 rsvd;
1384 };
1385
1386 struct nix_stats_rsp {
1387 struct mbox_msghdr hdr;
1388 u16 pcifunc;
1389 struct {
1390 u64 octs;
1391 u64 ucast;
1392 u64 bcast;
1393 u64 mcast;
1394 u64 drop;
1395 u64 drop_octs;
1396 u64 drop_mcast;
1397 u64 drop_bcast;
1398 u64 err;
1399 u64 rsvd[5];
1400 } rx;
1401 struct {
1402 u64 ucast;
1403 u64 bcast;
1404 u64 mcast;
1405 u64 drop;
1406 u64 octs;
1407 } tx;
1408 };
1409
1410 /* NPC mbox message structs */
1411
1412 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1413 #define NPC_MCAM_INVALID_MAP 0xFFFF
1414
1415 /* NPC mailbox error codes
1416 * Range 701 - 800.
1417 */
1418 enum npc_af_status {
1419 NPC_MCAM_INVALID_REQ = -701,
1420 NPC_MCAM_ALLOC_DENIED = -702,
1421 NPC_MCAM_ALLOC_FAILED = -703,
1422 NPC_MCAM_PERM_DENIED = -704,
1423 NPC_FLOW_INTF_INVALID = -707,
1424 NPC_FLOW_CHAN_INVALID = -708,
1425 NPC_FLOW_NO_NIXLF = -709,
1426 NPC_FLOW_NOT_SUPPORTED = -710,
1427 NPC_FLOW_VF_PERM_DENIED = -711,
1428 NPC_FLOW_VF_NOT_INIT = -712,
1429 NPC_FLOW_VF_OVERLAP = -713,
1430 };
1431
1432 struct npc_mcam_alloc_entry_req {
1433 struct mbox_msghdr hdr;
1434 #define NPC_MAX_NONCONTIG_ENTRIES 256
1435 u8 contig; /* Contiguous entries ? */
1436 #define NPC_MCAM_ANY_PRIO 0
1437 #define NPC_MCAM_LOWER_PRIO 1
1438 #define NPC_MCAM_HIGHER_PRIO 2
1439 u8 priority; /* Lower or higher w.r.t ref_entry */
1440 u16 ref_entry;
1441 u16 count; /* Number of entries requested */
1442 };
1443
1444 struct npc_mcam_alloc_entry_rsp {
1445 struct mbox_msghdr hdr;
1446 u16 entry; /* Entry allocated or start index if contiguous.
1447 * Invalid incase of non-contiguous.
1448 */
1449 u16 count; /* Number of entries allocated */
1450 u16 free_count; /* Number of entries available */
1451 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1452 };
1453
1454 struct npc_mcam_free_entry_req {
1455 struct mbox_msghdr hdr;
1456 u16 entry; /* Entry index to be freed */
1457 u8 all; /* If all entries allocated to this PFVF to be freed */
1458 };
1459
1460 struct mcam_entry {
1461 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1462 u64 kw[NPC_MAX_KWS_IN_KEY];
1463 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1464 u64 action;
1465 u64 vtag_action;
1466 };
1467
1468 struct npc_mcam_write_entry_req {
1469 struct mbox_msghdr hdr;
1470 struct mcam_entry entry_data;
1471 u16 entry; /* MCAM entry to write this match key */
1472 u16 cntr; /* Counter for this MCAM entry */
1473 u8 intf; /* Rx or Tx interface */
1474 u8 enable_entry;/* Enable this MCAM entry ? */
1475 u8 set_cntr; /* Set counter for this entry ? */
1476 };
1477
1478 /* Enable/Disable a given entry */
1479 struct npc_mcam_ena_dis_entry_req {
1480 struct mbox_msghdr hdr;
1481 u16 entry;
1482 };
1483
1484 struct npc_mcam_shift_entry_req {
1485 struct mbox_msghdr hdr;
1486 #define NPC_MCAM_MAX_SHIFTS 64
1487 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1488 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1489 u16 shift_count; /* Number of entries to shift */
1490 };
1491
1492 struct npc_mcam_shift_entry_rsp {
1493 struct mbox_msghdr hdr;
1494 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1495 };
1496
1497 struct npc_mcam_alloc_counter_req {
1498 struct mbox_msghdr hdr;
1499 u8 contig; /* Contiguous counters ? */
1500 #define NPC_MAX_NONCONTIG_COUNTERS 64
1501 u16 count; /* Number of counters requested */
1502 };
1503
1504 struct npc_mcam_alloc_counter_rsp {
1505 struct mbox_msghdr hdr;
1506 u16 cntr; /* Counter allocated or start index if contiguous.
1507 * Invalid incase of non-contiguous.
1508 */
1509 u16 count; /* Number of counters allocated */
1510 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1511 };
1512
1513 struct npc_mcam_oper_counter_req {
1514 struct mbox_msghdr hdr;
1515 u16 cntr; /* Free a counter or clear/fetch it's stats */
1516 };
1517
1518 struct npc_mcam_oper_counter_rsp {
1519 struct mbox_msghdr hdr;
1520 u64 stat; /* valid only while fetching counter's stats */
1521 };
1522
1523 struct npc_mcam_unmap_counter_req {
1524 struct mbox_msghdr hdr;
1525 u16 cntr;
1526 u16 entry; /* Entry and counter to be unmapped */
1527 u8 all; /* Unmap all entries using this counter ? */
1528 };
1529
1530 struct npc_mcam_alloc_and_write_entry_req {
1531 struct mbox_msghdr hdr;
1532 struct mcam_entry entry_data;
1533 u16 ref_entry;
1534 u8 priority; /* Lower or higher w.r.t ref_entry */
1535 u8 intf; /* Rx or Tx interface */
1536 u8 enable_entry;/* Enable this MCAM entry ? */
1537 u8 alloc_cntr; /* Allocate counter and map ? */
1538 };
1539
1540 struct npc_mcam_alloc_and_write_entry_rsp {
1541 struct mbox_msghdr hdr;
1542 u16 entry;
1543 u16 cntr;
1544 };
1545
1546 struct npc_get_kex_cfg_rsp {
1547 struct mbox_msghdr hdr;
1548 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1549 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1550 #define NPC_MAX_INTF 2
1551 #define NPC_MAX_LID 8
1552 #define NPC_MAX_LT 16
1553 #define NPC_MAX_LD 2
1554 #define NPC_MAX_LFL 16
1555 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1556 u64 kex_ld_flags[NPC_MAX_LD];
1557 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1558 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1559 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1560 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1561 #define MKEX_NAME_LEN 128
1562 u8 mkex_pfl_name[MKEX_NAME_LEN];
1563 };
1564
1565 struct ptp_get_cap_rsp {
1566 struct mbox_msghdr hdr;
1567 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1568 u64 cap;
1569 };
1570
1571 struct get_rep_cnt_rsp {
1572 struct mbox_msghdr hdr;
1573 u16 rep_cnt;
1574 u16 rep_pf_map[64];
1575 u64 rsvd;
1576 };
1577
1578 struct esw_cfg_req {
1579 struct mbox_msghdr hdr;
1580 u8 ena;
1581 u64 rsvd;
1582 };
1583
1584 struct rep_evt_data {
1585 u8 port_state;
1586 u8 vf_state;
1587 u16 rx_mode;
1588 u16 rx_flags;
1589 u16 mtu;
1590 u8 mac[ETH_ALEN];
1591 u64 rsvd[5];
1592 };
1593
1594 struct rep_event {
1595 struct mbox_msghdr hdr;
1596 u16 pcifunc;
1597 #define RVU_EVENT_PORT_STATE BIT_ULL(0)
1598 #define RVU_EVENT_PFVF_STATE BIT_ULL(1)
1599 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2)
1600 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3)
1601 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4)
1602 u16 event;
1603 struct rep_evt_data evt_data;
1604 };
1605
1606 struct flow_msg {
1607 unsigned char dmac[6];
1608 unsigned char smac[6];
1609 __be16 etype;
1610 __be16 vlan_etype;
1611 __be16 vlan_tci;
1612 union {
1613 __be32 ip4src;
1614 __be32 ip6src[4];
1615 };
1616 union {
1617 __be32 ip4dst;
1618 __be32 ip6dst[4];
1619 };
1620 union {
1621 __be32 spi;
1622 };
1623
1624 u8 tos;
1625 u8 ip_ver;
1626 u8 ip_proto;
1627 u8 tc;
1628 __be16 sport;
1629 __be16 dport;
1630 union {
1631 u8 ip_flag;
1632 u8 next_header;
1633 };
1634 __be16 vlan_itci;
1635 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1636 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1637 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1638 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1639 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1640 u32 mpls_lse[4];
1641 u8 icmp_type;
1642 u8 icmp_code;
1643 __be16 tcp_flags;
1644 u16 sq_id;
1645 };
1646
1647 struct npc_install_flow_req {
1648 struct mbox_msghdr hdr;
1649 struct flow_msg packet;
1650 struct flow_msg mask;
1651 u64 features;
1652 u16 entry;
1653 u16 channel;
1654 u16 chan_mask;
1655 u8 intf;
1656 u8 set_cntr; /* If counter is available set counter for this entry ? */
1657 u8 default_rule;
1658 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1659 u16 vf;
1660 /* action */
1661 u32 index;
1662 u16 match_id;
1663 u8 flow_key_alg;
1664 u8 op;
1665 /* vtag rx action */
1666 u8 vtag0_type;
1667 u8 vtag0_valid;
1668 u8 vtag1_type;
1669 u8 vtag1_valid;
1670 /* vtag tx action */
1671 u16 vtag0_def;
1672 u8 vtag0_op;
1673 u16 vtag1_def;
1674 u8 vtag1_op;
1675 /* old counter value */
1676 u16 cntr_val;
1677 };
1678
1679 struct npc_install_flow_rsp {
1680 struct mbox_msghdr hdr;
1681 int counter; /* negative if no counter else counter number */
1682 };
1683
1684 struct npc_delete_flow_req {
1685 struct mbox_msghdr hdr;
1686 u16 entry;
1687 u16 start;/*Disable range of entries */
1688 u16 end;
1689 u8 all; /* PF + VFs */
1690 };
1691
1692 struct npc_delete_flow_rsp {
1693 struct mbox_msghdr hdr;
1694 u16 cntr_val;
1695 };
1696
1697 struct npc_mcam_read_entry_req {
1698 struct mbox_msghdr hdr;
1699 u16 entry; /* MCAM entry to read */
1700 };
1701
1702 struct npc_mcam_read_entry_rsp {
1703 struct mbox_msghdr hdr;
1704 struct mcam_entry entry_data;
1705 u8 intf;
1706 u8 enable;
1707 };
1708
1709 struct npc_mcam_read_base_rule_rsp {
1710 struct mbox_msghdr hdr;
1711 struct mcam_entry entry;
1712 };
1713
1714 struct npc_mcam_get_stats_req {
1715 struct mbox_msghdr hdr;
1716 u16 entry; /* mcam entry */
1717 };
1718
1719 struct npc_mcam_get_stats_rsp {
1720 struct mbox_msghdr hdr;
1721 u64 stat; /* counter stats */
1722 u8 stat_ena; /* enabled */
1723 };
1724
1725 struct npc_get_field_hash_info_req {
1726 struct mbox_msghdr hdr;
1727 u8 intf;
1728 };
1729
1730 struct npc_get_field_hash_info_rsp {
1731 struct mbox_msghdr hdr;
1732 u64 secret_key[3];
1733 #define NPC_MAX_HASH 2
1734 #define NPC_MAX_HASH_MASK 2
1735 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1736 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1737 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1738 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1739 };
1740
1741 enum ptp_op {
1742 PTP_OP_ADJFINE = 0,
1743 PTP_OP_GET_CLOCK = 1,
1744 PTP_OP_GET_TSTMP = 2,
1745 PTP_OP_SET_THRESH = 3,
1746 PTP_OP_PPS_ON = 4,
1747 PTP_OP_ADJTIME = 5,
1748 PTP_OP_SET_CLOCK = 6,
1749 };
1750
1751 struct ptp_req {
1752 struct mbox_msghdr hdr;
1753 u8 op;
1754 s64 scaled_ppm;
1755 u64 thresh;
1756 u64 period;
1757 int pps_on;
1758 s64 delta;
1759 u64 clk;
1760 };
1761
1762 struct ptp_rsp {
1763 struct mbox_msghdr hdr;
1764 u64 clk;
1765 u64 tsc;
1766 };
1767
1768 struct npc_get_field_status_req {
1769 struct mbox_msghdr hdr;
1770 u8 intf;
1771 u8 field;
1772 };
1773
1774 struct npc_get_field_status_rsp {
1775 struct mbox_msghdr hdr;
1776 u8 enable;
1777 };
1778
1779 struct set_vf_perm {
1780 struct mbox_msghdr hdr;
1781 u16 vf;
1782 #define RESET_VF_PERM BIT_ULL(0)
1783 #define VF_TRUSTED BIT_ULL(1)
1784 u64 flags;
1785 };
1786
1787 struct lmtst_tbl_setup_req {
1788 struct mbox_msghdr hdr;
1789 u64 dis_sched_early_comp :1;
1790 u64 sch_ena :1;
1791 u64 dis_line_pref :1;
1792 u64 ssow_pf_func :13;
1793 u16 base_pcifunc;
1794 u8 use_local_lmt_region;
1795 u64 lmt_iova;
1796 u64 rsvd[4];
1797 };
1798
1799 struct ndc_sync_op {
1800 struct mbox_msghdr hdr;
1801 u8 nix_lf_tx_sync;
1802 u8 nix_lf_rx_sync;
1803 u8 npa_lf_sync;
1804 };
1805
1806 /* CPT mailbox error codes
1807 * Range 901 - 1000.
1808 */
1809 enum cpt_af_status {
1810 CPT_AF_ERR_PARAM = -901,
1811 CPT_AF_ERR_GRP_INVALID = -902,
1812 CPT_AF_ERR_LF_INVALID = -903,
1813 CPT_AF_ERR_ACCESS_DENIED = -904,
1814 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1815 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1816 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1817 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1818 };
1819
1820 /* CPT mbox message formats */
1821 struct cpt_rd_wr_reg_msg {
1822 struct mbox_msghdr hdr;
1823 u64 reg_offset;
1824 u64 *ret_val;
1825 u64 val;
1826 u8 is_write;
1827 int blkaddr;
1828 };
1829
1830 struct cpt_lf_alloc_req_msg {
1831 struct mbox_msghdr hdr;
1832 u16 nix_pf_func;
1833 u16 sso_pf_func;
1834 u16 eng_grpmsk;
1835 u8 blkaddr;
1836 u8 ctx_ilen_valid : 1;
1837 u8 ctx_ilen : 7;
1838 };
1839
1840 #define CPT_INLINE_INBOUND 0
1841 #define CPT_INLINE_OUTBOUND 1
1842
1843 /* Mailbox message request format for CPT IPsec
1844 * inline inbound and outbound configuration.
1845 */
1846 struct cpt_inline_ipsec_cfg_msg {
1847 struct mbox_msghdr hdr;
1848 u8 enable;
1849 u8 slot;
1850 u8 dir;
1851 u8 sso_pf_func_ovrd;
1852 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1853 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1854 };
1855
1856 /* Mailbox message request and response format for CPT stats. */
1857 struct cpt_sts_req {
1858 struct mbox_msghdr hdr;
1859 u8 blkaddr;
1860 };
1861
1862 struct cpt_sts_rsp {
1863 struct mbox_msghdr hdr;
1864 u64 inst_req_pc;
1865 u64 inst_lat_pc;
1866 u64 rd_req_pc;
1867 u64 rd_lat_pc;
1868 u64 rd_uc_pc;
1869 u64 active_cycles_pc;
1870 u64 ctx_mis_pc;
1871 u64 ctx_hit_pc;
1872 u64 ctx_aop_pc;
1873 u64 ctx_aop_lat_pc;
1874 u64 ctx_ifetch_pc;
1875 u64 ctx_ifetch_lat_pc;
1876 u64 ctx_ffetch_pc;
1877 u64 ctx_ffetch_lat_pc;
1878 u64 ctx_wback_pc;
1879 u64 ctx_wback_lat_pc;
1880 u64 ctx_psh_pc;
1881 u64 ctx_psh_lat_pc;
1882 u64 ctx_err;
1883 u64 ctx_enc_id;
1884 u64 ctx_flush_timer;
1885 u64 rxc_time;
1886 u64 rxc_time_cfg;
1887 u64 rxc_active_sts;
1888 u64 rxc_zombie_sts;
1889 u64 busy_sts_ae;
1890 u64 free_sts_ae;
1891 u64 busy_sts_se;
1892 u64 free_sts_se;
1893 u64 busy_sts_ie;
1894 u64 free_sts_ie;
1895 u64 exe_err_info;
1896 u64 cptclk_cnt;
1897 u64 diag;
1898 u64 rxc_dfrg;
1899 u64 x2p_link_cfg0;
1900 u64 x2p_link_cfg1;
1901 };
1902
1903 /* Mailbox message request format to configure reassembly timeout. */
1904 struct cpt_rxc_time_cfg_req {
1905 struct mbox_msghdr hdr;
1906 int blkaddr;
1907 u32 step;
1908 u16 zombie_thres;
1909 u16 zombie_limit;
1910 u16 active_thres;
1911 u16 active_limit;
1912 };
1913
1914 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1915 struct cpt_inst_lmtst_req {
1916 struct mbox_msghdr hdr;
1917 u64 inst[8];
1918 u64 rsvd;
1919 };
1920
1921 /* Mailbox message format to request for CPT LF reset */
1922 struct cpt_lf_rst_req {
1923 struct mbox_msghdr hdr;
1924 u32 slot;
1925 u32 rsvd;
1926 };
1927
1928 /* Mailbox message format to request for CPT faulted engines */
1929 struct cpt_flt_eng_info_req {
1930 struct mbox_msghdr hdr;
1931 int blkaddr;
1932 bool reset;
1933 u32 rsvd;
1934 };
1935
1936 struct cpt_flt_eng_info_rsp {
1937 struct mbox_msghdr hdr;
1938 #define CPT_AF_MAX_FLT_INT_VECS 3
1939 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1940 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS];
1941 u64 rsvd;
1942 };
1943
1944 struct sdp_node_info {
1945 /* Node to which this PF belons to */
1946 u8 node_id;
1947 u8 max_vfs;
1948 u8 num_pf_rings;
1949 u8 pf_srn;
1950 #define SDP_MAX_VFS 128
1951 u8 vf_rings[SDP_MAX_VFS];
1952 };
1953
1954 struct sdp_chan_info_msg {
1955 struct mbox_msghdr hdr;
1956 struct sdp_node_info info;
1957 };
1958
1959 struct sdp_get_chan_info_msg {
1960 struct mbox_msghdr hdr;
1961 u16 chan_base;
1962 u16 num_chan;
1963 };
1964
1965 /* CGX mailbox error codes
1966 * Range 1101 - 1200.
1967 */
1968 enum cgx_af_status {
1969 LMAC_AF_ERR_INVALID_PARAM = -1101,
1970 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1971 LMAC_AF_ERR_PERM_DENIED = -1103,
1972 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1973 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1974 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1975 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1976 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1977 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1978 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1979 };
1980
1981 enum mcs_direction {
1982 MCS_RX,
1983 MCS_TX,
1984 };
1985
1986 enum mcs_rsrc_type {
1987 MCS_RSRC_TYPE_FLOWID,
1988 MCS_RSRC_TYPE_SECY,
1989 MCS_RSRC_TYPE_SC,
1990 MCS_RSRC_TYPE_SA,
1991 };
1992
1993 struct mcs_alloc_rsrc_req {
1994 struct mbox_msghdr hdr;
1995 u8 rsrc_type;
1996 u8 rsrc_cnt; /* Resources count */
1997 u8 mcs_id; /* MCS block ID */
1998 u8 dir; /* Macsec ingress or egress side */
1999 u8 all; /* Allocate all resource type one each */
2000 u64 rsvd;
2001 };
2002
2003 struct mcs_alloc_rsrc_rsp {
2004 struct mbox_msghdr hdr;
2005 u8 flow_ids[128]; /* Index of reserved entries */
2006 u8 secy_ids[128];
2007 u8 sc_ids[128];
2008 u8 sa_ids[256];
2009 u8 rsrc_type;
2010 u8 rsrc_cnt; /* No of entries reserved */
2011 u8 mcs_id;
2012 u8 dir;
2013 u8 all;
2014 u8 rsvd[256]; /* reserved fields for future expansion */
2015 };
2016
2017 struct mcs_free_rsrc_req {
2018 struct mbox_msghdr hdr;
2019 u8 rsrc_id; /* Index of the entry to be freed */
2020 u8 rsrc_type;
2021 u8 mcs_id;
2022 u8 dir;
2023 u8 all; /* Free all the cam resources */
2024 u64 rsvd;
2025 };
2026
2027 struct mcs_flowid_entry_write_req {
2028 struct mbox_msghdr hdr;
2029 u64 data[4];
2030 u64 mask[4];
2031 u64 sci; /* CNF10K-B for tx_secy_mem_map */
2032 u8 flow_id;
2033 u8 secy_id; /* secyid for which flowid is mapped */
2034 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
2035 u8 ena; /* Enable tcam entry */
2036 u8 ctrl_pkt;
2037 u8 mcs_id;
2038 u8 dir;
2039 u64 rsvd;
2040 };
2041
2042 struct mcs_secy_plcy_write_req {
2043 struct mbox_msghdr hdr;
2044 u64 plcy;
2045 u8 secy_id;
2046 u8 mcs_id;
2047 u8 dir;
2048 u64 rsvd;
2049 };
2050
2051 /* RX SC_CAM mapping */
2052 struct mcs_rx_sc_cam_write_req {
2053 struct mbox_msghdr hdr;
2054 u64 sci; /* SCI */
2055 u64 secy_id; /* secy index mapped to SC */
2056 u8 sc_id; /* SC CAM entry index */
2057 u8 mcs_id;
2058 u64 rsvd;
2059 };
2060
2061 struct mcs_sa_plcy_write_req {
2062 struct mbox_msghdr hdr;
2063 u64 plcy[2][9]; /* Support 2 SA policy */
2064 u8 sa_index[2];
2065 u8 sa_cnt;
2066 u8 mcs_id;
2067 u8 dir;
2068 u64 rsvd;
2069 };
2070
2071 struct mcs_tx_sc_sa_map {
2072 struct mbox_msghdr hdr;
2073 u8 sa_index0;
2074 u8 sa_index1;
2075 u8 rekey_ena;
2076 u8 sa_index0_vld;
2077 u8 sa_index1_vld;
2078 u8 tx_sa_active;
2079 u64 sectag_sci;
2080 u8 sc_id; /* used as index for SA_MEM_MAP */
2081 u8 mcs_id;
2082 u64 rsvd;
2083 };
2084
2085 struct mcs_rx_sc_sa_map {
2086 struct mbox_msghdr hdr;
2087 u8 sa_index;
2088 u8 sa_in_use;
2089 u8 sc_id;
2090 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
2091 u8 mcs_id;
2092 u64 rsvd;
2093 };
2094
2095 struct mcs_flowid_ena_dis_entry {
2096 struct mbox_msghdr hdr;
2097 u8 flow_id;
2098 u8 ena;
2099 u8 mcs_id;
2100 u8 dir;
2101 u64 rsvd;
2102 };
2103
2104 struct mcs_pn_table_write_req {
2105 struct mbox_msghdr hdr;
2106 u64 next_pn;
2107 u8 pn_id;
2108 u8 mcs_id;
2109 u8 dir;
2110 u64 rsvd;
2111 };
2112
2113 struct mcs_hw_info {
2114 struct mbox_msghdr hdr;
2115 u8 num_mcs_blks; /* Number of MCS blocks */
2116 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2117 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2118 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2119 u16 sa_entries; /* PN table entries = SA entries */
2120 u64 rsvd[16];
2121 };
2122
2123 struct mcs_set_active_lmac {
2124 struct mbox_msghdr hdr;
2125 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2126 u8 mcs_id;
2127 u16 chan_base; /* MCS channel base */
2128 u64 rsvd;
2129 };
2130
2131 struct mcs_set_lmac_mode {
2132 struct mbox_msghdr hdr;
2133 u8 mode; /* 1:Bypass 0:Operational */
2134 u8 lmac_id;
2135 u8 mcs_id;
2136 u64 rsvd;
2137 };
2138
2139 struct mcs_port_reset_req {
2140 struct mbox_msghdr hdr;
2141 u8 reset;
2142 u8 mcs_id;
2143 u8 port_id;
2144 u64 rsvd;
2145 };
2146
2147 struct mcs_port_cfg_set_req {
2148 struct mbox_msghdr hdr;
2149 u8 cstm_tag_rel_mode_sel;
2150 u8 custom_hdr_enb;
2151 u8 fifo_skid;
2152 u8 port_mode;
2153 u8 port_id;
2154 u8 mcs_id;
2155 u64 rsvd;
2156 };
2157
2158 struct mcs_port_cfg_get_req {
2159 struct mbox_msghdr hdr;
2160 u8 port_id;
2161 u8 mcs_id;
2162 u64 rsvd;
2163 };
2164
2165 struct mcs_port_cfg_get_rsp {
2166 struct mbox_msghdr hdr;
2167 u8 cstm_tag_rel_mode_sel;
2168 u8 custom_hdr_enb;
2169 u8 fifo_skid;
2170 u8 port_mode;
2171 u8 port_id;
2172 u8 mcs_id;
2173 u64 rsvd;
2174 };
2175
2176 struct mcs_custom_tag_cfg_get_req {
2177 struct mbox_msghdr hdr;
2178 u8 mcs_id;
2179 u8 dir;
2180 u64 rsvd;
2181 };
2182
2183 struct mcs_custom_tag_cfg_get_rsp {
2184 struct mbox_msghdr hdr;
2185 u16 cstm_etype[8];
2186 u8 cstm_indx[8];
2187 u8 cstm_etype_en;
2188 u8 mcs_id;
2189 u8 dir;
2190 u64 rsvd;
2191 };
2192
2193 /* MCS mailbox error codes
2194 * Range 1201 - 1300.
2195 */
2196 enum mcs_af_status {
2197 MCS_AF_ERR_INVALID_MCSID = -1201,
2198 MCS_AF_ERR_NOT_MAPPED = -1202,
2199 };
2200
2201 struct mcs_set_pn_threshold {
2202 struct mbox_msghdr hdr;
2203 u64 threshold;
2204 u8 xpn; /* '1' for setting xpn threshold */
2205 u8 mcs_id;
2206 u8 dir;
2207 u64 rsvd;
2208 };
2209
2210 enum mcs_ctrl_pkt_rulew_type {
2211 MCS_CTRL_PKT_RULE_TYPE_ETH,
2212 MCS_CTRL_PKT_RULE_TYPE_DA,
2213 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2214 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2215 MCS_CTRL_PKT_RULE_TYPE_MAC,
2216 };
2217
2218 struct mcs_alloc_ctrl_pkt_rule_req {
2219 struct mbox_msghdr hdr;
2220 u8 rule_type;
2221 u8 mcs_id; /* MCS block ID */
2222 u8 dir; /* Macsec ingress or egress side */
2223 u64 rsvd;
2224 };
2225
2226 struct mcs_alloc_ctrl_pkt_rule_rsp {
2227 struct mbox_msghdr hdr;
2228 u8 rule_idx;
2229 u8 rule_type;
2230 u8 mcs_id;
2231 u8 dir;
2232 u64 rsvd;
2233 };
2234
2235 struct mcs_free_ctrl_pkt_rule_req {
2236 struct mbox_msghdr hdr;
2237 u8 rule_idx;
2238 u8 rule_type;
2239 u8 mcs_id;
2240 u8 dir;
2241 u8 all;
2242 u64 rsvd;
2243 };
2244
2245 struct mcs_ctrl_pkt_rule_write_req {
2246 struct mbox_msghdr hdr;
2247 u64 data0;
2248 u64 data1;
2249 u64 data2;
2250 u8 rule_idx;
2251 u8 rule_type;
2252 u8 mcs_id;
2253 u8 dir;
2254 u64 rsvd;
2255 };
2256
2257 struct mcs_stats_req {
2258 struct mbox_msghdr hdr;
2259 u8 id;
2260 u8 mcs_id;
2261 u8 dir;
2262 u64 rsvd;
2263 };
2264
2265 struct mcs_flowid_stats {
2266 struct mbox_msghdr hdr;
2267 u64 tcam_hit_cnt;
2268 u64 rsvd;
2269 };
2270
2271 struct mcs_secy_stats {
2272 struct mbox_msghdr hdr;
2273 u64 ctl_pkt_bcast_cnt;
2274 u64 ctl_pkt_mcast_cnt;
2275 u64 ctl_pkt_ucast_cnt;
2276 u64 ctl_octet_cnt;
2277 u64 unctl_pkt_bcast_cnt;
2278 u64 unctl_pkt_mcast_cnt;
2279 u64 unctl_pkt_ucast_cnt;
2280 u64 unctl_octet_cnt;
2281 /* Valid only for RX */
2282 u64 octet_decrypted_cnt;
2283 u64 octet_validated_cnt;
2284 u64 pkt_port_disabled_cnt;
2285 u64 pkt_badtag_cnt;
2286 u64 pkt_nosa_cnt;
2287 u64 pkt_nosaerror_cnt;
2288 u64 pkt_tagged_ctl_cnt;
2289 u64 pkt_untaged_cnt;
2290 u64 pkt_ctl_cnt; /* CN10K-B */
2291 u64 pkt_notag_cnt; /* CNF10K-B */
2292 /* Valid only for TX */
2293 u64 octet_encrypted_cnt;
2294 u64 octet_protected_cnt;
2295 u64 pkt_noactivesa_cnt;
2296 u64 pkt_toolong_cnt;
2297 u64 pkt_untagged_cnt;
2298 u64 rsvd[4];
2299 };
2300
2301 struct mcs_port_stats {
2302 struct mbox_msghdr hdr;
2303 u64 tcam_miss_cnt;
2304 u64 parser_err_cnt;
2305 u64 preempt_err_cnt; /* CNF10K-B */
2306 u64 sectag_insert_err_cnt;
2307 u64 rsvd[4];
2308 };
2309
2310 /* Only for CN10K-B */
2311 struct mcs_sa_stats {
2312 struct mbox_msghdr hdr;
2313 /* RX */
2314 u64 pkt_invalid_cnt;
2315 u64 pkt_nosaerror_cnt;
2316 u64 pkt_notvalid_cnt;
2317 u64 pkt_ok_cnt;
2318 u64 pkt_nosa_cnt;
2319 /* TX */
2320 u64 pkt_encrypt_cnt;
2321 u64 pkt_protected_cnt;
2322 u64 rsvd[4];
2323 };
2324
2325 struct mcs_sc_stats {
2326 struct mbox_msghdr hdr;
2327 /* RX */
2328 u64 hit_cnt;
2329 u64 pkt_invalid_cnt;
2330 u64 pkt_late_cnt;
2331 u64 pkt_notvalid_cnt;
2332 u64 pkt_unchecked_cnt;
2333 u64 pkt_delay_cnt; /* CNF10K-B */
2334 u64 pkt_ok_cnt; /* CNF10K-B */
2335 u64 octet_decrypt_cnt; /* CN10K-B */
2336 u64 octet_validate_cnt; /* CN10K-B */
2337 /* TX */
2338 u64 pkt_encrypt_cnt;
2339 u64 pkt_protected_cnt;
2340 u64 octet_encrypt_cnt; /* CN10K-B */
2341 u64 octet_protected_cnt; /* CN10K-B */
2342 u64 rsvd[4];
2343 };
2344
2345 struct mcs_clear_stats {
2346 struct mbox_msghdr hdr;
2347 #define MCS_FLOWID_STATS 0
2348 #define MCS_SECY_STATS 1
2349 #define MCS_SC_STATS 2
2350 #define MCS_SA_STATS 3
2351 #define MCS_PORT_STATS 4
2352 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2353 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2354 u8 mcs_id;
2355 u8 dir;
2356 u8 all; /* All resources stats mapped to PF are cleared */
2357 };
2358
2359 struct mcs_intr_cfg {
2360 struct mbox_msghdr hdr;
2361 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2362 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2363 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2364 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2365 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2366 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2367 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2368 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2369 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2370 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2371 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2372 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2373 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2374 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2375 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2376 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2377 u64 intr_mask; /* Interrupt enable mask */
2378 u8 mcs_id;
2379 u8 lmac_id;
2380 u64 rsvd;
2381 };
2382
2383 struct mcs_intr_info {
2384 struct mbox_msghdr hdr;
2385 u64 intr_mask;
2386 int sa_id;
2387 u8 mcs_id;
2388 u8 lmac_id;
2389 u64 rsvd;
2390 };
2391
2392 #endif /* MBOX_H */
2393