1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
3
4 #include "ixgbe_x540.h"
5 #include "ixgbe_x550.h"
6 #include "ixgbe_type.h"
7 #include "ixgbe_common.h"
8 #include "ixgbe_mbx.h"
9 #include "ixgbe_phy.h"
10
11 static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
12 static int ixgbe_setup_fc_x550em(struct ixgbe_hw *);
13 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
14 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
15 static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
16
ixgbe_get_invariants_X550_x(struct ixgbe_hw * hw)17 static int ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
18 {
19 struct ixgbe_mac_info *mac = &hw->mac;
20 struct ixgbe_phy_info *phy = &hw->phy;
21 struct ixgbe_link_info *link = &hw->link;
22
23 /* Start with X540 invariants, since so simular */
24 ixgbe_get_invariants_X540(hw);
25
26 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
27 phy->ops.set_phy_power = NULL;
28
29 link->addr = IXGBE_CS4227;
30
31 return 0;
32 }
33
ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw * hw)34 static int ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
35 {
36 struct ixgbe_phy_info *phy = &hw->phy;
37
38 /* Start with X540 invariants, since so similar */
39 ixgbe_get_invariants_X540(hw);
40
41 phy->ops.set_phy_power = NULL;
42
43 return 0;
44 }
45
ixgbe_get_invariants_X550_a(struct ixgbe_hw * hw)46 static int ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
47 {
48 struct ixgbe_mac_info *mac = &hw->mac;
49 struct ixgbe_phy_info *phy = &hw->phy;
50
51 /* Start with X540 invariants, since so simular */
52 ixgbe_get_invariants_X540(hw);
53
54 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
55 phy->ops.set_phy_power = NULL;
56
57 return 0;
58 }
59
ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw * hw)60 static int ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
61 {
62 struct ixgbe_phy_info *phy = &hw->phy;
63
64 /* Start with X540 invariants, since so similar */
65 ixgbe_get_invariants_X540(hw);
66
67 phy->ops.set_phy_power = NULL;
68
69 return 0;
70 }
71
72 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
73 * @hw: pointer to hardware structure
74 **/
ixgbe_setup_mux_ctl(struct ixgbe_hw * hw)75 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
76 {
77 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
78
79 if (hw->bus.lan_id) {
80 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
81 esdp |= IXGBE_ESDP_SDP1_DIR;
82 }
83 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
84 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
85 IXGBE_WRITE_FLUSH(hw);
86 }
87
88 /**
89 * ixgbe_read_cs4227 - Read CS4227 register
90 * @hw: pointer to hardware structure
91 * @reg: register number to write
92 * @value: pointer to receive value read
93 *
94 * Returns status code
95 */
ixgbe_read_cs4227(struct ixgbe_hw * hw,u16 reg,u16 * value)96 static int ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
97 {
98 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
99 }
100
101 /**
102 * ixgbe_write_cs4227 - Write CS4227 register
103 * @hw: pointer to hardware structure
104 * @reg: register number to write
105 * @value: value to write to register
106 *
107 * Returns status code
108 */
ixgbe_write_cs4227(struct ixgbe_hw * hw,u16 reg,u16 value)109 static int ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
110 {
111 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
112 }
113
114 /**
115 * ixgbe_read_pe - Read register from port expander
116 * @hw: pointer to hardware structure
117 * @reg: register number to read
118 * @value: pointer to receive read value
119 *
120 * Returns status code
121 */
ixgbe_read_pe(struct ixgbe_hw * hw,u8 reg,u8 * value)122 static int ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
123 {
124 int status;
125
126 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
127 if (status)
128 hw_err(hw, "port expander access failed with %d\n", status);
129 return status;
130 }
131
132 /**
133 * ixgbe_write_pe - Write register to port expander
134 * @hw: pointer to hardware structure
135 * @reg: register number to write
136 * @value: value to write
137 *
138 * Returns status code
139 */
ixgbe_write_pe(struct ixgbe_hw * hw,u8 reg,u8 value)140 static int ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
141 {
142 int status;
143
144 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
145 value);
146 if (status)
147 hw_err(hw, "port expander access failed with %d\n", status);
148 return status;
149 }
150
151 /**
152 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
153 * @hw: pointer to hardware structure
154 *
155 * This function assumes that the caller has acquired the proper semaphore.
156 * Returns error code
157 */
ixgbe_reset_cs4227(struct ixgbe_hw * hw)158 static int ixgbe_reset_cs4227(struct ixgbe_hw *hw)
159 {
160 int status;
161 u32 retry;
162 u16 value;
163 u8 reg;
164
165 /* Trigger hard reset. */
166 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
167 if (status)
168 return status;
169 reg |= IXGBE_PE_BIT1;
170 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
171 if (status)
172 return status;
173
174 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
175 if (status)
176 return status;
177 reg &= ~IXGBE_PE_BIT1;
178 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
179 if (status)
180 return status;
181
182 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
183 if (status)
184 return status;
185 reg &= ~IXGBE_PE_BIT1;
186 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
187 if (status)
188 return status;
189
190 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
191
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status)
194 return status;
195 reg |= IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status)
198 return status;
199
200 /* Wait for the reset to complete. */
201 msleep(IXGBE_CS4227_RESET_DELAY);
202 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
203 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
204 &value);
205 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
206 break;
207 msleep(IXGBE_CS4227_CHECK_DELAY);
208 }
209 if (retry == IXGBE_CS4227_RETRIES) {
210 hw_err(hw, "CS4227 reset did not complete\n");
211 return -EIO;
212 }
213
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
215 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
216 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
217 return -EIO;
218 }
219
220 return 0;
221 }
222
223 /**
224 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
225 * @hw: pointer to hardware structure
226 */
ixgbe_check_cs4227(struct ixgbe_hw * hw)227 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
228 {
229 u32 swfw_mask = hw->phy.phy_semaphore_mask;
230 int status;
231 u16 value;
232 u8 retry;
233
234 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
235 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
236 if (status) {
237 hw_err(hw, "semaphore failed with %d\n", status);
238 msleep(IXGBE_CS4227_CHECK_DELAY);
239 continue;
240 }
241
242 /* Get status of reset flow. */
243 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
244 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
245 goto out;
246
247 if (status || value != IXGBE_CS4227_RESET_PENDING)
248 break;
249
250 /* Reset is pending. Wait and check again. */
251 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
252 msleep(IXGBE_CS4227_CHECK_DELAY);
253 }
254 /* If still pending, assume other instance failed. */
255 if (retry == IXGBE_CS4227_RETRIES) {
256 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
257 if (status) {
258 hw_err(hw, "semaphore failed with %d\n", status);
259 return;
260 }
261 }
262
263 /* Reset the CS4227. */
264 status = ixgbe_reset_cs4227(hw);
265 if (status) {
266 hw_err(hw, "CS4227 reset failed: %d", status);
267 goto out;
268 }
269
270 /* Reset takes so long, temporarily release semaphore in case the
271 * other driver instance is waiting for the reset indication.
272 */
273 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
274 IXGBE_CS4227_RESET_PENDING);
275 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
276 usleep_range(10000, 12000);
277 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
278 if (status) {
279 hw_err(hw, "semaphore failed with %d", status);
280 return;
281 }
282
283 /* Record completion for next time. */
284 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
285 IXGBE_CS4227_RESET_COMPLETE);
286
287 out:
288 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
289 msleep(hw->eeprom.semaphore_delay);
290 }
291
292 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
293 * @hw: pointer to hardware structure
294 *
295 * Returns error code
296 */
ixgbe_identify_phy_x550em(struct ixgbe_hw * hw)297 static int ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
298 {
299 switch (hw->device_id) {
300 case IXGBE_DEV_ID_X550EM_A_SFP:
301 if (hw->bus.lan_id)
302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
303 else
304 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
305 return ixgbe_identify_module_generic(hw);
306 case IXGBE_DEV_ID_X550EM_X_SFP:
307 /* set up for CS4227 usage */
308 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
309 ixgbe_setup_mux_ctl(hw);
310 ixgbe_check_cs4227(hw);
311 fallthrough;
312 case IXGBE_DEV_ID_X550EM_A_SFP_N:
313 return ixgbe_identify_module_generic(hw);
314 case IXGBE_DEV_ID_X550EM_X_KX4:
315 hw->phy.type = ixgbe_phy_x550em_kx4;
316 break;
317 case IXGBE_DEV_ID_X550EM_X_XFI:
318 hw->phy.type = ixgbe_phy_x550em_xfi;
319 break;
320 case IXGBE_DEV_ID_X550EM_X_KR:
321 case IXGBE_DEV_ID_X550EM_A_KR:
322 case IXGBE_DEV_ID_X550EM_A_KR_L:
323 hw->phy.type = ixgbe_phy_x550em_kr;
324 break;
325 case IXGBE_DEV_ID_X550EM_A_10G_T:
326 if (hw->bus.lan_id)
327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
328 else
329 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
330 fallthrough;
331 case IXGBE_DEV_ID_X550EM_X_10G_T:
332 return ixgbe_identify_phy_generic(hw);
333 case IXGBE_DEV_ID_X550EM_X_1G_T:
334 hw->phy.type = ixgbe_phy_ext_1g_t;
335 break;
336 case IXGBE_DEV_ID_X550EM_A_1G_T:
337 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
338 hw->phy.type = ixgbe_phy_fw;
339 hw->phy.ops.read_reg = NULL;
340 hw->phy.ops.write_reg = NULL;
341 if (hw->bus.lan_id)
342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
343 else
344 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
345 break;
346 default:
347 break;
348 }
349 return 0;
350 }
351
ixgbe_read_phy_reg_x550em(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)352 static int ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
353 u32 device_type, u16 *phy_data)
354 {
355 return -EOPNOTSUPP;
356 }
357
ixgbe_write_phy_reg_x550em(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)358 static int ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
359 u32 device_type, u16 phy_data)
360 {
361 return -EOPNOTSUPP;
362 }
363
364 /**
365 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
366 * @hw: pointer to the hardware structure
367 * @addr: I2C bus address to read from
368 * @reg: I2C device register to read from
369 * @val: pointer to location to receive read value
370 *
371 * Returns an error code on error.
372 **/
ixgbe_read_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)373 static int ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
374 u16 reg, u16 *val)
375 {
376 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
377 }
378
379 /**
380 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
381 * @hw: pointer to the hardware structure
382 * @addr: I2C bus address to read from
383 * @reg: I2C device register to read from
384 * @val: pointer to location to receive read value
385 *
386 * Returns an error code on error.
387 **/
388 static int
ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)389 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
390 u16 reg, u16 *val)
391 {
392 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
393 }
394
395 /**
396 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
397 * @hw: pointer to the hardware structure
398 * @addr: I2C bus address to write to
399 * @reg: I2C device register to write to
400 * @val: value to write
401 *
402 * Returns an error code on error.
403 **/
ixgbe_write_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)404 static int ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
405 u8 addr, u16 reg, u16 val)
406 {
407 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
408 }
409
410 /**
411 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
412 * @hw: pointer to the hardware structure
413 * @addr: I2C bus address to write to
414 * @reg: I2C device register to write to
415 * @val: value to write
416 *
417 * Returns an error code on error.
418 **/
419 static int
ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)420 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
421 u8 addr, u16 reg, u16 val)
422 {
423 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
424 }
425
426 /**
427 * ixgbe_fw_phy_activity - Perform an activity on a PHY
428 * @hw: pointer to hardware structure
429 * @activity: activity to perform
430 * @data: Pointer to 4 32-bit words of data
431 */
ixgbe_fw_phy_activity(struct ixgbe_hw * hw,u16 activity,u32 (* data)[FW_PHY_ACT_DATA_COUNT])432 int ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
433 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
434 {
435 union {
436 struct ixgbe_hic_phy_activity_req cmd;
437 struct ixgbe_hic_phy_activity_resp rsp;
438 } hic;
439 u16 retries = FW_PHY_ACT_RETRIES;
440 int rc;
441 u32 i;
442
443 do {
444 memset(&hic, 0, sizeof(hic));
445 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
446 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
447 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
448 hic.cmd.port_number = hw->bus.lan_id;
449 hic.cmd.activity_id = cpu_to_le16(activity);
450 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
451 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
452
453 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
454 IXGBE_HI_COMMAND_TIMEOUT,
455 true);
456 if (rc)
457 return rc;
458 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
459 FW_CEM_RESP_STATUS_SUCCESS) {
460 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
461 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
462 return 0;
463 }
464 usleep_range(20, 30);
465 --retries;
466 } while (retries > 0);
467
468 return -EIO;
469 }
470
471 static const struct {
472 u16 fw_speed;
473 ixgbe_link_speed phy_speed;
474 } ixgbe_fw_map[] = {
475 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
476 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
477 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
478 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
479 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
480 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
481 };
482
483 /**
484 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
485 * @hw: pointer to hardware structure
486 *
487 * Returns error code
488 */
ixgbe_get_phy_id_fw(struct ixgbe_hw * hw)489 static int ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
490 {
491 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
492 u16 phy_speeds;
493 u16 phy_id_lo;
494 int rc;
495 u16 i;
496
497 if (hw->phy.id)
498 return 0;
499
500 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
501 if (rc)
502 return rc;
503
504 hw->phy.speeds_supported = 0;
505 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
506 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
507 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
508 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
509 }
510
511 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
512 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
513 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
514 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
515 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
516 return -EFAULT;
517
518 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
519 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
520 IXGBE_LINK_SPEED_1GB_FULL;
521 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
522 return 0;
523 }
524
525 /**
526 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
527 * @hw: pointer to hardware structure
528 *
529 * Returns error code
530 */
ixgbe_identify_phy_fw(struct ixgbe_hw * hw)531 static int ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
532 {
533 if (hw->bus.lan_id)
534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
535 else
536 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
537
538 hw->phy.type = ixgbe_phy_fw;
539 hw->phy.ops.read_reg = NULL;
540 hw->phy.ops.write_reg = NULL;
541 return ixgbe_get_phy_id_fw(hw);
542 }
543
544 /**
545 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
546 * @hw: pointer to hardware structure
547 *
548 * Returns error code
549 */
ixgbe_shutdown_fw_phy(struct ixgbe_hw * hw)550 static int ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
551 {
552 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
553
554 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
555 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
556 }
557
558 /**
559 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
560 * @hw: pointer to hardware structure
561 */
ixgbe_setup_fw_link(struct ixgbe_hw * hw)562 static int ixgbe_setup_fw_link(struct ixgbe_hw *hw)
563 {
564 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
565 int rc;
566 u16 i;
567
568 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
569 return 0;
570
571 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
572 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
573 return -EINVAL;
574 }
575
576 switch (hw->fc.requested_mode) {
577 case ixgbe_fc_full:
578 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
579 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
580 break;
581 case ixgbe_fc_rx_pause:
582 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
583 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
584 break;
585 case ixgbe_fc_tx_pause:
586 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
587 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
588 break;
589 default:
590 break;
591 }
592
593 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
594 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
595 setup[0] |= ixgbe_fw_map[i].fw_speed;
596 }
597 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
598
599 if (hw->phy.eee_speeds_advertised)
600 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
601
602 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
603 if (rc)
604 return rc;
605
606 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
607 return -EIO;
608
609 return 0;
610 }
611
612 /**
613 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
614 * @hw: pointer to hardware structure
615 *
616 * Called at init time to set up flow control.
617 */
ixgbe_fc_autoneg_fw(struct ixgbe_hw * hw)618 static int ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
619 {
620 if (hw->fc.requested_mode == ixgbe_fc_default)
621 hw->fc.requested_mode = ixgbe_fc_full;
622
623 return ixgbe_setup_fw_link(hw);
624 }
625
626 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
627 * @hw: pointer to hardware structure
628 *
629 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
630 * ixgbe_hw struct in order to set up EEPROM access.
631 **/
ixgbe_init_eeprom_params_X550(struct ixgbe_hw * hw)632 static int ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
633 {
634 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
635
636 if (eeprom->type == ixgbe_eeprom_uninitialized) {
637 u16 eeprom_size;
638 u32 eec;
639
640 eeprom->semaphore_delay = 10;
641 eeprom->type = ixgbe_flash;
642
643 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
644 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
645 eeprom->word_size = BIT(eeprom_size +
646 IXGBE_EEPROM_WORD_SIZE_SHIFT);
647
648 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
649 eeprom->type, eeprom->word_size);
650 }
651
652 return 0;
653 }
654
655 /**
656 * ixgbe_iosf_wait - Wait for IOSF command completion
657 * @hw: pointer to hardware structure
658 * @ctrl: pointer to location to receive final IOSF control value
659 *
660 * Return: failing status on timeout
661 *
662 * Note: ctrl can be NULL if the IOSF control register value is not needed
663 */
ixgbe_iosf_wait(struct ixgbe_hw * hw,u32 * ctrl)664 static int ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
665 {
666 u32 i, command;
667
668 /* Check every 10 usec to see if the address cycle completed.
669 * The SB IOSF BUSY bit will clear when the operation is
670 * complete.
671 */
672 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
673 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
674 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
675 break;
676 udelay(10);
677 }
678 if (ctrl)
679 *ctrl = command;
680 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
681 hw_dbg(hw, "IOSF wait timed out\n");
682 return -EIO;
683 }
684
685 return 0;
686 }
687
688 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
689 * IOSF device
690 * @hw: pointer to hardware structure
691 * @reg_addr: 32 bit PHY register to write
692 * @device_type: 3 bit device type
693 * @phy_data: Pointer to read data from the register
694 **/
ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u32 * data)695 static int ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
696 u32 device_type, u32 *data)
697 {
698 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
699 u32 command, error;
700 int ret;
701
702 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
703 if (ret)
704 return ret;
705
706 ret = ixgbe_iosf_wait(hw, NULL);
707 if (ret)
708 goto out;
709
710 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
711 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
712
713 /* Write IOSF control register */
714 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
715
716 ret = ixgbe_iosf_wait(hw, &command);
717
718 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
719 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
720 hw_dbg(hw, "Failed to read, error %x\n", error);
721 ret = -EIO;
722 goto out;
723 }
724
725 if (!ret)
726 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
727
728 out:
729 hw->mac.ops.release_swfw_sync(hw, gssr);
730 return ret;
731 }
732
733 /**
734 * ixgbe_get_phy_token - Get the token for shared PHY access
735 * @hw: Pointer to hardware structure
736 */
ixgbe_get_phy_token(struct ixgbe_hw * hw)737 static int ixgbe_get_phy_token(struct ixgbe_hw *hw)
738 {
739 struct ixgbe_hic_phy_token_req token_cmd;
740 int status;
741
742 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
743 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
744 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
745 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
746 token_cmd.port_number = hw->bus.lan_id;
747 token_cmd.command_type = FW_PHY_TOKEN_REQ;
748 token_cmd.pad = 0;
749 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
750 IXGBE_HI_COMMAND_TIMEOUT,
751 true);
752 if (status)
753 return status;
754 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
755 return 0;
756 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
757 return -EIO;
758
759 return -EAGAIN;
760 }
761
762 /**
763 * ixgbe_put_phy_token - Put the token for shared PHY access
764 * @hw: Pointer to hardware structure
765 */
ixgbe_put_phy_token(struct ixgbe_hw * hw)766 static int ixgbe_put_phy_token(struct ixgbe_hw *hw)
767 {
768 struct ixgbe_hic_phy_token_req token_cmd;
769 int status;
770
771 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
772 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
773 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
774 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
775 token_cmd.port_number = hw->bus.lan_id;
776 token_cmd.command_type = FW_PHY_TOKEN_REL;
777 token_cmd.pad = 0;
778 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
779 IXGBE_HI_COMMAND_TIMEOUT,
780 true);
781 if (status)
782 return status;
783 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
784 return 0;
785 return -EIO;
786 }
787
788 /**
789 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
790 * @hw: pointer to hardware structure
791 * @reg_addr: 32 bit PHY register to write
792 * @device_type: 3 bit device type
793 * @data: Data to write to the register
794 **/
ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,__always_unused u32 device_type,u32 data)795 static int ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
796 __always_unused u32 device_type,
797 u32 data)
798 {
799 struct ixgbe_hic_internal_phy_req write_cmd;
800
801 memset(&write_cmd, 0, sizeof(write_cmd));
802 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
803 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
804 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
805 write_cmd.port_number = hw->bus.lan_id;
806 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
807 write_cmd.address = cpu_to_be16(reg_addr);
808 write_cmd.write_data = cpu_to_be32(data);
809
810 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
811 IXGBE_HI_COMMAND_TIMEOUT, false);
812 }
813
814 /**
815 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
816 * @hw: pointer to hardware structure
817 * @reg_addr: 32 bit PHY register to write
818 * @device_type: 3 bit device type
819 * @data: Pointer to read data from the register
820 **/
ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,__always_unused u32 device_type,u32 * data)821 static int ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
822 __always_unused u32 device_type,
823 u32 *data)
824 {
825 union {
826 struct ixgbe_hic_internal_phy_req cmd;
827 struct ixgbe_hic_internal_phy_resp rsp;
828 } hic;
829 int status;
830
831 memset(&hic, 0, sizeof(hic));
832 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
833 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
834 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
835 hic.cmd.port_number = hw->bus.lan_id;
836 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
837 hic.cmd.address = cpu_to_be16(reg_addr);
838
839 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
840 IXGBE_HI_COMMAND_TIMEOUT, true);
841
842 /* Extract the register value from the response. */
843 *data = be32_to_cpu(hic.rsp.read_data);
844
845 return status;
846 }
847
848 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
849 * @hw: pointer to hardware structure
850 * @offset: offset of word in the EEPROM to read
851 * @words: number of words
852 * @data: word(s) read from the EEPROM
853 *
854 * Reads a 16 bit word(s) from the EEPROM using the hostif.
855 **/
ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)856 static int ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
857 u16 offset, u16 words, u16 *data)
858 {
859 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
860 struct ixgbe_hic_read_shadow_ram buffer;
861 u32 current_word = 0;
862 u16 words_to_read;
863 int status;
864 u32 i;
865
866 /* Take semaphore for the entire operation. */
867 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
868 if (status) {
869 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
870 return status;
871 }
872
873 while (words) {
874 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
875 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
876 else
877 words_to_read = words;
878
879 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
880 buffer.hdr.req.buf_lenh = 0;
881 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
882 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
883
884 /* convert offset from words to bytes */
885 buffer.address = (__force u32)cpu_to_be32((offset +
886 current_word) * 2);
887 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
888 buffer.pad2 = 0;
889 buffer.pad3 = 0;
890
891 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
892 IXGBE_HI_COMMAND_TIMEOUT);
893 if (status) {
894 hw_dbg(hw, "Host interface command failed\n");
895 goto out;
896 }
897
898 for (i = 0; i < words_to_read; i++) {
899 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
900 2 * i;
901 u32 value = IXGBE_READ_REG(hw, reg);
902
903 data[current_word] = (u16)(value & 0xffff);
904 current_word++;
905 i++;
906 if (i < words_to_read) {
907 value >>= 16;
908 data[current_word] = (u16)(value & 0xffff);
909 current_word++;
910 }
911 }
912 words -= words_to_read;
913 }
914
915 out:
916 hw->mac.ops.release_swfw_sync(hw, mask);
917 return status;
918 }
919
920 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
921 * @hw: pointer to hardware structure
922 * @ptr: pointer offset in eeprom
923 * @size: size of section pointed by ptr, if 0 first word will be used as size
924 * @csum: address of checksum to update
925 *
926 * Returns error status for any failure
927 **/
ixgbe_checksum_ptr_x550(struct ixgbe_hw * hw,u16 ptr,u16 size,u16 * csum,u16 * buffer,u32 buffer_size)928 static int ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
929 u16 size, u16 *csum, u16 *buffer,
930 u32 buffer_size)
931 {
932 u16 length, bufsz, i, start;
933 u16 *local_buffer;
934 u16 buf[256];
935 int status;
936
937 bufsz = ARRAY_SIZE(buf);
938
939 /* Read a chunk at the pointer location */
940 if (!buffer) {
941 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
942 if (status) {
943 hw_dbg(hw, "Failed to read EEPROM image\n");
944 return status;
945 }
946 local_buffer = buf;
947 } else {
948 if (buffer_size < ptr)
949 return -EINVAL;
950 local_buffer = &buffer[ptr];
951 }
952
953 if (size) {
954 start = 0;
955 length = size;
956 } else {
957 start = 1;
958 length = local_buffer[0];
959
960 /* Skip pointer section if length is invalid. */
961 if (length == 0xFFFF || length == 0 ||
962 (ptr + length) >= hw->eeprom.word_size)
963 return 0;
964 }
965
966 if (buffer && ((u32)start + (u32)length > buffer_size))
967 return -EINVAL;
968
969 for (i = start; length; i++, length--) {
970 if (i == bufsz && !buffer) {
971 ptr += bufsz;
972 i = 0;
973 if (length < bufsz)
974 bufsz = length;
975
976 /* Read a chunk at the pointer location */
977 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
978 bufsz, buf);
979 if (status) {
980 hw_dbg(hw, "Failed to read EEPROM image\n");
981 return status;
982 }
983 }
984 *csum += local_buffer[i];
985 }
986 return 0;
987 }
988
989 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
990 * @hw: pointer to hardware structure
991 * @buffer: pointer to buffer containing calculated checksum
992 * @buffer_size: size of buffer
993 *
994 * Returns a negative error code on error, or the 16-bit checksum
995 **/
ixgbe_calc_checksum_X550(struct ixgbe_hw * hw,u16 * buffer,u32 buffer_size)996 static int ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
997 u32 buffer_size)
998 {
999 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1000 u16 pointer, i, size;
1001 u16 *local_buffer;
1002 u16 checksum = 0;
1003 int status;
1004
1005 hw->eeprom.ops.init_params(hw);
1006
1007 if (!buffer) {
1008 /* Read pointer area */
1009 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1010 IXGBE_EEPROM_LAST_WORD + 1,
1011 eeprom_ptrs);
1012 if (status) {
1013 hw_dbg(hw, "Failed to read EEPROM image\n");
1014 return status;
1015 }
1016 local_buffer = eeprom_ptrs;
1017 } else {
1018 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1019 return -EINVAL;
1020 local_buffer = buffer;
1021 }
1022
1023 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1024 * checksum word itself
1025 */
1026 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1027 if (i != IXGBE_EEPROM_CHECKSUM)
1028 checksum += local_buffer[i];
1029
1030 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1031 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1032 */
1033 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1034 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1035 continue;
1036
1037 pointer = local_buffer[i];
1038
1039 /* Skip pointer section if the pointer is invalid. */
1040 if (pointer == 0xFFFF || pointer == 0 ||
1041 pointer >= hw->eeprom.word_size)
1042 continue;
1043
1044 switch (i) {
1045 case IXGBE_PCIE_GENERAL_PTR:
1046 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1047 break;
1048 case IXGBE_PCIE_CONFIG0_PTR:
1049 case IXGBE_PCIE_CONFIG1_PTR:
1050 size = IXGBE_PCIE_CONFIG_SIZE;
1051 break;
1052 default:
1053 size = 0;
1054 break;
1055 }
1056
1057 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1058 buffer, buffer_size);
1059 if (status)
1060 return status;
1061 }
1062
1063 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1064
1065 return (int)checksum;
1066 }
1067
1068 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1069 * @hw: pointer to hardware structure
1070 *
1071 * Returns a negative error code on error, or the 16-bit checksum
1072 **/
ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw * hw)1073 static int ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1074 {
1075 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1076 }
1077
1078 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1079 * @hw: pointer to hardware structure
1080 * @offset: offset of word in the EEPROM to read
1081 * @data: word read from the EEPROM
1082 *
1083 * Reads a 16 bit word from the EEPROM using the hostif.
1084 **/
ixgbe_read_ee_hostif_X550(struct ixgbe_hw * hw,u16 offset,u16 * data)1085 static int ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1086 {
1087 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1088 struct ixgbe_hic_read_shadow_ram buffer;
1089 int status;
1090
1091 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1092 buffer.hdr.req.buf_lenh = 0;
1093 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1094 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1095
1096 /* convert offset from words to bytes */
1097 buffer.address = (__force u32)cpu_to_be32(offset * 2);
1098 /* one word */
1099 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1100
1101 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1102 if (status)
1103 return status;
1104
1105 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1106 IXGBE_HI_COMMAND_TIMEOUT);
1107 if (!status) {
1108 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1109 FW_NVM_DATA_OFFSET);
1110 }
1111
1112 hw->mac.ops.release_swfw_sync(hw, mask);
1113 return status;
1114 }
1115
1116 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1117 * @hw: pointer to hardware structure
1118 * @checksum_val: calculated checksum
1119 *
1120 * Performs checksum calculation and validates the EEPROM checksum. If the
1121 * caller does not need checksum_val, the value can be NULL.
1122 **/
ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw * hw,u16 * checksum_val)1123 static int ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1124 u16 *checksum_val)
1125 {
1126 u16 read_checksum = 0;
1127 u16 checksum;
1128 int status;
1129
1130 /* Read the first word from the EEPROM. If this times out or fails, do
1131 * not continue or we could be in for a very long wait while every
1132 * EEPROM read fails
1133 */
1134 status = hw->eeprom.ops.read(hw, 0, &checksum);
1135 if (status) {
1136 hw_dbg(hw, "EEPROM read failed\n");
1137 return status;
1138 }
1139
1140 status = hw->eeprom.ops.calc_checksum(hw);
1141 if (status < 0)
1142 return status;
1143
1144 checksum = (u16)(status & 0xffff);
1145
1146 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1147 &read_checksum);
1148 if (status)
1149 return status;
1150
1151 /* Verify read checksum from EEPROM is the same as
1152 * calculated checksum
1153 */
1154 if (read_checksum != checksum) {
1155 status = -EIO;
1156 hw_dbg(hw, "Invalid EEPROM checksum");
1157 }
1158
1159 /* If the user cares, return the calculated checksum */
1160 if (checksum_val)
1161 *checksum_val = checksum;
1162
1163 return status;
1164 }
1165
1166 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1167 * @hw: pointer to hardware structure
1168 * @offset: offset of word in the EEPROM to write
1169 * @data: word write to the EEPROM
1170 *
1171 * Write a 16 bit word to the EEPROM using the hostif.
1172 **/
ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw * hw,u16 offset,u16 data)1173 static int ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1174 u16 data)
1175 {
1176 struct ixgbe_hic_write_shadow_ram buffer;
1177 int status;
1178
1179 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1180 buffer.hdr.req.buf_lenh = 0;
1181 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1182 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1183
1184 /* one word */
1185 buffer.length = cpu_to_be16(sizeof(u16));
1186 buffer.data = data;
1187 buffer.address = cpu_to_be32(offset * 2);
1188
1189 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1190 IXGBE_HI_COMMAND_TIMEOUT, false);
1191 return status;
1192 }
1193
1194 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1195 * @hw: pointer to hardware structure
1196 * @offset: offset of word in the EEPROM to write
1197 * @data: word write to the EEPROM
1198 *
1199 * Write a 16 bit word to the EEPROM using the hostif.
1200 **/
ixgbe_write_ee_hostif_X550(struct ixgbe_hw * hw,u16 offset,u16 data)1201 static int ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1202 {
1203 int status = 0;
1204
1205 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1206 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1207 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1208 } else {
1209 hw_dbg(hw, "write ee hostif failed to get semaphore");
1210 status = -EBUSY;
1211 }
1212
1213 return status;
1214 }
1215
1216 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1217 * @hw: pointer to hardware structure
1218 *
1219 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1220 **/
ixgbe_update_flash_X550(struct ixgbe_hw * hw)1221 static int ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1222 {
1223 union ixgbe_hic_hdr2 buffer;
1224 int status = 0;
1225
1226 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1227 buffer.req.buf_lenh = 0;
1228 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1229 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1230
1231 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1232 IXGBE_HI_COMMAND_TIMEOUT, false);
1233 return status;
1234 }
1235
1236 /**
1237 * ixgbe_get_bus_info_X550em - Set PCI bus info
1238 * @hw: pointer to hardware structure
1239 *
1240 * Sets bus link width and speed to unknown because X550em is
1241 * not a PCI device.
1242 **/
ixgbe_get_bus_info_X550em(struct ixgbe_hw * hw)1243 static int ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1244 {
1245 hw->bus.type = ixgbe_bus_type_internal;
1246 hw->bus.width = ixgbe_bus_width_unknown;
1247 hw->bus.speed = ixgbe_bus_speed_unknown;
1248
1249 hw->mac.ops.set_lan_id(hw);
1250
1251 return 0;
1252 }
1253
1254 /**
1255 * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
1256 * @hw: pointer t hardware structure
1257 *
1258 * Returns true if in FW NVM recovery mode.
1259 */
ixgbe_fw_recovery_mode_X550(struct ixgbe_hw * hw)1260 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1261 {
1262 u32 fwsm;
1263
1264 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1265 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1266 }
1267
1268 /** ixgbe_disable_rx_x550 - Disable RX unit
1269 *
1270 * Enables the Rx DMA unit for x550
1271 **/
ixgbe_disable_rx_x550(struct ixgbe_hw * hw)1272 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1273 {
1274 struct ixgbe_hic_disable_rxen fw_cmd;
1275 u32 rxctrl, pfdtxgswc;
1276 int status;
1277
1278 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1279 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1280 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1281 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1282 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1283 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1284 hw->mac.set_lben = true;
1285 } else {
1286 hw->mac.set_lben = false;
1287 }
1288
1289 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1290 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1291 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1292 fw_cmd.port_number = hw->bus.lan_id;
1293
1294 status = ixgbe_host_interface_command(hw, &fw_cmd,
1295 sizeof(struct ixgbe_hic_disable_rxen),
1296 IXGBE_HI_COMMAND_TIMEOUT, true);
1297
1298 /* If we fail - disable RX using register write */
1299 if (status) {
1300 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1301 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1302 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1303 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1304 }
1305 }
1306 }
1307 }
1308
1309 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1310 * @hw: pointer to hardware structure
1311 *
1312 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1313 * checksum and updates the EEPROM and instructs the hardware to update
1314 * the flash.
1315 **/
ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw * hw)1316 static int ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1317 {
1318 u16 checksum = 0;
1319 int status;
1320
1321 /* Read the first word from the EEPROM. If this times out or fails, do
1322 * not continue or we could be in for a very long wait while every
1323 * EEPROM read fails
1324 */
1325 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1326 if (status) {
1327 hw_dbg(hw, "EEPROM read failed\n");
1328 return status;
1329 }
1330
1331 status = ixgbe_calc_eeprom_checksum_X550(hw);
1332 if (status < 0)
1333 return status;
1334
1335 checksum = (u16)(status & 0xffff);
1336
1337 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1338 checksum);
1339 if (status)
1340 return status;
1341
1342 status = ixgbe_update_flash_X550(hw);
1343
1344 return status;
1345 }
1346
1347 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1348 * @hw: pointer to hardware structure
1349 * @offset: offset of word in the EEPROM to write
1350 * @words: number of words
1351 * @data: word(s) write to the EEPROM
1352 *
1353 *
1354 * Write a 16 bit word(s) to the EEPROM using the hostif.
1355 **/
ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1356 static int ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1357 u16 offset, u16 words,
1358 u16 *data)
1359 {
1360 int status = 0;
1361 u32 i = 0;
1362
1363 /* Take semaphore for the entire operation. */
1364 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1365 if (status) {
1366 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1367 return status;
1368 }
1369
1370 for (i = 0; i < words; i++) {
1371 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1372 data[i]);
1373 if (status) {
1374 hw_dbg(hw, "Eeprom buffered write failed\n");
1375 break;
1376 }
1377 }
1378
1379 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1380
1381 return status;
1382 }
1383
1384 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1385 * IOSF device
1386 *
1387 * @hw: pointer to hardware structure
1388 * @reg_addr: 32 bit PHY register to write
1389 * @device_type: 3 bit device type
1390 * @data: Data to write to the register
1391 **/
ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u32 data)1392 static int ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1393 u32 device_type, u32 data)
1394 {
1395 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1396 u32 command, error;
1397 int ret;
1398
1399 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1400 if (ret)
1401 return ret;
1402
1403 ret = ixgbe_iosf_wait(hw, NULL);
1404 if (ret)
1405 goto out;
1406
1407 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1408 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1409
1410 /* Write IOSF control register */
1411 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1412
1413 /* Write IOSF data register */
1414 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1415
1416 ret = ixgbe_iosf_wait(hw, &command);
1417
1418 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1419 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
1420 hw_dbg(hw, "Failed to write, error %x\n", error);
1421 return -EIO;
1422 }
1423
1424 out:
1425 hw->mac.ops.release_swfw_sync(hw, gssr);
1426 return ret;
1427 }
1428
1429 /**
1430 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1431 * @hw: pointer to hardware structure
1432 *
1433 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1434 **/
ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw * hw)1435 static int ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1436 {
1437 u32 reg_val;
1438 int status;
1439
1440 /* Disable training protocol FSM. */
1441 status = ixgbe_read_iosf_sb_reg_x550(hw,
1442 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1443 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1444 if (status)
1445 return status;
1446
1447 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1448 status = ixgbe_write_iosf_sb_reg_x550(hw,
1449 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451 if (status)
1452 return status;
1453
1454 /* Disable Flex from training TXFFE. */
1455 status = ixgbe_read_iosf_sb_reg_x550(hw,
1456 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1457 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1458 if (status)
1459 return status;
1460
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1464 status = ixgbe_write_iosf_sb_reg_x550(hw,
1465 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1466 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1467 if (status)
1468 return status;
1469
1470 status = ixgbe_read_iosf_sb_reg_x550(hw,
1471 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1472 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1473 if (status)
1474 return status;
1475
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1479 status = ixgbe_write_iosf_sb_reg_x550(hw,
1480 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482 if (status)
1483 return status;
1484
1485 /* Enable override for coefficients. */
1486 status = ixgbe_read_iosf_sb_reg_x550(hw,
1487 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1488 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1489 if (status)
1490 return status;
1491
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1496 status = ixgbe_write_iosf_sb_reg_x550(hw,
1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1499 return status;
1500 }
1501
1502 /**
1503 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1504 * internal PHY
1505 * @hw: pointer to hardware structure
1506 **/
ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw * hw)1507 static int ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1508 {
1509 u32 link_ctrl;
1510 int status;
1511
1512 /* Restart auto-negotiation. */
1513 status = hw->mac.ops.read_iosf_sb_reg(hw,
1514 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1516
1517 if (status) {
1518 hw_dbg(hw, "Auto-negotiation did not complete\n");
1519 return status;
1520 }
1521
1522 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1523 status = hw->mac.ops.write_iosf_sb_reg(hw,
1524 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1525 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1526
1527 if (hw->mac.type == ixgbe_mac_x550em_a) {
1528 u32 flx_mask_st20;
1529
1530 /* Indicate to FW that AN restart has been asserted */
1531 status = hw->mac.ops.read_iosf_sb_reg(hw,
1532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1533 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1534
1535 if (status) {
1536 hw_dbg(hw, "Auto-negotiation did not complete\n");
1537 return status;
1538 }
1539
1540 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1541 status = hw->mac.ops.write_iosf_sb_reg(hw,
1542 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1543 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1544 }
1545
1546 return status;
1547 }
1548
1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1550 * @hw: pointer to hardware structure
1551 * @speed: the link speed to force
1552 *
1553 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1554 * internal and external PHY at a specific speed, without autonegotiation.
1555 **/
ixgbe_setup_ixfi_x550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed)1556 static int ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1557 {
1558 struct ixgbe_mac_info *mac = &hw->mac;
1559 u32 reg_val;
1560 int status;
1561
1562 /* iXFI is only supported with X552 */
1563 if (mac->type != ixgbe_mac_X550EM_x)
1564 return -EIO;
1565
1566 /* Disable AN and force speed to 10G Serial. */
1567 status = ixgbe_read_iosf_sb_reg_x550(hw,
1568 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1569 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1570 if (status)
1571 return status;
1572
1573 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1574 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1575
1576 /* Select forced link speed for internal PHY. */
1577 switch (*speed) {
1578 case IXGBE_LINK_SPEED_10GB_FULL:
1579 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1580 break;
1581 case IXGBE_LINK_SPEED_1GB_FULL:
1582 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1583 break;
1584 default:
1585 /* Other link speeds are not supported by internal KR PHY. */
1586 return -EINVAL;
1587 }
1588
1589 status = ixgbe_write_iosf_sb_reg_x550(hw,
1590 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1591 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1592 if (status)
1593 return status;
1594
1595 /* Additional configuration needed for x550em_x */
1596 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1597 status = ixgbe_setup_ixfi_x550em_x(hw);
1598 if (status)
1599 return status;
1600 }
1601
1602 /* Toggle port SW reset by AN reset. */
1603 status = ixgbe_restart_an_internal_phy_x550em(hw);
1604
1605 return status;
1606 }
1607
1608 /**
1609 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1610 * @hw: pointer to hardware structure
1611 * @linear: true if SFP module is linear
1612 */
ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw * hw,bool * linear)1613 static int ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1614 {
1615 switch (hw->phy.sfp_type) {
1616 case ixgbe_sfp_type_not_present:
1617 return -ENOENT;
1618 case ixgbe_sfp_type_da_cu_core0:
1619 case ixgbe_sfp_type_da_cu_core1:
1620 *linear = true;
1621 break;
1622 case ixgbe_sfp_type_srlr_core0:
1623 case ixgbe_sfp_type_srlr_core1:
1624 case ixgbe_sfp_type_da_act_lmt_core0:
1625 case ixgbe_sfp_type_da_act_lmt_core1:
1626 case ixgbe_sfp_type_1g_sx_core0:
1627 case ixgbe_sfp_type_1g_sx_core1:
1628 case ixgbe_sfp_type_1g_lx_core0:
1629 case ixgbe_sfp_type_1g_lx_core1:
1630 *linear = false;
1631 break;
1632 case ixgbe_sfp_type_unknown:
1633 case ixgbe_sfp_type_1g_cu_core0:
1634 case ixgbe_sfp_type_1g_cu_core1:
1635 default:
1636 return -EOPNOTSUPP;
1637 }
1638
1639 return 0;
1640 }
1641
1642 /**
1643 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1644 * @hw: pointer to hardware structure
1645 * @speed: the link speed to force
1646 * @autoneg_wait_to_complete: unused
1647 *
1648 * Configures the extern PHY and the integrated KR PHY for SFP support.
1649 */
1650 static int
ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1651 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1652 ixgbe_link_speed speed,
1653 __always_unused bool autoneg_wait_to_complete)
1654 {
1655 bool setup_linear = false;
1656 u16 reg_slice, reg_val;
1657 int status;
1658
1659 /* Check if SFP module is supported and linear */
1660 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1661
1662 /* If no SFP module present, then return success. Return success since
1663 * there is no reason to configure CS4227 and SFP not present error is
1664 * not accepted in the setup MAC link flow.
1665 */
1666 if (status == -ENOENT)
1667 return 0;
1668
1669 if (status)
1670 return status;
1671
1672 /* Configure internal PHY for KR/KX. */
1673 ixgbe_setup_kr_speed_x550em(hw, speed);
1674
1675 /* Configure CS4227 LINE side to proper mode. */
1676 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1677 if (setup_linear)
1678 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1679 else
1680 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1681
1682 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1683 reg_val);
1684
1685 return status;
1686 }
1687
1688 /**
1689 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1690 * @hw: pointer to hardware structure
1691 * @speed: the link speed to force
1692 *
1693 * Configures the integrated PHY for native SFI mode. Used to connect the
1694 * internal PHY directly to an SFP cage, without autonegotiation.
1695 **/
ixgbe_setup_sfi_x550a(struct ixgbe_hw * hw,ixgbe_link_speed * speed)1696 static int ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1697 {
1698 struct ixgbe_mac_info *mac = &hw->mac;
1699 u32 reg_val;
1700 int status;
1701
1702 /* Disable all AN and force speed to 10G Serial. */
1703 status = mac->ops.read_iosf_sb_reg(hw,
1704 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1705 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1706 if (status)
1707 return status;
1708
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1713
1714 /* Select forced link speed for internal PHY. */
1715 switch (*speed) {
1716 case IXGBE_LINK_SPEED_10GB_FULL:
1717 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1718 break;
1719 case IXGBE_LINK_SPEED_1GB_FULL:
1720 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1721 break;
1722 default:
1723 /* Other link speeds are not supported by internal PHY. */
1724 return -EINVAL;
1725 }
1726
1727 status = mac->ops.write_iosf_sb_reg(hw,
1728 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1729 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1730
1731 /* Toggle port SW reset by AN reset. */
1732 status = ixgbe_restart_an_internal_phy_x550em(hw);
1733
1734 return status;
1735 }
1736
1737 /**
1738 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1739 * @hw: pointer to hardware structure
1740 * @speed: link speed
1741 * @autoneg_wait_to_complete: unused
1742 *
1743 * Configure the integrated PHY for native SFP support.
1744 */
1745 static int
ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1746 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1747 __always_unused bool autoneg_wait_to_complete)
1748 {
1749 bool setup_linear = false;
1750 u32 reg_phy_int;
1751 int ret_val;
1752
1753 /* Check if SFP module is supported and linear */
1754 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1755
1756 /* If no SFP module present, then return success. Return success since
1757 * SFP not present error is not excepted in the setup MAC link flow.
1758 */
1759 if (ret_val == -ENOENT)
1760 return 0;
1761
1762 if (ret_val)
1763 return ret_val;
1764
1765 /* Configure internal PHY for native SFI based on module type */
1766 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1767 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1768 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1769 if (ret_val)
1770 return ret_val;
1771
1772 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1773 if (!setup_linear)
1774 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1775
1776 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1777 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1778 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1779 if (ret_val)
1780 return ret_val;
1781
1782 /* Setup SFI internal link. */
1783 return ixgbe_setup_sfi_x550a(hw, &speed);
1784 }
1785
1786 /**
1787 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1788 * @hw: pointer to hardware structure
1789 * @speed: link speed
1790 * @autoneg_wait_to_complete: unused
1791 *
1792 * Configure the integrated PHY for SFP support.
1793 */
1794 static int
ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1795 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1796 __always_unused bool autoneg_wait_to_complete)
1797 {
1798 u32 reg_slice, slice_offset;
1799 bool setup_linear = false;
1800 u16 reg_phy_ext;
1801 int ret_val;
1802
1803 /* Check if SFP module is supported and linear */
1804 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1805
1806 /* If no SFP module present, then return success. Return success since
1807 * SFP not present error is not excepted in the setup MAC link flow.
1808 */
1809 if (ret_val == -ENOENT)
1810 return 0;
1811
1812 if (ret_val)
1813 return ret_val;
1814
1815 /* Configure internal PHY for KR/KX. */
1816 ixgbe_setup_kr_speed_x550em(hw, speed);
1817
1818 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1819 return -EFAULT;
1820
1821 /* Get external PHY SKU id */
1822 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1823 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1824 if (ret_val)
1825 return ret_val;
1826
1827 /* When configuring quad port CS4223, the MAC instance is part
1828 * of the slice offset.
1829 */
1830 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1831 slice_offset = (hw->bus.lan_id +
1832 (hw->bus.instance_id << 1)) << 12;
1833 else
1834 slice_offset = hw->bus.lan_id << 12;
1835
1836 /* Configure CS4227/CS4223 LINE side to proper mode. */
1837 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1838
1839 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1840 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1841 if (ret_val)
1842 return ret_val;
1843
1844 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1845 (IXGBE_CS4227_EDC_MODE_SR << 1));
1846
1847 if (setup_linear)
1848 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1849 else
1850 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1851
1852 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1853 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1854 if (ret_val)
1855 return ret_val;
1856
1857 /* Flush previous write with a read */
1858 return hw->phy.ops.read_reg(hw, reg_slice,
1859 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1860 }
1861
1862 /**
1863 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1864 * @hw: pointer to hardware structure
1865 * @speed: new link speed
1866 * @autoneg_wait: true when waiting for completion is needed
1867 *
1868 * Setup internal/external PHY link speed based on link speed, then set
1869 * external PHY auto advertised link speed.
1870 *
1871 * Returns error status for any failure
1872 **/
ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait)1873 static int ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1874 ixgbe_link_speed speed,
1875 bool autoneg_wait)
1876 {
1877 ixgbe_link_speed force_speed;
1878 int status;
1879
1880 /* Setup internal/external PHY link speed to iXFI (10G), unless
1881 * only 1G is auto advertised then setup KX link.
1882 */
1883 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1884 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1885 else
1886 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1887
1888 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1889 */
1890 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1891 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1892 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1893
1894 if (status)
1895 return status;
1896 }
1897
1898 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1899 }
1900
1901 /** ixgbe_check_link_t_X550em - Determine link and speed status
1902 * @hw: pointer to hardware structure
1903 * @speed: pointer to link speed
1904 * @link_up: true when link is up
1905 * @link_up_wait_to_complete: bool used to wait for link up or not
1906 *
1907 * Check that both the MAC and X557 external PHY have link.
1908 **/
ixgbe_check_link_t_X550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)1909 static int ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1910 ixgbe_link_speed *speed,
1911 bool *link_up,
1912 bool link_up_wait_to_complete)
1913 {
1914 u32 status;
1915 u16 i, autoneg_status;
1916
1917 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1918 return -EIO;
1919
1920 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1921 link_up_wait_to_complete);
1922
1923 /* If check link fails or MAC link is not up, then return */
1924 if (status || !(*link_up))
1925 return status;
1926
1927 /* MAC link is up, so check external PHY link.
1928 * Link status is latching low, and can only be used to detect link
1929 * drop, and not the current status of the link without performing
1930 * back-to-back reads.
1931 */
1932 for (i = 0; i < 2; i++) {
1933 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1934 &autoneg_status);
1935
1936 if (status)
1937 return status;
1938 }
1939
1940 /* If external PHY link is not up, then indicate link not up */
1941 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1942 *link_up = false;
1943
1944 return 0;
1945 }
1946
1947 /**
1948 * ixgbe_setup_sgmii - Set up link for sgmii
1949 * @hw: pointer to hardware structure
1950 * @speed: unused
1951 * @autoneg_wait_to_complete: unused
1952 */
1953 static int
ixgbe_setup_sgmii(struct ixgbe_hw * hw,__always_unused ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1954 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1955 __always_unused bool autoneg_wait_to_complete)
1956 {
1957 struct ixgbe_mac_info *mac = &hw->mac;
1958 u32 lval, sval, flx_val;
1959 int rc;
1960
1961 rc = mac->ops.read_iosf_sb_reg(hw,
1962 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1963 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1964 if (rc)
1965 return rc;
1966
1967 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1968 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1970 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1971 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1972 rc = mac->ops.write_iosf_sb_reg(hw,
1973 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1974 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1975 if (rc)
1976 return rc;
1977
1978 rc = mac->ops.read_iosf_sb_reg(hw,
1979 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1980 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1981 if (rc)
1982 return rc;
1983
1984 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1985 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1986 rc = mac->ops.write_iosf_sb_reg(hw,
1987 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1988 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1989 if (rc)
1990 return rc;
1991
1992 rc = mac->ops.read_iosf_sb_reg(hw,
1993 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1994 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1995 if (rc)
1996 return rc;
1997
1998 rc = mac->ops.read_iosf_sb_reg(hw,
1999 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2000 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2001 if (rc)
2002 return rc;
2003
2004 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2005 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2006 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2008 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2009
2010 rc = mac->ops.write_iosf_sb_reg(hw,
2011 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2012 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2013 if (rc)
2014 return rc;
2015
2016 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2017 return rc;
2018 }
2019
2020 /**
2021 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2022 * @hw: pointer to hardware structure
2023 * @speed: the link speed to force
2024 * @autoneg_wait: true when waiting for completion is needed
2025 */
ixgbe_setup_sgmii_fw(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait)2026 static int ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2027 bool autoneg_wait)
2028 {
2029 struct ixgbe_mac_info *mac = &hw->mac;
2030 u32 lval, sval, flx_val;
2031 int rc;
2032
2033 rc = mac->ops.read_iosf_sb_reg(hw,
2034 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2036 if (rc)
2037 return rc;
2038
2039 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2040 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2041 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2042 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2043 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2044 rc = mac->ops.write_iosf_sb_reg(hw,
2045 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2046 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2047 if (rc)
2048 return rc;
2049
2050 rc = mac->ops.read_iosf_sb_reg(hw,
2051 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2052 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2053 if (rc)
2054 return rc;
2055
2056 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2057 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2058 rc = mac->ops.write_iosf_sb_reg(hw,
2059 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2060 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2061 if (rc)
2062 return rc;
2063
2064 rc = mac->ops.write_iosf_sb_reg(hw,
2065 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2066 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2067 if (rc)
2068 return rc;
2069
2070 rc = mac->ops.read_iosf_sb_reg(hw,
2071 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2072 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2073 if (rc)
2074 return rc;
2075
2076 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2077 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2078 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2080 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2081
2082 rc = mac->ops.write_iosf_sb_reg(hw,
2083 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2084 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2085 if (rc)
2086 return rc;
2087
2088 ixgbe_restart_an_internal_phy_x550em(hw);
2089
2090 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2091 }
2092
2093 /**
2094 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2095 * @hw: pointer to hardware structure
2096 *
2097 * Enable flow control according to IEEE clause 37.
2098 */
ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw * hw)2099 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2100 {
2101 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2102 ixgbe_link_speed speed;
2103 int status = -EIO;
2104 bool link_up;
2105
2106 /* AN should have completed when the cable was plugged in.
2107 * Look for reasons to bail out. Bail out if:
2108 * - FC autoneg is disabled, or if
2109 * - link is not up.
2110 */
2111 if (hw->fc.disable_fc_autoneg)
2112 goto out;
2113
2114 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2115 if (!link_up)
2116 goto out;
2117
2118 /* Check if auto-negotiation has completed */
2119 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2120 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2121 status = -EIO;
2122 goto out;
2123 }
2124
2125 /* Negotiate the flow control */
2126 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2127 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2128 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2129 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2130 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2131
2132 out:
2133 if (!status) {
2134 hw->fc.fc_was_autonegged = true;
2135 } else {
2136 hw->fc.fc_was_autonegged = false;
2137 hw->fc.current_mode = hw->fc.requested_mode;
2138 }
2139 }
2140
2141 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2142 * @hw: pointer to hardware structure
2143 **/
ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw * hw)2144 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2145 {
2146 struct ixgbe_mac_info *mac = &hw->mac;
2147
2148 switch (mac->ops.get_media_type(hw)) {
2149 case ixgbe_media_type_fiber:
2150 mac->ops.setup_fc = NULL;
2151 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2152 break;
2153 case ixgbe_media_type_copper:
2154 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2155 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2156 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2157 break;
2158 }
2159 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2160 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2161 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2162 mac->ops.check_link = ixgbe_check_mac_link_generic;
2163 break;
2164 case ixgbe_media_type_backplane:
2165 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2166 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2167 break;
2168 default:
2169 break;
2170 }
2171 }
2172
2173 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2174 * @hw: pointer to hardware structure
2175 **/
ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw * hw)2176 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2177 {
2178 struct ixgbe_mac_info *mac = &hw->mac;
2179
2180 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2181
2182 switch (mac->ops.get_media_type(hw)) {
2183 case ixgbe_media_type_fiber:
2184 /* CS4227 does not support autoneg, so disable the laser control
2185 * functions for SFP+ fiber
2186 */
2187 mac->ops.disable_tx_laser = NULL;
2188 mac->ops.enable_tx_laser = NULL;
2189 mac->ops.flap_tx_laser = NULL;
2190 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2191 switch (hw->device_id) {
2192 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2193 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2194 break;
2195 case IXGBE_DEV_ID_X550EM_A_SFP:
2196 mac->ops.setup_mac_link =
2197 ixgbe_setup_mac_link_sfp_x550a;
2198 break;
2199 default:
2200 mac->ops.setup_mac_link =
2201 ixgbe_setup_mac_link_sfp_x550em;
2202 break;
2203 }
2204 mac->ops.set_rate_select_speed =
2205 ixgbe_set_soft_rate_select_speed;
2206 break;
2207 case ixgbe_media_type_copper:
2208 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2209 break;
2210 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2211 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2212 mac->ops.check_link = ixgbe_check_link_t_X550em;
2213 break;
2214 case ixgbe_media_type_backplane:
2215 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2216 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2217 mac->ops.setup_link = ixgbe_setup_sgmii;
2218 break;
2219 default:
2220 break;
2221 }
2222
2223 /* Additional modification for X550em_a devices */
2224 if (hw->mac.type == ixgbe_mac_x550em_a)
2225 ixgbe_init_mac_link_ops_X550em_a(hw);
2226 }
2227
2228 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2229 * @hw: pointer to hardware structure
2230 */
ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw * hw)2231 static int ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2232 {
2233 bool linear;
2234 int status;
2235
2236 /* Check if SFP module is supported */
2237 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2238 if (status)
2239 return status;
2240
2241 ixgbe_init_mac_link_ops_X550em(hw);
2242 hw->phy.ops.reset = NULL;
2243
2244 return 0;
2245 }
2246
2247 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2248 * @hw: pointer to hardware structure
2249 * @speed: pointer to link speed
2250 * @autoneg: true when autoneg or autotry is enabled
2251 **/
ixgbe_get_link_capabilities_X550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)2252 static int ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2253 ixgbe_link_speed *speed,
2254 bool *autoneg)
2255 {
2256 if (hw->phy.type == ixgbe_phy_fw) {
2257 *autoneg = true;
2258 *speed = hw->phy.speeds_supported;
2259 return 0;
2260 }
2261
2262 /* SFP */
2263 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2264 /* CS4227 SFP must not enable auto-negotiation */
2265 *autoneg = false;
2266
2267 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2268 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2270 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2271 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2272 return 0;
2273 }
2274
2275 /* Link capabilities are based on SFP */
2276 if (hw->phy.multispeed_fiber)
2277 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2278 IXGBE_LINK_SPEED_1GB_FULL;
2279 else
2280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2281 } else {
2282 switch (hw->phy.type) {
2283 case ixgbe_phy_x550em_kx4:
2284 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2285 IXGBE_LINK_SPEED_2_5GB_FULL |
2286 IXGBE_LINK_SPEED_10GB_FULL;
2287 break;
2288 case ixgbe_phy_x550em_xfi:
2289 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2290 IXGBE_LINK_SPEED_10GB_FULL;
2291 break;
2292 case ixgbe_phy_ext_1g_t:
2293 case ixgbe_phy_sgmii:
2294 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2295 break;
2296 case ixgbe_phy_x550em_kr:
2297 if (hw->mac.type == ixgbe_mac_x550em_a) {
2298 /* check different backplane modes */
2299 if (hw->phy.nw_mng_if_sel &
2300 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2301 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2302 break;
2303 } else if (hw->device_id ==
2304 IXGBE_DEV_ID_X550EM_A_KR_L) {
2305 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2306 break;
2307 }
2308 }
2309 fallthrough;
2310 default:
2311 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2312 IXGBE_LINK_SPEED_1GB_FULL;
2313 break;
2314 }
2315 *autoneg = true;
2316 }
2317 return 0;
2318 }
2319
2320 /**
2321 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2322 * @hw: pointer to hardware structure
2323 * @lsc: pointer to boolean flag which indicates whether external Base T
2324 * PHY interrupt is lsc
2325 * @is_overtemp: indicate whether an overtemp event encountered
2326 *
2327 * Determime if external Base T PHY interrupt cause is high temperature
2328 * failure alarm or link status change.
2329 **/
ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw * hw,bool * lsc,bool * is_overtemp)2330 static int ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2331 bool *is_overtemp)
2332 {
2333 u32 status;
2334 u16 reg;
2335
2336 *is_overtemp = false;
2337 *lsc = false;
2338
2339 /* Vendor alarm triggered */
2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2341 MDIO_MMD_VEND1,
2342 ®);
2343
2344 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2345 return status;
2346
2347 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2349 MDIO_MMD_VEND1,
2350 ®);
2351
2352 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2353 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2354 return status;
2355
2356 /* Global alarm triggered */
2357 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2358 MDIO_MMD_VEND1,
2359 ®);
2360
2361 if (status)
2362 return status;
2363
2364 /* If high temperature failure, then return over temp error and exit */
2365 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2366 /* power down the PHY in case the PHY FW didn't already */
2367 ixgbe_set_copper_phy_power(hw, false);
2368 *is_overtemp = true;
2369 return -EIO;
2370 }
2371 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2372 /* device fault alarm triggered */
2373 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2374 MDIO_MMD_VEND1,
2375 ®);
2376 if (status)
2377 return status;
2378
2379 /* if device fault was due to high temp alarm handle and exit */
2380 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2381 /* power down the PHY in case the PHY FW didn't */
2382 ixgbe_set_copper_phy_power(hw, false);
2383 *is_overtemp = true;
2384 return -EIO;
2385 }
2386 }
2387
2388 /* Vendor alarm 2 triggered */
2389 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2390 MDIO_MMD_AN, ®);
2391
2392 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2393 return status;
2394
2395 /* link connect/disconnect event occurred */
2396 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2397 MDIO_MMD_AN, ®);
2398
2399 if (status)
2400 return status;
2401
2402 /* Indicate LSC */
2403 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2404 *lsc = true;
2405
2406 return 0;
2407 }
2408
2409 /**
2410 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2411 * @hw: pointer to hardware structure
2412 *
2413 * Enable link status change and temperature failure alarm for the external
2414 * Base T PHY
2415 *
2416 * Returns PHY access status
2417 **/
ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw * hw)2418 static int ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2419 {
2420 bool lsc, overtemp;
2421 u32 status;
2422 u16 reg;
2423
2424 /* Clear interrupt flags */
2425 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2426
2427 /* Enable link status change alarm */
2428
2429 /* Enable the LASI interrupts on X552 devices to receive notifications
2430 * of the link configurations of the external PHY and correspondingly
2431 * support the configuration of the internal iXFI link, since iXFI does
2432 * not support auto-negotiation. This is not required for X553 devices
2433 * having KR support, which performs auto-negotiations and which is used
2434 * as the internal link to the external PHY. Hence adding a check here
2435 * to avoid enabling LASI interrupts for X553 devices.
2436 */
2437 if (hw->mac.type != ixgbe_mac_x550em_a) {
2438 status = hw->phy.ops.read_reg(hw,
2439 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2440 MDIO_MMD_AN, ®);
2441 if (status)
2442 return status;
2443
2444 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2445
2446 status = hw->phy.ops.write_reg(hw,
2447 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2448 MDIO_MMD_AN, reg);
2449 if (status)
2450 return status;
2451 }
2452
2453 /* Enable high temperature failure and global fault alarms */
2454 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2455 MDIO_MMD_VEND1,
2456 ®);
2457 if (status)
2458 return status;
2459
2460 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2461 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2462
2463 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2464 MDIO_MMD_VEND1,
2465 reg);
2466 if (status)
2467 return status;
2468
2469 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2470 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2471 MDIO_MMD_VEND1,
2472 ®);
2473 if (status)
2474 return status;
2475
2476 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2477 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2478
2479 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2480 MDIO_MMD_VEND1,
2481 reg);
2482 if (status)
2483 return status;
2484
2485 /* Enable chip-wide vendor alarm */
2486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2487 MDIO_MMD_VEND1,
2488 ®);
2489 if (status)
2490 return status;
2491
2492 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2493
2494 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2495 MDIO_MMD_VEND1,
2496 reg);
2497
2498 return status;
2499 }
2500
2501 /**
2502 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2503 * @hw: pointer to hardware structure
2504 * @is_overtemp: indicate whether an overtemp event encountered
2505 *
2506 * Handle external Base T PHY interrupt. If high temperature
2507 * failure alarm then return error, else if link status change
2508 * then setup internal/external PHY link
2509 **/
ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw * hw,bool * is_overtemp)2510 static int ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2511 bool *is_overtemp)
2512 {
2513 struct ixgbe_phy_info *phy = &hw->phy;
2514 bool lsc;
2515 u32 status;
2516
2517 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2518 if (status)
2519 return status;
2520
2521 if (lsc && phy->ops.setup_internal_link)
2522 return phy->ops.setup_internal_link(hw);
2523
2524 return 0;
2525 }
2526
2527 /**
2528 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2529 * @hw: pointer to hardware structure
2530 * @speed: link speed
2531 *
2532 * Configures the integrated KR PHY.
2533 **/
ixgbe_setup_kr_speed_x550em(struct ixgbe_hw * hw,ixgbe_link_speed speed)2534 static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2535 ixgbe_link_speed speed)
2536 {
2537 u32 reg_val;
2538 int status;
2539
2540 status = hw->mac.ops.read_iosf_sb_reg(hw,
2541 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2542 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2543 if (status)
2544 return status;
2545
2546 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2547 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2548 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2549
2550 /* Advertise 10G support. */
2551 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2552 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2553
2554 /* Advertise 1G support. */
2555 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2556 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2557
2558 status = hw->mac.ops.write_iosf_sb_reg(hw,
2559 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2560 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2561
2562 if (hw->mac.type == ixgbe_mac_x550em_a) {
2563 /* Set lane mode to KR auto negotiation */
2564 status = hw->mac.ops.read_iosf_sb_reg(hw,
2565 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2566 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2567
2568 if (status)
2569 return status;
2570
2571 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2573 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2575 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2576
2577 status = hw->mac.ops.write_iosf_sb_reg(hw,
2578 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2579 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2580 }
2581
2582 return ixgbe_restart_an_internal_phy_x550em(hw);
2583 }
2584
2585 /**
2586 * ixgbe_setup_kr_x550em - Configure the KR PHY
2587 * @hw: pointer to hardware structure
2588 **/
ixgbe_setup_kr_x550em(struct ixgbe_hw * hw)2589 static int ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2590 {
2591 /* leave link alone for 2.5G */
2592 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2593 return 0;
2594
2595 if (ixgbe_check_reset_blocked(hw))
2596 return 0;
2597
2598 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2599 }
2600
2601 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2602 * @hw: address of hardware structure
2603 * @link_up: address of boolean to indicate link status
2604 *
2605 * Returns error code if unable to get link status.
2606 **/
ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw * hw,bool * link_up)2607 static int ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2608 {
2609 u32 ret;
2610 u16 autoneg_status;
2611
2612 *link_up = false;
2613
2614 /* read this twice back to back to indicate current status */
2615 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2616 &autoneg_status);
2617 if (ret)
2618 return ret;
2619
2620 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2621 &autoneg_status);
2622 if (ret)
2623 return ret;
2624
2625 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2626
2627 return 0;
2628 }
2629
2630 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2631 * @hw: point to hardware structure
2632 *
2633 * Configures the link between the integrated KR PHY and the external X557 PHY
2634 * The driver will call this function when it gets a link status change
2635 * interrupt from the X557 PHY. This function configures the link speed
2636 * between the PHYs to match the link speed of the BASE-T link.
2637 *
2638 * A return of a non-zero value indicates an error, and the base driver should
2639 * not report link up.
2640 **/
ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw * hw)2641 static int ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2642 {
2643 ixgbe_link_speed force_speed;
2644 bool link_up;
2645 u32 status;
2646 u16 speed;
2647
2648 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2649 return -EIO;
2650
2651 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2652 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2653 speed = IXGBE_LINK_SPEED_10GB_FULL |
2654 IXGBE_LINK_SPEED_1GB_FULL;
2655 return ixgbe_setup_kr_speed_x550em(hw, speed);
2656 }
2657
2658 /* If link is not up, then there is no setup necessary so return */
2659 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2660 if (status)
2661 return status;
2662
2663 if (!link_up)
2664 return 0;
2665
2666 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2667 MDIO_MMD_AN,
2668 &speed);
2669 if (status)
2670 return status;
2671
2672 /* If link is not still up, then no setup is necessary so return */
2673 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2674 if (status)
2675 return status;
2676
2677 if (!link_up)
2678 return 0;
2679
2680 /* clear everything but the speed and duplex bits */
2681 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2682
2683 switch (speed) {
2684 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2685 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2686 break;
2687 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2688 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2689 break;
2690 default:
2691 /* Internal PHY does not support anything else */
2692 return -EINVAL;
2693 }
2694
2695 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2696 }
2697
2698 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2699 * @hw: pointer to hardware structure
2700 **/
ixgbe_reset_phy_t_X550em(struct ixgbe_hw * hw)2701 static int ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2702 {
2703 int status;
2704
2705 status = ixgbe_reset_phy_generic(hw);
2706
2707 if (status)
2708 return status;
2709
2710 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2711 return ixgbe_enable_lasi_ext_t_x550em(hw);
2712 }
2713
2714 /**
2715 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2716 * @hw: pointer to hardware structure
2717 * @led_idx: led number to turn on
2718 **/
ixgbe_led_on_t_x550em(struct ixgbe_hw * hw,u32 led_idx)2719 static int ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2720 {
2721 u16 phy_data;
2722
2723 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2724 return -EINVAL;
2725
2726 /* To turn on the LED, set mode to ON. */
2727 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2728 MDIO_MMD_VEND1, &phy_data);
2729 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2730 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2731 MDIO_MMD_VEND1, phy_data);
2732
2733 return 0;
2734 }
2735
2736 /**
2737 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2738 * @hw: pointer to hardware structure
2739 * @led_idx: led number to turn off
2740 **/
ixgbe_led_off_t_x550em(struct ixgbe_hw * hw,u32 led_idx)2741 static int ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2742 {
2743 u16 phy_data;
2744
2745 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2746 return -EINVAL;
2747
2748 /* To turn on the LED, set mode to ON. */
2749 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2750 MDIO_MMD_VEND1, &phy_data);
2751 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2752 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2753 MDIO_MMD_VEND1, phy_data);
2754
2755 return 0;
2756 }
2757
2758 /**
2759 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2760 * @hw: pointer to the HW structure
2761 * @maj: driver version major number
2762 * @min: driver version minor number
2763 * @build: driver version build number
2764 * @sub: driver version sub build number
2765 * @len: length of driver_ver string
2766 * @driver_ver: driver string
2767 *
2768 * Sends driver version number to firmware through the manageability
2769 * block. On success return 0
2770 * else returns -EBUSY when encountering an error acquiring
2771 * semaphore, -EIO when command fails or -ENIVAL when incorrect
2772 * params passed.
2773 **/
ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub,u16 len,const char * driver_ver)2774 int ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2775 u8 build, u8 sub, u16 len,
2776 const char *driver_ver)
2777 {
2778 struct ixgbe_hic_drv_info2 fw_cmd;
2779 int ret_val;
2780 int i;
2781
2782 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2783 return -EINVAL;
2784
2785 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2786 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2787 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2788 fw_cmd.port_num = (u8)hw->bus.func;
2789 fw_cmd.ver_maj = maj;
2790 fw_cmd.ver_min = min;
2791 fw_cmd.ver_build = build;
2792 fw_cmd.ver_sub = sub;
2793 fw_cmd.hdr.checksum = 0;
2794 memcpy(fw_cmd.driver_string, driver_ver, len);
2795 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2796 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2797
2798 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2799 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2800 sizeof(fw_cmd),
2801 IXGBE_HI_COMMAND_TIMEOUT,
2802 true);
2803 if (ret_val)
2804 continue;
2805
2806 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2807 FW_CEM_RESP_STATUS_SUCCESS)
2808 return -EIO;
2809 return 0;
2810 }
2811
2812 return ret_val;
2813 }
2814
2815 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2816 * @hw: pointer to hardware structure
2817 * @lcd_speed: pointer to lowest common link speed
2818 *
2819 * Determine lowest common link speed with link partner.
2820 **/
ixgbe_get_lcd_t_x550em(struct ixgbe_hw * hw,ixgbe_link_speed * lcd_speed)2821 static int ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2822 ixgbe_link_speed *lcd_speed)
2823 {
2824 u16 word = hw->eeprom.ctrl_word_3;
2825 u16 an_lp_status;
2826 int status;
2827
2828 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2829
2830 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2831 MDIO_MMD_AN,
2832 &an_lp_status);
2833 if (status)
2834 return status;
2835
2836 /* If link partner advertised 1G, return 1G */
2837 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2838 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2839 return 0;
2840 }
2841
2842 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2843 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2844 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2845 return 0;
2846
2847 /* Link partner not capable of lower speeds, return 10G */
2848 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2849 return 0;
2850 }
2851
2852 /**
2853 * ixgbe_setup_fc_x550em - Set up flow control
2854 * @hw: pointer to hardware structure
2855 */
ixgbe_setup_fc_x550em(struct ixgbe_hw * hw)2856 static int ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2857 {
2858 bool pause, asm_dir;
2859 u32 reg_val;
2860 int rc = 0;
2861
2862 /* Validate the requested mode */
2863 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2864 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2865 return -EINVAL;
2866 }
2867
2868 /* 10gig parts do not have a word in the EEPROM to determine the
2869 * default flow control setting, so we explicitly set it to full.
2870 */
2871 if (hw->fc.requested_mode == ixgbe_fc_default)
2872 hw->fc.requested_mode = ixgbe_fc_full;
2873
2874 /* Determine PAUSE and ASM_DIR bits. */
2875 switch (hw->fc.requested_mode) {
2876 case ixgbe_fc_none:
2877 pause = false;
2878 asm_dir = false;
2879 break;
2880 case ixgbe_fc_tx_pause:
2881 pause = false;
2882 asm_dir = true;
2883 break;
2884 case ixgbe_fc_rx_pause:
2885 /* Rx Flow control is enabled and Tx Flow control is
2886 * disabled by software override. Since there really
2887 * isn't a way to advertise that we are capable of RX
2888 * Pause ONLY, we will advertise that we support both
2889 * symmetric and asymmetric Rx PAUSE, as such we fall
2890 * through to the fc_full statement. Later, we will
2891 * disable the adapter's ability to send PAUSE frames.
2892 */
2893 fallthrough;
2894 case ixgbe_fc_full:
2895 pause = true;
2896 asm_dir = true;
2897 break;
2898 default:
2899 hw_err(hw, "Flow control param set incorrectly\n");
2900 return -EIO;
2901 }
2902
2903 switch (hw->device_id) {
2904 case IXGBE_DEV_ID_X550EM_X_KR:
2905 case IXGBE_DEV_ID_X550EM_A_KR:
2906 case IXGBE_DEV_ID_X550EM_A_KR_L:
2907 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2908 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2909 IXGBE_SB_IOSF_TARGET_KR_PHY,
2910 ®_val);
2911 if (rc)
2912 return rc;
2913
2914 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2915 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2916 if (pause)
2917 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2918 if (asm_dir)
2919 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2920 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2921 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2922 IXGBE_SB_IOSF_TARGET_KR_PHY,
2923 reg_val);
2924
2925 /* This device does not fully support AN. */
2926 hw->fc.disable_fc_autoneg = true;
2927 break;
2928 case IXGBE_DEV_ID_X550EM_X_XFI:
2929 hw->fc.disable_fc_autoneg = true;
2930 break;
2931 default:
2932 break;
2933 }
2934 return rc;
2935 }
2936
2937 /**
2938 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2939 * @hw: pointer to hardware structure
2940 **/
ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw * hw)2941 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2942 {
2943 u32 link_s1, lp_an_page_low, an_cntl_1;
2944 ixgbe_link_speed speed;
2945 int status = -EIO;
2946 bool link_up;
2947
2948 /* AN should have completed when the cable was plugged in.
2949 * Look for reasons to bail out. Bail out if:
2950 * - FC autoneg is disabled, or if
2951 * - link is not up.
2952 */
2953 if (hw->fc.disable_fc_autoneg) {
2954 hw_err(hw, "Flow control autoneg is disabled");
2955 goto out;
2956 }
2957
2958 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2959 if (!link_up) {
2960 hw_err(hw, "The link is down");
2961 goto out;
2962 }
2963
2964 /* Check at auto-negotiation has completed */
2965 status = hw->mac.ops.read_iosf_sb_reg(hw,
2966 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2967 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2968
2969 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2970 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2971 status = -EIO;
2972 goto out;
2973 }
2974
2975 /* Read the 10g AN autoc and LP ability registers and resolve
2976 * local flow control settings accordingly
2977 */
2978 status = hw->mac.ops.read_iosf_sb_reg(hw,
2979 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2980 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2981
2982 if (status) {
2983 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2984 goto out;
2985 }
2986
2987 status = hw->mac.ops.read_iosf_sb_reg(hw,
2988 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2989 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2990
2991 if (status) {
2992 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2993 goto out;
2994 }
2995
2996 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2997 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2998 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2999 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3000 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3001
3002 out:
3003 if (!status) {
3004 hw->fc.fc_was_autonegged = true;
3005 } else {
3006 hw->fc.fc_was_autonegged = false;
3007 hw->fc.current_mode = hw->fc.requested_mode;
3008 }
3009 }
3010
3011 /**
3012 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3013 * @hw: pointer to hardware structure
3014 **/
ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw * hw)3015 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3016 {
3017 hw->fc.fc_was_autonegged = false;
3018 hw->fc.current_mode = hw->fc.requested_mode;
3019 }
3020
3021 /** ixgbe_enter_lplu_x550em - Transition to low power states
3022 * @hw: pointer to hardware structure
3023 *
3024 * Configures Low Power Link Up on transition to low power states
3025 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3026 * the X557 PHY immediately prior to entering LPLU.
3027 **/
ixgbe_enter_lplu_t_x550em(struct ixgbe_hw * hw)3028 static int ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3029 {
3030 u16 an_10g_cntl_reg, autoneg_reg, speed;
3031 ixgbe_link_speed lcd_speed;
3032 u32 save_autoneg;
3033 bool link_up;
3034 int status;
3035
3036 /* If blocked by MNG FW, then don't restart AN */
3037 if (ixgbe_check_reset_blocked(hw))
3038 return 0;
3039
3040 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3041 if (status)
3042 return status;
3043
3044 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3045 &hw->eeprom.ctrl_word_3);
3046 if (status)
3047 return status;
3048
3049 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3050 * manageability disabled, then force link down by entering
3051 * low power mode.
3052 */
3053 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3054 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3055 return ixgbe_set_copper_phy_power(hw, false);
3056
3057 /* Determine LCD */
3058 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3059 if (status)
3060 return status;
3061
3062 /* If no valid LCD link speed, then force link down and exit. */
3063 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3064 return ixgbe_set_copper_phy_power(hw, false);
3065
3066 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3067 MDIO_MMD_AN,
3068 &speed);
3069 if (status)
3070 return status;
3071
3072 /* If no link now, speed is invalid so take link down */
3073 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3074 if (status)
3075 return ixgbe_set_copper_phy_power(hw, false);
3076
3077 /* clear everything but the speed bits */
3078 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3079
3080 /* If current speed is already LCD, then exit. */
3081 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3082 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3083 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3084 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3085 return 0;
3086
3087 /* Clear AN completed indication */
3088 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3089 MDIO_MMD_AN,
3090 &autoneg_reg);
3091 if (status)
3092 return status;
3093
3094 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3095 MDIO_MMD_AN,
3096 &an_10g_cntl_reg);
3097 if (status)
3098 return status;
3099
3100 status = hw->phy.ops.read_reg(hw,
3101 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3102 MDIO_MMD_AN,
3103 &autoneg_reg);
3104 if (status)
3105 return status;
3106
3107 save_autoneg = hw->phy.autoneg_advertised;
3108
3109 /* Setup link at least common link speed */
3110 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3111
3112 /* restore autoneg from before setting lplu speed */
3113 hw->phy.autoneg_advertised = save_autoneg;
3114
3115 return status;
3116 }
3117
3118 /**
3119 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3120 * @hw: pointer to hardware structure
3121 */
ixgbe_reset_phy_fw(struct ixgbe_hw * hw)3122 static int ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3123 {
3124 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3125 int rc;
3126
3127 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3128 return 0;
3129
3130 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3131 if (rc)
3132 return rc;
3133 memset(store, 0, sizeof(store));
3134
3135 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3136 if (rc)
3137 return rc;
3138
3139 return ixgbe_setup_fw_link(hw);
3140 }
3141
3142 /**
3143 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3144 * @hw: pointer to hardware structure
3145 *
3146 * Return true when an overtemp event detected, otherwise false.
3147 */
ixgbe_check_overtemp_fw(struct ixgbe_hw * hw)3148 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3149 {
3150 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3151 int rc;
3152
3153 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3154 if (rc)
3155 return false;
3156
3157 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3158 ixgbe_shutdown_fw_phy(hw);
3159 return true;
3160 }
3161 return false;
3162 }
3163
3164 /**
3165 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3166 * @hw: pointer to hardware structure
3167 *
3168 * Read NW_MNG_IF_SEL register and save field values.
3169 */
ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw * hw)3170 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3171 {
3172 /* Save NW management interface connected on board. This is used
3173 * to determine internal PHY mode.
3174 */
3175 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3176
3177 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3178 * PHY address. This register field was has only been used for X552.
3179 */
3180 if (hw->mac.type == ixgbe_mac_x550em_a &&
3181 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3182 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
3183 hw->phy.nw_mng_if_sel);
3184 }
3185 }
3186
3187 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3188 * @hw: pointer to hardware structure
3189 *
3190 * Initialize any function pointers that were not able to be
3191 * set during init_shared_code because the PHY/SFP type was
3192 * not known. Perform the SFP init if necessary.
3193 **/
ixgbe_init_phy_ops_X550em(struct ixgbe_hw * hw)3194 static int ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3195 {
3196 struct ixgbe_phy_info *phy = &hw->phy;
3197 int ret_val;
3198
3199 hw->mac.ops.set_lan_id(hw);
3200
3201 ixgbe_read_mng_if_sel_x550em(hw);
3202
3203 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3204 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3205 ixgbe_setup_mux_ctl(hw);
3206 }
3207
3208 /* Identify the PHY or SFP module */
3209 ret_val = phy->ops.identify(hw);
3210 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3211 return ret_val;
3212
3213 /* Setup function pointers based on detected hardware */
3214 ixgbe_init_mac_link_ops_X550em(hw);
3215 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3216 phy->ops.reset = NULL;
3217
3218 /* Set functions pointers based on phy type */
3219 switch (hw->phy.type) {
3220 case ixgbe_phy_x550em_kx4:
3221 phy->ops.setup_link = NULL;
3222 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3223 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3224 break;
3225 case ixgbe_phy_x550em_kr:
3226 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3227 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3228 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3229 break;
3230 case ixgbe_phy_x550em_xfi:
3231 /* link is managed by HW */
3232 phy->ops.setup_link = NULL;
3233 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3234 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3235 break;
3236 case ixgbe_phy_x550em_ext_t:
3237 /* Save NW management interface connected on board. This is used
3238 * to determine internal PHY mode
3239 */
3240 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3241
3242 /* If internal link mode is XFI, then setup iXFI internal link,
3243 * else setup KR now.
3244 */
3245 phy->ops.setup_internal_link =
3246 ixgbe_setup_internal_phy_t_x550em;
3247
3248 /* setup SW LPLU only for first revision */
3249 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3250 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3251 IXGBE_FUSES0_REV_MASK))
3252 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3253
3254 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3255 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3256 break;
3257 case ixgbe_phy_sgmii:
3258 phy->ops.setup_link = NULL;
3259 break;
3260 case ixgbe_phy_fw:
3261 phy->ops.setup_link = ixgbe_setup_fw_link;
3262 phy->ops.reset = ixgbe_reset_phy_fw;
3263 break;
3264 case ixgbe_phy_ext_1g_t:
3265 phy->ops.setup_link = NULL;
3266 phy->ops.read_reg = NULL;
3267 phy->ops.write_reg = NULL;
3268 phy->ops.reset = NULL;
3269 break;
3270 default:
3271 break;
3272 }
3273
3274 return ret_val;
3275 }
3276
3277 /** ixgbe_get_media_type_X550em - Get media type
3278 * @hw: pointer to hardware structure
3279 *
3280 * Returns the media type (fiber, copper, backplane)
3281 *
3282 */
ixgbe_get_media_type_X550em(struct ixgbe_hw * hw)3283 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3284 {
3285 enum ixgbe_media_type media_type;
3286
3287 /* Detect if there is a copper PHY attached. */
3288 switch (hw->device_id) {
3289 case IXGBE_DEV_ID_X550EM_A_SGMII:
3290 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3291 hw->phy.type = ixgbe_phy_sgmii;
3292 fallthrough;
3293 case IXGBE_DEV_ID_X550EM_X_KR:
3294 case IXGBE_DEV_ID_X550EM_X_KX4:
3295 case IXGBE_DEV_ID_X550EM_X_XFI:
3296 case IXGBE_DEV_ID_X550EM_A_KR:
3297 case IXGBE_DEV_ID_X550EM_A_KR_L:
3298 media_type = ixgbe_media_type_backplane;
3299 break;
3300 case IXGBE_DEV_ID_X550EM_X_SFP:
3301 case IXGBE_DEV_ID_X550EM_A_SFP:
3302 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3303 media_type = ixgbe_media_type_fiber;
3304 break;
3305 case IXGBE_DEV_ID_X550EM_X_1G_T:
3306 case IXGBE_DEV_ID_X550EM_X_10G_T:
3307 case IXGBE_DEV_ID_X550EM_A_10G_T:
3308 case IXGBE_DEV_ID_X550EM_A_1G_T:
3309 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3310 media_type = ixgbe_media_type_copper;
3311 break;
3312 default:
3313 media_type = ixgbe_media_type_unknown;
3314 break;
3315 }
3316 return media_type;
3317 }
3318
3319 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3320 ** @hw: pointer to hardware structure
3321 **/
ixgbe_init_ext_t_x550em(struct ixgbe_hw * hw)3322 static int ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3323 {
3324 int status;
3325 u16 reg;
3326
3327 status = hw->phy.ops.read_reg(hw,
3328 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3329 MDIO_MMD_PMAPMD,
3330 ®);
3331 if (status)
3332 return status;
3333
3334 /* If PHY FW reset completed bit is set then this is the first
3335 * SW instance after a power on so the PHY FW must be un-stalled.
3336 */
3337 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3338 status = hw->phy.ops.read_reg(hw,
3339 IXGBE_MDIO_GLOBAL_RES_PR_10,
3340 MDIO_MMD_VEND1,
3341 ®);
3342 if (status)
3343 return status;
3344
3345 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3346
3347 status = hw->phy.ops.write_reg(hw,
3348 IXGBE_MDIO_GLOBAL_RES_PR_10,
3349 MDIO_MMD_VEND1,
3350 reg);
3351 if (status)
3352 return status;
3353 }
3354
3355 return status;
3356 }
3357
3358 /**
3359 * ixgbe_set_mdio_speed - Set MDIO clock speed
3360 * @hw: pointer to hardware structure
3361 */
ixgbe_set_mdio_speed(struct ixgbe_hw * hw)3362 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3363 {
3364 u32 hlreg0;
3365
3366 switch (hw->device_id) {
3367 case IXGBE_DEV_ID_X550EM_X_10G_T:
3368 case IXGBE_DEV_ID_X550EM_A_SGMII:
3369 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3370 case IXGBE_DEV_ID_X550EM_A_10G_T:
3371 case IXGBE_DEV_ID_X550EM_A_SFP:
3372 /* Config MDIO clock speed before the first MDIO PHY access */
3373 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3374 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3375 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3376 break;
3377 case IXGBE_DEV_ID_X550EM_A_1G_T:
3378 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3379 /* Select fast MDIO clock speed for these devices */
3380 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3381 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3382 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3383 break;
3384 default:
3385 break;
3386 }
3387 }
3388
3389 /** ixgbe_reset_hw_X550em - Perform hardware reset
3390 ** @hw: pointer to hardware structure
3391 **
3392 ** Resets the hardware by resetting the transmit and receive units, masks
3393 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3394 ** reset.
3395 **/
ixgbe_reset_hw_X550em(struct ixgbe_hw * hw)3396 static int ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3397 {
3398 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3399 ixgbe_link_speed link_speed;
3400 bool link_up = false;
3401 u32 ctrl = 0;
3402 int status;
3403 u32 i;
3404
3405 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3406 status = hw->mac.ops.stop_adapter(hw);
3407 if (status)
3408 return status;
3409
3410 /* flush pending Tx transactions */
3411 ixgbe_clear_tx_pending(hw);
3412
3413 /* set MDIO speed before talking to the PHY in case it's the 1st time */
3414 ixgbe_set_mdio_speed(hw);
3415
3416 /* PHY ops must be identified and initialized prior to reset */
3417 status = hw->phy.ops.init(hw);
3418 if (status == -EOPNOTSUPP || status == -EFAULT)
3419 return status;
3420
3421 /* start the external PHY */
3422 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3423 status = ixgbe_init_ext_t_x550em(hw);
3424 if (status)
3425 return status;
3426 }
3427
3428 /* Setup SFP module if there is one present. */
3429 if (hw->phy.sfp_setup_needed) {
3430 status = hw->mac.ops.setup_sfp(hw);
3431 hw->phy.sfp_setup_needed = false;
3432 }
3433
3434 if (status == -EOPNOTSUPP)
3435 return status;
3436
3437 /* Reset PHY */
3438 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3439 hw->phy.ops.reset(hw);
3440
3441 mac_reset_top:
3442 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3443 * If link reset is used when link is up, it might reset the PHY when
3444 * mng is using it. If link is down or the flag to force full link
3445 * reset is set, then perform link reset.
3446 */
3447 ctrl = IXGBE_CTRL_LNK_RST;
3448
3449 if (!hw->force_full_reset) {
3450 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3451 if (link_up)
3452 ctrl = IXGBE_CTRL_RST;
3453 }
3454
3455 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3456 if (status) {
3457 hw_dbg(hw, "semaphore failed with %d", status);
3458 return -EBUSY;
3459 }
3460
3461 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3462 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3463 IXGBE_WRITE_FLUSH(hw);
3464 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3465 usleep_range(1000, 1200);
3466
3467 /* Poll for reset bit to self-clear meaning reset is complete */
3468 for (i = 0; i < 10; i++) {
3469 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3470 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3471 break;
3472 udelay(1);
3473 }
3474
3475 if (ctrl & IXGBE_CTRL_RST_MASK) {
3476 status = -EIO;
3477 hw_dbg(hw, "Reset polling failed to complete.\n");
3478 }
3479
3480 msleep(50);
3481
3482 /* Double resets are required for recovery from certain error
3483 * clear the multicast table. Also reset num_rar_entries to 128,
3484 * since we modify this value when programming the SAN MAC address.
3485 */
3486 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3487 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3488 goto mac_reset_top;
3489 }
3490
3491 /* Store the permanent mac address */
3492 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3493
3494 /* Store MAC address from RAR0, clear receive address registers, and
3495 * clear the multicast table. Also reset num_rar_entries to 128,
3496 * since we modify this value when programming the SAN MAC address.
3497 */
3498 hw->mac.num_rar_entries = 128;
3499 hw->mac.ops.init_rx_addrs(hw);
3500
3501 ixgbe_set_mdio_speed(hw);
3502
3503 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3504 ixgbe_setup_mux_ctl(hw);
3505
3506 return status;
3507 }
3508
3509 /** ixgbe_set_ethertype_anti_spoofing_x550 - Enable/Disable Ethertype
3510 * anti-spoofing
3511 * @hw: pointer to hardware structure
3512 * @enable: enable or disable switch for Ethertype anti-spoofing
3513 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3514 **/
ixgbe_set_ethertype_anti_spoofing_x550(struct ixgbe_hw * hw,bool enable,int vf)3515 void ixgbe_set_ethertype_anti_spoofing_x550(struct ixgbe_hw *hw,
3516 bool enable, int vf)
3517 {
3518 int vf_target_reg = vf >> 3;
3519 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3520 u32 pfvfspoof;
3521
3522 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3523 if (enable)
3524 pfvfspoof |= BIT(vf_target_shift);
3525 else
3526 pfvfspoof &= ~BIT(vf_target_shift);
3527
3528 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3529 }
3530
3531 /** ixgbe_set_source_address_pruning_x550 - Enable/Disable src address pruning
3532 * @hw: pointer to hardware structure
3533 * @enable: enable or disable source address pruning
3534 * @pool: Rx pool to set source address pruning for
3535 **/
ixgbe_set_source_address_pruning_x550(struct ixgbe_hw * hw,bool enable,unsigned int pool)3536 void ixgbe_set_source_address_pruning_x550(struct ixgbe_hw *hw,
3537 bool enable,
3538 unsigned int pool)
3539 {
3540 u64 pfflp;
3541
3542 /* max rx pool is 63 */
3543 if (pool > 63)
3544 return;
3545
3546 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3547 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3548
3549 if (enable)
3550 pfflp |= (1ULL << pool);
3551 else
3552 pfflp &= ~(1ULL << pool);
3553
3554 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3555 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3556 }
3557
3558 /**
3559 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3560 * @hw: pointer to hardware structure
3561 *
3562 * Called at init time to set up flow control.
3563 **/
ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw * hw)3564 static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3565 {
3566 u32 an_cntl = 0;
3567 int status = 0;
3568
3569 /* Validate the requested mode */
3570 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3571 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3572 return -EINVAL;
3573 }
3574
3575 if (hw->fc.requested_mode == ixgbe_fc_default)
3576 hw->fc.requested_mode = ixgbe_fc_full;
3577
3578 /* Set up the 1G and 10G flow control advertisement registers so the
3579 * HW will be able to do FC autoneg once the cable is plugged in. If
3580 * we link at 10G, the 1G advertisement is harmless and vice versa.
3581 */
3582 status = hw->mac.ops.read_iosf_sb_reg(hw,
3583 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3584 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3585
3586 if (status) {
3587 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3588 return status;
3589 }
3590
3591 /* The possible values of fc.requested_mode are:
3592 * 0: Flow control is completely disabled
3593 * 1: Rx flow control is enabled (we can receive pause frames,
3594 * but not send pause frames).
3595 * 2: Tx flow control is enabled (we can send pause frames but
3596 * we do not support receiving pause frames).
3597 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3598 * other: Invalid.
3599 */
3600 switch (hw->fc.requested_mode) {
3601 case ixgbe_fc_none:
3602 /* Flow control completely disabled by software override. */
3603 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3604 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3605 break;
3606 case ixgbe_fc_tx_pause:
3607 /* Tx Flow control is enabled, and Rx Flow control is
3608 * disabled by software override.
3609 */
3610 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3611 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3612 break;
3613 case ixgbe_fc_rx_pause:
3614 /* Rx Flow control is enabled and Tx Flow control is
3615 * disabled by software override. Since there really
3616 * isn't a way to advertise that we are capable of RX
3617 * Pause ONLY, we will advertise that we support both
3618 * symmetric and asymmetric Rx PAUSE, as such we fall
3619 * through to the fc_full statement. Later, we will
3620 * disable the adapter's ability to send PAUSE frames.
3621 */
3622 case ixgbe_fc_full:
3623 /* Flow control (both Rx and Tx) is enabled by SW override. */
3624 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3625 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3626 break;
3627 default:
3628 hw_err(hw, "Flow control param set incorrectly\n");
3629 return -EIO;
3630 }
3631
3632 status = hw->mac.ops.write_iosf_sb_reg(hw,
3633 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3634 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3635
3636 /* Restart auto-negotiation. */
3637 status = ixgbe_restart_an_internal_phy_x550em(hw);
3638
3639 return status;
3640 }
3641
3642 /**
3643 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3644 * @hw: pointer to hardware structure
3645 * @state: set mux if 1, clear if 0
3646 */
ixgbe_set_mux(struct ixgbe_hw * hw,u8 state)3647 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3648 {
3649 u32 esdp;
3650
3651 if (!hw->bus.lan_id)
3652 return;
3653 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3654 if (state)
3655 esdp |= IXGBE_ESDP_SDP1;
3656 else
3657 esdp &= ~IXGBE_ESDP_SDP1;
3658 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3659 IXGBE_WRITE_FLUSH(hw);
3660 }
3661
3662 /**
3663 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3664 * @hw: pointer to hardware structure
3665 * @mask: Mask to specify which semaphore to acquire
3666 *
3667 * Acquires the SWFW semaphore and sets the I2C MUX
3668 */
ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw * hw,u32 mask)3669 static int ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3670 {
3671 int status;
3672
3673 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3674 if (status)
3675 return status;
3676
3677 if (mask & IXGBE_GSSR_I2C_MASK)
3678 ixgbe_set_mux(hw, 1);
3679
3680 return 0;
3681 }
3682
3683 /**
3684 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3685 * @hw: pointer to hardware structure
3686 * @mask: Mask to specify which semaphore to release
3687 *
3688 * Releases the SWFW semaphore and sets the I2C MUX
3689 */
ixgbe_release_swfw_sync_X550em(struct ixgbe_hw * hw,u32 mask)3690 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3691 {
3692 if (mask & IXGBE_GSSR_I2C_MASK)
3693 ixgbe_set_mux(hw, 0);
3694
3695 ixgbe_release_swfw_sync_X540(hw, mask);
3696 }
3697
3698 /**
3699 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3700 * @hw: pointer to hardware structure
3701 * @mask: Mask to specify which semaphore to acquire
3702 *
3703 * Acquires the SWFW semaphore and get the shared PHY token as needed
3704 */
ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw * hw,u32 mask)3705 static int ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3706 {
3707 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3708 int retries = FW_PHY_TOKEN_RETRIES;
3709 int status;
3710
3711 while (--retries) {
3712 status = 0;
3713 if (hmask)
3714 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3715 if (status)
3716 return status;
3717 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3718 return 0;
3719
3720 status = ixgbe_get_phy_token(hw);
3721 if (!status)
3722 return 0;
3723 if (hmask)
3724 ixgbe_release_swfw_sync_X540(hw, hmask);
3725 if (status != -EAGAIN)
3726 return status;
3727 msleep(FW_PHY_TOKEN_DELAY);
3728 }
3729
3730 return status;
3731 }
3732
3733 /**
3734 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3735 * @hw: pointer to hardware structure
3736 * @mask: Mask to specify which semaphore to release
3737 *
3738 * Release the SWFW semaphore and puts the shared PHY token as needed
3739 */
ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw * hw,u32 mask)3740 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3741 {
3742 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3743
3744 if (mask & IXGBE_GSSR_TOKEN_SM)
3745 ixgbe_put_phy_token(hw);
3746
3747 if (hmask)
3748 ixgbe_release_swfw_sync_X540(hw, hmask);
3749 }
3750
3751 /**
3752 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3753 * @hw: pointer to hardware structure
3754 * @reg_addr: 32 bit address of PHY register to read
3755 * @device_type: 5 bit device type
3756 * @phy_data: Pointer to read data from PHY register
3757 *
3758 * Reads a value from a specified PHY register using the SWFW lock and PHY
3759 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3760 * instances.
3761 */
ixgbe_read_phy_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)3762 static int ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3763 u32 device_type, u16 *phy_data)
3764 {
3765 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3766 int status;
3767
3768 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3769 return -EBUSY;
3770
3771 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3772
3773 hw->mac.ops.release_swfw_sync(hw, mask);
3774
3775 return status;
3776 }
3777
3778 /**
3779 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3780 * @hw: pointer to hardware structure
3781 * @reg_addr: 32 bit PHY register to write
3782 * @device_type: 5 bit device type
3783 * @phy_data: Data to write to the PHY register
3784 *
3785 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3786 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3787 */
ixgbe_write_phy_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)3788 static int ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3789 u32 device_type, u16 phy_data)
3790 {
3791 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3792 int status;
3793
3794 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3795 return -EBUSY;
3796
3797 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3798 hw->mac.ops.release_swfw_sync(hw, mask);
3799
3800 return status;
3801 }
3802
3803 #define X550_COMMON_MAC \
3804 .init_hw = &ixgbe_init_hw_generic, \
3805 .start_hw = &ixgbe_start_hw_X540, \
3806 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3807 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3808 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3809 .get_device_caps = &ixgbe_get_device_caps_generic, \
3810 .stop_adapter = &ixgbe_stop_adapter_generic, \
3811 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3812 .read_analog_reg8 = NULL, \
3813 .write_analog_reg8 = NULL, \
3814 .set_rxpba = &ixgbe_set_rxpba_generic, \
3815 .check_link = &ixgbe_check_mac_link_generic, \
3816 .blink_led_start = &ixgbe_blink_led_start_X540, \
3817 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3818 .set_rar = &ixgbe_set_rar_generic, \
3819 .clear_rar = &ixgbe_clear_rar_generic, \
3820 .set_vmdq = &ixgbe_set_vmdq_generic, \
3821 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3822 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3823 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3824 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3825 .enable_mc = &ixgbe_enable_mc_generic, \
3826 .disable_mc = &ixgbe_disable_mc_generic, \
3827 .clear_vfta = &ixgbe_clear_vfta_generic, \
3828 .set_vfta = &ixgbe_set_vfta_generic, \
3829 .fc_enable = &ixgbe_fc_enable_generic, \
3830 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3831 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3832 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3833 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3834 .set_source_address_pruning = \
3835 &ixgbe_set_source_address_pruning_x550, \
3836 .set_ethertype_anti_spoofing = \
3837 &ixgbe_set_ethertype_anti_spoofing_x550, \
3838 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3839 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3840 .get_thermal_sensor_data = NULL, \
3841 .init_thermal_sensor_thresh = NULL, \
3842 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \
3843 .enable_rx = &ixgbe_enable_rx_generic, \
3844 .disable_rx = &ixgbe_disable_rx_x550, \
3845
3846 static const struct ixgbe_mac_operations mac_ops_X550 = {
3847 X550_COMMON_MAC
3848 .led_on = ixgbe_led_on_generic,
3849 .led_off = ixgbe_led_off_generic,
3850 .init_led_link_act = ixgbe_init_led_link_act_generic,
3851 .reset_hw = &ixgbe_reset_hw_X540,
3852 .get_media_type = &ixgbe_get_media_type_X540,
3853 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3854 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3855 .setup_link = &ixgbe_setup_mac_link_X540,
3856 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3857 .get_bus_info = &ixgbe_get_bus_info_generic,
3858 .setup_sfp = NULL,
3859 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3860 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3861 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3862 .prot_autoc_read = prot_autoc_read_generic,
3863 .prot_autoc_write = prot_autoc_write_generic,
3864 .setup_fc = ixgbe_setup_fc_generic,
3865 .fc_autoneg = ixgbe_fc_autoneg,
3866 };
3867
3868 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3869 X550_COMMON_MAC
3870 .led_on = ixgbe_led_on_t_x550em,
3871 .led_off = ixgbe_led_off_t_x550em,
3872 .init_led_link_act = ixgbe_init_led_link_act_generic,
3873 .reset_hw = &ixgbe_reset_hw_X550em,
3874 .get_media_type = &ixgbe_get_media_type_X550em,
3875 .get_san_mac_addr = NULL,
3876 .get_wwn_prefix = NULL,
3877 .setup_link = &ixgbe_setup_mac_link_X540,
3878 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3879 .get_bus_info = &ixgbe_get_bus_info_X550em,
3880 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3881 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3882 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3883 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3884 .setup_fc = NULL, /* defined later */
3885 .fc_autoneg = ixgbe_fc_autoneg,
3886 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3887 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3888 };
3889
3890 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3891 X550_COMMON_MAC
3892 .led_on = NULL,
3893 .led_off = NULL,
3894 .init_led_link_act = NULL,
3895 .reset_hw = &ixgbe_reset_hw_X550em,
3896 .get_media_type = &ixgbe_get_media_type_X550em,
3897 .get_san_mac_addr = NULL,
3898 .get_wwn_prefix = NULL,
3899 .setup_link = &ixgbe_setup_mac_link_X540,
3900 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3901 .get_bus_info = &ixgbe_get_bus_info_X550em,
3902 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3903 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3904 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3905 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3906 .setup_fc = NULL,
3907 .fc_autoneg = ixgbe_fc_autoneg,
3908 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3909 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3910 };
3911
3912 static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3913 X550_COMMON_MAC
3914 .led_on = ixgbe_led_on_t_x550em,
3915 .led_off = ixgbe_led_off_t_x550em,
3916 .init_led_link_act = ixgbe_init_led_link_act_generic,
3917 .reset_hw = ixgbe_reset_hw_X550em,
3918 .get_media_type = ixgbe_get_media_type_X550em,
3919 .get_san_mac_addr = NULL,
3920 .get_wwn_prefix = NULL,
3921 .setup_link = &ixgbe_setup_mac_link_X540,
3922 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3923 .get_bus_info = ixgbe_get_bus_info_X550em,
3924 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3925 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3926 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3927 .setup_fc = ixgbe_setup_fc_x550em,
3928 .fc_autoneg = ixgbe_fc_autoneg,
3929 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3930 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3931 };
3932
3933 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3934 X550_COMMON_MAC
3935 .led_on = ixgbe_led_on_generic,
3936 .led_off = ixgbe_led_off_generic,
3937 .init_led_link_act = ixgbe_init_led_link_act_generic,
3938 .reset_hw = ixgbe_reset_hw_X550em,
3939 .get_media_type = ixgbe_get_media_type_X550em,
3940 .get_san_mac_addr = NULL,
3941 .get_wwn_prefix = NULL,
3942 .setup_link = NULL, /* defined later */
3943 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3944 .get_bus_info = ixgbe_get_bus_info_X550em,
3945 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3946 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3947 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3948 .setup_fc = ixgbe_setup_fc_x550em,
3949 .fc_autoneg = ixgbe_fc_autoneg,
3950 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3951 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3952 };
3953
3954 #define X550_COMMON_EEP \
3955 .read = &ixgbe_read_ee_hostif_X550, \
3956 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3957 .write = &ixgbe_write_ee_hostif_X550, \
3958 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3959 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3960 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3961 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3962
3963 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3964 X550_COMMON_EEP
3965 .init_params = &ixgbe_init_eeprom_params_X550,
3966 };
3967
3968 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3969 X550_COMMON_EEP
3970 .init_params = &ixgbe_init_eeprom_params_X540,
3971 };
3972
3973 #define X550_COMMON_PHY \
3974 .identify_sfp = &ixgbe_identify_module_generic, \
3975 .reset = NULL, \
3976 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3977 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3978 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3979 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3980 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3981 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3982 .setup_link = &ixgbe_setup_phy_link_generic, \
3983 .set_phy_power = NULL,
3984
3985 static const struct ixgbe_phy_operations phy_ops_X550 = {
3986 X550_COMMON_PHY
3987 .check_overtemp = &ixgbe_tn_check_overtemp,
3988 .init = NULL,
3989 .identify = &ixgbe_identify_phy_generic,
3990 .read_reg = &ixgbe_read_phy_reg_generic,
3991 .write_reg = &ixgbe_write_phy_reg_generic,
3992 };
3993
3994 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3995 X550_COMMON_PHY
3996 .check_overtemp = &ixgbe_tn_check_overtemp,
3997 .init = &ixgbe_init_phy_ops_X550em,
3998 .identify = &ixgbe_identify_phy_x550em,
3999 .read_reg = &ixgbe_read_phy_reg_generic,
4000 .write_reg = &ixgbe_write_phy_reg_generic,
4001 };
4002
4003 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4004 X550_COMMON_PHY
4005 .check_overtemp = NULL,
4006 .init = ixgbe_init_phy_ops_X550em,
4007 .identify = ixgbe_identify_phy_x550em,
4008 .read_reg = NULL,
4009 .write_reg = NULL,
4010 .read_reg_mdi = NULL,
4011 .write_reg_mdi = NULL,
4012 };
4013
4014 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4015 X550_COMMON_PHY
4016 .check_overtemp = &ixgbe_tn_check_overtemp,
4017 .init = &ixgbe_init_phy_ops_X550em,
4018 .identify = &ixgbe_identify_phy_x550em,
4019 .read_reg = &ixgbe_read_phy_reg_x550a,
4020 .write_reg = &ixgbe_write_phy_reg_x550a,
4021 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4022 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4023 };
4024
4025 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4026 X550_COMMON_PHY
4027 .check_overtemp = ixgbe_check_overtemp_fw,
4028 .init = ixgbe_init_phy_ops_X550em,
4029 .identify = ixgbe_identify_phy_fw,
4030 .read_reg = NULL,
4031 .write_reg = NULL,
4032 .read_reg_mdi = NULL,
4033 .write_reg_mdi = NULL,
4034 };
4035
4036 static const struct ixgbe_link_operations link_ops_x550em_x = {
4037 .read_link = &ixgbe_read_i2c_combined_generic,
4038 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4039 .write_link = &ixgbe_write_i2c_combined_generic,
4040 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4041 };
4042
4043 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4044 IXGBE_MVALS_INIT(X550)
4045 };
4046
4047 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4048 IXGBE_MVALS_INIT(X550EM_x)
4049 };
4050
4051 const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4052 IXGBE_MVALS_INIT(X550EM_a)
4053 };
4054
4055 const struct ixgbe_info ixgbe_X550_info = {
4056 .mac = ixgbe_mac_X550,
4057 .get_invariants = &ixgbe_get_invariants_X540,
4058 .mac_ops = &mac_ops_X550,
4059 .eeprom_ops = &eeprom_ops_X550,
4060 .phy_ops = &phy_ops_X550,
4061 .mbx_ops = &mbx_ops_generic,
4062 .mvals = ixgbe_mvals_X550,
4063 };
4064
4065 const struct ixgbe_info ixgbe_X550EM_x_info = {
4066 .mac = ixgbe_mac_X550EM_x,
4067 .get_invariants = &ixgbe_get_invariants_X550_x,
4068 .mac_ops = &mac_ops_X550EM_x,
4069 .eeprom_ops = &eeprom_ops_X550EM_x,
4070 .phy_ops = &phy_ops_X550EM_x,
4071 .mbx_ops = &mbx_ops_generic,
4072 .mvals = ixgbe_mvals_X550EM_x,
4073 .link_ops = &link_ops_x550em_x,
4074 };
4075
4076 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4077 .mac = ixgbe_mac_X550EM_x,
4078 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4079 .mac_ops = &mac_ops_X550EM_x_fw,
4080 .eeprom_ops = &eeprom_ops_X550EM_x,
4081 .phy_ops = &phy_ops_x550em_x_fw,
4082 .mbx_ops = &mbx_ops_generic,
4083 .mvals = ixgbe_mvals_X550EM_x,
4084 };
4085
4086 const struct ixgbe_info ixgbe_x550em_a_info = {
4087 .mac = ixgbe_mac_x550em_a,
4088 .get_invariants = &ixgbe_get_invariants_X550_a,
4089 .mac_ops = &mac_ops_x550em_a,
4090 .eeprom_ops = &eeprom_ops_X550EM_x,
4091 .phy_ops = &phy_ops_x550em_a,
4092 .mbx_ops = &mbx_ops_generic,
4093 .mvals = ixgbe_mvals_x550em_a,
4094 };
4095
4096 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4097 .mac = ixgbe_mac_x550em_a,
4098 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4099 .mac_ops = &mac_ops_x550em_a_fw,
4100 .eeprom_ops = &eeprom_ops_X550EM_x,
4101 .phy_ops = &phy_ops_x550em_a_fw,
4102 .mbx_ops = &mbx_ops_generic,
4103 .mvals = ixgbe_mvals_x550em_a,
4104 };
4105