1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/sched.h>
7
8 #include "ixgbe.h"
9 #include "ixgbe_mbx.h"
10 #include "ixgbe_phy.h"
11 #include "ixgbe_x540.h"
12
13 #define IXGBE_X540_MAX_TX_QUEUES 128
14 #define IXGBE_X540_MAX_RX_QUEUES 128
15 #define IXGBE_X540_RAR_ENTRIES 128
16 #define IXGBE_X540_MC_TBL_SIZE 128
17 #define IXGBE_X540_VFT_TBL_SIZE 128
18 #define IXGBE_X540_RX_PB_SIZE 384
19
20 static int ixgbe_update_flash_X540(struct ixgbe_hw *hw);
21 static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
22 static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
23 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
24
ixgbe_get_media_type_X540(struct ixgbe_hw * hw)25 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
26 {
27 return ixgbe_media_type_copper;
28 }
29
ixgbe_get_invariants_X540(struct ixgbe_hw * hw)30 int ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
31 {
32 struct ixgbe_mac_info *mac = &hw->mac;
33 struct ixgbe_phy_info *phy = &hw->phy;
34
35 /* set_phy_power was set by default to NULL */
36 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
37
38 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
39 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
40 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
41 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
42 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
43 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
44 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
45
46 return 0;
47 }
48
49 /**
50 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
51 * @hw: pointer to hardware structure
52 * @speed: new link speed
53 * @autoneg_wait_to_complete: true when waiting for completion is needed
54 **/
ixgbe_setup_mac_link_X540(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)55 int ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete)
57 {
58 return hw->phy.ops.setup_link_speed(hw, speed,
59 autoneg_wait_to_complete);
60 }
61
62 /**
63 * ixgbe_reset_hw_X540 - Perform hardware reset
64 * @hw: pointer to hardware structure
65 *
66 * Resets the hardware by resetting the transmit and receive units, masks
67 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
68 * reset.
69 *
70 * Return: 0 on success or negative value on failure
71 */
ixgbe_reset_hw_X540(struct ixgbe_hw * hw)72 int ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
73 {
74 u32 swfw_mask = hw->phy.phy_semaphore_mask;
75 u32 ctrl, i;
76 int status;
77
78 /* Call adapter stop to disable tx/rx and clear interrupts */
79 status = hw->mac.ops.stop_adapter(hw);
80 if (status)
81 return status;
82
83 /* flush pending Tx transactions */
84 ixgbe_clear_tx_pending(hw);
85
86 mac_reset_top:
87 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
88 if (status) {
89 hw_dbg(hw, "semaphore failed with %d", status);
90 return -EBUSY;
91 }
92
93 ctrl = IXGBE_CTRL_RST;
94 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
95 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
96 IXGBE_WRITE_FLUSH(hw);
97 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
98 usleep_range(1000, 1200);
99
100 /* Poll for reset bit to self-clear indicating reset is complete */
101 for (i = 0; i < 10; i++) {
102 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
103 if (!(ctrl & IXGBE_CTRL_RST_MASK))
104 break;
105 udelay(1);
106 }
107
108 if (ctrl & IXGBE_CTRL_RST_MASK) {
109 status = -EIO;
110 hw_dbg(hw, "Reset polling failed to complete.\n");
111 }
112 msleep(100);
113
114 /*
115 * Double resets are required for recovery from certain error
116 * conditions. Between resets, it is necessary to stall to allow time
117 * for any pending HW events to complete.
118 */
119 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
120 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
121 goto mac_reset_top;
122 }
123
124 /* Set the Rx packet buffer size. */
125 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
126
127 /* Store the permanent mac address */
128 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
129
130 /*
131 * Store MAC address from RAR0, clear receive address registers, and
132 * clear the multicast table. Also reset num_rar_entries to 128,
133 * since we modify this value when programming the SAN MAC address.
134 */
135 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
136 hw->mac.ops.init_rx_addrs(hw);
137
138 /* The following is not supported by E610. */
139 if (hw->mac.type == ixgbe_mac_e610)
140 return status;
141
142 /* Store the permanent SAN mac address */
143 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
144
145 /* Add the SAN MAC address to RAR if it's a valid address */
146 if (is_valid_ether_addr(hw->mac.san_addr)) {
147 /* Save the SAN MAC RAR index */
148 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
149
150 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
151 hw->mac.san_addr, 0, IXGBE_RAH_AV);
152
153 /* clear VMDq pool/queue selection for this RAR */
154 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
155 IXGBE_CLEAR_VMDQ_ALL);
156
157 /* Reserve the last RAR for the SAN MAC address */
158 hw->mac.num_rar_entries--;
159 }
160
161 /* Store the alternative WWNN/WWPN prefix */
162 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
163 &hw->mac.wwpn_prefix);
164
165 return status;
166 }
167
168 /**
169 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
170 * @hw: pointer to hardware structure
171 *
172 * Starts the hardware using the generic start_hw function
173 * and the generation start_hw function.
174 * Then performs revision-specific operations, if any.
175 **/
ixgbe_start_hw_X540(struct ixgbe_hw * hw)176 int ixgbe_start_hw_X540(struct ixgbe_hw *hw)
177 {
178 int ret_val;
179
180 ret_val = ixgbe_start_hw_generic(hw);
181 if (ret_val)
182 return ret_val;
183
184 return ixgbe_start_hw_gen2(hw);
185 }
186
187 /**
188 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
189 * @hw: pointer to hardware structure
190 *
191 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
192 * ixgbe_hw struct in order to set up EEPROM access.
193 **/
ixgbe_init_eeprom_params_X540(struct ixgbe_hw * hw)194 int ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
195 {
196 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
197
198 if (eeprom->type == ixgbe_eeprom_uninitialized) {
199 u16 eeprom_size;
200 u32 eec;
201
202 eeprom->semaphore_delay = 10;
203 eeprom->type = ixgbe_flash;
204
205 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
206 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
207 eeprom->word_size = BIT(eeprom_size +
208 IXGBE_EEPROM_WORD_SIZE_SHIFT);
209
210 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
211 eeprom->type, eeprom->word_size);
212 }
213
214 return 0;
215 }
216
217 /**
218 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
219 * @hw: pointer to hardware structure
220 * @offset: offset of word in the EEPROM to read
221 * @data: word read from the EEPROM
222 *
223 * Reads a 16 bit word from the EEPROM using the EERD register.
224 **/
ixgbe_read_eerd_X540(struct ixgbe_hw * hw,u16 offset,u16 * data)225 static int ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
226 {
227 int status;
228
229 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
230 return -EBUSY;
231
232 status = ixgbe_read_eerd_generic(hw, offset, data);
233
234 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
235 return status;
236 }
237
238 /**
239 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
240 * @hw: pointer to hardware structure
241 * @offset: offset of word in the EEPROM to read
242 * @words: number of words
243 * @data: word(s) read from the EEPROM
244 *
245 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
246 **/
ixgbe_read_eerd_buffer_X540(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)247 static int ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
248 u16 offset, u16 words, u16 *data)
249 {
250 int status;
251
252 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
253 return -EBUSY;
254
255 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
256
257 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
258 return status;
259 }
260
261 /**
262 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
263 * @hw: pointer to hardware structure
264 * @offset: offset of word in the EEPROM to write
265 * @data: word write to the EEPROM
266 *
267 * Write a 16 bit word to the EEPROM using the EEWR register.
268 **/
ixgbe_write_eewr_X540(struct ixgbe_hw * hw,u16 offset,u16 data)269 static int ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
270 {
271 int status;
272
273 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
274 return -EBUSY;
275
276 status = ixgbe_write_eewr_generic(hw, offset, data);
277
278 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
279 return status;
280 }
281
282 /**
283 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
284 * @hw: pointer to hardware structure
285 * @offset: offset of word in the EEPROM to write
286 * @words: number of words
287 * @data: word(s) write to the EEPROM
288 *
289 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
290 **/
ixgbe_write_eewr_buffer_X540(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)291 static int ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
292 u16 offset, u16 words, u16 *data)
293 {
294 int status;
295
296 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
297 return -EBUSY;
298
299 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
300
301 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
302 return status;
303 }
304
305 /**
306 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
307 *
308 * This function does not use synchronization for EERD and EEWR. It can
309 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
310 *
311 * @hw: pointer to hardware structure
312 **/
ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw * hw)313 static int ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
314 {
315 u16 i;
316 u16 j;
317 u16 checksum = 0;
318 u16 length = 0;
319 u16 pointer = 0;
320 u16 word = 0;
321 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
322 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
323
324 /*
325 * Do not use hw->eeprom.ops.read because we do not want to take
326 * the synchronization semaphores here. Instead use
327 * ixgbe_read_eerd_generic
328 */
329
330 /* Include 0x0-0x3F in the checksum */
331 for (i = 0; i < checksum_last_word; i++) {
332 if (ixgbe_read_eerd_generic(hw, i, &word)) {
333 hw_dbg(hw, "EEPROM read failed\n");
334 return -EIO;
335 }
336 checksum += word;
337 }
338
339 /*
340 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
341 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
342 */
343 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
344 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
345 continue;
346
347 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
348 hw_dbg(hw, "EEPROM read failed\n");
349 break;
350 }
351
352 /* Skip pointer section if the pointer is invalid. */
353 if (pointer == 0xFFFF || pointer == 0 ||
354 pointer >= hw->eeprom.word_size)
355 continue;
356
357 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
358 hw_dbg(hw, "EEPROM read failed\n");
359 return -EIO;
360 }
361
362 /* Skip pointer section if length is invalid. */
363 if (length == 0xFFFF || length == 0 ||
364 (pointer + length) >= hw->eeprom.word_size)
365 continue;
366
367 for (j = pointer + 1; j <= pointer + length; j++) {
368 if (ixgbe_read_eerd_generic(hw, j, &word)) {
369 hw_dbg(hw, "EEPROM read failed\n");
370 return -EIO;
371 }
372 checksum += word;
373 }
374 }
375
376 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
377
378 return (int)checksum;
379 }
380
381 /**
382 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
383 * @hw: pointer to hardware structure
384 * @checksum_val: calculated checksum
385 *
386 * Performs checksum calculation and validates the EEPROM checksum. If the
387 * caller does not need checksum_val, the value can be NULL.
388 **/
ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw * hw,u16 * checksum_val)389 static int ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
390 u16 *checksum_val)
391 {
392 u16 read_checksum = 0;
393 u16 checksum;
394 int status;
395
396 /* Read the first word from the EEPROM. If this times out or fails, do
397 * not continue or we could be in for a very long wait while every
398 * EEPROM read fails
399 */
400 status = hw->eeprom.ops.read(hw, 0, &checksum);
401 if (status) {
402 hw_dbg(hw, "EEPROM read failed\n");
403 return status;
404 }
405
406 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
407 return -EBUSY;
408
409 status = hw->eeprom.ops.calc_checksum(hw);
410 if (status < 0)
411 goto out;
412
413 checksum = (u16)(status & 0xffff);
414
415 /* Do not use hw->eeprom.ops.read because we do not want to take
416 * the synchronization semaphores twice here.
417 */
418 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
419 &read_checksum);
420 if (status)
421 goto out;
422
423 /* Verify read checksum from EEPROM is the same as
424 * calculated checksum
425 */
426 if (read_checksum != checksum) {
427 hw_dbg(hw, "Invalid EEPROM checksum");
428 status = -EIO;
429 }
430
431 /* If the user cares, return the calculated checksum */
432 if (checksum_val)
433 *checksum_val = checksum;
434
435 out:
436 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
437
438 return status;
439 }
440
441 /**
442 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
443 * @hw: pointer to hardware structure
444 *
445 * After writing EEPROM to shadow RAM using EEWR register, software calculates
446 * checksum and updates the EEPROM and instructs the hardware to update
447 * the flash.
448 **/
ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw * hw)449 static int ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
450 {
451 u16 checksum;
452 int status;
453
454 /* Read the first word from the EEPROM. If this times out or fails, do
455 * not continue or we could be in for a very long wait while every
456 * EEPROM read fails
457 */
458 status = hw->eeprom.ops.read(hw, 0, &checksum);
459 if (status) {
460 hw_dbg(hw, "EEPROM read failed\n");
461 return status;
462 }
463
464 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
465 return -EBUSY;
466
467 status = hw->eeprom.ops.calc_checksum(hw);
468 if (status < 0)
469 goto out;
470
471 checksum = (u16)(status & 0xffff);
472
473 /* Do not use hw->eeprom.ops.write because we do not want to
474 * take the synchronization semaphores twice here.
475 */
476 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
477 if (status)
478 goto out;
479
480 status = ixgbe_update_flash_X540(hw);
481
482 out:
483 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
484 return status;
485 }
486
487 /**
488 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
489 * @hw: pointer to hardware structure
490 *
491 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
492 * EEPROM from shadow RAM to the flash device.
493 **/
ixgbe_update_flash_X540(struct ixgbe_hw * hw)494 static int ixgbe_update_flash_X540(struct ixgbe_hw *hw)
495 {
496 int status;
497 u32 flup;
498
499 status = ixgbe_poll_flash_update_done_X540(hw);
500 if (status == -EIO) {
501 hw_dbg(hw, "Flash update time out\n");
502 return status;
503 }
504
505 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
506 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
507
508 status = ixgbe_poll_flash_update_done_X540(hw);
509 if (status == 0)
510 hw_dbg(hw, "Flash update complete\n");
511 else
512 hw_dbg(hw, "Flash update time out\n");
513
514 if (hw->revision_id == 0) {
515 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
516
517 if (flup & IXGBE_EEC_SEC1VAL) {
518 flup |= IXGBE_EEC_FLUP;
519 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
520 }
521
522 status = ixgbe_poll_flash_update_done_X540(hw);
523 if (status == 0)
524 hw_dbg(hw, "Flash update complete\n");
525 else
526 hw_dbg(hw, "Flash update time out\n");
527 }
528
529 return status;
530 }
531
532 /**
533 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
534 * @hw: pointer to hardware structure
535 *
536 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
537 * flash update is done.
538 **/
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw * hw)539 static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
540 {
541 u32 i;
542 u32 reg;
543
544 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
545 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
546 if (reg & IXGBE_EEC_FLUDONE)
547 return 0;
548 udelay(5);
549 }
550 return -EIO;
551 }
552
553 /**
554 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
555 * @hw: pointer to hardware structure
556 * @mask: Mask to specify which semaphore to acquire
557 *
558 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
559 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
560 **/
ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw * hw,u32 mask)561 int ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
562 {
563 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
564 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
565 u32 fwmask = swmask << 5;
566 u32 timeout = 200;
567 u32 hwmask = 0;
568 u32 swfw_sync;
569 u32 i;
570
571 if (swmask & IXGBE_GSSR_EEP_SM)
572 hwmask = IXGBE_GSSR_FLASH_SM;
573
574 /* SW only mask does not have FW bit pair */
575 if (mask & IXGBE_GSSR_SW_MNG_SM)
576 swmask |= IXGBE_GSSR_SW_MNG_SM;
577
578 swmask |= swi2c_mask;
579 fwmask |= swi2c_mask << 2;
580 for (i = 0; i < timeout; i++) {
581 /* SW NVM semaphore bit is used for access to all
582 * SW_FW_SYNC bits (not just NVM)
583 */
584 if (ixgbe_get_swfw_sync_semaphore(hw))
585 return -EBUSY;
586
587 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
588 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
589 swfw_sync |= swmask;
590 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
591 ixgbe_release_swfw_sync_semaphore(hw);
592 usleep_range(5000, 6000);
593 return 0;
594 }
595 /* Firmware currently using resource (fwmask), hardware
596 * currently using resource (hwmask), or other software
597 * thread currently using resource (swmask)
598 */
599 ixgbe_release_swfw_sync_semaphore(hw);
600 usleep_range(5000, 10000);
601 }
602
603 /* If the resource is not released by the FW/HW the SW can assume that
604 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
605 * of the requested resource(s) while ignoring the corresponding FW/HW
606 * bits in the SW_FW_SYNC register.
607 */
608 if (ixgbe_get_swfw_sync_semaphore(hw))
609 return -EBUSY;
610 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
611 if (swfw_sync & (fwmask | hwmask)) {
612 swfw_sync |= swmask;
613 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
614 ixgbe_release_swfw_sync_semaphore(hw);
615 usleep_range(5000, 6000);
616 return 0;
617 }
618 /* If the resource is not released by other SW the SW can assume that
619 * the other SW malfunctions. In that case the SW should clear all SW
620 * flags that it does not own and then repeat the whole process once
621 * again.
622 */
623 if (swfw_sync & swmask) {
624 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
625 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
626 IXGBE_GSSR_SW_MNG_SM;
627
628 if (swi2c_mask)
629 rmask |= IXGBE_GSSR_I2C_MASK;
630 ixgbe_release_swfw_sync_X540(hw, rmask);
631 ixgbe_release_swfw_sync_semaphore(hw);
632 return -EBUSY;
633 }
634 ixgbe_release_swfw_sync_semaphore(hw);
635
636 return -EBUSY;
637 }
638
639 /**
640 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
641 * @hw: pointer to hardware structure
642 * @mask: Mask to specify which semaphore to release
643 *
644 * Releases the SWFW semaphore through the SW_FW_SYNC register
645 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
646 **/
ixgbe_release_swfw_sync_X540(struct ixgbe_hw * hw,u32 mask)647 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
648 {
649 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
650 u32 swfw_sync;
651
652 if (mask & IXGBE_GSSR_I2C_MASK)
653 swmask |= mask & IXGBE_GSSR_I2C_MASK;
654 ixgbe_get_swfw_sync_semaphore(hw);
655
656 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
657 swfw_sync &= ~swmask;
658 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
659
660 ixgbe_release_swfw_sync_semaphore(hw);
661 usleep_range(5000, 6000);
662 }
663
664 /**
665 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
666 * @hw: pointer to hardware structure
667 *
668 * Sets the hardware semaphores so SW/FW can gain control of shared resources
669 */
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw * hw)670 static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
671 {
672 u32 timeout = 2000;
673 u32 i;
674 u32 swsm;
675
676 /* Get SMBI software semaphore between device drivers first */
677 for (i = 0; i < timeout; i++) {
678 /* If the SMBI bit is 0 when we read it, then the bit will be
679 * set and we have the semaphore
680 */
681 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
682 if (!(swsm & IXGBE_SWSM_SMBI))
683 break;
684 usleep_range(50, 100);
685 }
686
687 if (i == timeout) {
688 hw_dbg(hw,
689 "Software semaphore SMBI between device drivers not granted.\n");
690 return -EIO;
691 }
692
693 /* Now get the semaphore between SW/FW through the REGSMP bit */
694 for (i = 0; i < timeout; i++) {
695 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
696 if (!(swsm & IXGBE_SWFW_REGSMP))
697 return 0;
698
699 usleep_range(50, 100);
700 }
701
702 /* Release semaphores and return error if SW NVM semaphore
703 * was not granted because we do not have access to the EEPROM
704 */
705 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
706 ixgbe_release_swfw_sync_semaphore(hw);
707 return -EIO;
708 }
709
710 /**
711 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
712 * @hw: pointer to hardware structure
713 *
714 * This function clears hardware semaphore bits.
715 **/
ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw * hw)716 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
717 {
718 u32 swsm;
719
720 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
721
722 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
723 swsm &= ~IXGBE_SWFW_REGSMP;
724 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
725
726 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
727 swsm &= ~IXGBE_SWSM_SMBI;
728 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
729
730 IXGBE_WRITE_FLUSH(hw);
731 }
732
733 /**
734 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
735 * @hw: pointer to hardware structure
736 *
737 * This function reset hardware semaphore bits for a semaphore that may
738 * have be left locked due to a catastrophic failure.
739 **/
ixgbe_init_swfw_sync_X540(struct ixgbe_hw * hw)740 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
741 {
742 u32 rmask;
743
744 /* First try to grab the semaphore but we don't need to bother
745 * looking to see whether we got the lock or not since we do
746 * the same thing regardless of whether we got the lock or not.
747 * We got the lock - we release it.
748 * We timeout trying to get the lock - we force its release.
749 */
750 ixgbe_get_swfw_sync_semaphore(hw);
751 ixgbe_release_swfw_sync_semaphore(hw);
752
753 /* Acquire and release all software resources. */
754 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
755 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
756 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
757
758 ixgbe_acquire_swfw_sync_X540(hw, rmask);
759 ixgbe_release_swfw_sync_X540(hw, rmask);
760 }
761
762 /**
763 * ixgbe_blink_led_start_X540 - Blink LED based on index.
764 * @hw: pointer to hardware structure
765 * @index: led number to blink
766 *
767 * Devices that implement the version 2 interface:
768 * X540
769 **/
ixgbe_blink_led_start_X540(struct ixgbe_hw * hw,u32 index)770 int ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
771 {
772 u32 macc_reg;
773 u32 ledctl_reg;
774 ixgbe_link_speed speed;
775 bool link_up;
776
777 if (index > 3)
778 return -EINVAL;
779
780 /* Link should be up in order for the blink bit in the LED control
781 * register to work. Force link and speed in the MAC if link is down.
782 * This will be reversed when we stop the blinking.
783 */
784 hw->mac.ops.check_link(hw, &speed, &link_up, false);
785 if (!link_up) {
786 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
787 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
788 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
789 }
790 /* Set the LED to LINK_UP + BLINK. */
791 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
792 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
793 ledctl_reg |= IXGBE_LED_BLINK(index);
794 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
795 IXGBE_WRITE_FLUSH(hw);
796
797 return 0;
798 }
799
800 /**
801 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
802 * @hw: pointer to hardware structure
803 * @index: led number to stop blinking
804 *
805 * Devices that implement the version 2 interface:
806 * X540
807 **/
ixgbe_blink_led_stop_X540(struct ixgbe_hw * hw,u32 index)808 int ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
809 {
810 u32 macc_reg;
811 u32 ledctl_reg;
812
813 if (index > 3)
814 return -EINVAL;
815
816 /* Restore the LED to its default value. */
817 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
818 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
819 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
820 ledctl_reg &= ~IXGBE_LED_BLINK(index);
821 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
822
823 /* Unforce link and speed in the MAC. */
824 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
825 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
826 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
827 IXGBE_WRITE_FLUSH(hw);
828
829 return 0;
830 }
831 static const struct ixgbe_mac_operations mac_ops_X540 = {
832 .init_hw = &ixgbe_init_hw_generic,
833 .reset_hw = &ixgbe_reset_hw_X540,
834 .start_hw = &ixgbe_start_hw_X540,
835 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
836 .get_media_type = &ixgbe_get_media_type_X540,
837 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
838 .get_mac_addr = &ixgbe_get_mac_addr_generic,
839 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
840 .get_device_caps = &ixgbe_get_device_caps_generic,
841 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
842 .stop_adapter = &ixgbe_stop_adapter_generic,
843 .get_bus_info = &ixgbe_get_bus_info_generic,
844 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
845 .read_analog_reg8 = NULL,
846 .write_analog_reg8 = NULL,
847 .setup_link = &ixgbe_setup_mac_link_X540,
848 .set_rxpba = &ixgbe_set_rxpba_generic,
849 .check_link = &ixgbe_check_mac_link_generic,
850 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
851 .led_on = &ixgbe_led_on_generic,
852 .led_off = &ixgbe_led_off_generic,
853 .init_led_link_act = ixgbe_init_led_link_act_generic,
854 .blink_led_start = &ixgbe_blink_led_start_X540,
855 .blink_led_stop = &ixgbe_blink_led_stop_X540,
856 .set_rar = &ixgbe_set_rar_generic,
857 .clear_rar = &ixgbe_clear_rar_generic,
858 .set_vmdq = &ixgbe_set_vmdq_generic,
859 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
860 .clear_vmdq = &ixgbe_clear_vmdq_generic,
861 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
862 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
863 .enable_mc = &ixgbe_enable_mc_generic,
864 .disable_mc = &ixgbe_disable_mc_generic,
865 .clear_vfta = &ixgbe_clear_vfta_generic,
866 .set_vfta = &ixgbe_set_vfta_generic,
867 .fc_enable = &ixgbe_fc_enable_generic,
868 .setup_fc = ixgbe_setup_fc_generic,
869 .fc_autoneg = ixgbe_fc_autoneg,
870 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
871 .init_uta_tables = &ixgbe_init_uta_tables_generic,
872 .setup_sfp = NULL,
873 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
874 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
875 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
876 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
877 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
878 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
879 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
880 .get_thermal_sensor_data = NULL,
881 .init_thermal_sensor_thresh = NULL,
882 .prot_autoc_read = &prot_autoc_read_generic,
883 .prot_autoc_write = &prot_autoc_write_generic,
884 .enable_rx = &ixgbe_enable_rx_generic,
885 .disable_rx = &ixgbe_disable_rx_generic,
886 };
887
888 static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
889 .init_params = &ixgbe_init_eeprom_params_X540,
890 .read = &ixgbe_read_eerd_X540,
891 .read_buffer = &ixgbe_read_eerd_buffer_X540,
892 .write = &ixgbe_write_eewr_X540,
893 .write_buffer = &ixgbe_write_eewr_buffer_X540,
894 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
895 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
896 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
897 };
898
899 static const struct ixgbe_phy_operations phy_ops_X540 = {
900 .identify = &ixgbe_identify_phy_generic,
901 .identify_sfp = &ixgbe_identify_sfp_module_generic,
902 .init = NULL,
903 .reset = NULL,
904 .read_reg = &ixgbe_read_phy_reg_generic,
905 .write_reg = &ixgbe_write_phy_reg_generic,
906 .setup_link = &ixgbe_setup_phy_link_generic,
907 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
908 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
909 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
910 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
911 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
912 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
913 .check_overtemp = &ixgbe_tn_check_overtemp,
914 .set_phy_power = &ixgbe_set_copper_phy_power,
915 };
916
917 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
918 IXGBE_MVALS_INIT(X540)
919 };
920
921 const struct ixgbe_info ixgbe_X540_info = {
922 .mac = ixgbe_mac_X540,
923 .get_invariants = &ixgbe_get_invariants_X540,
924 .mac_ops = &mac_ops_X540,
925 .eeprom_ops = &eeprom_ops_X540,
926 .phy_ops = &phy_ops_X540,
927 .mbx_ops = &mbx_ops_generic,
928 .mvals = ixgbe_mvals_X540,
929 };
930