1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2024 Hisilicon Limited. */ 3 4 #ifndef __HBG_COMMON_H 5 #define __HBG_COMMON_H 6 7 #include <linux/ethtool.h> 8 #include <linux/netdevice.h> 9 #include <linux/pci.h> 10 #include "hbg_reg.h" 11 12 #define HBG_STATUS_DISABLE 0x0 13 #define HBG_STATUS_ENABLE 0x1 14 #define HBG_RX_SKIP1 0x00 15 #define HBG_RX_SKIP2 0x01 16 #define HBG_VECTOR_NUM 4 17 #define HBG_PCU_CACHE_LINE_SIZE 32 18 #define HBG_TX_TIMEOUT_BUF_LEN 1024 19 #define HBG_RX_DESCR 0x01 20 21 #define HBG_PACKET_HEAD_SIZE ((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \ 22 HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE) 23 24 enum hbg_dir { 25 HBG_DIR_TX = 1 << 0, 26 HBG_DIR_RX = 1 << 1, 27 HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX, 28 }; 29 30 enum hbg_tx_state { 31 HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */ 32 HBG_TX_STATE_START, 33 }; 34 35 enum hbg_nic_state { 36 HBG_NIC_STATE_EVENT_HANDLING = 0, 37 HBG_NIC_STATE_RESETTING, 38 HBG_NIC_STATE_RESET_FAIL, 39 }; 40 41 enum hbg_reset_type { 42 HBG_RESET_TYPE_NONE = 0, 43 HBG_RESET_TYPE_FLR, 44 HBG_RESET_TYPE_FUNCTION, 45 }; 46 47 struct hbg_buffer { 48 u32 state; 49 dma_addr_t state_dma; 50 51 struct sk_buff *skb; 52 dma_addr_t skb_dma; 53 u32 skb_len; 54 55 enum hbg_dir dir; 56 struct hbg_ring *ring; 57 struct hbg_priv *priv; 58 }; 59 60 struct hbg_ring { 61 struct hbg_buffer *queue; 62 dma_addr_t queue_dma; 63 64 union { 65 u32 head; 66 u32 ntc; 67 }; 68 union { 69 u32 tail; 70 u32 ntu; 71 }; 72 u32 len; 73 74 enum hbg_dir dir; 75 struct hbg_priv *priv; 76 struct napi_struct napi; 77 char *tout_log_buf; /* tx timeout log buffer */ 78 }; 79 80 enum hbg_hw_event_type { 81 HBG_HW_EVENT_NONE = 0, 82 HBG_HW_EVENT_INIT, /* driver is loading */ 83 HBG_HW_EVENT_RESET, 84 }; 85 86 struct hbg_dev_specs { 87 u32 mac_id; 88 struct sockaddr mac_addr; 89 u32 phy_addr; 90 u32 mdio_frequency; 91 u32 rx_fifo_num; 92 u32 tx_fifo_num; 93 u32 vlan_layers; 94 u32 max_mtu; 95 u32 min_mtu; 96 u32 uc_mac_num; 97 98 u32 max_frame_len; 99 u32 rx_buf_size; 100 }; 101 102 struct hbg_irq_info { 103 const char *name; 104 u32 mask; 105 bool re_enable; 106 bool need_print; 107 u64 count; 108 109 void (*irq_handle)(struct hbg_priv *priv, struct hbg_irq_info *info); 110 }; 111 112 struct hbg_vector { 113 char name[HBG_VECTOR_NUM][32]; 114 struct hbg_irq_info *info_array; 115 u32 info_array_len; 116 }; 117 118 struct hbg_mac { 119 struct mii_bus *mdio_bus; 120 struct phy_device *phydev; 121 u8 phy_addr; 122 123 u32 speed; 124 u32 duplex; 125 u32 autoneg; 126 u32 link_status; 127 u32 pause_autoneg; 128 }; 129 130 struct hbg_mac_table_entry { 131 u8 addr[ETH_ALEN]; 132 }; 133 134 struct hbg_mac_filter { 135 struct hbg_mac_table_entry *mac_table; 136 u32 table_max_len; 137 bool enabled; 138 }; 139 140 /* saved for restore after rest */ 141 struct hbg_user_def { 142 struct ethtool_pauseparam pause_param; 143 }; 144 145 struct hbg_priv { 146 struct net_device *netdev; 147 struct pci_dev *pdev; 148 u8 __iomem *io_base; 149 struct hbg_dev_specs dev_specs; 150 unsigned long state; 151 struct hbg_mac mac; 152 struct hbg_vector vectors; 153 struct hbg_ring tx_ring; 154 struct hbg_ring rx_ring; 155 struct hbg_mac_filter filter; 156 enum hbg_reset_type reset_type; 157 struct hbg_user_def user_def; 158 }; 159 160 #endif 161