1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Atlantic Network Driver 3 * 4 * Copyright (C) 2014-2019 aQuantia Corporation 5 * Copyright (C) 2019-2020 Marvell International Ltd. 6 */ 7 8 /* File hw_atl_llh_internal.h: Preprocessor definitions 9 * for Atlantic registers. 10 */ 11 12 #ifndef HW_ATL_LLH_INTERNAL_H 13 #define HW_ATL_LLH_INTERNAL_H 14 15 /* COM Temperature Sense Reset Bitfield Definitions */ 16 #define HW_ATL_TS_RESET_ADR 0x00003100 17 #define HW_ATL_TS_RESET_MSK 0x00000004 18 #define HW_ATL_TS_RESET_SHIFT 2 19 #define HW_ATL_TS_RESET_WIDTH 1 20 21 /* COM Temperature Sense Power Down Bitfield Definitions */ 22 #define HW_ATL_TS_POWER_DOWN_ADR 0x00003100 23 #define HW_ATL_TS_POWER_DOWN_MSK 0x00000001 24 #define HW_ATL_TS_POWER_DOWN_SHIFT 0 25 #define HW_ATL_TS_POWER_DOWN_WIDTH 1 26 27 /* COM Temperature Sense Ready Bitfield Definitions */ 28 #define HW_ATL_TS_READY_ADR 0x00003120 29 #define HW_ATL_TS_READY_MSK 0x80000000 30 #define HW_ATL_TS_READY_SHIFT 31 31 #define HW_ATL_TS_READY_WIDTH 1 32 33 /* COM Temperature Sense Ready Latch High Bitfield Definitions */ 34 #define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120 35 #define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000 36 #define HW_ATL_TS_READY_LATCH_HIGH_SHIFT 30 37 #define HW_ATL_TS_READY_LATCH_HIGH_WIDTH 1 38 39 /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */ 40 #define HW_ATL_TS_DATA_OUT_ADR 0x00003120 41 #define HW_ATL_TS_DATA_OUT_MSK 0x00000FFF 42 #define HW_ATL_TS_DATA_OUT_SHIFT 0 43 #define HW_ATL_TS_DATA_OUT_WIDTH 12 44 45 /* SMBUS0 Received Data register */ 46 #define HW_ATL_SMB0_RECEIVED_DATA_ADR 0x00000748 47 /* SMBUS0 Transmitted Data register */ 48 #define HW_ATL_SMB0_TRANSMITTED_DATA_ADR 0x00000608 49 50 /* SMBUS0 Global Provisioning 2 register */ 51 #define HW_ATL_SMB0_PROVISIONING2_ADR 0x00000604 52 53 /* SMBUS0 Bus Busy Bitfield Definitions */ 54 #define HW_ATL_SMB0_BUS_BUSY_ADR 0x00000744 55 #define HW_ATL_SMB0_BUS_BUSY_MSK 0x00000080 56 #define HW_ATL_SMB0_BUS_BUSY_SHIFT 7 57 #define HW_ATL_SMB0_BUS_BUSY_WIDTH 1 58 59 /* SMBUS0 Byte Transfer Complete Bitfield Definitions */ 60 #define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_ADR 0x00000744 61 #define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_MSK 0x00000002 62 #define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_SHIFT 1 63 #define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_WIDTH 1 64 65 /* SMBUS0 Receive Acknowledge Bitfield Definitions */ 66 #define HW_ATL_SMB0_RX_ACKNOWLEDGED_ADR 0x00000744 67 #define HW_ATL_SMB0_RX_ACKNOWLEDGED_MSK 0x00000100 68 #define HW_ATL_SMB0_RX_ACKNOWLEDGED_SHIFT 8 69 #define HW_ATL_SMB0_RX_ACKNOWLEDGED_WIDTH 1 70 71 /* SMBUS0 Repeated Start Detect Bitfield Definitions */ 72 #define HW_ATL_SMB0_REPEATED_START_DETECT_ADR 0x00000744 73 #define HW_ATL_SMB0_REPEATED_START_DETECT_MSK 0x00000004 74 #define HW_ATL_SMB0_REPEATED_START_DETECT_SHIFT 2 75 #define HW_ATL_SMB0_REPEATED_START_DETECT_WIDTH 1 76 77 /* global microprocessor semaphore definitions 78 * base address: 0x000003a0 79 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 80 */ 81 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 82 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 83 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 84 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 85 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 86 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 87 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 88 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 89 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 90 91 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 92 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 93 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 94 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 95 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 96 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 97 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 98 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 99 100 /* preprocessor definitions for msm rx errors counter register */ 101 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 102 103 /* preprocessor definitions for msm rx unicast frames counter register */ 104 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 105 106 /* preprocessor definitions for msm rx multicast frames counter register */ 107 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 108 109 /* preprocessor definitions for msm rx broadcast frames counter register */ 110 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 111 112 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 113 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 114 115 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 116 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 117 118 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 119 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 120 121 /* preprocessor definitions for msm tx unicast frames counter register */ 122 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 123 124 /* preprocessor definitions for msm tx multicast frames counter register */ 125 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 126 127 /* preprocessor definitions for global mif identification */ 128 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 129 130 /* register address for bitfield iamr_lsw[1f:0] */ 131 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 132 /* register address for bitfield rx dma drop packet counter [1f:0] */ 133 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 134 135 /* register address for bitfield imcr_lsw[1f:0] */ 136 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 137 /* register address for bitfield imsr_lsw[1f:0] */ 138 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 139 /* register address for bitfield itr_reg_res_dsbl */ 140 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 141 /* bitmask for bitfield itr_reg_res_dsbl */ 142 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 143 /* lower bit position of bitfield itr_reg_res_dsbl */ 144 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 145 /* register address for bitfield iscr_lsw[1f:0] */ 146 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 147 /* register address for bitfield isr_lsw[1f:0] */ 148 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000 149 /* register address for bitfield itr_reset */ 150 #define HW_ATL_ITR_RES_ADR 0x00002300 151 /* bitmask for bitfield itr_reset */ 152 #define HW_ATL_ITR_RES_MSK 0x80000000 153 /* lower bit position of bitfield itr_reset */ 154 #define HW_ATL_ITR_RES_SHIFT 31 155 156 /* register address for bitfield rsc_en */ 157 #define HW_ATL_ITR_RSC_EN_ADR 0x00002200 158 159 /* register address for bitfield rsc_delay */ 160 #define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204 161 /* bitmask for bitfield rsc_delay */ 162 #define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f 163 /* width of bitfield rsc_delay */ 164 #define HW_ATL_ITR_RSC_DELAY_WIDTH 4 165 /* lower bit position of bitfield rsc_delay */ 166 #define HW_ATL_ITR_RSC_DELAY_SHIFT 0 167 168 /* register address for bitfield dca{d}_cpuid[7:0] */ 169 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 170 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 171 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 172 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 173 #define HW_ATL_RDM_DCADCPUID_SHIFT 0 174 /* register address for bitfield dca_en */ 175 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 176 177 /* rx dca_en bitfield definitions 178 * preprocessor definitions for the bitfield "dca_en". 179 * port="pif_rdm_dca_en_i" 180 */ 181 182 /* register address for bitfield dca_en */ 183 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 184 /* bitmask for bitfield dca_en */ 185 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000 186 /* inverted bitmask for bitfield dca_en */ 187 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 188 /* lower bit position of bitfield dca_en */ 189 #define HW_ATL_RDM_DCA_EN_SHIFT 31 190 /* width of bitfield dca_en */ 191 #define HW_ATL_RDM_DCA_EN_WIDTH 1 192 /* default value of bitfield dca_en */ 193 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 194 195 /* rx dca_mode[3:0] bitfield definitions 196 * preprocessor definitions for the bitfield "dca_mode[3:0]". 197 * port="pif_rdm_dca_mode_i[3:0]" 198 */ 199 200 /* register address for bitfield dca_mode[3:0] */ 201 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 202 /* bitmask for bitfield dca_mode[3:0] */ 203 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 204 /* inverted bitmask for bitfield dca_mode[3:0] */ 205 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 206 /* lower bit position of bitfield dca_mode[3:0] */ 207 #define HW_ATL_RDM_DCA_MODE_SHIFT 0 208 /* width of bitfield dca_mode[3:0] */ 209 #define HW_ATL_RDM_DCA_MODE_WIDTH 4 210 /* default value of bitfield dca_mode[3:0] */ 211 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 212 213 /* rx desc{d}_data_size[4:0] bitfield definitions 214 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 215 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 216 * port="pif_rdm_desc0_data_size_i[4:0]" 217 */ 218 219 /* register address for bitfield desc{d}_data_size[4:0] */ 220 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 221 (0x00005b18 + (descriptor) * 0x20) 222 /* bitmask for bitfield desc{d}_data_size[4:0] */ 223 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 224 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 225 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 226 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 227 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 228 /* width of bitfield desc{d}_data_size[4:0] */ 229 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 230 /* default value of bitfield desc{d}_data_size[4:0] */ 231 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 232 233 /* rx dca{d}_desc_en bitfield definitions 234 * preprocessor definitions for the bitfield "dca{d}_desc_en". 235 * parameter: dca {d} | stride size 0x4 | range [0, 31] 236 * port="pif_rdm_dca_desc_en_i[0]" 237 */ 238 239 /* register address for bitfield dca{d}_desc_en */ 240 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 241 /* bitmask for bitfield dca{d}_desc_en */ 242 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 243 /* inverted bitmask for bitfield dca{d}_desc_en */ 244 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 245 /* lower bit position of bitfield dca{d}_desc_en */ 246 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 247 /* width of bitfield dca{d}_desc_en */ 248 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 249 /* default value of bitfield dca{d}_desc_en */ 250 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 251 252 /* rx desc{d}_en bitfield definitions 253 * preprocessor definitions for the bitfield "desc{d}_en". 254 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 255 * port="pif_rdm_desc_en_i[0]" 256 */ 257 258 /* register address for bitfield desc{d}_en */ 259 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 260 /* bitmask for bitfield desc{d}_en */ 261 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000 262 /* inverted bitmask for bitfield desc{d}_en */ 263 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 264 /* lower bit position of bitfield desc{d}_en */ 265 #define HW_ATL_RDM_DESCDEN_SHIFT 31 266 /* width of bitfield desc{d}_en */ 267 #define HW_ATL_RDM_DESCDEN_WIDTH 1 268 /* default value of bitfield desc{d}_en */ 269 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 270 271 /* rx desc{d}_hdr_size[4:0] bitfield definitions 272 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 273 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 274 * port="pif_rdm_desc0_hdr_size_i[4:0]" 275 */ 276 277 /* register address for bitfield desc{d}_hdr_size[4:0] */ 278 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 279 (0x00005b18 + (descriptor) * 0x20) 280 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 281 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 282 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 283 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 284 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 285 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 286 /* width of bitfield desc{d}_hdr_size[4:0] */ 287 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 288 /* default value of bitfield desc{d}_hdr_size[4:0] */ 289 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 290 291 /* rx desc{d}_hdr_split bitfield definitions 292 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 293 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 294 * port="pif_rdm_desc_hdr_split_i[0]" 295 */ 296 297 /* register address for bitfield desc{d}_hdr_split */ 298 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 299 (0x00005b08 + (descriptor) * 0x20) 300 /* bitmask for bitfield desc{d}_hdr_split */ 301 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 302 /* inverted bitmask for bitfield desc{d}_hdr_split */ 303 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 304 /* lower bit position of bitfield desc{d}_hdr_split */ 305 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 306 /* width of bitfield desc{d}_hdr_split */ 307 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 308 /* default value of bitfield desc{d}_hdr_split */ 309 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 310 311 /* rx desc{d}_hd[c:0] bitfield definitions 312 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 313 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 314 * port="rdm_pif_desc0_hd_o[12:0]" 315 */ 316 317 /* register address for bitfield desc{d}_hd[c:0] */ 318 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 319 /* bitmask for bitfield desc{d}_hd[c:0] */ 320 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 321 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 322 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 323 /* lower bit position of bitfield desc{d}_hd[c:0] */ 324 #define HW_ATL_RDM_DESCDHD_SHIFT 0 325 /* width of bitfield desc{d}_hd[c:0] */ 326 #define HW_ATL_RDM_DESCDHD_WIDTH 13 327 328 /* rx desc{d}_len[9:0] bitfield definitions 329 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 330 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 331 * port="pif_rdm_desc0_len_i[9:0]" 332 */ 333 334 /* register address for bitfield desc{d}_len[9:0] */ 335 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 336 /* bitmask for bitfield desc{d}_len[9:0] */ 337 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 338 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 339 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 340 /* lower bit position of bitfield desc{d}_len[9:0] */ 341 #define HW_ATL_RDM_DESCDLEN_SHIFT 3 342 /* width of bitfield desc{d}_len[9:0] */ 343 #define HW_ATL_RDM_DESCDLEN_WIDTH 10 344 /* default value of bitfield desc{d}_len[9:0] */ 345 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 346 347 /* rx desc{d}_reset bitfield definitions 348 * preprocessor definitions for the bitfield "desc{d}_reset". 349 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 350 * port="pif_rdm_q_pf_res_i[0]" 351 */ 352 353 /* register address for bitfield desc{d}_reset */ 354 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 355 /* bitmask for bitfield desc{d}_reset */ 356 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 357 /* inverted bitmask for bitfield desc{d}_reset */ 358 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 359 /* lower bit position of bitfield desc{d}_reset */ 360 #define HW_ATL_RDM_DESCDRESET_SHIFT 25 361 /* width of bitfield desc{d}_reset */ 362 #define HW_ATL_RDM_DESCDRESET_WIDTH 1 363 /* default value of bitfield desc{d}_reset */ 364 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 365 366 /* rdm_desc_init_i bitfield definitions 367 * preprocessor definitions for the bitfield rdm_desc_init_i. 368 * port="pif_rdm_desc_init_i" 369 */ 370 371 /* register address for bitfield rdm_desc_init_i */ 372 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR 0x00005a00 373 /* bitmask for bitfield rdm_desc_init_i */ 374 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK 0xffffffff 375 /* inverted bitmask for bitfield rdm_desc_init_i */ 376 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN 0x00000000 377 /* lower bit position of bitfield rdm_desc_init_i */ 378 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT 0 379 /* width of bitfield rdm_desc_init_i */ 380 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32 381 /* default value of bitfield rdm_desc_init_i */ 382 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0 383 384 /* rdm_desc_init_done_i bitfield definitions 385 * preprocessor definitions for the bitfield rdm_desc_init_done_i. 386 * port="pif_rdm_desc_init_done_i" 387 */ 388 389 /* register address for bitfield rdm_desc_init_done_i */ 390 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10 391 /* bitmask for bitfield rdm_desc_init_done_i */ 392 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U 393 /* inverted bitmask for bitfield rdm_desc_init_done_i */ 394 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe 395 /* lower bit position of bitfield rdm_desc_init_done_i */ 396 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U 397 /* width of bitfield rdm_desc_init_done_i */ 398 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1 399 /* default value of bitfield rdm_desc_init_done_i */ 400 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0 401 402 403 /* rx int_desc_wrb_en bitfield definitions 404 * preprocessor definitions for the bitfield "int_desc_wrb_en". 405 * port="pif_rdm_int_desc_wrb_en_i" 406 */ 407 408 /* register address for bitfield int_desc_wrb_en */ 409 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 410 /* bitmask for bitfield int_desc_wrb_en */ 411 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 412 /* inverted bitmask for bitfield int_desc_wrb_en */ 413 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 414 /* lower bit position of bitfield int_desc_wrb_en */ 415 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 416 /* width of bitfield int_desc_wrb_en */ 417 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 418 /* default value of bitfield int_desc_wrb_en */ 419 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 420 421 /* rx dca{d}_hdr_en bitfield definitions 422 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 423 * parameter: dca {d} | stride size 0x4 | range [0, 31] 424 * port="pif_rdm_dca_hdr_en_i[0]" 425 */ 426 427 /* register address for bitfield dca{d}_hdr_en */ 428 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 429 /* bitmask for bitfield dca{d}_hdr_en */ 430 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 431 /* inverted bitmask for bitfield dca{d}_hdr_en */ 432 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 433 /* lower bit position of bitfield dca{d}_hdr_en */ 434 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 435 /* width of bitfield dca{d}_hdr_en */ 436 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 437 /* default value of bitfield dca{d}_hdr_en */ 438 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 439 440 /* rx dca{d}_pay_en bitfield definitions 441 * preprocessor definitions for the bitfield "dca{d}_pay_en". 442 * parameter: dca {d} | stride size 0x4 | range [0, 31] 443 * port="pif_rdm_dca_pay_en_i[0]" 444 */ 445 446 /* register address for bitfield dca{d}_pay_en */ 447 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 448 /* bitmask for bitfield dca{d}_pay_en */ 449 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 450 /* inverted bitmask for bitfield dca{d}_pay_en */ 451 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 452 /* lower bit position of bitfield dca{d}_pay_en */ 453 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 454 /* width of bitfield dca{d}_pay_en */ 455 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 456 /* default value of bitfield dca{d}_pay_en */ 457 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 458 459 /* RX rdm_int_rim_en Bitfield Definitions 460 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 461 * PORT="pif_rdm_int_rim_en_i" 462 */ 463 464 /* Register address for bitfield rdm_int_rim_en */ 465 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 466 /* Bitmask for bitfield rdm_int_rim_en */ 467 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 468 /* Inverted bitmask for bitfield rdm_int_rim_en */ 469 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 470 /* Lower bit position of bitfield rdm_int_rim_en */ 471 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 472 /* Width of bitfield rdm_int_rim_en */ 473 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 474 /* Default value of bitfield rdm_int_rim_en */ 475 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 476 477 /* general interrupt mapping register definitions 478 * preprocessor definitions for general interrupt mapping register 479 * base address: 0x00002180 480 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 481 */ 482 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 483 484 /* general interrupt status register definitions 485 * preprocessor definitions for general interrupt status register 486 * address: 0x000021A0 487 */ 488 489 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 490 491 /* interrupt global control register definitions 492 * preprocessor definitions for interrupt global control register 493 * address: 0x00002300 494 */ 495 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 496 497 /* interrupt throttle register definitions 498 * preprocessor definitions for interrupt throttle register 499 * base address: 0x00002800 500 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 501 */ 502 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 503 504 /* rx dma descriptor base address lsw definitions 505 * preprocessor definitions for rx dma descriptor base address lsw 506 * base address: 0x00005b00 507 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 508 */ 509 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 510 (0x00005b00u + (descriptor) * 0x20) 511 512 /* rx dma descriptor base address msw definitions 513 * preprocessor definitions for rx dma descriptor base address msw 514 * base address: 0x00005b04 515 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 516 */ 517 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 518 (0x00005b04u + (descriptor) * 0x20) 519 520 /* rx dma descriptor status register definitions 521 * preprocessor definitions for rx dma descriptor status register 522 * base address: 0x00005b14 523 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 524 */ 525 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 526 (0x00005b14u + (descriptor) * 0x20) 527 528 /* rx dma descriptor tail pointer register definitions 529 * preprocessor definitions for rx dma descriptor tail pointer register 530 * base address: 0x00005b10 531 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 532 */ 533 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 534 (0x00005b10u + (descriptor) * 0x20) 535 536 /* rx interrupt moderation control register definitions 537 * Preprocessor definitions for RX Interrupt Moderation Control Register 538 * Base Address: 0x00005A40 539 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 540 */ 541 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 542 543 /* rx filter multicast filter mask register definitions 544 * preprocessor definitions for rx filter multicast filter mask register 545 * address: 0x00005270 546 */ 547 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 548 549 /* rx filter multicast filter register definitions 550 * preprocessor definitions for rx filter multicast filter register 551 * base address: 0x00005250 552 * parameter: filter {f} | stride size 0x4 | range [0, 7] 553 */ 554 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 555 556 /* RX Filter RSS Control Register 1 Definitions 557 * Preprocessor definitions for RX Filter RSS Control Register 1 558 * Address: 0x000054C0 559 */ 560 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 561 562 /* RX Filter Control Register 2 Definitions 563 * Preprocessor definitions for RX Filter Control Register 2 564 * Address: 0x00005104 565 */ 566 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 567 568 /* tx tx dma debug control [1f:0] bitfield definitions 569 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 570 * port="pif_tdm_debug_cntl_i[31:0]" 571 */ 572 573 /* register address for bitfield tx dma debug control [1f:0] */ 574 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 575 /* bitmask for bitfield tx dma debug control [1f:0] */ 576 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 577 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 578 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 579 /* lower bit position of bitfield tx dma debug control [1f:0] */ 580 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 581 /* width of bitfield tx dma debug control [1f:0] */ 582 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 583 /* default value of bitfield tx dma debug control [1f:0] */ 584 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 585 586 /* tx dma descriptor base address lsw definitions 587 * preprocessor definitions for tx dma descriptor base address lsw 588 * base address: 0x00007c00 589 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 590 */ 591 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 592 (0x00007c00u + (descriptor) * 0x40) 593 594 /* tx dma descriptor tail pointer register definitions 595 * preprocessor definitions for tx dma descriptor tail pointer register 596 * base address: 0x00007c10 597 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 598 */ 599 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 600 (0x00007c10u + (descriptor) * 0x40) 601 602 /* rx dma_sys_loopback bitfield definitions 603 * preprocessor definitions for the bitfield "dma_sys_loopback". 604 * port="pif_rpb_dma_sys_lbk_i" 605 */ 606 607 /* register address for bitfield dma_sys_loopback */ 608 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 609 /* bitmask for bitfield dma_sys_loopback */ 610 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 611 /* inverted bitmask for bitfield dma_sys_loopback */ 612 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 613 /* lower bit position of bitfield dma_sys_loopback */ 614 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 615 /* width of bitfield dma_sys_loopback */ 616 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 617 /* default value of bitfield dma_sys_loopback */ 618 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 619 620 /* rx dma_net_loopback bitfield definitions 621 * preprocessor definitions for the bitfield "dma_net_loopback". 622 * port="pif_rpb_dma_net_lbk_i" 623 */ 624 625 /* register address for bitfield dma_net_loopback */ 626 #define HW_ATL_RPB_DMA_NET_LBK_ADR 0x00005000 627 /* bitmask for bitfield dma_net_loopback */ 628 #define HW_ATL_RPB_DMA_NET_LBK_MSK 0x00000010 629 /* inverted bitmask for bitfield dma_net_loopback */ 630 #define HW_ATL_RPB_DMA_NET_LBK_MSKN 0xffffffef 631 /* lower bit position of bitfield dma_net_loopback */ 632 #define HW_ATL_RPB_DMA_NET_LBK_SHIFT 4 633 /* width of bitfield dma_net_loopback */ 634 #define HW_ATL_RPB_DMA_NET_LBK_WIDTH 1 635 /* default value of bitfield dma_net_loopback */ 636 #define HW_ATL_RPB_DMA_NET_LBK_DEFAULT 0x0 637 638 /* rx rx_tc_mode bitfield definitions 639 * preprocessor definitions for the bitfield "rx_tc_mode". 640 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 641 */ 642 643 /* register address for bitfield rx_tc_mode */ 644 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 645 /* bitmask for bitfield rx_tc_mode */ 646 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 647 /* inverted bitmask for bitfield rx_tc_mode */ 648 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 649 /* lower bit position of bitfield rx_tc_mode */ 650 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 651 /* width of bitfield rx_tc_mode */ 652 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 653 /* default value of bitfield rx_tc_mode */ 654 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 655 656 /* rx rx_buf_en bitfield definitions 657 * preprocessor definitions for the bitfield "rx_buf_en". 658 * port="pif_rpb_rx_buf_en_i" 659 */ 660 661 /* register address for bitfield rx_buf_en */ 662 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 663 /* bitmask for bitfield rx_buf_en */ 664 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 665 /* inverted bitmask for bitfield rx_buf_en */ 666 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 667 /* lower bit position of bitfield rx_buf_en */ 668 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 669 /* width of bitfield rx_buf_en */ 670 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 671 /* default value of bitfield rx_buf_en */ 672 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 673 674 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 675 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 676 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 677 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 678 */ 679 680 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 681 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 682 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 683 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 684 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 685 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 686 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 687 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 688 /* width of bitfield rx{b}_hi_thresh[d:0] */ 689 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 690 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 691 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 692 693 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 694 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 695 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 696 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 697 */ 698 699 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 700 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 701 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 702 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 703 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 704 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 705 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 706 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 707 /* width of bitfield rx{b}_lo_thresh[d:0] */ 708 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 709 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 710 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 711 712 /* rx rx_fc_mode[1:0] bitfield definitions 713 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 714 * port="pif_rpb_rx_fc_mode_i[1:0]" 715 */ 716 717 /* register address for bitfield rx_fc_mode[1:0] */ 718 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 719 /* bitmask for bitfield rx_fc_mode[1:0] */ 720 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 721 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 722 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 723 /* lower bit position of bitfield rx_fc_mode[1:0] */ 724 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 725 /* width of bitfield rx_fc_mode[1:0] */ 726 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 727 /* default value of bitfield rx_fc_mode[1:0] */ 728 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 729 730 /* rx rx{b}_buf_size[8:0] bitfield definitions 731 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 732 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 733 * port="pif_rpb_rx0_buf_size_i[8:0]" 734 */ 735 736 /* register address for bitfield rx{b}_buf_size[8:0] */ 737 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 738 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 739 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 740 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 741 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 742 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 743 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 744 /* width of bitfield rx{b}_buf_size[8:0] */ 745 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 746 /* default value of bitfield rx{b}_buf_size[8:0] */ 747 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 748 749 /* rx rx{b}_xoff_en bitfield definitions 750 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 751 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 752 * port="pif_rpb_rx_xoff_en_i[0]" 753 */ 754 755 /* register address for bitfield rx{b}_xoff_en */ 756 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 757 /* bitmask for bitfield rx{b}_xoff_en */ 758 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 759 /* inverted bitmask for bitfield rx{b}_xoff_en */ 760 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 761 /* lower bit position of bitfield rx{b}_xoff_en */ 762 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 763 /* width of bitfield rx{b}_xoff_en */ 764 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 765 /* default value of bitfield rx{b}_xoff_en */ 766 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 767 768 /* rx l2_bc_thresh[f:0] bitfield definitions 769 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 770 * port="pif_rpf_l2_bc_thresh_i[15:0]" 771 */ 772 773 /* register address for bitfield l2_bc_thresh[f:0] */ 774 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 775 /* bitmask for bitfield l2_bc_thresh[f:0] */ 776 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 777 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 778 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 779 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 780 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16 781 /* width of bitfield l2_bc_thresh[f:0] */ 782 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16 783 /* default value of bitfield l2_bc_thresh[f:0] */ 784 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 785 786 /* rx l2_bc_en bitfield definitions 787 * preprocessor definitions for the bitfield "l2_bc_en". 788 * port="pif_rpf_l2_bc_en_i" 789 */ 790 791 /* register address for bitfield l2_bc_en */ 792 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100 793 /* bitmask for bitfield l2_bc_en */ 794 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001 795 /* inverted bitmask for bitfield l2_bc_en */ 796 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 797 /* lower bit position of bitfield l2_bc_en */ 798 #define HW_ATL_RPFL2BC_EN_SHIFT 0 799 /* width of bitfield l2_bc_en */ 800 #define HW_ATL_RPFL2BC_EN_WIDTH 1 801 /* default value of bitfield l2_bc_en */ 802 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 803 804 /* rx l2_bc_act[2:0] bitfield definitions 805 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 806 * port="pif_rpf_l2_bc_act_i[2:0]" 807 */ 808 809 /* register address for bitfield l2_bc_act[2:0] */ 810 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 811 /* bitmask for bitfield l2_bc_act[2:0] */ 812 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 813 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 814 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 815 /* lower bit position of bitfield l2_bc_act[2:0] */ 816 #define HW_ATL_RPFL2BC_ACT_SHIFT 12 817 /* width of bitfield l2_bc_act[2:0] */ 818 #define HW_ATL_RPFL2BC_ACT_WIDTH 3 819 /* default value of bitfield l2_bc_act[2:0] */ 820 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 821 822 /* rx l2_mc_en{f} bitfield definitions 823 * preprocessor definitions for the bitfield "l2_mc_en{f}". 824 * parameter: filter {f} | stride size 0x4 | range [0, 7] 825 * port="pif_rpf_l2_mc_en_i[0]" 826 */ 827 828 /* register address for bitfield l2_mc_en{f} */ 829 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 830 /* bitmask for bitfield l2_mc_en{f} */ 831 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 832 /* inverted bitmask for bitfield l2_mc_en{f} */ 833 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 834 /* lower bit position of bitfield l2_mc_en{f} */ 835 #define HW_ATL_RPFL2MC_ENF_SHIFT 31 836 /* width of bitfield l2_mc_en{f} */ 837 #define HW_ATL_RPFL2MC_ENF_WIDTH 1 838 /* default value of bitfield l2_mc_en{f} */ 839 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 840 841 /* rx l2_promis_mode bitfield definitions 842 * preprocessor definitions for the bitfield "l2_promis_mode". 843 * port="pif_rpf_l2_promis_mode_i" 844 */ 845 846 /* register address for bitfield l2_promis_mode */ 847 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 848 /* bitmask for bitfield l2_promis_mode */ 849 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 850 /* inverted bitmask for bitfield l2_promis_mode */ 851 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 852 /* lower bit position of bitfield l2_promis_mode */ 853 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 854 /* width of bitfield l2_promis_mode */ 855 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 856 /* default value of bitfield l2_promis_mode */ 857 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 858 859 /* rx l2_uc_act{f}[2:0] bitfield definitions 860 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 861 * parameter: filter {f} | stride size 0x8 | range [0, 37] 862 * port="pif_rpf_l2_uc_act0_i[2:0]" 863 */ 864 865 /* register address for bitfield l2_uc_act{f}[2:0] */ 866 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 867 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 868 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 869 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 870 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 871 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 872 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16 873 /* width of bitfield l2_uc_act{f}[2:0] */ 874 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3 875 /* default value of bitfield l2_uc_act{f}[2:0] */ 876 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 877 878 /* rx l2_uc_en{f} bitfield definitions 879 * preprocessor definitions for the bitfield "l2_uc_en{f}". 880 * parameter: filter {f} | stride size 0x8 | range [0, 37] 881 * port="pif_rpf_l2_uc_en_i[0]" 882 */ 883 884 /* register address for bitfield l2_uc_en{f} */ 885 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 886 /* bitmask for bitfield l2_uc_en{f} */ 887 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 888 /* inverted bitmask for bitfield l2_uc_en{f} */ 889 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 890 /* lower bit position of bitfield l2_uc_en{f} */ 891 #define HW_ATL_RPFL2UC_ENF_SHIFT 31 892 /* width of bitfield l2_uc_en{f} */ 893 #define HW_ATL_RPFL2UC_ENF_WIDTH 1 894 /* default value of bitfield l2_uc_en{f} */ 895 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 896 897 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 898 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 899 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 900 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 901 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 902 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 903 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 904 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 905 906 /* rx l2_mc_accept_all bitfield definitions 907 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 908 * PORT="pif_rpf_l2_mc_all_accept_i" 909 */ 910 911 /* Register address for bitfield l2_mc_accept_all */ 912 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 913 /* Bitmask for bitfield l2_mc_accept_all */ 914 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 915 /* Inverted bitmask for bitfield l2_mc_accept_all */ 916 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 917 /* Lower bit position of bitfield l2_mc_accept_all */ 918 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 919 /* Width of bitfield l2_mc_accept_all */ 920 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 921 /* Default value of bitfield l2_mc_accept_all */ 922 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 923 924 /* width of bitfield rx_tc_up{t}[2:0] */ 925 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 926 /* default value of bitfield rx_tc_up{t}[2:0] */ 927 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 928 929 /* rx rss_key_addr[4:0] bitfield definitions 930 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 931 * port="pif_rpf_rss_key_addr_i[4:0]" 932 */ 933 934 /* register address for bitfield rss_key_addr[4:0] */ 935 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 936 /* bitmask for bitfield rss_key_addr[4:0] */ 937 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 938 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 939 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 940 /* lower bit position of bitfield rss_key_addr[4:0] */ 941 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 942 /* width of bitfield rss_key_addr[4:0] */ 943 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 944 /* default value of bitfield rss_key_addr[4:0] */ 945 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 946 947 /* rx rss_key_wr_data[1f:0] bitfield definitions 948 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 949 * port="pif_rpf_rss_key_wr_data_i[31:0]" 950 */ 951 952 /* register address for bitfield rss_key_wr_data[1f:0] */ 953 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 954 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 955 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 956 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 957 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 958 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 959 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 960 /* width of bitfield rss_key_wr_data[1f:0] */ 961 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 962 /* default value of bitfield rss_key_wr_data[1f:0] */ 963 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 964 965 /* rx rss_key_wr_en_i bitfield definitions 966 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 967 * port="pif_rpf_rss_key_wr_en_i" 968 */ 969 970 /* register address for bitfield rss_key_wr_en_i */ 971 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 972 /* bitmask for bitfield rss_key_wr_en_i */ 973 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 974 /* inverted bitmask for bitfield rss_key_wr_en_i */ 975 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 976 /* lower bit position of bitfield rss_key_wr_en_i */ 977 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 978 /* width of bitfield rss_key_wr_en_i */ 979 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 980 /* default value of bitfield rss_key_wr_en_i */ 981 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 982 983 /* rx rss_redir_addr[3:0] bitfield definitions 984 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 985 * port="pif_rpf_rss_redir_addr_i[3:0]" 986 */ 987 988 /* register address for bitfield rss_redir_addr[3:0] */ 989 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 990 /* bitmask for bitfield rss_redir_addr[3:0] */ 991 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 992 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 993 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 994 /* lower bit position of bitfield rss_redir_addr[3:0] */ 995 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 996 /* width of bitfield rss_redir_addr[3:0] */ 997 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 998 /* default value of bitfield rss_redir_addr[3:0] */ 999 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 1000 1001 /* rx rss_redir_wr_data[f:0] bitfield definitions 1002 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 1003 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 1004 */ 1005 1006 /* register address for bitfield rss_redir_wr_data[f:0] */ 1007 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 1008 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 1009 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 1010 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 1011 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 1012 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 1013 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 1014 /* width of bitfield rss_redir_wr_data[f:0] */ 1015 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 1016 /* default value of bitfield rss_redir_wr_data[f:0] */ 1017 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 1018 1019 /* rx rss_redir_wr_en_i bitfield definitions 1020 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 1021 * port="pif_rpf_rss_redir_wr_en_i" 1022 */ 1023 1024 /* register address for bitfield rss_redir_wr_en_i */ 1025 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 1026 /* bitmask for bitfield rss_redir_wr_en_i */ 1027 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 1028 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 1029 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 1030 /* lower bit position of bitfield rss_redir_wr_en_i */ 1031 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 1032 /* width of bitfield rss_redir_wr_en_i */ 1033 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 1034 /* default value of bitfield rss_redir_wr_en_i */ 1035 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 1036 1037 /* rx tpo_rpf_sys_loopback bitfield definitions 1038 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 1039 * port="pif_rpf_tpo_pkt_sys_lbk_i" 1040 */ 1041 1042 /* register address for bitfield tpo_rpf_sys_loopback */ 1043 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 1044 /* bitmask for bitfield tpo_rpf_sys_loopback */ 1045 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 1046 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 1047 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 1048 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 1049 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 1050 /* width of bitfield tpo_rpf_sys_loopback */ 1051 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 1052 /* default value of bitfield tpo_rpf_sys_loopback */ 1053 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 1054 1055 /* rx vl_inner_tpid[f:0] bitfield definitions 1056 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 1057 * port="pif_rpf_vl_inner_tpid_i[15:0]" 1058 */ 1059 1060 /* register address for bitfield vl_inner_tpid[f:0] */ 1061 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 1062 /* bitmask for bitfield vl_inner_tpid[f:0] */ 1063 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 1064 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 1065 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 1066 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 1067 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 1068 /* width of bitfield vl_inner_tpid[f:0] */ 1069 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 1070 /* default value of bitfield vl_inner_tpid[f:0] */ 1071 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 1072 1073 /* rx vl_outer_tpid[f:0] bitfield definitions 1074 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 1075 * port="pif_rpf_vl_outer_tpid_i[15:0]" 1076 */ 1077 1078 /* register address for bitfield vl_outer_tpid[f:0] */ 1079 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 1080 /* bitmask for bitfield vl_outer_tpid[f:0] */ 1081 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 1082 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 1083 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 1084 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 1085 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 1086 /* width of bitfield vl_outer_tpid[f:0] */ 1087 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 1088 /* default value of bitfield vl_outer_tpid[f:0] */ 1089 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 1090 1091 /* rx vl_promis_mode bitfield definitions 1092 * preprocessor definitions for the bitfield "vl_promis_mode". 1093 * port="pif_rpf_vl_promis_mode_i" 1094 */ 1095 1096 /* register address for bitfield vl_promis_mode */ 1097 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 1098 /* bitmask for bitfield vl_promis_mode */ 1099 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 1100 /* inverted bitmask for bitfield vl_promis_mode */ 1101 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 1102 /* lower bit position of bitfield vl_promis_mode */ 1103 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 1104 /* width of bitfield vl_promis_mode */ 1105 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 1106 /* default value of bitfield vl_promis_mode */ 1107 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 1108 1109 /* RX vl_accept_untagged_mode Bitfield Definitions 1110 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 1111 * PORT="pif_rpf_vl_accept_untagged_i" 1112 */ 1113 1114 /* Register address for bitfield vl_accept_untagged_mode */ 1115 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 1116 /* Bitmask for bitfield vl_accept_untagged_mode */ 1117 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 1118 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 1119 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 1120 /* Lower bit position of bitfield vl_accept_untagged_mode */ 1121 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 1122 /* Width of bitfield vl_accept_untagged_mode */ 1123 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 1124 /* Default value of bitfield vl_accept_untagged_mode */ 1125 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 1126 1127 /* rX vl_untagged_act[2:0] Bitfield Definitions 1128 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1129 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 1130 */ 1131 1132 /* Register address for bitfield vl_untagged_act[2:0] */ 1133 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1134 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1135 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1136 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1137 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1138 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1139 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1140 /* Width of bitfield vl_untagged_act[2:0] */ 1141 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1142 /* Default value of bitfield vl_untagged_act[2:0] */ 1143 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1144 1145 /* RX vl_en{F} Bitfield Definitions 1146 * Preprocessor definitions for the bitfield "vl_en{F}". 1147 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1148 * PORT="pif_rpf_vl_en_i[0]" 1149 */ 1150 1151 /* Register address for bitfield vl_en{F} */ 1152 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1153 /* Bitmask for bitfield vl_en{F} */ 1154 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1155 /* Inverted bitmask for bitfield vl_en{F} */ 1156 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1157 /* Lower bit position of bitfield vl_en{F} */ 1158 #define HW_ATL_RPF_VL_EN_F_SHIFT 31 1159 /* Width of bitfield vl_en{F} */ 1160 #define HW_ATL_RPF_VL_EN_F_WIDTH 1 1161 /* Default value of bitfield vl_en{F} */ 1162 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1163 1164 /* RX vl_act{F}[2:0] Bitfield Definitions 1165 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1166 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1167 * PORT="pif_rpf_vl_act0_i[2:0]" 1168 */ 1169 1170 /* Register address for bitfield vl_act{F}[2:0] */ 1171 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1172 /* Bitmask for bitfield vl_act{F}[2:0] */ 1173 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1174 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1175 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1176 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1177 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1178 /* Width of bitfield vl_act{F}[2:0] */ 1179 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1180 /* Default value of bitfield vl_act{F}[2:0] */ 1181 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1182 1183 /* RX vl_id{F}[B:0] Bitfield Definitions 1184 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1185 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1186 * PORT="pif_rpf_vl_id0_i[11:0]" 1187 */ 1188 1189 /* Register address for bitfield vl_id{F}[B:0] */ 1190 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1191 /* Bitmask for bitfield vl_id{F}[B:0] */ 1192 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1193 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1194 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1195 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1196 #define HW_ATL_RPF_VL_ID_F_SHIFT 0 1197 /* Width of bitfield vl_id{F}[B:0] */ 1198 #define HW_ATL_RPF_VL_ID_F_WIDTH 12 1199 /* Default value of bitfield vl_id{F}[B:0] */ 1200 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1201 1202 /* RX vl_rxq_en{F} Bitfield Definitions 1203 * Preprocessor definitions for the bitfield "vl_rxq{F}". 1204 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1205 * PORT="pif_rpf_vl_rxq_en_i" 1206 */ 1207 1208 /* Register address for bitfield vl_rxq_en{F} */ 1209 #define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1210 /* Bitmask for bitfield vl_rxq_en{F} */ 1211 #define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000 1212 /* Inverted bitmask for bitfield vl_rxq_en{F}[ */ 1213 #define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF 1214 /* Lower bit position of bitfield vl_rxq_en{F} */ 1215 #define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28 1216 /* Width of bitfield vl_rxq_en{F} */ 1217 #define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1 1218 /* Default value of bitfield vl_rxq_en{F} */ 1219 #define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0 1220 1221 /* RX vl_rxq{F}[4:0] Bitfield Definitions 1222 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]". 1223 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1224 * PORT="pif_rpf_vl_rxq0_i[4:0]" 1225 */ 1226 1227 /* Register address for bitfield vl_rxq{F}[4:0] */ 1228 #define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1229 /* Bitmask for bitfield vl_rxq{F}[4:0] */ 1230 #define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000 1231 /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */ 1232 #define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF 1233 /* Lower bit position of bitfield vl_rxq{F}[4:0] */ 1234 #define HW_ATL_RPF_VL_RXQ_F_SHIFT 20 1235 /* Width of bitfield vl_rxw{F}[4:0] */ 1236 #define HW_ATL_RPF_VL_RXQ_F_WIDTH 5 1237 /* Default value of bitfield vl_rxq{F}[4:0] */ 1238 #define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0 1239 1240 /* rx et_en{f} bitfield definitions 1241 * preprocessor definitions for the bitfield "et_en{f}". 1242 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1243 * port="pif_rpf_et_en_i[0]" 1244 */ 1245 1246 /* register address for bitfield et_en{f} */ 1247 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1248 /* bitmask for bitfield et_en{f} */ 1249 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1250 /* inverted bitmask for bitfield et_en{f} */ 1251 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1252 /* lower bit position of bitfield et_en{f} */ 1253 #define HW_ATL_RPF_ET_ENF_SHIFT 31 1254 /* width of bitfield et_en{f} */ 1255 #define HW_ATL_RPF_ET_ENF_WIDTH 1 1256 /* default value of bitfield et_en{f} */ 1257 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1258 1259 /* rx et_up{f}_en bitfield definitions 1260 * preprocessor definitions for the bitfield "et_up{f}_en". 1261 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1262 * port="pif_rpf_et_up_en_i[0]" 1263 */ 1264 1265 /* register address for bitfield et_up{f}_en */ 1266 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1267 /* bitmask for bitfield et_up{f}_en */ 1268 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1269 /* inverted bitmask for bitfield et_up{f}_en */ 1270 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1271 /* lower bit position of bitfield et_up{f}_en */ 1272 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1273 /* width of bitfield et_up{f}_en */ 1274 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1275 /* default value of bitfield et_up{f}_en */ 1276 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1277 1278 /* rx et_rxq{f}_en bitfield definitions 1279 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1280 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1281 * port="pif_rpf_et_rxq_en_i[0]" 1282 */ 1283 1284 /* register address for bitfield et_rxq{f}_en */ 1285 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1286 /* bitmask for bitfield et_rxq{f}_en */ 1287 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1288 /* inverted bitmask for bitfield et_rxq{f}_en */ 1289 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1290 /* lower bit position of bitfield et_rxq{f}_en */ 1291 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1292 /* width of bitfield et_rxq{f}_en */ 1293 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1294 /* default value of bitfield et_rxq{f}_en */ 1295 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1296 1297 /* rx et_up{f}[2:0] bitfield definitions 1298 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1299 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1300 * port="pif_rpf_et_up0_i[2:0]" 1301 */ 1302 1303 /* register address for bitfield et_up{f}[2:0] */ 1304 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1305 /* bitmask for bitfield et_up{f}[2:0] */ 1306 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1307 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1308 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1309 /* lower bit position of bitfield et_up{f}[2:0] */ 1310 #define HW_ATL_RPF_ET_UPF_SHIFT 26 1311 /* width of bitfield et_up{f}[2:0] */ 1312 #define HW_ATL_RPF_ET_UPF_WIDTH 3 1313 /* default value of bitfield et_up{f}[2:0] */ 1314 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1315 1316 /* rx et_rxq{f}[4:0] bitfield definitions 1317 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1318 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1319 * port="pif_rpf_et_rxq0_i[4:0]" 1320 */ 1321 1322 /* register address for bitfield et_rxq{f}[4:0] */ 1323 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1324 /* bitmask for bitfield et_rxq{f}[4:0] */ 1325 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1326 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1327 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1328 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1329 #define HW_ATL_RPF_ET_RXQF_SHIFT 20 1330 /* width of bitfield et_rxq{f}[4:0] */ 1331 #define HW_ATL_RPF_ET_RXQF_WIDTH 5 1332 /* default value of bitfield et_rxq{f}[4:0] */ 1333 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1334 1335 /* rx et_mng_rxq{f} bitfield definitions 1336 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1337 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1338 * port="pif_rpf_et_mng_rxq_i[0]" 1339 */ 1340 1341 /* register address for bitfield et_mng_rxq{f} */ 1342 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1343 /* bitmask for bitfield et_mng_rxq{f} */ 1344 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1345 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1346 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1347 /* lower bit position of bitfield et_mng_rxq{f} */ 1348 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1349 /* width of bitfield et_mng_rxq{f} */ 1350 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1351 /* default value of bitfield et_mng_rxq{f} */ 1352 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1353 1354 /* rx et_act{f}[2:0] bitfield definitions 1355 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1356 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1357 * port="pif_rpf_et_act0_i[2:0]" 1358 */ 1359 1360 /* register address for bitfield et_act{f}[2:0] */ 1361 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1362 /* bitmask for bitfield et_act{f}[2:0] */ 1363 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1364 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1365 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1366 /* lower bit position of bitfield et_act{f}[2:0] */ 1367 #define HW_ATL_RPF_ET_ACTF_SHIFT 16 1368 /* width of bitfield et_act{f}[2:0] */ 1369 #define HW_ATL_RPF_ET_ACTF_WIDTH 3 1370 /* default value of bitfield et_act{f}[2:0] */ 1371 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1372 1373 /* rx et_val{f}[f:0] bitfield definitions 1374 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1375 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1376 * port="pif_rpf_et_val0_i[15:0]" 1377 */ 1378 1379 /* register address for bitfield et_val{f}[f:0] */ 1380 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1381 /* bitmask for bitfield et_val{f}[f:0] */ 1382 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1383 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1384 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1385 /* lower bit position of bitfield et_val{f}[f:0] */ 1386 #define HW_ATL_RPF_ET_VALF_SHIFT 0 1387 /* width of bitfield et_val{f}[f:0] */ 1388 #define HW_ATL_RPF_ET_VALF_WIDTH 16 1389 /* default value of bitfield et_val{f}[f:0] */ 1390 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1391 1392 /* RX l3_l4_en{F} Bitfield Definitions 1393 * Preprocessor definitions for the bitfield "l3_l4_en{F}". 1394 * Parameter: filter {F} | stride size 0x4 | range [0, 7] 1395 * PORT="pif_rpf_l3_l4_en_i[0]" 1396 */ 1397 1398 #define HW_ATL_RPF_L3_REG_CTRL_ADR(filter) (0x00005380 + (filter) * 0x4) 1399 1400 /* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions 1401 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]". 1402 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1403 * PORT="pif_rpf_l3_sa0_i[31:0]" 1404 */ 1405 1406 /* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */ 1407 #define HW_ATL_RPF_L3_SRCA_ADR(filter) (0x000053B0 + (filter) * 0x4) 1408 /* Bitmask for bitfield l3_sa0[1F:0] */ 1409 #define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu 1410 /* Inverted bitmask for bitfield l3_sa0[1F:0] */ 1411 #define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu 1412 /* Lower bit position of bitfield l3_sa0[1F:0] */ 1413 #define HW_ATL_RPF_L3_SRCA_SHIFT 0 1414 /* Width of bitfield l3_sa0[1F:0] */ 1415 #define HW_ATL_RPF_L3_SRCA_WIDTH 32 1416 /* Default value of bitfield l3_sa0[1F:0] */ 1417 #define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0 1418 1419 /* RX rpf_l3_da{D}[1F:0] Bitfield Definitions 1420 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]". 1421 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1422 * PORT="pif_rpf_l3_da0_i[31:0]" 1423 */ 1424 1425 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */ 1426 #define HW_ATL_RPF_L3_DSTA_ADR(filter) (0x000053D0 + (filter) * 0x4) 1427 /* Bitmask for bitfield l3_da0[1F:0] */ 1428 #define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu 1429 /* Inverted bitmask for bitfield l3_da0[1F:0] */ 1430 #define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu 1431 /* Lower bit position of bitfield l3_da0[1F:0] */ 1432 #define HW_ATL_RPF_L3_DSTA_SHIFT 0 1433 /* Width of bitfield l3_da0[1F:0] */ 1434 #define HW_ATL_RPF_L3_DSTA_WIDTH 32 1435 /* Default value of bitfield l3_da0[1F:0] */ 1436 #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0 1437 1438 /* RX l4_sp{D}[F:0] Bitfield Definitions 1439 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]". 1440 * Parameter: srcport {D} | stride size 0x4 | range [0, 7] 1441 * PORT="pif_rpf_l4_sp0_i[15:0]" 1442 */ 1443 1444 /* Register address for bitfield l4_sp{D}[F:0] */ 1445 #define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4) 1446 /* Bitmask for bitfield l4_sp{D}[F:0] */ 1447 #define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu 1448 /* Inverted bitmask for bitfield l4_sp{D}[F:0] */ 1449 #define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u 1450 /* Lower bit position of bitfield l4_sp{D}[F:0] */ 1451 #define HW_ATL_RPF_L4_SPD_SHIFT 0 1452 /* Width of bitfield l4_sp{D}[F:0] */ 1453 #define HW_ATL_RPF_L4_SPD_WIDTH 16 1454 /* Default value of bitfield l4_sp{D}[F:0] */ 1455 #define HW_ATL_RPF_L4_SPD_DEFAULT 0x0 1456 1457 /* RX l4_dp{D}[F:0] Bitfield Definitions 1458 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]". 1459 * Parameter: destport {D} | stride size 0x4 | range [0, 7] 1460 * PORT="pif_rpf_l4_dp0_i[15:0]" 1461 */ 1462 1463 /* Register address for bitfield l4_dp{D}[F:0] */ 1464 #define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4) 1465 /* Bitmask for bitfield l4_dp{D}[F:0] */ 1466 #define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu 1467 /* Inverted bitmask for bitfield l4_dp{D}[F:0] */ 1468 #define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u 1469 /* Lower bit position of bitfield l4_dp{D}[F:0] */ 1470 #define HW_ATL_RPF_L4_DPD_SHIFT 0 1471 /* Width of bitfield l4_dp{D}[F:0] */ 1472 #define HW_ATL_RPF_L4_DPD_WIDTH 16 1473 /* Default value of bitfield l4_dp{D}[F:0] */ 1474 #define HW_ATL_RPF_L4_DPD_DEFAULT 0x0 1475 1476 /* rx ipv4_chk_en bitfield definitions 1477 * preprocessor definitions for the bitfield "ipv4_chk_en". 1478 * port="pif_rpo_ipv4_chk_en_i" 1479 */ 1480 1481 /* register address for bitfield ipv4_chk_en */ 1482 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1483 /* bitmask for bitfield ipv4_chk_en */ 1484 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1485 /* inverted bitmask for bitfield ipv4_chk_en */ 1486 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1487 /* lower bit position of bitfield ipv4_chk_en */ 1488 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1489 /* width of bitfield ipv4_chk_en */ 1490 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1491 /* default value of bitfield ipv4_chk_en */ 1492 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1493 1494 /* rx desc{d}_vl_strip bitfield definitions 1495 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1496 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1497 * port="pif_rpo_desc_vl_strip_i[0]" 1498 */ 1499 1500 /* register address for bitfield desc{d}_vl_strip */ 1501 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1502 (0x00005b08 + (descriptor) * 0x20) 1503 /* bitmask for bitfield desc{d}_vl_strip */ 1504 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1505 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1506 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1507 /* lower bit position of bitfield desc{d}_vl_strip */ 1508 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1509 /* width of bitfield desc{d}_vl_strip */ 1510 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1511 /* default value of bitfield desc{d}_vl_strip */ 1512 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1513 1514 /* rx l4_chk_en bitfield definitions 1515 * preprocessor definitions for the bitfield "l4_chk_en". 1516 * port="pif_rpo_l4_chk_en_i" 1517 */ 1518 1519 /* register address for bitfield l4_chk_en */ 1520 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1521 /* bitmask for bitfield l4_chk_en */ 1522 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1523 /* inverted bitmask for bitfield l4_chk_en */ 1524 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1525 /* lower bit position of bitfield l4_chk_en */ 1526 #define HW_ATL_RPOL4CHK_EN_SHIFT 0 1527 /* width of bitfield l4_chk_en */ 1528 #define HW_ATL_RPOL4CHK_EN_WIDTH 1 1529 /* default value of bitfield l4_chk_en */ 1530 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1531 1532 /* RX outer_vl_ins_mode Bitfield Definitions 1533 * Preprocessor definitions for the bitfield "outer_vl_ins_mode". 1534 * PORT="pif_rpo_outer_vl_mode_i" 1535 */ 1536 1537 /* Register address for bitfield outer_vl_ins_mode */ 1538 #define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580 1539 /* Bitmask for bitfield outer_vl_ins_mode */ 1540 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004 1541 /* Inverted bitmask for bitfield outer_vl_ins_mode */ 1542 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB 1543 /* Lower bit position of bitfield outer_vl_ins_mode */ 1544 #define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2 1545 /* Width of bitfield outer_vl_ins_mode */ 1546 #define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1 1547 /* Default value of bitfield outer_vl_ins_mode */ 1548 #define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0 1549 1550 /* rx reg_res_dsbl bitfield definitions 1551 * preprocessor definitions for the bitfield "reg_res_dsbl". 1552 * port="pif_rx_reg_res_dsbl_i" 1553 */ 1554 1555 /* register address for bitfield reg_res_dsbl */ 1556 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1557 /* bitmask for bitfield reg_res_dsbl */ 1558 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1559 /* inverted bitmask for bitfield reg_res_dsbl */ 1560 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1561 /* lower bit position of bitfield reg_res_dsbl */ 1562 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1563 /* width of bitfield reg_res_dsbl */ 1564 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1565 /* default value of bitfield reg_res_dsbl */ 1566 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1567 1568 /* tx dca{d}_cpuid[7:0] bitfield definitions 1569 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1570 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1571 * port="pif_tdm_dca0_cpuid_i[7:0]" 1572 */ 1573 1574 /* register address for bitfield dca{d}_cpuid[7:0] */ 1575 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1576 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1577 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1578 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1579 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1580 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1581 #define HW_ATL_TDM_DCADCPUID_SHIFT 0 1582 /* width of bitfield dca{d}_cpuid[7:0] */ 1583 #define HW_ATL_TDM_DCADCPUID_WIDTH 8 1584 /* default value of bitfield dca{d}_cpuid[7:0] */ 1585 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1586 1587 /* tx lso_en[1f:0] bitfield definitions 1588 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1589 * port="pif_tdm_lso_en_i[31:0]" 1590 */ 1591 1592 /* register address for bitfield lso_en[1f:0] */ 1593 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1594 /* bitmask for bitfield lso_en[1f:0] */ 1595 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1596 /* inverted bitmask for bitfield lso_en[1f:0] */ 1597 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1598 /* lower bit position of bitfield lso_en[1f:0] */ 1599 #define HW_ATL_TDM_LSO_EN_SHIFT 0 1600 /* width of bitfield lso_en[1f:0] */ 1601 #define HW_ATL_TDM_LSO_EN_WIDTH 32 1602 /* default value of bitfield lso_en[1f:0] */ 1603 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1604 1605 /* tx dca_en bitfield definitions 1606 * preprocessor definitions for the bitfield "dca_en". 1607 * port="pif_tdm_dca_en_i" 1608 */ 1609 1610 /* register address for bitfield dca_en */ 1611 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1612 /* bitmask for bitfield dca_en */ 1613 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1614 /* inverted bitmask for bitfield dca_en */ 1615 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1616 /* lower bit position of bitfield dca_en */ 1617 #define HW_ATL_TDM_DCA_EN_SHIFT 31 1618 /* width of bitfield dca_en */ 1619 #define HW_ATL_TDM_DCA_EN_WIDTH 1 1620 /* default value of bitfield dca_en */ 1621 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1622 1623 /* tx dca_mode[3:0] bitfield definitions 1624 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1625 * port="pif_tdm_dca_mode_i[3:0]" 1626 */ 1627 1628 /* register address for bitfield dca_mode[3:0] */ 1629 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1630 /* bitmask for bitfield dca_mode[3:0] */ 1631 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1632 /* inverted bitmask for bitfield dca_mode[3:0] */ 1633 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1634 /* lower bit position of bitfield dca_mode[3:0] */ 1635 #define HW_ATL_TDM_DCA_MODE_SHIFT 0 1636 /* width of bitfield dca_mode[3:0] */ 1637 #define HW_ATL_TDM_DCA_MODE_WIDTH 4 1638 /* default value of bitfield dca_mode[3:0] */ 1639 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1640 1641 /* tx dca{d}_desc_en bitfield definitions 1642 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1643 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1644 * port="pif_tdm_dca_desc_en_i[0]" 1645 */ 1646 1647 /* register address for bitfield dca{d}_desc_en */ 1648 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1649 /* bitmask for bitfield dca{d}_desc_en */ 1650 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1651 /* inverted bitmask for bitfield dca{d}_desc_en */ 1652 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1653 /* lower bit position of bitfield dca{d}_desc_en */ 1654 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1655 /* width of bitfield dca{d}_desc_en */ 1656 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1657 /* default value of bitfield dca{d}_desc_en */ 1658 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1659 1660 /* tx desc{d}_en bitfield definitions 1661 * preprocessor definitions for the bitfield "desc{d}_en". 1662 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1663 * port="pif_tdm_desc_en_i[0]" 1664 */ 1665 1666 /* register address for bitfield desc{d}_en */ 1667 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1668 /* bitmask for bitfield desc{d}_en */ 1669 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1670 /* inverted bitmask for bitfield desc{d}_en */ 1671 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1672 /* lower bit position of bitfield desc{d}_en */ 1673 #define HW_ATL_TDM_DESCDEN_SHIFT 31 1674 /* width of bitfield desc{d}_en */ 1675 #define HW_ATL_TDM_DESCDEN_WIDTH 1 1676 /* default value of bitfield desc{d}_en */ 1677 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1678 1679 /* tx desc{d}_hd[c:0] bitfield definitions 1680 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1681 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1682 * port="tdm_pif_desc0_hd_o[12:0]" 1683 */ 1684 1685 /* register address for bitfield desc{d}_hd[c:0] */ 1686 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1687 /* bitmask for bitfield desc{d}_hd[c:0] */ 1688 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1689 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1690 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1691 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1692 #define HW_ATL_TDM_DESCDHD_SHIFT 0 1693 /* width of bitfield desc{d}_hd[c:0] */ 1694 #define HW_ATL_TDM_DESCDHD_WIDTH 13 1695 1696 /* tx desc{d}_len[9:0] bitfield definitions 1697 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1698 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1699 * port="pif_tdm_desc0_len_i[9:0]" 1700 */ 1701 1702 /* register address for bitfield desc{d}_len[9:0] */ 1703 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1704 /* bitmask for bitfield desc{d}_len[9:0] */ 1705 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1706 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1707 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1708 /* lower bit position of bitfield desc{d}_len[9:0] */ 1709 #define HW_ATL_TDM_DESCDLEN_SHIFT 3 1710 /* width of bitfield desc{d}_len[9:0] */ 1711 #define HW_ATL_TDM_DESCDLEN_WIDTH 10 1712 /* default value of bitfield desc{d}_len[9:0] */ 1713 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1714 1715 /* tx int_desc_wrb_en bitfield definitions 1716 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1717 * port="pif_tdm_int_desc_wrb_en_i" 1718 */ 1719 1720 /* register address for bitfield int_desc_wrb_en */ 1721 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1722 /* bitmask for bitfield int_desc_wrb_en */ 1723 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1724 /* inverted bitmask for bitfield int_desc_wrb_en */ 1725 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1726 /* lower bit position of bitfield int_desc_wrb_en */ 1727 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1728 /* width of bitfield int_desc_wrb_en */ 1729 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1730 /* default value of bitfield int_desc_wrb_en */ 1731 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1732 1733 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1734 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1735 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1736 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1737 */ 1738 1739 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1740 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1741 (0x00007c18 + (descriptor) * 0x40) 1742 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1743 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1744 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1745 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1746 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1747 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1748 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1749 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1750 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1751 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1752 1753 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1754 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1755 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1756 */ 1757 1758 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1759 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1760 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1761 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1762 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1763 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1764 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1765 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1766 /* width of bitfield lso_tcp_flag_first[b:0] */ 1767 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1768 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1769 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1770 1771 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1772 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1773 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1774 */ 1775 1776 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1777 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1778 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1779 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1780 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1781 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1782 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1783 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1784 /* width of bitfield lso_tcp_flag_last[b:0] */ 1785 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1786 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1787 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1788 1789 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1790 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1791 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1792 */ 1793 1794 /* Register address for bitfield lro_rsc_max[1F:0] */ 1795 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1796 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1797 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1798 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1799 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1800 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1801 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1802 /* Width of bitfield lro_rsc_max[1F:0] */ 1803 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1804 /* Default value of bitfield lro_rsc_max[1F:0] */ 1805 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1806 1807 /* RX lro_en[1F:0] Bitfield Definitions 1808 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1809 * PORT="pif_rpo_lro_en_i[31:0]" 1810 */ 1811 1812 /* Register address for bitfield lro_en[1F:0] */ 1813 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1814 /* Bitmask for bitfield lro_en[1F:0] */ 1815 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1816 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1817 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1818 /* Lower bit position of bitfield lro_en[1F:0] */ 1819 #define HW_ATL_RPO_LRO_EN_SHIFT 0 1820 /* Width of bitfield lro_en[1F:0] */ 1821 #define HW_ATL_RPO_LRO_EN_WIDTH 32 1822 /* Default value of bitfield lro_en[1F:0] */ 1823 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1824 1825 /* RX lro_ptopt_en Bitfield Definitions 1826 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1827 * PORT="pif_rpo_lro_ptopt_en_i" 1828 */ 1829 1830 /* Register address for bitfield lro_ptopt_en */ 1831 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1832 /* Bitmask for bitfield lro_ptopt_en */ 1833 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1834 /* Inverted bitmask for bitfield lro_ptopt_en */ 1835 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1836 /* Lower bit position of bitfield lro_ptopt_en */ 1837 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1838 /* Width of bitfield lro_ptopt_en */ 1839 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1840 /* Default value of bitfield lro_ptopt_en */ 1841 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1842 1843 /* RX lro_q_ses_lmt Bitfield Definitions 1844 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1845 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1846 */ 1847 1848 /* Register address for bitfield lro_q_ses_lmt */ 1849 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1850 /* Bitmask for bitfield lro_q_ses_lmt */ 1851 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1852 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1853 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1854 /* Lower bit position of bitfield lro_q_ses_lmt */ 1855 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1856 /* Width of bitfield lro_q_ses_lmt */ 1857 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1858 /* Default value of bitfield lro_q_ses_lmt */ 1859 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1860 1861 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1862 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1863 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1864 */ 1865 1866 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1867 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1868 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1869 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1870 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1871 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1872 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1873 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1874 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1875 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1876 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1877 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1878 1879 /* RX lro_pkt_min[4:0] Bitfield Definitions 1880 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1881 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1882 */ 1883 1884 /* Register address for bitfield lro_pkt_min[4:0] */ 1885 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1886 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1887 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1888 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1889 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1890 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1891 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1892 /* Width of bitfield lro_pkt_min[4:0] */ 1893 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1894 /* Default value of bitfield lro_pkt_min[4:0] */ 1895 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1896 1897 /* Width of bitfield lro{L}_des_max[1:0] */ 1898 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1899 /* Default value of bitfield lro{L}_des_max[1:0] */ 1900 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1901 1902 /* RX lro_tb_div[11:0] Bitfield Definitions 1903 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1904 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1905 */ 1906 1907 /* Register address for bitfield lro_tb_div[11:0] */ 1908 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1909 /* Bitmask for bitfield lro_tb_div[11:0] */ 1910 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1911 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1912 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1913 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1914 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1915 /* Width of bitfield lro_tb_div[11:0] */ 1916 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1917 /* Default value of bitfield lro_tb_div[11:0] */ 1918 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1919 1920 /* RX lro_ina_ival[9:0] Bitfield Definitions 1921 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1922 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1923 */ 1924 1925 /* Register address for bitfield lro_ina_ival[9:0] */ 1926 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1927 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1928 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1929 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1930 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1931 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1932 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1933 /* Width of bitfield lro_ina_ival[9:0] */ 1934 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1935 /* Default value of bitfield lro_ina_ival[9:0] */ 1936 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1937 1938 /* RX lro_max_ival[9:0] Bitfield Definitions 1939 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1940 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1941 */ 1942 1943 /* Register address for bitfield lro_max_ival[9:0] */ 1944 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1945 /* Bitmask for bitfield lro_max_ival[9:0] */ 1946 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1947 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1948 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1949 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1950 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1951 /* Width of bitfield lro_max_ival[9:0] */ 1952 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1953 /* Default value of bitfield lro_max_ival[9:0] */ 1954 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1955 1956 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1957 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1958 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1959 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1960 */ 1961 1962 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1963 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1964 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1965 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1966 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1967 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1968 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1969 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1970 /* Width of bitfield dca{D}_cpuid[7:0] */ 1971 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1972 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1973 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1974 1975 /* TX dca{D}_desc_en Bitfield Definitions 1976 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1977 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1978 * PORT="pif_tdm_dca_desc_en_i[0]" 1979 */ 1980 1981 /* Register address for bitfield dca{D}_desc_en */ 1982 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1983 /* Bitmask for bitfield dca{D}_desc_en */ 1984 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1985 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1986 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1987 /* Lower bit position of bitfield dca{D}_desc_en */ 1988 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1989 /* Width of bitfield dca{D}_desc_en */ 1990 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1991 /* Default value of bitfield dca{D}_desc_en */ 1992 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1993 1994 /* TX desc{D}_en Bitfield Definitions 1995 * Preprocessor definitions for the bitfield "desc{D}_en". 1996 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1997 * PORT="pif_tdm_desc_en_i[0]" 1998 */ 1999 2000 /* Register address for bitfield desc{D}_en */ 2001 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 2002 /* Bitmask for bitfield desc{D}_en */ 2003 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 2004 /* Inverted bitmask for bitfield desc{D}_en */ 2005 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 2006 /* Lower bit position of bitfield desc{D}_en */ 2007 #define HW_ATL_TDM_DESC_DEN_SHIFT 31 2008 /* Width of bitfield desc{D}_en */ 2009 #define HW_ATL_TDM_DESC_DEN_WIDTH 1 2010 /* Default value of bitfield desc{D}_en */ 2011 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 2012 2013 /* TX desc{D}_hd[C:0] Bitfield Definitions 2014 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 2015 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 2016 * PORT="tdm_pif_desc0_hd_o[12:0]" 2017 */ 2018 2019 /* Register address for bitfield desc{D}_hd[C:0] */ 2020 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 2021 /* Bitmask for bitfield desc{D}_hd[C:0] */ 2022 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 2023 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 2024 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 2025 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 2026 #define HW_ATL_TDM_DESC_DHD_SHIFT 0 2027 /* Width of bitfield desc{D}_hd[C:0] */ 2028 #define HW_ATL_TDM_DESC_DHD_WIDTH 13 2029 2030 /* TX desc{D}_len[9:0] Bitfield Definitions 2031 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 2032 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 2033 * PORT="pif_tdm_desc0_len_i[9:0]" 2034 */ 2035 2036 /* Register address for bitfield desc{D}_len[9:0] */ 2037 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 2038 /* Bitmask for bitfield desc{D}_len[9:0] */ 2039 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 2040 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 2041 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 2042 /* Lower bit position of bitfield desc{D}_len[9:0] */ 2043 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3 2044 /* Width of bitfield desc{D}_len[9:0] */ 2045 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10 2046 /* Default value of bitfield desc{D}_len[9:0] */ 2047 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 2048 2049 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 2050 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 2051 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 2052 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 2053 */ 2054 2055 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 2056 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 2057 (0x00007C18 + (descriptor) * 0x40) 2058 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 2059 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 2060 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 2061 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 2062 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 2063 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 2064 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 2065 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 2066 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 2067 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 2068 2069 /* TX tdm_int_mod_en Bitfield Definitions 2070 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 2071 * PORT="pif_tdm_int_mod_en_i" 2072 */ 2073 2074 /* Register address for bitfield tdm_int_mod_en */ 2075 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 2076 /* Bitmask for bitfield tdm_int_mod_en */ 2077 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 2078 /* Inverted bitmask for bitfield tdm_int_mod_en */ 2079 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 2080 /* Lower bit position of bitfield tdm_int_mod_en */ 2081 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 2082 /* Width of bitfield tdm_int_mod_en */ 2083 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 2084 /* Default value of bitfield tdm_int_mod_en */ 2085 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 2086 2087 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 2088 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 2089 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 2090 */ 2091 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 2092 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 2093 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2094 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 2095 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2096 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 2097 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 2098 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 2099 /* width of bitfield lso_tcp_flag_mid[b:0] */ 2100 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 2101 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 2102 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 2103 2104 /* tx tx_tc_mode bitfield definitions 2105 * preprocessor definitions for the bitfield "tx_tc_mode". 2106 * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i" 2107 */ 2108 2109 /* register address for bitfield tx_tc_mode */ 2110 #define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 2111 /* bitmask for bitfield tx_tc_mode */ 2112 #define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 2113 /* inverted bitmask for bitfield tx_tc_mode */ 2114 #define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF 2115 /* lower bit position of bitfield tx_tc_mode */ 2116 #define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 2117 /* width of bitfield tx_tc_mode */ 2118 #define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 2119 /* default value of bitfield tx_tc_mode */ 2120 #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 2121 2122 /* tx tx_desc_rate_mode bitfield definitions 2123 * preprocessor definitions for the bitfield "tx_desc_rate_mode". 2124 * port="pif_tps_desc_rate_mode_i" 2125 */ 2126 2127 /* register address for bitfield tx_desc_rate_mode */ 2128 #define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900 2129 /* bitmask for bitfield tx_desc_rate_mode */ 2130 #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080 2131 /* inverted bitmask for bitfield tx_desc_rate_mode */ 2132 #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F 2133 /* lower bit position of bitfield tx_desc_rate_mode */ 2134 #define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7 2135 /* width of bitfield tx_desc_rate_mode */ 2136 #define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1 2137 /* default value of bitfield tx_desc_rate_mode */ 2138 #define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0 2139 2140 /* tx tx_buf_en bitfield definitions 2141 * preprocessor definitions for the bitfield "tx_buf_en". 2142 * port="pif_tpb_tx_buf_en_i" 2143 */ 2144 2145 /* register address for bitfield tx_buf_en */ 2146 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 2147 /* bitmask for bitfield tx_buf_en */ 2148 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 2149 /* inverted bitmask for bitfield tx_buf_en */ 2150 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 2151 /* lower bit position of bitfield tx_buf_en */ 2152 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 2153 /* width of bitfield tx_buf_en */ 2154 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 2155 /* default value of bitfield tx_buf_en */ 2156 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 2157 2158 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 2159 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 2160 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2161 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 2162 */ 2163 2164 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 2165 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2166 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2167 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 2168 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2169 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 2170 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 2171 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 2172 /* width of bitfield tx{b}_hi_thresh[c:0] */ 2173 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 2174 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 2175 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 2176 2177 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 2178 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 2179 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2180 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 2181 */ 2182 2183 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 2184 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2185 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2186 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 2187 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2188 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 2189 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 2190 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 2191 /* width of bitfield tx{b}_lo_thresh[c:0] */ 2192 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 2193 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 2194 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 2195 2196 /* tx dma_sys_loopback bitfield definitions 2197 * preprocessor definitions for the bitfield "dma_sys_loopback". 2198 * port="pif_tpb_dma_sys_lbk_i" 2199 */ 2200 2201 /* register address for bitfield dma_sys_loopback */ 2202 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 2203 /* bitmask for bitfield dma_sys_loopback */ 2204 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 2205 /* inverted bitmask for bitfield dma_sys_loopback */ 2206 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 2207 /* lower bit position of bitfield dma_sys_loopback */ 2208 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 2209 /* width of bitfield dma_sys_loopback */ 2210 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 2211 /* default value of bitfield dma_sys_loopback */ 2212 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 2213 2214 /* tx dma_net_loopback bitfield definitions 2215 * preprocessor definitions for the bitfield "dma_net_loopback". 2216 * port="pif_tpb_dma_net_lbk_i" 2217 */ 2218 2219 /* register address for bitfield dma_net_loopback */ 2220 #define HW_ATL_TPB_DMA_NET_LBK_ADR 0x00007000 2221 /* bitmask for bitfield dma_net_loopback */ 2222 #define HW_ATL_TPB_DMA_NET_LBK_MSK 0x00000010 2223 /* inverted bitmask for bitfield dma_net_loopback */ 2224 #define HW_ATL_TPB_DMA_NET_LBK_MSKN 0xffffffef 2225 /* lower bit position of bitfield dma_net_loopback */ 2226 #define HW_ATL_TPB_DMA_NET_LBK_SHIFT 4 2227 /* width of bitfield dma_net_loopback */ 2228 #define HW_ATL_TPB_DMA_NET_LBK_WIDTH 1 2229 /* default value of bitfield dma_net_loopback */ 2230 #define HW_ATL_TPB_DMA_NET_LBK_DEFAULT 0x0 2231 2232 /* tx tx{b}_buf_size[7:0] bitfield definitions 2233 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 2234 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2235 * port="pif_tpb_tx0_buf_size_i[7:0]" 2236 */ 2237 2238 /* register address for bitfield tx{b}_buf_size[7:0] */ 2239 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 2240 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 2241 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 2242 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 2243 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 2244 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 2245 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 2246 /* width of bitfield tx{b}_buf_size[7:0] */ 2247 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 2248 /* default value of bitfield tx{b}_buf_size[7:0] */ 2249 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 2250 2251 /* tx tx_scp_ins_en bitfield definitions 2252 * preprocessor definitions for the bitfield "tx_scp_ins_en". 2253 * port="pif_tpb_scp_ins_en_i" 2254 */ 2255 2256 /* register address for bitfield tx_scp_ins_en */ 2257 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 2258 /* bitmask for bitfield tx_scp_ins_en */ 2259 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 2260 /* inverted bitmask for bitfield tx_scp_ins_en */ 2261 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 2262 /* lower bit position of bitfield tx_scp_ins_en */ 2263 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 2264 /* width of bitfield tx_scp_ins_en */ 2265 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 2266 /* default value of bitfield tx_scp_ins_en */ 2267 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 2268 2269 /* tx tx_clk_gate_en bitfield definitions 2270 * preprocessor definitions for the bitfield "tx_clk_gate_en". 2271 * port="pif_tpb_clk_gate_en_i" 2272 */ 2273 2274 /* register address for bitfield tx_clk_gate_en */ 2275 #define HW_ATL_TPB_TX_CLK_GATE_EN_ADR 0x00007900 2276 /* bitmask for bitfield tx_clk_gate_en */ 2277 #define HW_ATL_TPB_TX_CLK_GATE_EN_MSK 0x00000010 2278 /* inverted bitmask for bitfield tx_clk_gate_en */ 2279 #define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN 0xffffffef 2280 /* lower bit position of bitfield tx_clk_gate_en */ 2281 #define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT 4 2282 /* width of bitfield tx_clk_gate_en */ 2283 #define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH 1 2284 /* default value of bitfield tx_clk_gate_en */ 2285 #define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT 0x1 2286 2287 /* tx ipv4_chk_en bitfield definitions 2288 * preprocessor definitions for the bitfield "ipv4_chk_en". 2289 * port="pif_tpo_ipv4_chk_en_i" 2290 */ 2291 2292 /* register address for bitfield ipv4_chk_en */ 2293 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 2294 /* bitmask for bitfield ipv4_chk_en */ 2295 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 2296 /* inverted bitmask for bitfield ipv4_chk_en */ 2297 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 2298 /* lower bit position of bitfield ipv4_chk_en */ 2299 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 2300 /* width of bitfield ipv4_chk_en */ 2301 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 2302 /* default value of bitfield ipv4_chk_en */ 2303 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 2304 2305 /* tx l4_chk_en bitfield definitions 2306 * preprocessor definitions for the bitfield "l4_chk_en". 2307 * port="pif_tpo_l4_chk_en_i" 2308 */ 2309 2310 /* register address for bitfield l4_chk_en */ 2311 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 2312 /* bitmask for bitfield l4_chk_en */ 2313 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 2314 /* inverted bitmask for bitfield l4_chk_en */ 2315 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 2316 /* lower bit position of bitfield l4_chk_en */ 2317 #define HW_ATL_TPOL4CHK_EN_SHIFT 0 2318 /* width of bitfield l4_chk_en */ 2319 #define HW_ATL_TPOL4CHK_EN_WIDTH 1 2320 /* default value of bitfield l4_chk_en */ 2321 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2322 2323 /* tx pkt_sys_loopback bitfield definitions 2324 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2325 * port="pif_tpo_pkt_sys_lbk_i" 2326 */ 2327 2328 /* register address for bitfield pkt_sys_loopback */ 2329 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2330 /* bitmask for bitfield pkt_sys_loopback */ 2331 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2332 /* inverted bitmask for bitfield pkt_sys_loopback */ 2333 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2334 /* lower bit position of bitfield pkt_sys_loopback */ 2335 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2336 /* width of bitfield pkt_sys_loopback */ 2337 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2338 /* default value of bitfield pkt_sys_loopback */ 2339 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2340 2341 /* tx data_tc_arb_mode bitfield definitions 2342 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2343 * port="pif_tps_data_tc_arb_mode_i" 2344 */ 2345 2346 /* register address for bitfield data_tc_arb_mode */ 2347 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2348 /* bitmask for bitfield data_tc_arb_mode */ 2349 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2350 /* inverted bitmask for bitfield data_tc_arb_mode */ 2351 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2352 /* lower bit position of bitfield data_tc_arb_mode */ 2353 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2354 /* width of bitfield data_tc_arb_mode */ 2355 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2356 /* default value of bitfield data_tc_arb_mode */ 2357 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2358 2359 /* tx desc{r}_rate_en bitfield definitions 2360 * preprocessor definitions for the bitfield "desc{r}_rate_en". 2361 * port="pif_tps_desc_rate_en_i[0]" 2362 */ 2363 2364 /* register address for bitfield desc{r}_rate_en */ 2365 #define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10) 2366 /* bitmask for bitfield desc{r}_rate_en */ 2367 #define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000 2368 /* inverted bitmask for bitfield desc{r}_rate_en */ 2369 #define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF 2370 /* lower bit position of bitfield desc{r}_rate_en */ 2371 #define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31 2372 /* width of bitfield desc{r}_rate_en */ 2373 #define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1 2374 /* default value of bitfield desc{r}_rate_en */ 2375 #define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0 2376 2377 /* tx desc{r}_rate_x bitfield definitions 2378 * preprocessor definitions for the bitfield "desc{r}_rate_x". 2379 * port="pif_tps_desc0_rate_x" 2380 */ 2381 /* register address for bitfield desc{r}_rate_x */ 2382 #define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10) 2383 /* bitmask for bitfield desc{r}_rate_x */ 2384 #define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000 2385 /* inverted bitmask for bitfield desc{r}_rate_x */ 2386 #define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF 2387 /* lower bit position of bitfield desc{r}_rate_x */ 2388 #define HW_ATL_TPS_DESC_RATE_X_SHIFT 16 2389 /* width of bitfield desc{r}_rate_x */ 2390 #define HW_ATL_TPS_DESC_RATE_X_WIDTH 10 2391 /* default value of bitfield desc{r}_rate_x */ 2392 #define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0 2393 2394 /* tx desc{r}_rate_y bitfield definitions 2395 * preprocessor definitions for the bitfield "desc{r}_rate_y". 2396 * port="pif_tps_desc0_rate_y" 2397 */ 2398 /* register address for bitfield desc{r}_rate_y */ 2399 #define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10) 2400 /* bitmask for bitfield desc{r}_rate_y */ 2401 #define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF 2402 /* inverted bitmask for bitfield desc{r}_rate_y */ 2403 #define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000 2404 /* lower bit position of bitfield desc{r}_rate_y */ 2405 #define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0 2406 /* width of bitfield desc{r}_rate_y */ 2407 #define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14 2408 /* default value of bitfield desc{r}_rate_y */ 2409 #define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0 2410 2411 /* tx desc_rate_ta_rst bitfield definitions 2412 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2413 * port="pif_tps_desc_rate_ta_rst_i" 2414 */ 2415 2416 /* register address for bitfield desc_rate_ta_rst */ 2417 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2418 /* bitmask for bitfield desc_rate_ta_rst */ 2419 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2420 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2421 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2422 /* lower bit position of bitfield desc_rate_ta_rst */ 2423 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2424 /* width of bitfield desc_rate_ta_rst */ 2425 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2426 /* default value of bitfield desc_rate_ta_rst */ 2427 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2428 2429 /* tx desc_rate_limit[a:0] bitfield definitions 2430 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2431 * port="pif_tps_desc_rate_lim_i[10:0]" 2432 */ 2433 2434 /* register address for bitfield desc_rate_limit[a:0] */ 2435 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2436 /* bitmask for bitfield desc_rate_limit[a:0] */ 2437 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2438 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2439 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2440 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2441 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2442 /* width of bitfield desc_rate_limit[a:0] */ 2443 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2444 /* default value of bitfield desc_rate_limit[a:0] */ 2445 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2446 2447 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2448 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2449 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2450 */ 2451 2452 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2453 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2454 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2455 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2456 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2457 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2458 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2459 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2460 /* width of bitfield desc_tc_arb_mode[1:0] */ 2461 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2462 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2463 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2464 2465 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2466 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2467 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2468 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2469 */ 2470 2471 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2472 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2473 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2474 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2475 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2476 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2477 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2478 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2479 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2480 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2481 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2482 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2483 2484 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2485 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2486 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2487 * port="pif_tps_desc_tc0_weight_i[8:0]" 2488 */ 2489 2490 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2491 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2492 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2493 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2494 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2495 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2496 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2497 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2498 /* width of bitfield desc_tc{t}_weight[8:0] */ 2499 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2500 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2501 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2502 2503 /* tx desc_vm_arb_mode bitfield definitions 2504 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2505 * port="pif_tps_desc_vm_arb_mode_i" 2506 */ 2507 2508 /* register address for bitfield desc_vm_arb_mode */ 2509 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2510 /* bitmask for bitfield desc_vm_arb_mode */ 2511 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2512 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2513 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2514 /* lower bit position of bitfield desc_vm_arb_mode */ 2515 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2516 /* width of bitfield desc_vm_arb_mode */ 2517 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2518 /* default value of bitfield desc_vm_arb_mode */ 2519 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2520 2521 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2522 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2523 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2524 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2525 */ 2526 2527 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2528 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2529 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2530 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2531 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2532 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2533 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2534 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2535 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2536 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2537 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2538 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2539 2540 /* tx data_tc{t}_weight[8:0] bitfield definitions 2541 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2542 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2543 * port="pif_tps_data_tc0_weight_i[8:0]" 2544 */ 2545 2546 /* register address for bitfield data_tc{t}_weight[8:0] */ 2547 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2548 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2549 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2550 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2551 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2552 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2553 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2554 /* width of bitfield data_tc{t}_weight[8:0] */ 2555 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2556 /* default value of bitfield data_tc{t}_weight[8:0] */ 2557 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2558 2559 /* tx reg_res_dsbl bitfield definitions 2560 * preprocessor definitions for the bitfield "reg_res_dsbl". 2561 * port="pif_tx_reg_res_dsbl_i" 2562 */ 2563 2564 /* register address for bitfield reg_res_dsbl */ 2565 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2566 /* bitmask for bitfield reg_res_dsbl */ 2567 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2568 /* inverted bitmask for bitfield reg_res_dsbl */ 2569 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2570 /* lower bit position of bitfield reg_res_dsbl */ 2571 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2572 /* width of bitfield reg_res_dsbl */ 2573 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2574 /* default value of bitfield reg_res_dsbl */ 2575 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2576 2577 /* mac_phy register access busy bitfield definitions 2578 * preprocessor definitions for the bitfield "register access busy". 2579 * port="msm_pif_reg_busy_o" 2580 */ 2581 2582 /* register address for bitfield register access busy */ 2583 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2584 /* bitmask for bitfield register access busy */ 2585 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2586 /* inverted bitmask for bitfield register access busy */ 2587 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2588 /* lower bit position of bitfield register access busy */ 2589 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2590 /* width of bitfield register access busy */ 2591 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2592 2593 /* mac_phy msm register address[7:0] bitfield definitions 2594 * preprocessor definitions for the bitfield "msm register address[7:0]". 2595 * port="pif_msm_reg_addr_i[7:0]" 2596 */ 2597 2598 /* register address for bitfield msm register address[7:0] */ 2599 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2600 /* bitmask for bitfield msm register address[7:0] */ 2601 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2602 /* inverted bitmask for bitfield msm register address[7:0] */ 2603 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2604 /* lower bit position of bitfield msm register address[7:0] */ 2605 #define HW_ATL_MSM_REG_ADDR_SHIFT 0 2606 /* width of bitfield msm register address[7:0] */ 2607 #define HW_ATL_MSM_REG_ADDR_WIDTH 8 2608 /* default value of bitfield msm register address[7:0] */ 2609 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2610 2611 /* mac_phy register read strobe bitfield definitions 2612 * preprocessor definitions for the bitfield "register read strobe". 2613 * port="pif_msm_reg_rden_i" 2614 */ 2615 2616 /* register address for bitfield register read strobe */ 2617 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2618 /* bitmask for bitfield register read strobe */ 2619 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2620 /* inverted bitmask for bitfield register read strobe */ 2621 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2622 /* lower bit position of bitfield register read strobe */ 2623 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2624 /* width of bitfield register read strobe */ 2625 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2626 /* default value of bitfield register read strobe */ 2627 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2628 2629 /* mac_phy msm register read data[31:0] bitfield definitions 2630 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2631 * port="msm_pif_reg_rd_data_o[31:0]" 2632 */ 2633 2634 /* register address for bitfield msm register read data[31:0] */ 2635 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2636 /* bitmask for bitfield msm register read data[31:0] */ 2637 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2638 /* inverted bitmask for bitfield msm register read data[31:0] */ 2639 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2640 /* lower bit position of bitfield msm register read data[31:0] */ 2641 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2642 /* width of bitfield msm register read data[31:0] */ 2643 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2644 2645 /* mac_phy msm register write data[31:0] bitfield definitions 2646 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2647 * port="pif_msm_reg_wr_data_i[31:0]" 2648 */ 2649 2650 /* register address for bitfield msm register write data[31:0] */ 2651 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2652 /* bitmask for bitfield msm register write data[31:0] */ 2653 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2654 /* inverted bitmask for bitfield msm register write data[31:0] */ 2655 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2656 /* lower bit position of bitfield msm register write data[31:0] */ 2657 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2658 /* width of bitfield msm register write data[31:0] */ 2659 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2660 /* default value of bitfield msm register write data[31:0] */ 2661 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2662 2663 /* mac_phy register write strobe bitfield definitions 2664 * preprocessor definitions for the bitfield "register write strobe". 2665 * port="pif_msm_reg_wren_i" 2666 */ 2667 2668 /* register address for bitfield register write strobe */ 2669 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2670 /* bitmask for bitfield register write strobe */ 2671 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2672 /* inverted bitmask for bitfield register write strobe */ 2673 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2674 /* lower bit position of bitfield register write strobe */ 2675 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2676 /* width of bitfield register write strobe */ 2677 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2678 /* default value of bitfield register write strobe */ 2679 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2680 2681 /* register address for bitfield PTP Digital Clock Read Enable */ 2682 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR 0x00004628 2683 /* bitmask for bitfield PTP Digital Clock Read Enable */ 2684 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK 0x00000010 2685 /* inverted bitmask for bitfield PTP Digital Clock Read Enable */ 2686 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSKN 0xFFFFFFEF 2687 /* lower bit position of bitfield PTP Digital Clock Read Enable */ 2688 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT 4 2689 /* width of bitfield PTP Digital Clock Read Enable */ 2690 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_WIDTH 1 2691 /* default value of bitfield PTP Digital Clock Read Enable */ 2692 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_DEFAULT 0x0 2693 2694 /* register address for ptp counter reading */ 2695 #define HW_ATL_PCS_PTP_TS_VAL_ADDR(index) (0x00004900 + (index) * 0x4) 2696 2697 /* mif soft reset bitfield definitions 2698 * preprocessor definitions for the bitfield "soft reset". 2699 * port="pif_glb_res_i" 2700 */ 2701 2702 /* register address for bitfield soft reset */ 2703 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2704 /* bitmask for bitfield soft reset */ 2705 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2706 /* inverted bitmask for bitfield soft reset */ 2707 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2708 /* lower bit position of bitfield soft reset */ 2709 #define HW_ATL_GLB_SOFT_RES_SHIFT 15 2710 /* width of bitfield soft reset */ 2711 #define HW_ATL_GLB_SOFT_RES_WIDTH 1 2712 /* default value of bitfield soft reset */ 2713 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2714 2715 /* mif register reset disable bitfield definitions 2716 * preprocessor definitions for the bitfield "register reset disable". 2717 * port="pif_glb_reg_res_dsbl_i" 2718 */ 2719 2720 /* register address for bitfield register reset disable */ 2721 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2722 /* bitmask for bitfield register reset disable */ 2723 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2724 /* inverted bitmask for bitfield register reset disable */ 2725 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2726 /* lower bit position of bitfield register reset disable */ 2727 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2728 /* width of bitfield register reset disable */ 2729 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2730 /* default value of bitfield register reset disable */ 2731 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2732 2733 /* tx dma debug control definitions */ 2734 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2735 2736 /* tx dma descriptor base address msw definitions */ 2737 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2738 (0x00007c04u + (descriptor) * 0x40) 2739 2740 /* tx dma total request limit */ 2741 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2742 2743 /* tx interrupt moderation control register definitions 2744 * Preprocessor definitions for TX Interrupt Moderation Control Register 2745 * Base Address: 0x00008980 2746 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2747 */ 2748 2749 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2750 2751 /* pcie reg_res_dsbl bitfield definitions 2752 * preprocessor definitions for the bitfield "reg_res_dsbl". 2753 * port="pif_pci_reg_res_dsbl_i" 2754 */ 2755 2756 /* register address for bitfield reg_res_dsbl */ 2757 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2758 /* bitmask for bitfield reg_res_dsbl */ 2759 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2760 /* inverted bitmask for bitfield reg_res_dsbl */ 2761 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2762 /* lower bit position of bitfield reg_res_dsbl */ 2763 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2764 /* width of bitfield reg_res_dsbl */ 2765 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2766 /* default value of bitfield reg_res_dsbl */ 2767 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2768 2769 /* PCI core control register */ 2770 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2771 2772 /* global microprocessor scratch pad definitions */ 2773 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2774 (0x00000300u + (scratch_scp) * 0x4) 2775 2776 /* register address for bitfield uP Force Interrupt */ 2777 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 2778 /* bitmask for bitfield uP Force Interrupt */ 2779 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 2780 /* inverted bitmask for bitfield uP Force Interrupt */ 2781 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD 2782 /* lower bit position of bitfield uP Force Interrupt */ 2783 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 2784 /* width of bitfield uP Force Interrupt */ 2785 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 2786 /* default value of bitfield uP Force Interrupt */ 2787 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 2788 2789 /* Preprocessor definitions for Global MDIO Interfaces 2790 * Address: 0x00000280 + 0x4 * Number of interface 2791 */ 2792 #define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN 0x00000280u 2793 2794 #define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) \ 2795 (HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN + (((number) - 1) * 0x4)) 2796 2797 /* MIF MDIO Busy Bitfield Definitions 2798 * Preprocessor definitions for the bitfield "MDIO Busy". 2799 * PORT="mdio_pif_busy_o" 2800 */ 2801 2802 /* Register address for bitfield MDIO Busy */ 2803 #define HW_ATL_MDIO_BUSY_ADR 0x00000284 2804 /* Bitmask for bitfield MDIO Busy */ 2805 #define HW_ATL_MDIO_BUSY_MSK 0x80000000 2806 /* Inverted bitmask for bitfield MDIO Busy */ 2807 #define HW_ATL_MDIO_BUSY_MSKN 0x7FFFFFFF 2808 /* Lower bit position of bitfield MDIO Busy */ 2809 #define HW_ATL_MDIO_BUSY_SHIFT 31 2810 /* Width of bitfield MDIO Busy */ 2811 #define HW_ATL_MDIO_BUSY_WIDTH 1 2812 2813 /* MIF MDIO Execute Operation Bitfield Definitions 2814 * Preprocessor definitions for the bitfield "MDIO Execute Operation". 2815 * PORT="pif_mdio_op_start_i" 2816 */ 2817 2818 /* Register address for bitfield MDIO Execute Operation */ 2819 #define HW_ATL_MDIO_EXECUTE_OPERATION_ADR 0x00000284 2820 /* Bitmask for bitfield MDIO Execute Operation */ 2821 #define HW_ATL_MDIO_EXECUTE_OPERATION_MSK 0x00008000 2822 /* Inverted bitmask for bitfield MDIO Execute Operation */ 2823 #define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN 0xFFFF7FFF 2824 /* Lower bit position of bitfield MDIO Execute Operation */ 2825 #define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT 15 2826 /* Width of bitfield MDIO Execute Operation */ 2827 #define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH 1 2828 /* Default value of bitfield MDIO Execute Operation */ 2829 #define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT 0x0 2830 2831 /* MIF Op Mode [1:0] Bitfield Definitions 2832 * Preprocessor definitions for the bitfield "Op Mode [1:0]". 2833 * PORT="pif_mdio_mode_i[1:0]" 2834 */ 2835 2836 /* Register address for bitfield Op Mode [1:0] */ 2837 #define HW_ATL_MDIO_OP_MODE_ADR 0x00000284 2838 /* Bitmask for bitfield Op Mode [1:0] */ 2839 #define HW_ATL_MDIO_OP_MODE_MSK 0x00003000 2840 /* Inverted bitmask for bitfield Op Mode [1:0] */ 2841 #define HW_ATL_MDIO_OP_MODE_MSKN 0xFFFFCFFF 2842 /* Lower bit position of bitfield Op Mode [1:0] */ 2843 #define HW_ATL_MDIO_OP_MODE_SHIFT 12 2844 /* Width of bitfield Op Mode [1:0] */ 2845 #define HW_ATL_MDIO_OP_MODE_WIDTH 2 2846 /* Default value of bitfield Op Mode [1:0] */ 2847 #define HW_ATL_MDIO_OP_MODE_DEFAULT 0x0 2848 2849 /* MIF PHY address Bitfield Definitions 2850 * Preprocessor definitions for the bitfield "PHY address". 2851 * PORT="pif_mdio_phy_addr_i[9:0]" 2852 */ 2853 2854 /* Register address for bitfield PHY address */ 2855 #define HW_ATL_MDIO_PHY_ADDRESS_ADR 0x00000284 2856 /* Bitmask for bitfield PHY address */ 2857 #define HW_ATL_MDIO_PHY_ADDRESS_MSK 0x000003FF 2858 /* Inverted bitmask for bitfield PHY address */ 2859 #define HW_ATL_MDIO_PHY_ADDRESS_MSKN 0xFFFFFC00 2860 /* Lower bit position of bitfield PHY address */ 2861 #define HW_ATL_MDIO_PHY_ADDRESS_SHIFT 0 2862 /* Width of bitfield PHY address */ 2863 #define HW_ATL_MDIO_PHY_ADDRESS_WIDTH 10 2864 /* Default value of bitfield PHY address */ 2865 #define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT 0x0 2866 2867 /* MIF MDIO WriteData [F:0] Bitfield Definitions 2868 * Preprocessor definitions for the bitfield "MDIO WriteData [F:0]". 2869 * PORT="pif_mdio_wdata_i[15:0]" 2870 */ 2871 2872 /* Register address for bitfield MDIO WriteData [F:0] */ 2873 #define HW_ATL_MDIO_WRITE_DATA_ADR 0x00000288 2874 /* Bitmask for bitfield MDIO WriteData [F:0] */ 2875 #define HW_ATL_MDIO_WRITE_DATA_MSK 0x0000FFFF 2876 /* Inverted bitmask for bitfield MDIO WriteData [F:0] */ 2877 #define HW_ATL_MDIO_WRITE_DATA_MSKN 0xFFFF0000 2878 /* Lower bit position of bitfield MDIO WriteData [F:0] */ 2879 #define HW_ATL_MDIO_WRITE_DATA_SHIFT 0 2880 /* Width of bitfield MDIO WriteData [F:0] */ 2881 #define HW_ATL_MDIO_WRITE_DATA_WIDTH 16 2882 /* Default value of bitfield MDIO WriteData [F:0] */ 2883 #define HW_ATL_MDIO_WRITE_DATA_DEFAULT 0x0 2884 2885 /* MIF MDIO Address [F:0] Bitfield Definitions 2886 * Preprocessor definitions for the bitfield "MDIO Address [F:0]". 2887 * PORT="pif_mdio_addr_i[15:0]" 2888 */ 2889 2890 /* Register address for bitfield MDIO Address [F:0] */ 2891 #define HW_ATL_MDIO_ADDRESS_ADR 0x0000028C 2892 /* Bitmask for bitfield MDIO Address [F:0] */ 2893 #define HW_ATL_MDIO_ADDRESS_MSK 0x0000FFFF 2894 /* Inverted bitmask for bitfield MDIO Address [F:0] */ 2895 #define HW_ATL_MDIO_ADDRESS_MSKN 0xFFFF0000 2896 /* Lower bit position of bitfield MDIO Address [F:0] */ 2897 #define HW_ATL_MDIO_ADDRESS_SHIFT 0 2898 /* Width of bitfield MDIO Address [F:0] */ 2899 #define HW_ATL_MDIO_ADDRESS_WIDTH 16 2900 /* Default value of bitfield MDIO Address [F:0] */ 2901 #define HW_ATL_MDIO_ADDRESS_DEFAULT 0x0 2902 2903 #define HW_ATL_MIF_RESET_TIMEOUT_ADR 0x00000348 2904 2905 #define HW_ATL_FW_SM_MDIO 0x0U 2906 #define HW_ATL_FW_SM_RAM 0x2U 2907 #define HW_ATL_FW_SM_RESET1 0x3U 2908 #define HW_ATL_FW_SM_RESET2 0x4U 2909 2910 #endif /* HW_ATL_LLH_INTERNAL_H */ 2911