1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <[email protected]>
4 * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <[email protected]>
7 */
8
9 #include <linux/netdevice.h>
10 #include <net/dsa.h>
11 #include <linux/if_bridge.h>
12
13 #include "qca8k.h"
14
15 #define MIB_DESC(_s, _o, _n) \
16 { \
17 .size = (_s), \
18 .offset = (_o), \
19 .name = (_n), \
20 }
21
22 const struct qca8k_mib_desc ar8327_mib[] = {
23 MIB_DESC(1, 0x00, "RxBroad"),
24 MIB_DESC(1, 0x04, "RxPause"),
25 MIB_DESC(1, 0x08, "RxMulti"),
26 MIB_DESC(1, 0x0c, "RxFcsErr"),
27 MIB_DESC(1, 0x10, "RxAlignErr"),
28 MIB_DESC(1, 0x14, "RxRunt"),
29 MIB_DESC(1, 0x18, "RxFragment"),
30 MIB_DESC(1, 0x1c, "Rx64Byte"),
31 MIB_DESC(1, 0x20, "Rx128Byte"),
32 MIB_DESC(1, 0x24, "Rx256Byte"),
33 MIB_DESC(1, 0x28, "Rx512Byte"),
34 MIB_DESC(1, 0x2c, "Rx1024Byte"),
35 MIB_DESC(1, 0x30, "Rx1518Byte"),
36 MIB_DESC(1, 0x34, "RxMaxByte"),
37 MIB_DESC(1, 0x38, "RxTooLong"),
38 MIB_DESC(2, 0x3c, "RxGoodByte"),
39 MIB_DESC(2, 0x44, "RxBadByte"),
40 MIB_DESC(1, 0x4c, "RxOverFlow"),
41 MIB_DESC(1, 0x50, "Filtered"),
42 MIB_DESC(1, 0x54, "TxBroad"),
43 MIB_DESC(1, 0x58, "TxPause"),
44 MIB_DESC(1, 0x5c, "TxMulti"),
45 MIB_DESC(1, 0x60, "TxUnderRun"),
46 MIB_DESC(1, 0x64, "Tx64Byte"),
47 MIB_DESC(1, 0x68, "Tx128Byte"),
48 MIB_DESC(1, 0x6c, "Tx256Byte"),
49 MIB_DESC(1, 0x70, "Tx512Byte"),
50 MIB_DESC(1, 0x74, "Tx1024Byte"),
51 MIB_DESC(1, 0x78, "Tx1518Byte"),
52 MIB_DESC(1, 0x7c, "TxMaxByte"),
53 MIB_DESC(1, 0x80, "TxOverSize"),
54 MIB_DESC(2, 0x84, "TxByte"),
55 MIB_DESC(1, 0x8c, "TxCollision"),
56 MIB_DESC(1, 0x90, "TxAbortCol"),
57 MIB_DESC(1, 0x94, "TxMultiCol"),
58 MIB_DESC(1, 0x98, "TxSingleCol"),
59 MIB_DESC(1, 0x9c, "TxExcDefer"),
60 MIB_DESC(1, 0xa0, "TxDefer"),
61 MIB_DESC(1, 0xa4, "TxLateCol"),
62 MIB_DESC(1, 0xa8, "RXUnicast"),
63 MIB_DESC(1, 0xac, "TXUnicast"),
64 };
65
qca8k_read(struct qca8k_priv * priv,u32 reg,u32 * val)66 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
67 {
68 return regmap_read(priv->regmap, reg, val);
69 }
70
qca8k_write(struct qca8k_priv * priv,u32 reg,u32 val)71 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
72 {
73 return regmap_write(priv->regmap, reg, val);
74 }
75
qca8k_rmw(struct qca8k_priv * priv,u32 reg,u32 mask,u32 write_val)76 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
77 {
78 return regmap_update_bits(priv->regmap, reg, mask, write_val);
79 }
80
81 static const struct regmap_range qca8k_readable_ranges[] = {
82 regmap_reg_range(0x0000, 0x00e4), /* Global control */
83 regmap_reg_range(0x0100, 0x0168), /* EEE control */
84 regmap_reg_range(0x0200, 0x0270), /* Parser control */
85 regmap_reg_range(0x0400, 0x0454), /* ACL */
86 regmap_reg_range(0x0600, 0x0718), /* Lookup */
87 regmap_reg_range(0x0800, 0x0b70), /* QM */
88 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
89 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
90 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
91 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
92 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
93 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
94 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
95 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
96 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
97 };
98
99 const struct regmap_access_table qca8k_readable_table = {
100 .yes_ranges = qca8k_readable_ranges,
101 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
102 };
103
qca8k_busy_wait(struct qca8k_priv * priv,u32 reg,u32 mask)104 static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
105 {
106 u32 val;
107
108 return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
109 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
110 }
111
qca8k_fdb_read(struct qca8k_priv * priv,struct qca8k_fdb * fdb)112 static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
113 {
114 u32 reg[QCA8K_ATU_TABLE_SIZE];
115 int ret;
116
117 /* load the ARL table into an array */
118 ret = regmap_bulk_read(priv->regmap, QCA8K_REG_ATU_DATA0, reg,
119 QCA8K_ATU_TABLE_SIZE);
120 if (ret)
121 return ret;
122
123 /* vid - 83:72 */
124 fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
125 /* aging - 67:64 */
126 fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
127 /* portmask - 54:48 */
128 fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
129 /* mac - 47:0 */
130 fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
131 fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
132 fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
133 fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
134 fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
135 fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
136
137 return 0;
138 }
139
qca8k_fdb_write(struct qca8k_priv * priv,u16 vid,u8 port_mask,const u8 * mac,u8 aging)140 static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask,
141 const u8 *mac, u8 aging)
142 {
143 u32 reg[QCA8K_ATU_TABLE_SIZE] = { 0 };
144
145 /* vid - 83:72 */
146 reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
147 /* aging - 67:64 */
148 reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
149 /* portmask - 54:48 */
150 reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
151 /* mac - 47:0 */
152 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
153 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
154 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
155 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
156 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
157 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
158
159 /* load the array into the ARL table */
160 regmap_bulk_write(priv->regmap, QCA8K_REG_ATU_DATA0, reg,
161 QCA8K_ATU_TABLE_SIZE);
162 }
163
qca8k_fdb_access(struct qca8k_priv * priv,enum qca8k_fdb_cmd cmd,int port)164 static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd,
165 int port)
166 {
167 u32 reg;
168 int ret;
169
170 /* Set the command and FDB index */
171 reg = QCA8K_ATU_FUNC_BUSY;
172 reg |= cmd;
173 if (port >= 0) {
174 reg |= QCA8K_ATU_FUNC_PORT_EN;
175 reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
176 }
177
178 /* Write the function register triggering the table access */
179 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
180 if (ret)
181 return ret;
182
183 /* wait for completion */
184 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
185 if (ret)
186 return ret;
187
188 /* Check for table full violation when adding an entry */
189 if (cmd == QCA8K_FDB_LOAD) {
190 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®);
191 if (ret < 0)
192 return ret;
193 if (reg & QCA8K_ATU_FUNC_FULL)
194 return -1;
195 }
196
197 return 0;
198 }
199
qca8k_fdb_next(struct qca8k_priv * priv,struct qca8k_fdb * fdb,int port)200 static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb,
201 int port)
202 {
203 int ret;
204
205 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
206 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
207 if (ret < 0)
208 return ret;
209
210 return qca8k_fdb_read(priv, fdb);
211 }
212
qca8k_fdb_add(struct qca8k_priv * priv,const u8 * mac,u16 port_mask,u16 vid,u8 aging)213 static int qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac,
214 u16 port_mask, u16 vid, u8 aging)
215 {
216 int ret;
217
218 mutex_lock(&priv->reg_mutex);
219 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
220 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
221 mutex_unlock(&priv->reg_mutex);
222
223 return ret;
224 }
225
qca8k_fdb_del(struct qca8k_priv * priv,const u8 * mac,u16 port_mask,u16 vid)226 static int qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac,
227 u16 port_mask, u16 vid)
228 {
229 int ret;
230
231 mutex_lock(&priv->reg_mutex);
232 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
233 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
234 mutex_unlock(&priv->reg_mutex);
235
236 return ret;
237 }
238
qca8k_fdb_flush(struct qca8k_priv * priv)239 void qca8k_fdb_flush(struct qca8k_priv *priv)
240 {
241 mutex_lock(&priv->reg_mutex);
242 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
243 mutex_unlock(&priv->reg_mutex);
244 }
245
qca8k_fdb_search_and_insert(struct qca8k_priv * priv,u8 port_mask,const u8 * mac,u16 vid,u8 aging)246 static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
247 const u8 *mac, u16 vid, u8 aging)
248 {
249 struct qca8k_fdb fdb = { 0 };
250 int ret;
251
252 mutex_lock(&priv->reg_mutex);
253
254 qca8k_fdb_write(priv, vid, 0, mac, 0);
255 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
256 if (ret < 0)
257 goto exit;
258
259 ret = qca8k_fdb_read(priv, &fdb);
260 if (ret < 0)
261 goto exit;
262
263 /* Rule exist. Delete first */
264 if (fdb.aging) {
265 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
266 if (ret)
267 goto exit;
268 } else {
269 fdb.aging = aging;
270 }
271
272 /* Add port to fdb portmask */
273 fdb.port_mask |= port_mask;
274
275 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
276 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
277
278 exit:
279 mutex_unlock(&priv->reg_mutex);
280 return ret;
281 }
282
qca8k_fdb_search_and_del(struct qca8k_priv * priv,u8 port_mask,const u8 * mac,u16 vid)283 static int qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
284 const u8 *mac, u16 vid)
285 {
286 struct qca8k_fdb fdb = { 0 };
287 int ret;
288
289 mutex_lock(&priv->reg_mutex);
290
291 qca8k_fdb_write(priv, vid, 0, mac, 0);
292 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
293 if (ret < 0)
294 goto exit;
295
296 ret = qca8k_fdb_read(priv, &fdb);
297 if (ret < 0)
298 goto exit;
299
300 /* Rule doesn't exist. Why delete? */
301 if (!fdb.aging) {
302 ret = -EINVAL;
303 goto exit;
304 }
305
306 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
307 if (ret)
308 goto exit;
309
310 /* Only port in the rule is this port. Don't re insert */
311 if (fdb.port_mask == port_mask)
312 goto exit;
313
314 /* Remove port from port mask */
315 fdb.port_mask &= ~port_mask;
316
317 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
318 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
319
320 exit:
321 mutex_unlock(&priv->reg_mutex);
322 return ret;
323 }
324
qca8k_vlan_access(struct qca8k_priv * priv,enum qca8k_vlan_cmd cmd,u16 vid)325 static int qca8k_vlan_access(struct qca8k_priv *priv,
326 enum qca8k_vlan_cmd cmd, u16 vid)
327 {
328 u32 reg;
329 int ret;
330
331 /* Set the command and VLAN index */
332 reg = QCA8K_VTU_FUNC1_BUSY;
333 reg |= cmd;
334 reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
335
336 /* Write the function register triggering the table access */
337 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
338 if (ret)
339 return ret;
340
341 /* wait for completion */
342 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
343 if (ret)
344 return ret;
345
346 /* Check for table full violation when adding an entry */
347 if (cmd == QCA8K_VLAN_LOAD) {
348 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®);
349 if (ret < 0)
350 return ret;
351 if (reg & QCA8K_VTU_FUNC1_FULL)
352 return -ENOMEM;
353 }
354
355 return 0;
356 }
357
qca8k_vlan_add(struct qca8k_priv * priv,u8 port,u16 vid,bool untagged)358 static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid,
359 bool untagged)
360 {
361 u32 reg;
362 int ret;
363
364 /* We do the right thing with VLAN 0 and treat it as untagged while
365 * preserving the tag on egress.
366 */
367 if (vid == 0)
368 return 0;
369
370 mutex_lock(&priv->reg_mutex);
371 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
372 if (ret < 0)
373 goto out;
374
375 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
376 if (ret < 0)
377 goto out;
378 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
379 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
380 if (untagged)
381 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
382 else
383 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
384
385 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
386 if (ret)
387 goto out;
388 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
389
390 out:
391 mutex_unlock(&priv->reg_mutex);
392
393 return ret;
394 }
395
qca8k_vlan_del(struct qca8k_priv * priv,u8 port,u16 vid)396 static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
397 {
398 u32 reg, mask;
399 int ret, i;
400 bool del;
401
402 mutex_lock(&priv->reg_mutex);
403 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
404 if (ret < 0)
405 goto out;
406
407 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
408 if (ret < 0)
409 goto out;
410 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
411 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
412
413 /* Check if we're the last member to be removed */
414 del = true;
415 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
416 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
417
418 if ((reg & mask) != mask) {
419 del = false;
420 break;
421 }
422 }
423
424 if (del) {
425 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
426 } else {
427 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
428 if (ret)
429 goto out;
430 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
431 }
432
433 out:
434 mutex_unlock(&priv->reg_mutex);
435
436 return ret;
437 }
438
qca8k_mib_init(struct qca8k_priv * priv)439 int qca8k_mib_init(struct qca8k_priv *priv)
440 {
441 int ret;
442
443 mutex_lock(&priv->reg_mutex);
444 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
445 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
446 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |
447 QCA8K_MIB_BUSY);
448 if (ret)
449 goto exit;
450
451 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
452 if (ret)
453 goto exit;
454
455 ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
456 if (ret)
457 goto exit;
458
459 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
460
461 exit:
462 mutex_unlock(&priv->reg_mutex);
463 return ret;
464 }
465
qca8k_port_set_status(struct qca8k_priv * priv,int port,int enable)466 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
467 {
468 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
469
470 /* Port 0 and 6 have no internal PHY */
471 if (port > 0 && port < 6)
472 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
473
474 if (enable)
475 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
476 else
477 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
478 }
479
qca8k_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)480 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset,
481 uint8_t *data)
482 {
483 struct qca8k_priv *priv = ds->priv;
484 int i;
485
486 if (stringset != ETH_SS_STATS)
487 return;
488
489 for (i = 0; i < priv->info->mib_count; i++)
490 ethtool_puts(&data, ar8327_mib[i].name);
491 }
492
qca8k_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)493 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
494 uint64_t *data)
495 {
496 struct qca8k_priv *priv = ds->priv;
497 const struct qca8k_mib_desc *mib;
498 u32 reg, i, val;
499 u32 hi = 0;
500 int ret;
501
502 if (priv->mgmt_conduit && priv->info->ops->autocast_mib &&
503 priv->info->ops->autocast_mib(ds, port, data) > 0)
504 return;
505
506 for (i = 0; i < priv->info->mib_count; i++) {
507 mib = &ar8327_mib[i];
508 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
509
510 ret = qca8k_read(priv, reg, &val);
511 if (ret < 0)
512 continue;
513
514 if (mib->size == 2) {
515 ret = qca8k_read(priv, reg + 4, &hi);
516 if (ret < 0)
517 continue;
518 }
519
520 data[i] = val;
521 if (mib->size == 2)
522 data[i] |= (u64)hi << 32;
523 }
524 }
525
qca8k_get_sset_count(struct dsa_switch * ds,int port,int sset)526 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
527 {
528 struct qca8k_priv *priv = ds->priv;
529
530 if (sset != ETH_SS_STATS)
531 return 0;
532
533 return priv->info->mib_count;
534 }
535
qca8k_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * eee)536 int qca8k_set_mac_eee(struct dsa_switch *ds, int port,
537 struct ethtool_keee *eee)
538 {
539 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
540 struct qca8k_priv *priv = ds->priv;
541 u32 reg;
542 int ret;
543
544 mutex_lock(&priv->reg_mutex);
545 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®);
546 if (ret < 0)
547 goto exit;
548
549 if (eee->eee_enabled)
550 reg |= lpi_en;
551 else
552 reg &= ~lpi_en;
553 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
554
555 exit:
556 mutex_unlock(&priv->reg_mutex);
557 return ret;
558 }
559
qca8k_port_configure_learning(struct dsa_switch * ds,int port,bool learning)560 static int qca8k_port_configure_learning(struct dsa_switch *ds, int port,
561 bool learning)
562 {
563 struct qca8k_priv *priv = ds->priv;
564
565 if (learning)
566 return regmap_set_bits(priv->regmap,
567 QCA8K_PORT_LOOKUP_CTRL(port),
568 QCA8K_PORT_LOOKUP_LEARN);
569 else
570 return regmap_clear_bits(priv->regmap,
571 QCA8K_PORT_LOOKUP_CTRL(port),
572 QCA8K_PORT_LOOKUP_LEARN);
573 }
574
qca8k_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)575 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
576 {
577 struct dsa_port *dp = dsa_to_port(ds, port);
578 struct qca8k_priv *priv = ds->priv;
579 bool learning = false;
580 u32 stp_state;
581
582 switch (state) {
583 case BR_STATE_DISABLED:
584 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
585 break;
586 case BR_STATE_BLOCKING:
587 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
588 break;
589 case BR_STATE_LISTENING:
590 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
591 break;
592 case BR_STATE_LEARNING:
593 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
594 learning = dp->learning;
595 break;
596 case BR_STATE_FORWARDING:
597 learning = dp->learning;
598 fallthrough;
599 default:
600 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
601 break;
602 }
603
604 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
605 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
606
607 qca8k_port_configure_learning(ds, port, learning);
608 }
609
qca8k_update_port_member(struct qca8k_priv * priv,int port,const struct net_device * bridge_dev,bool join)610 static int qca8k_update_port_member(struct qca8k_priv *priv, int port,
611 const struct net_device *bridge_dev,
612 bool join)
613 {
614 bool isolated = !!(priv->port_isolated_map & BIT(port)), other_isolated;
615 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp;
616 u32 port_mask = BIT(dp->cpu_dp->index);
617 int i, ret;
618
619 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
620 if (i == port)
621 continue;
622 if (dsa_is_cpu_port(priv->ds, i))
623 continue;
624
625 other_dp = dsa_to_port(priv->ds, i);
626 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
627 continue;
628
629 other_isolated = !!(priv->port_isolated_map & BIT(i));
630
631 /* Add/remove this port to/from the portvlan mask of the other
632 * ports in the bridge
633 */
634 if (join && !(isolated && other_isolated)) {
635 port_mask |= BIT(i);
636 ret = regmap_set_bits(priv->regmap,
637 QCA8K_PORT_LOOKUP_CTRL(i),
638 BIT(port));
639 } else {
640 ret = regmap_clear_bits(priv->regmap,
641 QCA8K_PORT_LOOKUP_CTRL(i),
642 BIT(port));
643 }
644
645 if (ret)
646 return ret;
647 }
648
649 /* Add/remove all other ports to/from this port's portvlan mask */
650 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
651 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
652
653 return ret;
654 }
655
qca8k_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)656 int qca8k_port_pre_bridge_flags(struct dsa_switch *ds, int port,
657 struct switchdev_brport_flags flags,
658 struct netlink_ext_ack *extack)
659 {
660 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
661 return -EINVAL;
662
663 return 0;
664 }
665
qca8k_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)666 int qca8k_port_bridge_flags(struct dsa_switch *ds, int port,
667 struct switchdev_brport_flags flags,
668 struct netlink_ext_ack *extack)
669 {
670 struct qca8k_priv *priv = ds->priv;
671 int ret;
672
673 if (flags.mask & BR_LEARNING) {
674 ret = qca8k_port_configure_learning(ds, port,
675 flags.val & BR_LEARNING);
676 if (ret)
677 return ret;
678 }
679
680 if (flags.mask & BR_ISOLATED) {
681 struct dsa_port *dp = dsa_to_port(ds, port);
682 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
683
684 if (flags.val & BR_ISOLATED)
685 priv->port_isolated_map |= BIT(port);
686 else
687 priv->port_isolated_map &= ~BIT(port);
688
689 ret = qca8k_update_port_member(priv, port, bridge_dev, true);
690 if (ret)
691 return ret;
692 }
693
694 return 0;
695 }
696
qca8k_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)697 int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
698 struct dsa_bridge bridge,
699 bool *tx_fwd_offload,
700 struct netlink_ext_ack *extack)
701 {
702 struct qca8k_priv *priv = ds->priv;
703
704 return qca8k_update_port_member(priv, port, bridge.dev, true);
705 }
706
qca8k_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)707 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
708 struct dsa_bridge bridge)
709 {
710 struct qca8k_priv *priv = ds->priv;
711 int err;
712
713 err = qca8k_update_port_member(priv, port, bridge.dev, false);
714 if (err)
715 dev_err(priv->dev,
716 "Failed to update switch config for bridge leave: %d\n",
717 err);
718 }
719
qca8k_port_fast_age(struct dsa_switch * ds,int port)720 void qca8k_port_fast_age(struct dsa_switch *ds, int port)
721 {
722 struct qca8k_priv *priv = ds->priv;
723
724 mutex_lock(&priv->reg_mutex);
725 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
726 mutex_unlock(&priv->reg_mutex);
727 }
728
qca8k_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)729 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
730 {
731 struct qca8k_priv *priv = ds->priv;
732 unsigned int secs = msecs / 1000;
733 u32 val;
734
735 /* AGE_TIME reg is set in 7s step */
736 val = secs / 7;
737
738 /* Handle case with 0 as val to NOT disable
739 * learning
740 */
741 if (!val)
742 val = 1;
743
744 return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL,
745 QCA8K_ATU_AGE_TIME_MASK,
746 QCA8K_ATU_AGE_TIME(val));
747 }
748
qca8k_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)749 int qca8k_port_enable(struct dsa_switch *ds, int port,
750 struct phy_device *phy)
751 {
752 struct qca8k_priv *priv = ds->priv;
753
754 qca8k_port_set_status(priv, port, 1);
755 priv->port_enabled_map |= BIT(port);
756
757 if (dsa_is_user_port(ds, port))
758 phy_support_asym_pause(phy);
759
760 return 0;
761 }
762
qca8k_port_disable(struct dsa_switch * ds,int port)763 void qca8k_port_disable(struct dsa_switch *ds, int port)
764 {
765 struct qca8k_priv *priv = ds->priv;
766
767 qca8k_port_set_status(priv, port, 0);
768 priv->port_enabled_map &= ~BIT(port);
769 }
770
qca8k_port_change_mtu(struct dsa_switch * ds,int port,int new_mtu)771 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
772 {
773 struct qca8k_priv *priv = ds->priv;
774 int ret;
775
776 /* We have only have a general MTU setting.
777 * DSA always set the CPU port's MTU to the largest MTU of the user
778 * ports.
779 * Setting MTU just for the CPU port is sufficient to correctly set a
780 * value for every port.
781 */
782 if (!dsa_is_cpu_port(ds, port))
783 return 0;
784
785 /* To change the MAX_FRAME_SIZE the cpu ports must be off or
786 * the switch panics.
787 * Turn off both cpu ports before applying the new value to prevent
788 * this.
789 */
790 if (priv->port_enabled_map & BIT(0))
791 qca8k_port_set_status(priv, 0, 0);
792
793 if (priv->port_enabled_map & BIT(6))
794 qca8k_port_set_status(priv, 6, 0);
795
796 /* Include L2 header / FCS length */
797 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu +
798 ETH_HLEN + ETH_FCS_LEN);
799
800 if (priv->port_enabled_map & BIT(0))
801 qca8k_port_set_status(priv, 0, 1);
802
803 if (priv->port_enabled_map & BIT(6))
804 qca8k_port_set_status(priv, 6, 1);
805
806 return ret;
807 }
808
qca8k_port_max_mtu(struct dsa_switch * ds,int port)809 int qca8k_port_max_mtu(struct dsa_switch *ds, int port)
810 {
811 return QCA8K_MAX_MTU;
812 }
813
qca8k_port_fdb_insert(struct qca8k_priv * priv,const u8 * addr,u16 port_mask,u16 vid)814 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
815 u16 port_mask, u16 vid)
816 {
817 /* Set the vid to the port vlan id if no vid is set */
818 if (!vid)
819 vid = QCA8K_PORT_VID_DEF;
820
821 return qca8k_fdb_add(priv, addr, port_mask, vid,
822 QCA8K_ATU_STATUS_STATIC);
823 }
824
qca8k_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)825 int qca8k_port_fdb_add(struct dsa_switch *ds, int port,
826 const unsigned char *addr, u16 vid,
827 struct dsa_db db)
828 {
829 struct qca8k_priv *priv = ds->priv;
830 u16 port_mask = BIT(port);
831
832 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
833 }
834
qca8k_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)835 int qca8k_port_fdb_del(struct dsa_switch *ds, int port,
836 const unsigned char *addr, u16 vid,
837 struct dsa_db db)
838 {
839 struct qca8k_priv *priv = ds->priv;
840 u16 port_mask = BIT(port);
841
842 if (!vid)
843 vid = QCA8K_PORT_VID_DEF;
844
845 return qca8k_fdb_del(priv, addr, port_mask, vid);
846 }
847
qca8k_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)848 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
849 dsa_fdb_dump_cb_t *cb, void *data)
850 {
851 struct qca8k_priv *priv = ds->priv;
852 struct qca8k_fdb _fdb = { 0 };
853 int cnt = QCA8K_NUM_FDB_RECORDS;
854 bool is_static;
855 int ret = 0;
856
857 mutex_lock(&priv->reg_mutex);
858 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
859 if (!_fdb.aging)
860 break;
861 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
862 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
863 if (ret)
864 break;
865 }
866 mutex_unlock(&priv->reg_mutex);
867
868 return 0;
869 }
870
qca8k_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)871 int qca8k_port_mdb_add(struct dsa_switch *ds, int port,
872 const struct switchdev_obj_port_mdb *mdb,
873 struct dsa_db db)
874 {
875 struct qca8k_priv *priv = ds->priv;
876 const u8 *addr = mdb->addr;
877 u16 vid = mdb->vid;
878
879 if (!vid)
880 vid = QCA8K_PORT_VID_DEF;
881
882 return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid,
883 QCA8K_ATU_STATUS_STATIC);
884 }
885
qca8k_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)886 int qca8k_port_mdb_del(struct dsa_switch *ds, int port,
887 const struct switchdev_obj_port_mdb *mdb,
888 struct dsa_db db)
889 {
890 struct qca8k_priv *priv = ds->priv;
891 const u8 *addr = mdb->addr;
892 u16 vid = mdb->vid;
893
894 if (!vid)
895 vid = QCA8K_PORT_VID_DEF;
896
897 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
898 }
899
qca8k_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)900 int qca8k_port_mirror_add(struct dsa_switch *ds, int port,
901 struct dsa_mall_mirror_tc_entry *mirror,
902 bool ingress, struct netlink_ext_ack *extack)
903 {
904 struct qca8k_priv *priv = ds->priv;
905 int monitor_port, ret;
906 u32 reg, val;
907
908 /* Check for existent entry */
909 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
910 return -EEXIST;
911
912 ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
913 if (ret)
914 return ret;
915
916 /* QCA83xx can have only one port set to mirror mode.
917 * Check that the correct port is requested and return error otherwise.
918 * When no mirror port is set, the values is set to 0xF
919 */
920 monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
921 if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
922 return -EEXIST;
923
924 /* Set the monitor port */
925 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
926 mirror->to_local_port);
927 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
928 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
929 if (ret)
930 return ret;
931
932 if (ingress) {
933 reg = QCA8K_PORT_LOOKUP_CTRL(port);
934 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
935 } else {
936 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
937 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
938 }
939
940 ret = regmap_update_bits(priv->regmap, reg, val, val);
941 if (ret)
942 return ret;
943
944 /* Track mirror port for tx and rx to decide when the
945 * mirror port has to be disabled.
946 */
947 if (ingress)
948 priv->mirror_rx |= BIT(port);
949 else
950 priv->mirror_tx |= BIT(port);
951
952 return 0;
953 }
954
qca8k_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)955 void qca8k_port_mirror_del(struct dsa_switch *ds, int port,
956 struct dsa_mall_mirror_tc_entry *mirror)
957 {
958 struct qca8k_priv *priv = ds->priv;
959 u32 reg, val;
960 int ret;
961
962 if (mirror->ingress) {
963 reg = QCA8K_PORT_LOOKUP_CTRL(port);
964 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
965 } else {
966 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
967 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
968 }
969
970 ret = regmap_clear_bits(priv->regmap, reg, val);
971 if (ret)
972 goto err;
973
974 if (mirror->ingress)
975 priv->mirror_rx &= ~BIT(port);
976 else
977 priv->mirror_tx &= ~BIT(port);
978
979 /* No port set to send packet to mirror port. Disable mirror port */
980 if (!priv->mirror_rx && !priv->mirror_tx) {
981 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
982 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
983 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
984 if (ret)
985 goto err;
986 }
987 err:
988 dev_err(priv->dev, "Failed to del mirror port from %d", port);
989 }
990
qca8k_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)991 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port,
992 bool vlan_filtering,
993 struct netlink_ext_ack *extack)
994 {
995 struct qca8k_priv *priv = ds->priv;
996 int ret;
997
998 if (vlan_filtering) {
999 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1000 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
1001 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1002 } else {
1003 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1004 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
1005 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1006 }
1007
1008 return ret;
1009 }
1010
qca8k_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1011 int qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1012 const struct switchdev_obj_port_vlan *vlan,
1013 struct netlink_ext_ack *extack)
1014 {
1015 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1016 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1017 struct qca8k_priv *priv = ds->priv;
1018 int ret;
1019
1020 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1021 if (ret) {
1022 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1023 return ret;
1024 }
1025
1026 if (pvid) {
1027 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1028 QCA8K_EGREES_VLAN_PORT_MASK(port),
1029 QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
1030 if (ret)
1031 return ret;
1032
1033 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1034 QCA8K_PORT_VLAN_CVID(vlan->vid) |
1035 QCA8K_PORT_VLAN_SVID(vlan->vid));
1036 }
1037
1038 return ret;
1039 }
1040
qca8k_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1041 int qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1042 const struct switchdev_obj_port_vlan *vlan)
1043 {
1044 struct qca8k_priv *priv = ds->priv;
1045 int ret;
1046
1047 ret = qca8k_vlan_del(priv, port, vlan->vid);
1048 if (ret)
1049 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1050
1051 return ret;
1052 }
1053
qca8k_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)1054 static bool qca8k_lag_can_offload(struct dsa_switch *ds,
1055 struct dsa_lag lag,
1056 struct netdev_lag_upper_info *info,
1057 struct netlink_ext_ack *extack)
1058 {
1059 struct dsa_port *dp;
1060 int members = 0;
1061
1062 if (!lag.id)
1063 return false;
1064
1065 dsa_lag_foreach_port(dp, ds->dst, &lag)
1066 /* Includes the port joining the LAG */
1067 members++;
1068
1069 if (members > QCA8K_NUM_PORTS_FOR_LAG) {
1070 NL_SET_ERR_MSG_MOD(extack,
1071 "Cannot offload more than 4 LAG ports");
1072 return false;
1073 }
1074
1075 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1076 NL_SET_ERR_MSG_MOD(extack,
1077 "Can only offload LAG using hash TX type");
1078 return false;
1079 }
1080
1081 if (info->hash_type != NETDEV_LAG_HASH_L2 &&
1082 info->hash_type != NETDEV_LAG_HASH_L23) {
1083 NL_SET_ERR_MSG_MOD(extack,
1084 "Can only offload L2 or L2+L3 TX hash");
1085 return false;
1086 }
1087
1088 return true;
1089 }
1090
qca8k_lag_setup_hash(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info)1091 static int qca8k_lag_setup_hash(struct dsa_switch *ds,
1092 struct dsa_lag lag,
1093 struct netdev_lag_upper_info *info)
1094 {
1095 struct net_device *lag_dev = lag.dev;
1096 struct qca8k_priv *priv = ds->priv;
1097 bool unique_lag = true;
1098 unsigned int i;
1099 u32 hash = 0;
1100
1101 switch (info->hash_type) {
1102 case NETDEV_LAG_HASH_L23:
1103 hash |= QCA8K_TRUNK_HASH_SIP_EN;
1104 hash |= QCA8K_TRUNK_HASH_DIP_EN;
1105 fallthrough;
1106 case NETDEV_LAG_HASH_L2:
1107 hash |= QCA8K_TRUNK_HASH_SA_EN;
1108 hash |= QCA8K_TRUNK_HASH_DA_EN;
1109 break;
1110 default: /* We should NEVER reach this */
1111 return -EOPNOTSUPP;
1112 }
1113
1114 /* Check if we are the unique configured LAG */
1115 dsa_lags_foreach_id(i, ds->dst)
1116 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) {
1117 unique_lag = false;
1118 break;
1119 }
1120
1121 /* Hash Mode is global. Make sure the same Hash Mode
1122 * is set to all the 4 possible lag.
1123 * If we are the unique LAG we can set whatever hash
1124 * mode we want.
1125 * To change hash mode it's needed to remove all LAG
1126 * and change the mode with the latest.
1127 */
1128 if (unique_lag) {
1129 priv->lag_hash_mode = hash;
1130 } else if (priv->lag_hash_mode != hash) {
1131 netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is not supported\n");
1132 return -EOPNOTSUPP;
1133 }
1134
1135 return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
1136 QCA8K_TRUNK_HASH_MASK, hash);
1137 }
1138
qca8k_lag_refresh_portmap(struct dsa_switch * ds,int port,struct dsa_lag lag,bool delete)1139 static int qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
1140 struct dsa_lag lag, bool delete)
1141 {
1142 struct qca8k_priv *priv = ds->priv;
1143 int ret, id, i;
1144 u32 val;
1145
1146 /* DSA LAG IDs are one-based, hardware is zero-based */
1147 id = lag.id - 1;
1148
1149 /* Read current port member */
1150 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
1151 if (ret)
1152 return ret;
1153
1154 /* Shift val to the correct trunk */
1155 val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
1156 val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
1157 if (delete)
1158 val &= ~BIT(port);
1159 else
1160 val |= BIT(port);
1161
1162 /* Update port member. With empty portmap disable trunk */
1163 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
1164 QCA8K_REG_GOL_TRUNK_MEMBER(id) |
1165 QCA8K_REG_GOL_TRUNK_EN(id),
1166 !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
1167 val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
1168
1169 /* Search empty member if adding or port on deleting */
1170 for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
1171 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
1172 if (ret)
1173 return ret;
1174
1175 val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
1176 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
1177
1178 if (delete) {
1179 /* If port flagged to be disabled assume this member is
1180 * empty
1181 */
1182 if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
1183 continue;
1184
1185 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
1186 if (val != port)
1187 continue;
1188 } else {
1189 /* If port flagged to be enabled assume this member is
1190 * already set
1191 */
1192 if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
1193 continue;
1194 }
1195
1196 /* We have found the member to add/remove */
1197 break;
1198 }
1199
1200 /* Set port in the correct port mask or disable port if in delete mode */
1201 return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
1202 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
1203 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
1204 !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
1205 port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
1206 }
1207
qca8k_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)1208 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag,
1209 struct netdev_lag_upper_info *info,
1210 struct netlink_ext_ack *extack)
1211 {
1212 int ret;
1213
1214 if (!qca8k_lag_can_offload(ds, lag, info, extack))
1215 return -EOPNOTSUPP;
1216
1217 ret = qca8k_lag_setup_hash(ds, lag, info);
1218 if (ret)
1219 return ret;
1220
1221 return qca8k_lag_refresh_portmap(ds, port, lag, false);
1222 }
1223
qca8k_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)1224 int qca8k_port_lag_leave(struct dsa_switch *ds, int port,
1225 struct dsa_lag lag)
1226 {
1227 return qca8k_lag_refresh_portmap(ds, port, lag, true);
1228 }
1229
qca8k_read_switch_id(struct qca8k_priv * priv)1230 int qca8k_read_switch_id(struct qca8k_priv *priv)
1231 {
1232 u32 val;
1233 u8 id;
1234 int ret;
1235
1236 if (!priv->info)
1237 return -ENODEV;
1238
1239 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
1240 if (ret < 0)
1241 return -ENODEV;
1242
1243 id = QCA8K_MASK_CTRL_DEVICE_ID(val);
1244 if (id != priv->info->id) {
1245 dev_err(priv->dev,
1246 "Switch id detected %x but expected %x",
1247 id, priv->info->id);
1248 return -ENODEV;
1249 }
1250
1251 priv->switch_id = id;
1252
1253 /* Save revision to communicate to the internal PHY driver */
1254 priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
1255
1256 return 0;
1257 }
1258