1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6185 family SERDES PCS support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2017 Andrew Lunn <[email protected]>
8 */
9 #include <linux/phylink.h>
10
11 #include "global2.h"
12 #include "port.h"
13 #include "serdes.h"
14
15 struct mv88e6185_pcs {
16 struct phylink_pcs phylink_pcs;
17 unsigned int irq;
18 char name[64];
19
20 struct mv88e6xxx_chip *chip;
21 int port;
22 };
23
pcs_to_mv88e6185_pcs(struct phylink_pcs * pcs)24 static struct mv88e6185_pcs *pcs_to_mv88e6185_pcs(struct phylink_pcs *pcs)
25 {
26 return container_of(pcs, struct mv88e6185_pcs, phylink_pcs);
27 }
28
mv88e6185_pcs_handle_irq(int irq,void * dev_id)29 static irqreturn_t mv88e6185_pcs_handle_irq(int irq, void *dev_id)
30 {
31 struct mv88e6185_pcs *mpcs = dev_id;
32 struct mv88e6xxx_chip *chip;
33 irqreturn_t ret = IRQ_NONE;
34 bool link_up;
35 u16 status;
36 int port;
37 int err;
38
39 chip = mpcs->chip;
40 port = mpcs->port;
41
42 mv88e6xxx_reg_lock(chip);
43 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
44 mv88e6xxx_reg_unlock(chip);
45
46 if (!err) {
47 link_up = !!(status & MV88E6XXX_PORT_STS_LINK);
48
49 phylink_pcs_change(&mpcs->phylink_pcs, link_up);
50
51 ret = IRQ_HANDLED;
52 }
53
54 return ret;
55 }
56
mv88e6185_pcs_get_state(struct phylink_pcs * pcs,unsigned int neg_mode,struct phylink_link_state * state)57 static void mv88e6185_pcs_get_state(struct phylink_pcs *pcs,
58 unsigned int neg_mode,
59 struct phylink_link_state *state)
60 {
61 struct mv88e6185_pcs *mpcs = pcs_to_mv88e6185_pcs(pcs);
62 struct mv88e6xxx_chip *chip = mpcs->chip;
63 int port = mpcs->port;
64 u16 status;
65 int err;
66
67 mv88e6xxx_reg_lock(chip);
68 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
69 mv88e6xxx_reg_unlock(chip);
70
71 if (err)
72 status = 0;
73
74 state->link = !!(status & MV88E6XXX_PORT_STS_LINK);
75 if (state->link) {
76 state->duplex = status & MV88E6XXX_PORT_STS_DUPLEX ?
77 DUPLEX_FULL : DUPLEX_HALF;
78
79 switch (status & MV88E6XXX_PORT_STS_SPEED_MASK) {
80 case MV88E6XXX_PORT_STS_SPEED_1000:
81 state->speed = SPEED_1000;
82 break;
83
84 case MV88E6XXX_PORT_STS_SPEED_100:
85 state->speed = SPEED_100;
86 break;
87
88 case MV88E6XXX_PORT_STS_SPEED_10:
89 state->speed = SPEED_10;
90 break;
91
92 default:
93 state->link = false;
94 break;
95 }
96 }
97 }
98
mv88e6185_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)99 static int mv88e6185_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
100 phy_interface_t interface,
101 const unsigned long *advertising,
102 bool permit_pause_to_mac)
103 {
104 return 0;
105 }
106
mv88e6185_pcs_an_restart(struct phylink_pcs * pcs)107 static void mv88e6185_pcs_an_restart(struct phylink_pcs *pcs)
108 {
109 }
110
111 static const struct phylink_pcs_ops mv88e6185_phylink_pcs_ops = {
112 .pcs_get_state = mv88e6185_pcs_get_state,
113 .pcs_config = mv88e6185_pcs_config,
114 .pcs_an_restart = mv88e6185_pcs_an_restart,
115 };
116
mv88e6185_pcs_init(struct mv88e6xxx_chip * chip,int port)117 static int mv88e6185_pcs_init(struct mv88e6xxx_chip *chip, int port)
118 {
119 struct mv88e6185_pcs *mpcs;
120 struct device *dev;
121 unsigned int irq;
122 int err;
123
124 /* There are no configurable serdes lanes on this switch chip, so
125 * we use the static cmode configuration to determine whether we
126 * have a PCS or not.
127 */
128 if (chip->ports[port].cmode != MV88E6185_PORT_STS_CMODE_SERDES &&
129 chip->ports[port].cmode != MV88E6185_PORT_STS_CMODE_1000BASE_X)
130 return 0;
131
132 dev = chip->dev;
133
134 mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
135 if (!mpcs)
136 return -ENOMEM;
137
138 mpcs->chip = chip;
139 mpcs->port = port;
140 mpcs->phylink_pcs.ops = &mv88e6185_phylink_pcs_ops;
141 mpcs->phylink_pcs.neg_mode = true;
142
143 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
144 if (irq) {
145 snprintf(mpcs->name, sizeof(mpcs->name),
146 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);
147
148 err = request_threaded_irq(irq, NULL, mv88e6185_pcs_handle_irq,
149 IRQF_ONESHOT, mpcs->name, mpcs);
150 if (err) {
151 kfree(mpcs);
152 return err;
153 }
154
155 mpcs->irq = irq;
156 } else {
157 mpcs->phylink_pcs.poll = true;
158 }
159
160 chip->ports[port].pcs_private = &mpcs->phylink_pcs;
161
162 return 0;
163 }
164
mv88e6185_pcs_teardown(struct mv88e6xxx_chip * chip,int port)165 static void mv88e6185_pcs_teardown(struct mv88e6xxx_chip *chip, int port)
166 {
167 struct mv88e6185_pcs *mpcs;
168
169 mpcs = chip->ports[port].pcs_private;
170 if (!mpcs)
171 return;
172
173 if (mpcs->irq)
174 free_irq(mpcs->irq, mpcs);
175
176 kfree(mpcs);
177
178 chip->ports[port].pcs_private = NULL;
179 }
180
mv88e6185_pcs_select(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)181 static struct phylink_pcs *mv88e6185_pcs_select(struct mv88e6xxx_chip *chip,
182 int port,
183 phy_interface_t interface)
184 {
185 return chip->ports[port].pcs_private;
186 }
187
188 const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops = {
189 .pcs_init = mv88e6185_pcs_init,
190 .pcs_teardown = mv88e6185_pcs_teardown,
191 .pcs_select = mv88e6185_pcs_select,
192 };
193