1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <[email protected]>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <[email protected]>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/property.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phylink.h>
34 #include <net/dsa.h>
35
36 #include "chip.h"
37 #include "devlink.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "hwtstamp.h"
41 #include "phy.h"
42 #include "port.h"
43 #include "ptp.h"
44 #include "serdes.h"
45 #include "smi.h"
46
assert_reg_lock(struct mv88e6xxx_chip * chip)47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48 {
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
51 dump_stack();
52 }
53 }
54
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
56 {
57 int err;
58
59 assert_reg_lock(chip);
60
61 err = mv88e6xxx_smi_read(chip, addr, reg, val);
62 if (err)
63 return err;
64
65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
66 addr, reg, *val);
67
68 return 0;
69 }
70
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
72 {
73 int err;
74
75 assert_reg_lock(chip);
76
77 err = mv88e6xxx_smi_write(chip, addr, reg, val);
78 if (err)
79 return err;
80
81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
82 addr, reg, val);
83
84 return 0;
85 }
86
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
88 u16 mask, u16 val)
89 {
90 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
91 u16 data;
92 int err;
93 int i;
94
95 /* There's no bus specific operation to wait for a mask. Even
96 * if the initial poll takes longer than 50ms, always do at
97 * least one more attempt.
98 */
99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
100 err = mv88e6xxx_read(chip, addr, reg, &data);
101 if (err)
102 return err;
103
104 if ((data & mask) == val)
105 return 0;
106
107 if (i < 2)
108 cpu_relax();
109 else
110 usleep_range(1000, 2000);
111 }
112
113 err = mv88e6xxx_read(chip, addr, reg, &data);
114 if (err)
115 return err;
116
117 if ((data & mask) == val)
118 return 0;
119
120 dev_err(chip->dev, "Timeout while waiting for switch\n");
121 return -ETIMEDOUT;
122 }
123
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
125 int bit, int val)
126 {
127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
128 val ? BIT(bit) : 0x0000);
129 }
130
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
132 {
133 struct mv88e6xxx_mdio_bus *mdio_bus;
134
135 mdio_bus = list_first_entry_or_null(&chip->mdios,
136 struct mv88e6xxx_mdio_bus, list);
137 if (!mdio_bus)
138 return NULL;
139
140 return mdio_bus->bus;
141 }
142
mv88e6xxx_g1_irq_mask(struct irq_data * d)143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
144 {
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 unsigned int n = d->hwirq;
147
148 chip->g1_irq.masked |= (1 << n);
149 }
150
mv88e6xxx_g1_irq_unmask(struct irq_data * d)151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
152 {
153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
154 unsigned int n = d->hwirq;
155
156 chip->g1_irq.masked &= ~(1 << n);
157 }
158
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
160 {
161 unsigned int nhandled = 0;
162 unsigned int sub_irq;
163 unsigned int n;
164 u16 reg;
165 u16 ctl1;
166 int err;
167
168 mv88e6xxx_reg_lock(chip);
169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
170 mv88e6xxx_reg_unlock(chip);
171
172 if (err)
173 goto out;
174
175 do {
176 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
177 if (reg & (1 << n)) {
178 sub_irq = irq_find_mapping(chip->g1_irq.domain,
179 n);
180 handle_nested_irq(sub_irq);
181 ++nhandled;
182 }
183 }
184
185 mv88e6xxx_reg_lock(chip);
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
187 if (err)
188 goto unlock;
189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
190 unlock:
191 mv88e6xxx_reg_unlock(chip);
192 if (err)
193 goto out;
194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
195 } while (reg & ctl1);
196
197 out:
198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
199 }
200
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
202 {
203 struct mv88e6xxx_chip *chip = dev_id;
204
205 return mv88e6xxx_g1_irq_thread_work(chip);
206 }
207
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
209 {
210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
211
212 mv88e6xxx_reg_lock(chip);
213 }
214
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
216 {
217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
219 u16 reg;
220 int err;
221
222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
223 if (err)
224 goto out;
225
226 reg &= ~mask;
227 reg |= (~chip->g1_irq.masked & mask);
228
229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
230 if (err)
231 goto out;
232
233 out:
234 mv88e6xxx_reg_unlock(chip);
235 }
236
237 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
238 .name = "mv88e6xxx-g1",
239 .irq_mask = mv88e6xxx_g1_irq_mask,
240 .irq_unmask = mv88e6xxx_g1_irq_unmask,
241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
243 };
244
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
246 unsigned int irq,
247 irq_hw_number_t hwirq)
248 {
249 struct mv88e6xxx_chip *chip = d->host_data;
250
251 irq_set_chip_data(irq, d->host_data);
252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
253 irq_set_noprobe(irq);
254
255 return 0;
256 }
257
258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
259 .map = mv88e6xxx_g1_irq_domain_map,
260 .xlate = irq_domain_xlate_twocell,
261 };
262
263 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
265 {
266 int irq, virq;
267 u16 mask;
268
269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
272
273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
274 virq = irq_find_mapping(chip->g1_irq.domain, irq);
275 irq_dispose_mapping(virq);
276 }
277
278 irq_domain_remove(chip->g1_irq.domain);
279 }
280
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
282 {
283 /*
284 * free_irq must be called without reg_lock taken because the irq
285 * handler takes this lock, too.
286 */
287 free_irq(chip->irq, chip);
288
289 mv88e6xxx_reg_lock(chip);
290 mv88e6xxx_g1_irq_free_common(chip);
291 mv88e6xxx_reg_unlock(chip);
292 }
293
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
295 {
296 int err, irq, virq;
297 u16 reg, mask;
298
299 chip->g1_irq.nirqs = chip->info->g1_irqs;
300 chip->g1_irq.domain = irq_domain_add_simple(
301 NULL, chip->g1_irq.nirqs, 0,
302 &mv88e6xxx_g1_irq_domain_ops, chip);
303 if (!chip->g1_irq.domain)
304 return -ENOMEM;
305
306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
307 irq_create_mapping(chip->g1_irq.domain, irq);
308
309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
310 chip->g1_irq.masked = ~0;
311
312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
313 if (err)
314 goto out_mapping;
315
316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
317
318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
319 if (err)
320 goto out_disable;
321
322 /* Reading the interrupt status clears (most of) them */
323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
324 if (err)
325 goto out_disable;
326
327 return 0;
328
329 out_disable:
330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
332
333 out_mapping:
334 for (irq = 0; irq < 16; irq++) {
335 virq = irq_find_mapping(chip->g1_irq.domain, irq);
336 irq_dispose_mapping(virq);
337 }
338
339 irq_domain_remove(chip->g1_irq.domain);
340
341 return err;
342 }
343
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
345 {
346 static struct lock_class_key lock_key;
347 static struct lock_class_key request_key;
348 int err;
349
350 err = mv88e6xxx_g1_irq_setup_common(chip);
351 if (err)
352 return err;
353
354 /* These lock classes tells lockdep that global 1 irqs are in
355 * a different category than their parent GPIO, so it won't
356 * report false recursion.
357 */
358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
359
360 snprintf(chip->irq_name, sizeof(chip->irq_name),
361 "mv88e6xxx-%s", dev_name(chip->dev));
362
363 mv88e6xxx_reg_unlock(chip);
364 err = request_threaded_irq(chip->irq, NULL,
365 mv88e6xxx_g1_irq_thread_fn,
366 IRQF_ONESHOT | IRQF_SHARED,
367 chip->irq_name, chip);
368 mv88e6xxx_reg_lock(chip);
369 if (err)
370 mv88e6xxx_g1_irq_free_common(chip);
371
372 return err;
373 }
374
mv88e6xxx_irq_poll(struct kthread_work * work)375 static void mv88e6xxx_irq_poll(struct kthread_work *work)
376 {
377 struct mv88e6xxx_chip *chip = container_of(work,
378 struct mv88e6xxx_chip,
379 irq_poll_work.work);
380 mv88e6xxx_g1_irq_thread_work(chip);
381
382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
383 msecs_to_jiffies(100));
384 }
385
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
387 {
388 int err;
389
390 err = mv88e6xxx_g1_irq_setup_common(chip);
391 if (err)
392 return err;
393
394 kthread_init_delayed_work(&chip->irq_poll_work,
395 mv88e6xxx_irq_poll);
396
397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev));
398 if (IS_ERR(chip->kworker))
399 return PTR_ERR(chip->kworker);
400
401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
402 msecs_to_jiffies(100));
403
404 return 0;
405 }
406
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
408 {
409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
410 kthread_destroy_worker(chip->kworker);
411
412 mv88e6xxx_reg_lock(chip);
413 mv88e6xxx_g1_irq_free_common(chip);
414 mv88e6xxx_reg_unlock(chip);
415 }
416
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
418 int port, phy_interface_t interface)
419 {
420 int err;
421
422 if (chip->info->ops->port_set_rgmii_delay) {
423 err = chip->info->ops->port_set_rgmii_delay(chip, port,
424 interface);
425 if (err && err != -EOPNOTSUPP)
426 return err;
427 }
428
429 if (chip->info->ops->port_set_cmode) {
430 err = chip->info->ops->port_set_cmode(chip, port,
431 interface);
432 if (err && err != -EOPNOTSUPP)
433 return err;
434 }
435
436 return 0;
437 }
438
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
440 int link, int speed, int duplex, int pause,
441 phy_interface_t mode)
442 {
443 int err;
444
445 if (!chip->info->ops->port_set_link)
446 return 0;
447
448 /* Port's MAC control must not be changed unless the link is down */
449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
450 if (err)
451 return err;
452
453 if (chip->info->ops->port_set_speed_duplex) {
454 err = chip->info->ops->port_set_speed_duplex(chip, port,
455 speed, duplex);
456 if (err && err != -EOPNOTSUPP)
457 goto restore_link;
458 }
459
460 if (chip->info->ops->port_set_pause) {
461 err = chip->info->ops->port_set_pause(chip, port, pause);
462 if (err)
463 goto restore_link;
464 }
465
466 err = mv88e6xxx_port_config_interface(chip, port, mode);
467 restore_link:
468 if (chip->info->ops->port_set_link(chip, port, link))
469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
470
471 return err;
472 }
473
mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip * chip,int port)474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
475 {
476 return port >= chip->info->internal_phys_offset &&
477 port < chip->info->num_internal_phys +
478 chip->info->internal_phys_offset;
479 }
480
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
482 {
483 u16 reg;
484 int err;
485
486 /* The 88e6250 family does not have the PHY detect bit. Instead,
487 * report whether the port is internal.
488 */
489 if (chip->info->family == MV88E6XXX_FAMILY_6250)
490 return mv88e6xxx_phy_is_internal(chip, port);
491
492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
493 if (err) {
494 dev_err(chip->dev,
495 "p%d: %s: failed to read port status\n",
496 port, __func__);
497 return err;
498 }
499
500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
501 }
502
503 static const u8 mv88e6185_phy_interface_modes[] = {
504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
511 };
512
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
514 struct phylink_config *config)
515 {
516 u8 cmode = chip->ports[port].cmode;
517
518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
519
520 if (mv88e6xxx_phy_is_internal(chip, port)) {
521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
522 } else {
523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
524 mv88e6185_phy_interface_modes[cmode])
525 __set_bit(mv88e6185_phy_interface_modes[cmode],
526 config->supported_interfaces);
527
528 config->mac_capabilities |= MAC_1000FD;
529 }
530 }
531
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
533 struct phylink_config *config)
534 {
535 u8 cmode = chip->ports[port].cmode;
536
537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
538 mv88e6185_phy_interface_modes[cmode])
539 __set_bit(mv88e6185_phy_interface_modes[cmode],
540 config->supported_interfaces);
541
542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
543 MAC_1000FD;
544 }
545
546 static const u8 mv88e6xxx_phy_interface_modes[] = {
547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
555 /* higher interface modes are not needed here, since ports supporting
556 * them are writable, and so the supported interfaces are filled in the
557 * corresponding .phylink_set_interfaces() implementation below
558 */
559 };
560
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
562 {
563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
564 mv88e6xxx_phy_interface_modes[cmode])
565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
567 phy_interface_set_rgmii(supported);
568 }
569
570 static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
572 struct phylink_config *config)
573 {
574 unsigned long *supported = config->supported_interfaces;
575 int err;
576 u16 reg;
577
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
579 if (err) {
580 dev_err(chip->dev, "p%d: failed to read port status\n", port);
581 return;
582 }
583
584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
590 break;
591
592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
594 __set_bit(PHY_INTERFACE_MODE_MII, supported);
595 break;
596
597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
602 break;
603
604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
606 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
607 break;
608
609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
611 break;
612
613 default:
614 dev_err(chip->dev,
615 "p%d: invalid port mode in status register: %04x\n",
616 port, reg);
617 }
618 }
619
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
621 struct phylink_config *config)
622 {
623 if (!mv88e6xxx_phy_is_internal(chip, port))
624 mv88e6250_setup_supported_interfaces(chip, port, config);
625
626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
627 }
628
mv88e6351_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
630 struct phylink_config *config)
631 {
632 unsigned long *supported = config->supported_interfaces;
633
634 /* Translate the default cmode */
635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
636
637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
638 MAC_1000FD;
639 }
640
mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip * chip,int port)641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
642 {
643 u16 reg, val;
644 int err;
645
646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
647 if (err)
648 return err;
649
650 /* If PHY_DETECT is zero, then we are not in auto-media mode */
651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
652 return 0xf;
653
654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
656 if (err)
657 return err;
658
659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
660 if (err)
661 return err;
662
663 /* Restore PHY_DETECT value */
664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
665 if (err)
666 return err;
667
668 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
669 }
670
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
672 struct phylink_config *config)
673 {
674 unsigned long *supported = config->supported_interfaces;
675 int err, cmode;
676
677 /* Translate the default cmode */
678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
679
680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
681 MAC_1000FD;
682
683 /* Port 4 supports automedia if the serdes is associated with it. */
684 if (port == 4) {
685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
686 if (err < 0)
687 dev_err(chip->dev, "p%d: failed to read scratch\n",
688 port);
689 if (err <= 0)
690 return;
691
692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
693 if (cmode < 0)
694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
695 port);
696 else
697 mv88e6xxx_translate_cmode(cmode, supported);
698 }
699 }
700
mv88e632x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
702 struct phylink_config *config)
703 {
704 unsigned long *supported = config->supported_interfaces;
705 int cmode;
706
707 /* Translate the default cmode */
708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
709
710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
711 MAC_1000FD;
712
713 /* Port 0/1 are serdes only ports */
714 if (port == 0 || port == 1) {
715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
716 if (cmode < 0)
717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
718 port);
719 else
720 mv88e6xxx_translate_cmode(cmode, supported);
721 }
722 }
723
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
725 struct phylink_config *config)
726 {
727 unsigned long *supported = config->supported_interfaces;
728
729 /* Translate the default cmode */
730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
731
732 /* No ethtool bits for 200Mbps */
733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
734 MAC_1000FD;
735
736 /* The C_Mode field is programmable on port 5 */
737 if (port == 5) {
738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
741
742 config->mac_capabilities |= MAC_2500FD;
743 }
744 }
745
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
747 struct phylink_config *config)
748 {
749 unsigned long *supported = config->supported_interfaces;
750
751 /* Translate the default cmode */
752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
753
754 /* No ethtool bits for 200Mbps */
755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
756 MAC_1000FD;
757
758 /* The C_Mode field is programmable on ports 9 and 10 */
759 if (port == 9 || port == 10) {
760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
763
764 config->mac_capabilities |= MAC_2500FD;
765 }
766 }
767
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
769 struct phylink_config *config)
770 {
771 unsigned long *supported = config->supported_interfaces;
772
773 mv88e6390_phylink_get_caps(chip, port, config);
774
775 /* For the 6x90X, ports 2-7 can be in automedia mode.
776 * (Note that 6x90 doesn't support RXAUI nor XAUI).
777 *
778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
779 * configured for 1000BASE-X, SGMII or 2500BASE-X.
780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
782 *
783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
784 * configured for 1000BASE-X, SGMII or 2500BASE-X.
785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
787 *
788 * For now, be permissive (as the old code was) and allow 1000BASE-X
789 * on ports 2..7.
790 */
791 if (port >= 2 && port <= 7)
792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
793
794 /* The C_Mode field can also be programmed for 10G speeds */
795 if (port == 9 || port == 10) {
796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
798
799 config->mac_capabilities |= MAC_10000FD;
800 }
801 }
802
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
804 struct phylink_config *config)
805 {
806 unsigned long *supported = config->supported_interfaces;
807 bool is_6191x =
808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
809 bool is_6361 =
810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
811
812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
813
814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
815 MAC_1000FD;
816
817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
818 if (port == 0 || port == 9 || port == 10) {
819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
821
822 /* 6191X supports >1G modes only on port 10 */
823 if (!is_6191x || port == 10) {
824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
825 config->mac_capabilities |= MAC_2500FD;
826
827 /* 6361 only supports up to 2500BaseX */
828 if (!is_6361) {
829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
832 config->mac_capabilities |= MAC_5000FD |
833 MAC_10000FD;
834 }
835 }
836 }
837
838 if (port == 0) {
839 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
844 }
845 }
846
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
848 struct phylink_config *config)
849 {
850 struct mv88e6xxx_chip *chip = ds->priv;
851
852 mv88e6xxx_reg_lock(chip);
853 chip->info->ops->phylink_get_caps(chip, port, config);
854 mv88e6xxx_reg_unlock(chip);
855
856 if (mv88e6xxx_phy_is_internal(chip, port)) {
857 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
858 config->supported_interfaces);
859 /* Internal ports with no phy-mode need GMII for PHYLIB */
860 __set_bit(PHY_INTERFACE_MODE_GMII,
861 config->supported_interfaces);
862 }
863 }
864
865 static struct phylink_pcs *
mv88e6xxx_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)866 mv88e6xxx_mac_select_pcs(struct phylink_config *config,
867 phy_interface_t interface)
868 {
869 struct dsa_port *dp = dsa_phylink_to_port(config);
870 struct mv88e6xxx_chip *chip = dp->ds->priv;
871 struct phylink_pcs *pcs = NULL;
872
873 if (chip->info->ops->pcs_ops)
874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
875 interface);
876
877 return pcs;
878 }
879
mv88e6xxx_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)880 static int mv88e6xxx_mac_prepare(struct phylink_config *config,
881 unsigned int mode, phy_interface_t interface)
882 {
883 struct dsa_port *dp = dsa_phylink_to_port(config);
884 struct mv88e6xxx_chip *chip = dp->ds->priv;
885 int port = dp->index;
886 int err = 0;
887
888 /* In inband mode, the link may come up at any time while the link
889 * is not forced down. Force the link down while we reconfigure the
890 * interface mode.
891 */
892 if (mode == MLO_AN_INBAND &&
893 chip->ports[port].interface != interface &&
894 chip->info->ops->port_set_link) {
895 mv88e6xxx_reg_lock(chip);
896 err = chip->info->ops->port_set_link(chip, port,
897 LINK_FORCED_DOWN);
898 mv88e6xxx_reg_unlock(chip);
899 }
900
901 return err;
902 }
903
mv88e6xxx_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)904 static void mv88e6xxx_mac_config(struct phylink_config *config,
905 unsigned int mode,
906 const struct phylink_link_state *state)
907 {
908 struct dsa_port *dp = dsa_phylink_to_port(config);
909 struct mv88e6xxx_chip *chip = dp->ds->priv;
910 int port = dp->index;
911 int err = 0;
912
913 mv88e6xxx_reg_lock(chip);
914
915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
916 err = mv88e6xxx_port_config_interface(chip, port,
917 state->interface);
918 if (err && err != -EOPNOTSUPP)
919 goto err_unlock;
920 }
921
922 err_unlock:
923 mv88e6xxx_reg_unlock(chip);
924
925 if (err && err != -EOPNOTSUPP)
926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
927 }
928
mv88e6xxx_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)929 static int mv88e6xxx_mac_finish(struct phylink_config *config,
930 unsigned int mode, phy_interface_t interface)
931 {
932 struct dsa_port *dp = dsa_phylink_to_port(config);
933 struct mv88e6xxx_chip *chip = dp->ds->priv;
934 int port = dp->index;
935 int err = 0;
936
937 /* Undo the forced down state above after completing configuration
938 * irrespective of its state on entry, which allows the link to come
939 * up in the in-band case where there is no separate SERDES. Also
940 * ensure that the link can come up if the PPU is in use and we are
941 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
942 */
943 mv88e6xxx_reg_lock(chip);
944
945 if (chip->info->ops->port_set_link &&
946 ((mode == MLO_AN_INBAND &&
947 chip->ports[port].interface != interface) ||
948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
950
951 mv88e6xxx_reg_unlock(chip);
952
953 chip->ports[port].interface = interface;
954
955 return err;
956 }
957
mv88e6xxx_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)958 static void mv88e6xxx_mac_link_down(struct phylink_config *config,
959 unsigned int mode,
960 phy_interface_t interface)
961 {
962 struct dsa_port *dp = dsa_phylink_to_port(config);
963 struct mv88e6xxx_chip *chip = dp->ds->priv;
964 const struct mv88e6xxx_ops *ops;
965 int port = dp->index;
966 int err = 0;
967
968 ops = chip->info->ops;
969
970 mv88e6xxx_reg_lock(chip);
971 /* Force the link down if we know the port may not be automatically
972 * updated by the switch or if we are using fixed-link mode.
973 */
974 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
975 mode == MLO_AN_FIXED) && ops->port_sync_link)
976 err = ops->port_sync_link(chip, port, mode, false);
977
978 if (!err && ops->port_set_speed_duplex)
979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
980 DUPLEX_UNFORCED);
981 mv88e6xxx_reg_unlock(chip);
982
983 if (err)
984 dev_err(chip->dev,
985 "p%d: failed to force MAC link down\n", port);
986 }
987
mv88e6xxx_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)988 static void mv88e6xxx_mac_link_up(struct phylink_config *config,
989 struct phy_device *phydev,
990 unsigned int mode, phy_interface_t interface,
991 int speed, int duplex,
992 bool tx_pause, bool rx_pause)
993 {
994 struct dsa_port *dp = dsa_phylink_to_port(config);
995 struct mv88e6xxx_chip *chip = dp->ds->priv;
996 const struct mv88e6xxx_ops *ops;
997 int port = dp->index;
998 int err = 0;
999
1000 ops = chip->info->ops;
1001
1002 mv88e6xxx_reg_lock(chip);
1003 /* Configure and force the link up if we know that the port may not
1004 * automatically updated by the switch or if we are using fixed-link
1005 * mode.
1006 */
1007 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1008 mode == MLO_AN_FIXED) {
1009 if (ops->port_set_speed_duplex) {
1010 err = ops->port_set_speed_duplex(chip, port,
1011 speed, duplex);
1012 if (err && err != -EOPNOTSUPP)
1013 goto error;
1014 }
1015
1016 if (ops->port_sync_link)
1017 err = ops->port_sync_link(chip, port, mode, true);
1018 }
1019 error:
1020 mv88e6xxx_reg_unlock(chip);
1021
1022 if (err && err != -EOPNOTSUPP)
1023 dev_err(chip->dev,
1024 "p%d: failed to configure MAC link up\n", port);
1025 }
1026
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1028 {
1029 int err;
1030
1031 if (!chip->info->ops->stats_snapshot)
1032 return -EOPNOTSUPP;
1033
1034 mv88e6xxx_reg_lock(chip);
1035 err = chip->info->ops->stats_snapshot(chip, port);
1036 mv88e6xxx_reg_unlock(chip);
1037
1038 return err;
1039 }
1040
1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \
1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1101 /* */
1102
1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1104 { #_string, _size, _reg, _type }
1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1107 };
1108
1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1110 MV88E6XXX_HW_STAT_ID_ ## _string
1111 enum mv88e6xxx_hw_stat_id {
1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1113 };
1114
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1116 const struct mv88e6xxx_hw_stat *s,
1117 int port, u16 bank1_select,
1118 u16 histogram)
1119 {
1120 u32 low;
1121 u32 high = 0;
1122 u16 reg = 0;
1123 int err;
1124 u64 value;
1125
1126 switch (s->type) {
1127 case STATS_TYPE_PORT:
1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1129 if (err)
1130 return U64_MAX;
1131
1132 low = reg;
1133 if (s->size == 4) {
1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1135 if (err)
1136 return U64_MAX;
1137 low |= ((u32)reg) << 16;
1138 }
1139 break;
1140 case STATS_TYPE_BANK1:
1141 reg = bank1_select;
1142 fallthrough;
1143 case STATS_TYPE_BANK0:
1144 reg |= s->reg | histogram;
1145 mv88e6xxx_g1_stats_read(chip, reg, &low);
1146 if (s->size == 8)
1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1148 break;
1149 default:
1150 return U64_MAX;
1151 }
1152 value = (((u64)high) << 32) | low;
1153 return value;
1154 }
1155
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t ** data,int types)1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1157 uint8_t **data, int types)
1158 {
1159 const struct mv88e6xxx_hw_stat *stat;
1160 int i;
1161
1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1163 stat = &mv88e6xxx_hw_stats[i];
1164 if (stat->type & types)
1165 ethtool_puts(data, stat->string);
1166 }
1167 }
1168
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t ** data)1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1170 uint8_t **data)
1171 {
1172 mv88e6xxx_stats_get_strings(chip, data,
1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1174 }
1175
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t ** data)1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1177 uint8_t **data)
1178 {
1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1180 }
1181
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t ** data)1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1183 uint8_t **data)
1184 {
1185 mv88e6xxx_stats_get_strings(chip, data,
1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1187 }
1188
1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1190 "atu_member_violation",
1191 "atu_miss_violation",
1192 "atu_full_violation",
1193 "vtu_member_violation",
1194 "vtu_miss_violation",
1195 };
1196
mv88e6xxx_atu_vtu_get_strings(uint8_t ** data)1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data)
1198 {
1199 unsigned int i;
1200
1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]);
1203 }
1204
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1206 u32 stringset, uint8_t *data)
1207 {
1208 struct mv88e6xxx_chip *chip = ds->priv;
1209
1210 if (stringset != ETH_SS_STATS)
1211 return;
1212
1213 mv88e6xxx_reg_lock(chip);
1214
1215 if (chip->info->ops->stats_get_strings)
1216 chip->info->ops->stats_get_strings(chip, &data);
1217
1218 if (chip->info->ops->serdes_get_strings)
1219 chip->info->ops->serdes_get_strings(chip, port, &data);
1220
1221 mv88e6xxx_atu_vtu_get_strings(&data);
1222
1223 mv88e6xxx_reg_unlock(chip);
1224 }
1225
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1227 int types)
1228 {
1229 const struct mv88e6xxx_hw_stat *stat;
1230 int i, j;
1231
1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1233 stat = &mv88e6xxx_hw_stats[i];
1234 if (stat->type & types)
1235 j++;
1236 }
1237 return j;
1238 }
1239
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1241 {
1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1243 STATS_TYPE_PORT);
1244 }
1245
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1247 {
1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1249 }
1250
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1252 {
1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1254 STATS_TYPE_BANK1);
1255 }
1256
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1258 {
1259 struct mv88e6xxx_chip *chip = ds->priv;
1260 int serdes_count = 0;
1261 int count = 0;
1262
1263 if (sset != ETH_SS_STATS)
1264 return 0;
1265
1266 mv88e6xxx_reg_lock(chip);
1267 if (chip->info->ops->stats_get_sset_count)
1268 count = chip->info->ops->stats_get_sset_count(chip);
1269 if (count < 0)
1270 goto out;
1271
1272 if (chip->info->ops->serdes_get_sset_count)
1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1274 port);
1275 if (serdes_count < 0) {
1276 count = serdes_count;
1277 goto out;
1278 }
1279 count += serdes_count;
1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1281
1282 out:
1283 mv88e6xxx_reg_unlock(chip);
1284
1285 return count;
1286 }
1287
mv88e6095_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1289 const struct mv88e6xxx_hw_stat *stat,
1290 uint64_t *data)
1291 {
1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1293 MV88E6XXX_G1_STATS_OP_HIST_RX);
1294 return 1;
1295 }
1296
mv88e6250_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1298 const struct mv88e6xxx_hw_stat *stat,
1299 uint64_t *data)
1300 {
1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1302 MV88E6XXX_G1_STATS_OP_HIST_RX);
1303 return 1;
1304 }
1305
mv88e6320_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1307 const struct mv88e6xxx_hw_stat *stat,
1308 uint64_t *data)
1309 {
1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1312 MV88E6XXX_G1_STATS_OP_HIST_RX);
1313 return 1;
1314 }
1315
mv88e6390_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1317 const struct mv88e6xxx_hw_stat *stat,
1318 uint64_t *data)
1319 {
1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1322 0);
1323 return 1;
1324 }
1325
mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_hw_stat * stat,uint64_t * data)1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1327 const struct mv88e6xxx_hw_stat *stat,
1328 uint64_t *data)
1329 {
1330 int ret = 0;
1331
1332 if (!(stat->type & chip->info->stats_type))
1333 return 0;
1334
1335 if (chip->info->ops->stats_get_stat) {
1336 mv88e6xxx_reg_lock(chip);
1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1338 mv88e6xxx_reg_unlock(chip);
1339 }
1340
1341 return ret;
1342 }
1343
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1345 uint64_t *data)
1346 {
1347 const struct mv88e6xxx_hw_stat *stat;
1348 size_t i, j;
1349
1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1351 stat = &mv88e6xxx_hw_stats[i];
1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1353 }
1354 return j;
1355 }
1356
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1358 uint64_t *data)
1359 {
1360 *data++ = chip->ports[port].atu_member_violation;
1361 *data++ = chip->ports[port].atu_miss_violation;
1362 *data++ = chip->ports[port].atu_full_violation;
1363 *data++ = chip->ports[port].vtu_member_violation;
1364 *data++ = chip->ports[port].vtu_miss_violation;
1365 }
1366
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1368 uint64_t *data)
1369 {
1370 size_t count;
1371
1372 count = mv88e6xxx_stats_get_stats(chip, port, data);
1373
1374 mv88e6xxx_reg_lock(chip);
1375 if (chip->info->ops->serdes_get_stats) {
1376 data += count;
1377 count = chip->info->ops->serdes_get_stats(chip, port, data);
1378 }
1379 data += count;
1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1381 mv88e6xxx_reg_unlock(chip);
1382 }
1383
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1385 uint64_t *data)
1386 {
1387 struct mv88e6xxx_chip *chip = ds->priv;
1388 int ret;
1389
1390 ret = mv88e6xxx_stats_snapshot(chip, port);
1391 if (ret < 0)
1392 return;
1393
1394 mv88e6xxx_get_stats(chip, port, data);
1395 }
1396
mv88e6xxx_get_eth_mac_stats(struct dsa_switch * ds,int port,struct ethtool_eth_mac_stats * mac_stats)1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1398 struct ethtool_eth_mac_stats *mac_stats)
1399 {
1400 struct mv88e6xxx_chip *chip = ds->priv;
1401 int ret;
1402
1403 ret = mv88e6xxx_stats_snapshot(chip, port);
1404 if (ret < 0)
1405 return;
1406
1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1408 mv88e6xxx_stats_get_stat(chip, port, \
1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1410 &mac_stats->stats._member)
1411
1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1426
1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP
1428
1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1433 }
1434
mv88e6xxx_get_rmon_stats(struct dsa_switch * ds,int port,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1436 struct ethtool_rmon_stats *rmon_stats,
1437 const struct ethtool_rmon_hist_range **ranges)
1438 {
1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1440 { 64, 64 },
1441 { 65, 127 },
1442 { 128, 255 },
1443 { 256, 511 },
1444 { 512, 1023 },
1445 { 1024, 65535 },
1446 {}
1447 };
1448 struct mv88e6xxx_chip *chip = ds->priv;
1449 int ret;
1450
1451 ret = mv88e6xxx_stats_snapshot(chip, port);
1452 if (ret < 0)
1453 return;
1454
1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1456 mv88e6xxx_stats_get_stat(chip, port, \
1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1458 &rmon_stats->stats._member)
1459
1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1470
1471 #undef MV88E6XXX_RMON_STAT_MAP
1472
1473 *ranges = rmon_ranges;
1474 }
1475
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1477 {
1478 struct mv88e6xxx_chip *chip = ds->priv;
1479 int len;
1480
1481 len = 32 * sizeof(u16);
1482 if (chip->info->ops->serdes_get_regs_len)
1483 len += chip->info->ops->serdes_get_regs_len(chip, port);
1484
1485 return len;
1486 }
1487
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1489 struct ethtool_regs *regs, void *_p)
1490 {
1491 struct mv88e6xxx_chip *chip = ds->priv;
1492 int err;
1493 u16 reg;
1494 u16 *p = _p;
1495 int i;
1496
1497 regs->version = chip->info->prod_num;
1498
1499 memset(p, 0xff, 32 * sizeof(u16));
1500
1501 mv88e6xxx_reg_lock(chip);
1502
1503 for (i = 0; i < 32; i++) {
1504
1505 err = mv88e6xxx_port_read(chip, port, i, ®);
1506 if (!err)
1507 p[i] = reg;
1508 }
1509
1510 if (chip->info->ops->serdes_get_regs)
1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1512
1513 mv88e6xxx_reg_unlock(chip);
1514 }
1515
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)1516 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1517 struct ethtool_keee *e)
1518 {
1519 /* Nothing to do on the port's MAC */
1520 return 0;
1521 }
1522
1523 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1525 {
1526 struct dsa_switch *ds = chip->ds;
1527 struct dsa_switch_tree *dst = ds->dst;
1528 struct dsa_port *dp, *other_dp;
1529 bool found = false;
1530 u16 pvlan;
1531
1532 /* dev is a physical switch */
1533 if (dev <= dst->last_switch) {
1534 list_for_each_entry(dp, &dst->ports, list) {
1535 if (dp->ds->index == dev && dp->index == port) {
1536 /* dp might be a DSA link or a user port, so it
1537 * might or might not have a bridge.
1538 * Use the "found" variable for both cases.
1539 */
1540 found = true;
1541 break;
1542 }
1543 }
1544 /* dev is a virtual bridge */
1545 } else {
1546 list_for_each_entry(dp, &dst->ports, list) {
1547 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1548
1549 if (!bridge_num)
1550 continue;
1551
1552 if (bridge_num + dst->last_switch != dev)
1553 continue;
1554
1555 found = true;
1556 break;
1557 }
1558 }
1559
1560 /* Prevent frames from unknown switch or virtual bridge */
1561 if (!found)
1562 return 0;
1563
1564 /* Frames from DSA links and CPU ports can egress any local port */
1565 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1566 return mv88e6xxx_port_mask(chip);
1567
1568 pvlan = 0;
1569
1570 /* Frames from standalone user ports can only egress on the
1571 * upstream port.
1572 */
1573 if (!dsa_port_bridge_dev_get(dp))
1574 return BIT(dsa_switch_upstream_port(ds));
1575
1576 /* Frames from bridged user ports can egress any local DSA
1577 * links and CPU ports, as well as any local member of their
1578 * bridge group.
1579 */
1580 dsa_switch_for_each_port(other_dp, ds)
1581 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1582 other_dp->type == DSA_PORT_TYPE_DSA ||
1583 dsa_port_bridge_same(dp, other_dp))
1584 pvlan |= BIT(other_dp->index);
1585
1586 return pvlan;
1587 }
1588
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1590 {
1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1592
1593 /* prevent frames from going back out of the port they came in on */
1594 output_ports &= ~BIT(port);
1595
1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1597 }
1598
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1599 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1600 u8 state)
1601 {
1602 struct mv88e6xxx_chip *chip = ds->priv;
1603 int err;
1604
1605 mv88e6xxx_reg_lock(chip);
1606 err = mv88e6xxx_port_set_state(chip, port, state);
1607 mv88e6xxx_reg_unlock(chip);
1608
1609 if (err)
1610 dev_err(ds->dev, "p%d: failed to update state\n", port);
1611 }
1612
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1614 {
1615 int err;
1616
1617 if (chip->info->ops->ieee_pri_map) {
1618 err = chip->info->ops->ieee_pri_map(chip);
1619 if (err)
1620 return err;
1621 }
1622
1623 if (chip->info->ops->ip_pri_map) {
1624 err = chip->info->ops->ip_pri_map(chip);
1625 if (err)
1626 return err;
1627 }
1628
1629 return 0;
1630 }
1631
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1633 {
1634 struct dsa_switch *ds = chip->ds;
1635 int target, port;
1636 int err;
1637
1638 if (!chip->info->global2_addr)
1639 return 0;
1640
1641 /* Initialize the routing port to the 32 possible target devices */
1642 for (target = 0; target < 32; target++) {
1643 port = dsa_routing_port(ds, target);
1644 if (port == ds->num_ports)
1645 port = 0x1f;
1646
1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1648 if (err)
1649 return err;
1650 }
1651
1652 if (chip->info->ops->set_cascade_port) {
1653 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1654 err = chip->info->ops->set_cascade_port(chip, port);
1655 if (err)
1656 return err;
1657 }
1658
1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1660 if (err)
1661 return err;
1662
1663 return 0;
1664 }
1665
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1667 {
1668 /* Clear all trunk masks and mapping */
1669 if (chip->info->global2_addr)
1670 return mv88e6xxx_g2_trunk_clear(chip);
1671
1672 return 0;
1673 }
1674
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1676 {
1677 if (chip->info->ops->rmu_disable)
1678 return chip->info->ops->rmu_disable(chip);
1679
1680 return 0;
1681 }
1682
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1684 {
1685 if (chip->info->ops->pot_clear)
1686 return chip->info->ops->pot_clear(chip);
1687
1688 return 0;
1689 }
1690
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1692 {
1693 if (chip->info->ops->mgmt_rsvd2cpu)
1694 return chip->info->ops->mgmt_rsvd2cpu(chip);
1695
1696 return 0;
1697 }
1698
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1700 {
1701 int err;
1702
1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1704 if (err)
1705 return err;
1706
1707 /* The chips that have a "learn2all" bit in Global1, ATU
1708 * Control are precisely those whose port registers have a
1709 * Message Port bit in Port Control 1 and hence implement
1710 * ->port_setup_message_port.
1711 */
1712 if (chip->info->ops->port_setup_message_port) {
1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1714 if (err)
1715 return err;
1716 }
1717
1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1719 }
1720
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1722 {
1723 int port;
1724 int err;
1725
1726 if (!chip->info->ops->irl_init_all)
1727 return 0;
1728
1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1730 /* Disable ingress rate limiting by resetting all per port
1731 * ingress rate limit resources to their initial state.
1732 */
1733 err = chip->info->ops->irl_init_all(chip, port);
1734 if (err)
1735 return err;
1736 }
1737
1738 return 0;
1739 }
1740
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1742 {
1743 if (chip->info->ops->set_switch_mac) {
1744 u8 addr[ETH_ALEN];
1745
1746 eth_random_addr(addr);
1747
1748 return chip->info->ops->set_switch_mac(chip, addr);
1749 }
1750
1751 return 0;
1752 }
1753
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1755 {
1756 struct dsa_switch_tree *dst = chip->ds->dst;
1757 struct dsa_switch *ds;
1758 struct dsa_port *dp;
1759 u16 pvlan = 0;
1760
1761 if (!mv88e6xxx_has_pvt(chip))
1762 return 0;
1763
1764 /* Skip the local source device, which uses in-chip port VLAN */
1765 if (dev != chip->ds->index) {
1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1767
1768 ds = dsa_switch_find(dst->index, dev);
1769 dp = ds ? dsa_to_port(ds, port) : NULL;
1770 if (dp && dp->lag) {
1771 /* As the PVT is used to limit flooding of
1772 * FORWARD frames, which use the LAG ID as the
1773 * source port, we must translate dev/port to
1774 * the special "LAG device" in the PVT, using
1775 * the LAG ID (one-based) as the port number
1776 * (zero-based).
1777 */
1778 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1779 port = dsa_port_lag_id_get(dp) - 1;
1780 }
1781 }
1782
1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1784 }
1785
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1787 {
1788 int dev, port;
1789 int err;
1790
1791 if (!mv88e6xxx_has_pvt(chip))
1792 return 0;
1793
1794 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1795 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1796 */
1797 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1798 if (err)
1799 return err;
1800
1801 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1802 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1803 err = mv88e6xxx_pvt_map(chip, dev, port);
1804 if (err)
1805 return err;
1806 }
1807 }
1808
1809 return 0;
1810 }
1811
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1813 u16 fid)
1814 {
1815 if (dsa_to_port(chip->ds, port)->lag)
1816 /* Hardware is incapable of fast-aging a LAG through a
1817 * regular ATU move operation. Until we have something
1818 * more fancy in place this is a no-op.
1819 */
1820 return -EOPNOTSUPP;
1821
1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1823 }
1824
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1825 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1826 {
1827 struct mv88e6xxx_chip *chip = ds->priv;
1828 int err;
1829
1830 mv88e6xxx_reg_lock(chip);
1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1832 mv88e6xxx_reg_unlock(chip);
1833
1834 if (err)
1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1836 port, err);
1837 }
1838
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1840 {
1841 if (!mv88e6xxx_max_vid(chip))
1842 return 0;
1843
1844 return mv88e6xxx_g1_vtu_flush(chip);
1845 }
1846
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1848 struct mv88e6xxx_vtu_entry *entry)
1849 {
1850 int err;
1851
1852 if (!chip->info->ops->vtu_getnext)
1853 return -EOPNOTSUPP;
1854
1855 memset(entry, 0, sizeof(*entry));
1856
1857 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1858 entry->valid = false;
1859
1860 err = chip->info->ops->vtu_getnext(chip, entry);
1861
1862 if (entry->vid != vid)
1863 entry->valid = false;
1864
1865 return err;
1866 }
1867
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1868 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1869 int (*cb)(struct mv88e6xxx_chip *chip,
1870 const struct mv88e6xxx_vtu_entry *entry,
1871 void *priv),
1872 void *priv)
1873 {
1874 struct mv88e6xxx_vtu_entry entry = {
1875 .vid = mv88e6xxx_max_vid(chip),
1876 .valid = false,
1877 };
1878 int err;
1879
1880 if (!chip->info->ops->vtu_getnext)
1881 return -EOPNOTSUPP;
1882
1883 do {
1884 err = chip->info->ops->vtu_getnext(chip, &entry);
1885 if (err)
1886 return err;
1887
1888 if (!entry.valid)
1889 break;
1890
1891 err = cb(chip, &entry, priv);
1892 if (err)
1893 return err;
1894 } while (entry.vid < mv88e6xxx_max_vid(chip));
1895
1896 return 0;
1897 }
1898
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1899 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1900 struct mv88e6xxx_vtu_entry *entry)
1901 {
1902 if (!chip->info->ops->vtu_loadpurge)
1903 return -EOPNOTSUPP;
1904
1905 return chip->info->ops->vtu_loadpurge(chip, entry);
1906 }
1907
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1908 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1909 {
1910 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID);
1911 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1912 return -ENOSPC;
1913
1914 /* Clear the database */
1915 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1916 }
1917
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)1918 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1919 struct mv88e6xxx_stu_entry *entry)
1920 {
1921 if (!chip->info->ops->stu_loadpurge)
1922 return -EOPNOTSUPP;
1923
1924 return chip->info->ops->stu_loadpurge(chip, entry);
1925 }
1926
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)1927 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1928 {
1929 struct mv88e6xxx_stu_entry stu = {
1930 .valid = true,
1931 .sid = 0
1932 };
1933
1934 if (!mv88e6xxx_has_stu(chip))
1935 return 0;
1936
1937 /* Make sure that SID 0 is always valid. This is used by VTU
1938 * entries that do not make use of the STU, e.g. when creating
1939 * a VLAN upper on a port that is also part of a VLAN
1940 * filtering bridge.
1941 */
1942 return mv88e6xxx_stu_loadpurge(chip, &stu);
1943 }
1944
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1945 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1946 {
1947 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1948 struct mv88e6xxx_mst *mst;
1949
1950 __set_bit(0, busy);
1951
1952 list_for_each_entry(mst, &chip->msts, node)
1953 __set_bit(mst->stu.sid, busy);
1954
1955 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1956
1957 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1958 }
1959
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)1960 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1961 {
1962 struct mv88e6xxx_mst *mst, *tmp;
1963 int err;
1964
1965 /* If the SID is zero, it is for a VLAN mapped to the default MSTI,
1966 * and mv88e6xxx_stu_setup() made sure it is always present, and thus,
1967 * should not be removed here.
1968 *
1969 * If the chip lacks STU support, numerically the "sid" variable will
1970 * happen to also be zero, but we don't want to rely on that fact, so
1971 * we explicitly test that first. In that case, there is also nothing
1972 * to do here.
1973 */
1974 if (!mv88e6xxx_has_stu(chip) || !sid)
1975 return 0;
1976
1977 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1978 if (mst->stu.sid != sid)
1979 continue;
1980
1981 if (!refcount_dec_and_test(&mst->refcnt))
1982 return 0;
1983
1984 mst->stu.valid = false;
1985 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1986 if (err) {
1987 refcount_set(&mst->refcnt, 1);
1988 return err;
1989 }
1990
1991 list_del(&mst->node);
1992 kfree(mst);
1993 return 0;
1994 }
1995
1996 return -ENOENT;
1997 }
1998
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)1999 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2000 u16 msti, u8 *sid)
2001 {
2002 struct mv88e6xxx_mst *mst;
2003 int err, i;
2004
2005 if (!mv88e6xxx_has_stu(chip)) {
2006 err = -EOPNOTSUPP;
2007 goto err;
2008 }
2009
2010 if (!msti) {
2011 *sid = 0;
2012 return 0;
2013 }
2014
2015 list_for_each_entry(mst, &chip->msts, node) {
2016 if (mst->br == br && mst->msti == msti) {
2017 refcount_inc(&mst->refcnt);
2018 *sid = mst->stu.sid;
2019 return 0;
2020 }
2021 }
2022
2023 err = mv88e6xxx_sid_get(chip, sid);
2024 if (err)
2025 goto err;
2026
2027 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2028 if (!mst) {
2029 err = -ENOMEM;
2030 goto err;
2031 }
2032
2033 INIT_LIST_HEAD(&mst->node);
2034 refcount_set(&mst->refcnt, 1);
2035 mst->br = br;
2036 mst->msti = msti;
2037 mst->stu.valid = true;
2038 mst->stu.sid = *sid;
2039
2040 /* The bridge starts out all ports in the disabled state. But
2041 * a STU state of disabled means to go by the port-global
2042 * state. So we set all user port's initial state to blocking,
2043 * to match the bridge's behavior.
2044 */
2045 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2046 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2047 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2048 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2049
2050 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2051 if (err)
2052 goto err_free;
2053
2054 list_add_tail(&mst->node, &chip->msts);
2055 return 0;
2056
2057 err_free:
2058 kfree(mst);
2059 err:
2060 return err;
2061 }
2062
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)2063 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2064 const struct switchdev_mst_state *st)
2065 {
2066 struct dsa_port *dp = dsa_to_port(ds, port);
2067 struct mv88e6xxx_chip *chip = ds->priv;
2068 struct mv88e6xxx_mst *mst;
2069 u8 state;
2070 int err;
2071
2072 if (!mv88e6xxx_has_stu(chip))
2073 return -EOPNOTSUPP;
2074
2075 switch (st->state) {
2076 case BR_STATE_DISABLED:
2077 case BR_STATE_BLOCKING:
2078 case BR_STATE_LISTENING:
2079 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2080 break;
2081 case BR_STATE_LEARNING:
2082 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2083 break;
2084 case BR_STATE_FORWARDING:
2085 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2086 break;
2087 default:
2088 return -EINVAL;
2089 }
2090
2091 list_for_each_entry(mst, &chip->msts, node) {
2092 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2093 mst->msti == st->msti) {
2094 if (mst->stu.state[port] == state)
2095 return 0;
2096
2097 mst->stu.state[port] = state;
2098 mv88e6xxx_reg_lock(chip);
2099 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2100 mv88e6xxx_reg_unlock(chip);
2101 return err;
2102 }
2103 }
2104
2105 return -ENOENT;
2106 }
2107
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)2108 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2109 u16 vid)
2110 {
2111 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2112 struct mv88e6xxx_chip *chip = ds->priv;
2113 struct mv88e6xxx_vtu_entry vlan;
2114 int err;
2115
2116 /* DSA and CPU ports have to be members of multiple vlans */
2117 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2118 return 0;
2119
2120 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2121 if (err)
2122 return err;
2123
2124 if (!vlan.valid)
2125 return 0;
2126
2127 dsa_switch_for_each_user_port(other_dp, ds) {
2128 struct net_device *other_br;
2129
2130 if (vlan.member[other_dp->index] ==
2131 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2132 continue;
2133
2134 if (dsa_port_bridge_same(dp, other_dp))
2135 break; /* same bridge, check next VLAN */
2136
2137 other_br = dsa_port_bridge_dev_get(other_dp);
2138 if (!other_br)
2139 continue;
2140
2141 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2142 port, vlan.vid, other_dp->index, netdev_name(other_br));
2143 return -EOPNOTSUPP;
2144 }
2145
2146 return 0;
2147 }
2148
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)2149 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2150 {
2151 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2152 struct net_device *br = dsa_port_bridge_dev_get(dp);
2153 struct mv88e6xxx_port *p = &chip->ports[port];
2154 u16 pvid = MV88E6XXX_VID_STANDALONE;
2155 bool drop_untagged = false;
2156 int err;
2157
2158 if (br) {
2159 if (br_vlan_enabled(br)) {
2160 pvid = p->bridge_pvid.vid;
2161 drop_untagged = !p->bridge_pvid.valid;
2162 } else {
2163 pvid = MV88E6XXX_VID_BRIDGED;
2164 }
2165 }
2166
2167 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2168 if (err)
2169 return err;
2170
2171 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2172 }
2173
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2174 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2175 bool vlan_filtering,
2176 struct netlink_ext_ack *extack)
2177 {
2178 struct mv88e6xxx_chip *chip = ds->priv;
2179 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2180 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2181 int err;
2182
2183 if (!mv88e6xxx_max_vid(chip))
2184 return -EOPNOTSUPP;
2185
2186 mv88e6xxx_reg_lock(chip);
2187
2188 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2189 if (err)
2190 goto unlock;
2191
2192 err = mv88e6xxx_port_commit_pvid(chip, port);
2193 if (err)
2194 goto unlock;
2195
2196 unlock:
2197 mv88e6xxx_reg_unlock(chip);
2198
2199 return err;
2200 }
2201
2202 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2203 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2204 const struct switchdev_obj_port_vlan *vlan)
2205 {
2206 struct mv88e6xxx_chip *chip = ds->priv;
2207 int err;
2208
2209 if (!mv88e6xxx_max_vid(chip))
2210 return -EOPNOTSUPP;
2211
2212 /* If the requested port doesn't belong to the same bridge as the VLAN
2213 * members, do not support it (yet) and fallback to software VLAN.
2214 */
2215 mv88e6xxx_reg_lock(chip);
2216 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2217 mv88e6xxx_reg_unlock(chip);
2218
2219 return err;
2220 }
2221
mv88e6xxx_port_db_get(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid,u16 * fid,struct mv88e6xxx_atu_entry * entry)2222 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip,
2223 const unsigned char *addr, u16 vid,
2224 u16 *fid, struct mv88e6xxx_atu_entry *entry)
2225 {
2226 struct mv88e6xxx_vtu_entry vlan;
2227 int err;
2228
2229 /* Ports have two private address databases: one for when the port is
2230 * standalone and one for when the port is under a bridge and the
2231 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2232 * address database to remain 100% empty, so we never load an ATU entry
2233 * into a standalone port's database. Therefore, translate the null
2234 * VLAN ID into the port's database used for VLAN-unaware bridging.
2235 */
2236 if (vid == 0) {
2237 *fid = MV88E6XXX_FID_BRIDGED;
2238 } else {
2239 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2240 if (err)
2241 return err;
2242
2243 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2244 if (!vlan.valid)
2245 return -EOPNOTSUPP;
2246
2247 *fid = vlan.fid;
2248 }
2249
2250 entry->state = 0;
2251 ether_addr_copy(entry->mac, addr);
2252 eth_addr_dec(entry->mac);
2253
2254 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry);
2255 }
2256
mv88e6xxx_port_db_find(struct mv88e6xxx_chip * chip,const unsigned char * addr,u16 vid)2257 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip,
2258 const unsigned char *addr, u16 vid)
2259 {
2260 struct mv88e6xxx_atu_entry entry;
2261 u16 fid;
2262 int err;
2263
2264 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2265 if (err)
2266 return false;
2267
2268 return entry.state && ether_addr_equal(entry.mac, addr);
2269 }
2270
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2271 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2272 const unsigned char *addr, u16 vid,
2273 u8 state)
2274 {
2275 struct mv88e6xxx_atu_entry entry;
2276 u16 fid;
2277 int err;
2278
2279 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2280 if (err)
2281 return err;
2282
2283 /* Initialize a fresh ATU entry if it isn't found */
2284 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2285 memset(&entry, 0, sizeof(entry));
2286 ether_addr_copy(entry.mac, addr);
2287 }
2288
2289 /* Purge the ATU entry only if no port is using it anymore */
2290 if (!state) {
2291 entry.portvec &= ~BIT(port);
2292 if (!entry.portvec)
2293 entry.state = 0;
2294 } else {
2295 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2296 entry.portvec = BIT(port);
2297 else
2298 entry.portvec |= BIT(port);
2299
2300 entry.state = state;
2301 }
2302
2303 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2304 }
2305
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2306 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2307 const struct mv88e6xxx_policy *policy)
2308 {
2309 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2310 enum mv88e6xxx_policy_action action = policy->action;
2311 const u8 *addr = policy->addr;
2312 u16 vid = policy->vid;
2313 u8 state;
2314 int err;
2315 int id;
2316
2317 if (!chip->info->ops->port_set_policy)
2318 return -EOPNOTSUPP;
2319
2320 switch (mapping) {
2321 case MV88E6XXX_POLICY_MAPPING_DA:
2322 case MV88E6XXX_POLICY_MAPPING_SA:
2323 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2324 state = 0; /* Dissociate the port and address */
2325 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2326 is_multicast_ether_addr(addr))
2327 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2328 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2329 is_unicast_ether_addr(addr))
2330 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2331 else
2332 return -EOPNOTSUPP;
2333
2334 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2335 state);
2336 if (err)
2337 return err;
2338 break;
2339 default:
2340 return -EOPNOTSUPP;
2341 }
2342
2343 /* Skip the port's policy clearing if the mapping is still in use */
2344 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2345 idr_for_each_entry(&chip->policies, policy, id)
2346 if (policy->port == port &&
2347 policy->mapping == mapping &&
2348 policy->action != action)
2349 return 0;
2350
2351 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2352 }
2353
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2354 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2355 struct ethtool_rx_flow_spec *fs)
2356 {
2357 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2358 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2359 enum mv88e6xxx_policy_mapping mapping;
2360 enum mv88e6xxx_policy_action action;
2361 struct mv88e6xxx_policy *policy;
2362 u16 vid = 0;
2363 u8 *addr;
2364 int err;
2365 int id;
2366
2367 if (fs->location != RX_CLS_LOC_ANY)
2368 return -EINVAL;
2369
2370 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2371 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2372 else
2373 return -EOPNOTSUPP;
2374
2375 switch (fs->flow_type & ~FLOW_EXT) {
2376 case ETHER_FLOW:
2377 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2378 is_zero_ether_addr(mac_mask->h_source)) {
2379 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2380 addr = mac_entry->h_dest;
2381 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2382 !is_zero_ether_addr(mac_mask->h_source)) {
2383 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2384 addr = mac_entry->h_source;
2385 } else {
2386 /* Cannot support DA and SA mapping in the same rule */
2387 return -EOPNOTSUPP;
2388 }
2389 break;
2390 default:
2391 return -EOPNOTSUPP;
2392 }
2393
2394 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2395 if (fs->m_ext.vlan_tci != htons(0xffff))
2396 return -EOPNOTSUPP;
2397 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2398 }
2399
2400 idr_for_each_entry(&chip->policies, policy, id) {
2401 if (policy->port == port && policy->mapping == mapping &&
2402 policy->action == action && policy->vid == vid &&
2403 ether_addr_equal(policy->addr, addr))
2404 return -EEXIST;
2405 }
2406
2407 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2408 if (!policy)
2409 return -ENOMEM;
2410
2411 fs->location = 0;
2412 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2413 GFP_KERNEL);
2414 if (err) {
2415 devm_kfree(chip->dev, policy);
2416 return err;
2417 }
2418
2419 memcpy(&policy->fs, fs, sizeof(*fs));
2420 ether_addr_copy(policy->addr, addr);
2421 policy->mapping = mapping;
2422 policy->action = action;
2423 policy->port = port;
2424 policy->vid = vid;
2425
2426 err = mv88e6xxx_policy_apply(chip, port, policy);
2427 if (err) {
2428 idr_remove(&chip->policies, fs->location);
2429 devm_kfree(chip->dev, policy);
2430 return err;
2431 }
2432
2433 return 0;
2434 }
2435
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2436 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2437 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2438 {
2439 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2440 struct mv88e6xxx_chip *chip = ds->priv;
2441 struct mv88e6xxx_policy *policy;
2442 int err;
2443 int id;
2444
2445 mv88e6xxx_reg_lock(chip);
2446
2447 switch (rxnfc->cmd) {
2448 case ETHTOOL_GRXCLSRLCNT:
2449 rxnfc->data = 0;
2450 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2451 rxnfc->rule_cnt = 0;
2452 idr_for_each_entry(&chip->policies, policy, id)
2453 if (policy->port == port)
2454 rxnfc->rule_cnt++;
2455 err = 0;
2456 break;
2457 case ETHTOOL_GRXCLSRULE:
2458 err = -ENOENT;
2459 policy = idr_find(&chip->policies, fs->location);
2460 if (policy) {
2461 memcpy(fs, &policy->fs, sizeof(*fs));
2462 err = 0;
2463 }
2464 break;
2465 case ETHTOOL_GRXCLSRLALL:
2466 rxnfc->data = 0;
2467 rxnfc->rule_cnt = 0;
2468 idr_for_each_entry(&chip->policies, policy, id)
2469 if (policy->port == port)
2470 rule_locs[rxnfc->rule_cnt++] = id;
2471 err = 0;
2472 break;
2473 default:
2474 err = -EOPNOTSUPP;
2475 break;
2476 }
2477
2478 mv88e6xxx_reg_unlock(chip);
2479
2480 return err;
2481 }
2482
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2483 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2484 struct ethtool_rxnfc *rxnfc)
2485 {
2486 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2487 struct mv88e6xxx_chip *chip = ds->priv;
2488 struct mv88e6xxx_policy *policy;
2489 int err;
2490
2491 mv88e6xxx_reg_lock(chip);
2492
2493 switch (rxnfc->cmd) {
2494 case ETHTOOL_SRXCLSRLINS:
2495 err = mv88e6xxx_policy_insert(chip, port, fs);
2496 break;
2497 case ETHTOOL_SRXCLSRLDEL:
2498 err = -ENOENT;
2499 policy = idr_remove(&chip->policies, fs->location);
2500 if (policy) {
2501 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2502 err = mv88e6xxx_policy_apply(chip, port, policy);
2503 devm_kfree(chip->dev, policy);
2504 }
2505 break;
2506 default:
2507 err = -EOPNOTSUPP;
2508 break;
2509 }
2510
2511 mv88e6xxx_reg_unlock(chip);
2512
2513 return err;
2514 }
2515
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2516 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2517 u16 vid)
2518 {
2519 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2520 u8 broadcast[ETH_ALEN];
2521
2522 eth_broadcast_addr(broadcast);
2523
2524 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2525 }
2526
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2527 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2528 {
2529 int port;
2530 int err;
2531
2532 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2533 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2534 struct net_device *brport;
2535
2536 if (dsa_is_unused_port(chip->ds, port))
2537 continue;
2538
2539 brport = dsa_port_to_bridge_port(dp);
2540 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2541 /* Skip bridged user ports where broadcast
2542 * flooding is disabled.
2543 */
2544 continue;
2545
2546 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2547 if (err)
2548 return err;
2549 }
2550
2551 return 0;
2552 }
2553
2554 struct mv88e6xxx_port_broadcast_sync_ctx {
2555 int port;
2556 bool flood;
2557 };
2558
2559 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2560 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2561 const struct mv88e6xxx_vtu_entry *vlan,
2562 void *_ctx)
2563 {
2564 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2565 u8 broadcast[ETH_ALEN];
2566 u8 state;
2567
2568 if (ctx->flood)
2569 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2570 else
2571 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2572
2573 eth_broadcast_addr(broadcast);
2574
2575 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2576 vlan->vid, state);
2577 }
2578
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2579 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2580 bool flood)
2581 {
2582 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2583 .port = port,
2584 .flood = flood,
2585 };
2586 struct mv88e6xxx_vtu_entry vid0 = {
2587 .vid = 0,
2588 };
2589 int err;
2590
2591 /* Update the port's private database... */
2592 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2593 if (err)
2594 return err;
2595
2596 /* ...and the database for all VLANs. */
2597 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2598 &ctx);
2599 }
2600
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2601 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2602 u16 vid, u8 member, bool warn)
2603 {
2604 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2605 struct mv88e6xxx_vtu_entry vlan;
2606 int i, err;
2607
2608 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2609 if (err)
2610 return err;
2611
2612 if (!vlan.valid) {
2613 memset(&vlan, 0, sizeof(vlan));
2614
2615 if (vid == MV88E6XXX_VID_STANDALONE)
2616 vlan.policy = true;
2617
2618 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2619 if (err)
2620 return err;
2621
2622 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2623 if (i == port)
2624 vlan.member[i] = member;
2625 else
2626 vlan.member[i] = non_member;
2627
2628 vlan.vid = vid;
2629 vlan.valid = true;
2630
2631 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2632 if (err)
2633 return err;
2634
2635 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2636 if (err)
2637 return err;
2638 } else if (vlan.member[port] != member) {
2639 vlan.member[port] = member;
2640
2641 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2642 if (err)
2643 return err;
2644 } else if (warn) {
2645 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2646 port, vid);
2647 }
2648
2649 /* Record FID used in SW FID map */
2650 bitmap_set(chip->fid_bitmap, vlan.fid, 1);
2651
2652 return 0;
2653 }
2654
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2655 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2656 const struct switchdev_obj_port_vlan *vlan,
2657 struct netlink_ext_ack *extack)
2658 {
2659 struct mv88e6xxx_chip *chip = ds->priv;
2660 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2661 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2662 struct mv88e6xxx_port *p = &chip->ports[port];
2663 bool warn;
2664 u8 member;
2665 int err;
2666
2667 if (!vlan->vid)
2668 return 0;
2669
2670 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2671 if (err)
2672 return err;
2673
2674 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2675 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2676 else if (untagged)
2677 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2678 else
2679 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2680
2681 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2682 * and then the CPU port. Do not warn for duplicates for the CPU port.
2683 */
2684 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2685
2686 mv88e6xxx_reg_lock(chip);
2687
2688 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2689 if (err) {
2690 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2691 vlan->vid, untagged ? 'u' : 't');
2692 goto out;
2693 }
2694
2695 if (pvid) {
2696 p->bridge_pvid.vid = vlan->vid;
2697 p->bridge_pvid.valid = true;
2698
2699 err = mv88e6xxx_port_commit_pvid(chip, port);
2700 if (err)
2701 goto out;
2702 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2703 /* The old pvid was reinstalled as a non-pvid VLAN */
2704 p->bridge_pvid.valid = false;
2705
2706 err = mv88e6xxx_port_commit_pvid(chip, port);
2707 if (err)
2708 goto out;
2709 }
2710
2711 out:
2712 mv88e6xxx_reg_unlock(chip);
2713
2714 return err;
2715 }
2716
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2717 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2718 int port, u16 vid)
2719 {
2720 struct mv88e6xxx_vtu_entry vlan;
2721 int i, err;
2722
2723 if (!vid)
2724 return 0;
2725
2726 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2727 if (err)
2728 return err;
2729
2730 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2731 * tell switchdev that this VLAN is likely handled in software.
2732 */
2733 if (!vlan.valid ||
2734 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2735 return -EOPNOTSUPP;
2736
2737 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2738
2739 /* keep the VLAN unless all ports are excluded */
2740 vlan.valid = false;
2741 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2742 if (vlan.member[i] !=
2743 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2744 vlan.valid = true;
2745 break;
2746 }
2747 }
2748
2749 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2750 if (err)
2751 return err;
2752
2753 if (!vlan.valid) {
2754 err = mv88e6xxx_mst_put(chip, vlan.sid);
2755 if (err)
2756 return err;
2757
2758 /* Record FID freed in SW FID map */
2759 bitmap_clear(chip->fid_bitmap, vlan.fid, 1);
2760 }
2761
2762 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2763 }
2764
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2765 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2766 const struct switchdev_obj_port_vlan *vlan)
2767 {
2768 struct mv88e6xxx_chip *chip = ds->priv;
2769 struct mv88e6xxx_port *p = &chip->ports[port];
2770 int err = 0;
2771 u16 pvid;
2772
2773 if (!mv88e6xxx_max_vid(chip))
2774 return -EOPNOTSUPP;
2775
2776 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2777 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2778 * switchdev workqueue to ensure that all FDB entries are deleted
2779 * before we remove the VLAN.
2780 */
2781 dsa_flush_workqueue();
2782
2783 mv88e6xxx_reg_lock(chip);
2784
2785 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2786 if (err)
2787 goto unlock;
2788
2789 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2790 if (err)
2791 goto unlock;
2792
2793 if (vlan->vid == pvid) {
2794 p->bridge_pvid.valid = false;
2795
2796 err = mv88e6xxx_port_commit_pvid(chip, port);
2797 if (err)
2798 goto unlock;
2799 }
2800
2801 unlock:
2802 mv88e6xxx_reg_unlock(chip);
2803
2804 return err;
2805 }
2806
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2807 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2808 {
2809 struct mv88e6xxx_chip *chip = ds->priv;
2810 struct mv88e6xxx_vtu_entry vlan;
2811 int err;
2812
2813 mv88e6xxx_reg_lock(chip);
2814
2815 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2816 if (err)
2817 goto unlock;
2818
2819 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2820
2821 unlock:
2822 mv88e6xxx_reg_unlock(chip);
2823
2824 return err;
2825 }
2826
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2827 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2828 struct dsa_bridge bridge,
2829 const struct switchdev_vlan_msti *msti)
2830 {
2831 struct mv88e6xxx_chip *chip = ds->priv;
2832 struct mv88e6xxx_vtu_entry vlan;
2833 u8 old_sid, new_sid;
2834 int err;
2835
2836 if (!mv88e6xxx_has_stu(chip))
2837 return -EOPNOTSUPP;
2838
2839 mv88e6xxx_reg_lock(chip);
2840
2841 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2842 if (err)
2843 goto unlock;
2844
2845 if (!vlan.valid) {
2846 err = -EINVAL;
2847 goto unlock;
2848 }
2849
2850 old_sid = vlan.sid;
2851
2852 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2853 if (err)
2854 goto unlock;
2855
2856 if (new_sid != old_sid) {
2857 vlan.sid = new_sid;
2858
2859 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2860 if (err) {
2861 mv88e6xxx_mst_put(chip, new_sid);
2862 goto unlock;
2863 }
2864 }
2865
2866 err = mv88e6xxx_mst_put(chip, old_sid);
2867
2868 unlock:
2869 mv88e6xxx_reg_unlock(chip);
2870 return err;
2871 }
2872
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2873 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2874 const unsigned char *addr, u16 vid,
2875 struct dsa_db db)
2876 {
2877 struct mv88e6xxx_chip *chip = ds->priv;
2878 int err;
2879
2880 mv88e6xxx_reg_lock(chip);
2881 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2882 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2883 if (err)
2884 goto out;
2885
2886 if (!mv88e6xxx_port_db_find(chip, addr, vid))
2887 err = -ENOSPC;
2888
2889 out:
2890 mv88e6xxx_reg_unlock(chip);
2891
2892 return err;
2893 }
2894
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2895 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2896 const unsigned char *addr, u16 vid,
2897 struct dsa_db db)
2898 {
2899 struct mv88e6xxx_chip *chip = ds->priv;
2900 int err;
2901
2902 mv88e6xxx_reg_lock(chip);
2903 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2904 mv88e6xxx_reg_unlock(chip);
2905
2906 return err;
2907 }
2908
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2909 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2910 u16 fid, u16 vid, int port,
2911 dsa_fdb_dump_cb_t *cb, void *data)
2912 {
2913 struct mv88e6xxx_atu_entry addr;
2914 bool is_static;
2915 int err;
2916
2917 addr.state = 0;
2918 eth_broadcast_addr(addr.mac);
2919
2920 do {
2921 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2922 if (err)
2923 return err;
2924
2925 if (!addr.state)
2926 break;
2927
2928 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2929 continue;
2930
2931 if (!is_unicast_ether_addr(addr.mac))
2932 continue;
2933
2934 is_static = (addr.state ==
2935 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2936 err = cb(addr.mac, vid, is_static, data);
2937 if (err)
2938 return err;
2939 } while (!is_broadcast_ether_addr(addr.mac));
2940
2941 return err;
2942 }
2943
2944 struct mv88e6xxx_port_db_dump_vlan_ctx {
2945 int port;
2946 dsa_fdb_dump_cb_t *cb;
2947 void *data;
2948 };
2949
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2950 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2951 const struct mv88e6xxx_vtu_entry *entry,
2952 void *_data)
2953 {
2954 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2955
2956 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2957 ctx->port, ctx->cb, ctx->data);
2958 }
2959
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2960 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2961 dsa_fdb_dump_cb_t *cb, void *data)
2962 {
2963 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2964 .port = port,
2965 .cb = cb,
2966 .data = data,
2967 };
2968 u16 fid;
2969 int err;
2970
2971 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2972 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2973 if (err)
2974 return err;
2975
2976 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2977 if (err)
2978 return err;
2979
2980 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2981 }
2982
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2983 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2984 dsa_fdb_dump_cb_t *cb, void *data)
2985 {
2986 struct mv88e6xxx_chip *chip = ds->priv;
2987 int err;
2988
2989 mv88e6xxx_reg_lock(chip);
2990 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2991 mv88e6xxx_reg_unlock(chip);
2992
2993 return err;
2994 }
2995
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)2996 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2997 struct dsa_bridge bridge)
2998 {
2999 struct dsa_switch *ds = chip->ds;
3000 struct dsa_switch_tree *dst = ds->dst;
3001 struct dsa_port *dp;
3002 int err;
3003
3004 list_for_each_entry(dp, &dst->ports, list) {
3005 if (dsa_port_offloads_bridge(dp, &bridge)) {
3006 if (dp->ds == ds) {
3007 /* This is a local bridge group member,
3008 * remap its Port VLAN Map.
3009 */
3010 err = mv88e6xxx_port_vlan_map(chip, dp->index);
3011 if (err)
3012 return err;
3013 } else {
3014 /* This is an external bridge group member,
3015 * remap its cross-chip Port VLAN Table entry.
3016 */
3017 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
3018 dp->index);
3019 if (err)
3020 return err;
3021 }
3022 }
3023 }
3024
3025 return 0;
3026 }
3027
3028 /* Treat the software bridge as a virtual single-port switch behind the
3029 * CPU and map in the PVT. First dst->last_switch elements are taken by
3030 * physical switches, so start from beyond that range.
3031 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)3032 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3033 unsigned int bridge_num)
3034 {
3035 u8 dev = bridge_num + ds->dst->last_switch;
3036 struct mv88e6xxx_chip *chip = ds->priv;
3037
3038 return mv88e6xxx_pvt_map(chip, dev, 0);
3039 }
3040
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)3041 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3042 struct dsa_bridge bridge,
3043 bool *tx_fwd_offload,
3044 struct netlink_ext_ack *extack)
3045 {
3046 struct mv88e6xxx_chip *chip = ds->priv;
3047 int err;
3048
3049 mv88e6xxx_reg_lock(chip);
3050
3051 err = mv88e6xxx_bridge_map(chip, bridge);
3052 if (err)
3053 goto unlock;
3054
3055 err = mv88e6xxx_port_set_map_da(chip, port, true);
3056 if (err)
3057 goto unlock;
3058
3059 err = mv88e6xxx_port_commit_pvid(chip, port);
3060 if (err)
3061 goto unlock;
3062
3063 if (mv88e6xxx_has_pvt(chip)) {
3064 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3065 if (err)
3066 goto unlock;
3067
3068 *tx_fwd_offload = true;
3069 }
3070
3071 unlock:
3072 mv88e6xxx_reg_unlock(chip);
3073
3074 return err;
3075 }
3076
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)3077 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3078 struct dsa_bridge bridge)
3079 {
3080 struct mv88e6xxx_chip *chip = ds->priv;
3081 int err;
3082
3083 mv88e6xxx_reg_lock(chip);
3084
3085 if (bridge.tx_fwd_offload &&
3086 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3087 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3088
3089 if (mv88e6xxx_bridge_map(chip, bridge) ||
3090 mv88e6xxx_port_vlan_map(chip, port))
3091 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3092
3093 err = mv88e6xxx_port_set_map_da(chip, port, false);
3094 if (err)
3095 dev_err(ds->dev,
3096 "port %d failed to restore map-DA: %pe\n",
3097 port, ERR_PTR(err));
3098
3099 err = mv88e6xxx_port_commit_pvid(chip, port);
3100 if (err)
3101 dev_err(ds->dev,
3102 "port %d failed to restore standalone pvid: %pe\n",
3103 port, ERR_PTR(err));
3104
3105 mv88e6xxx_reg_unlock(chip);
3106 }
3107
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)3108 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3109 int tree_index, int sw_index,
3110 int port, struct dsa_bridge bridge,
3111 struct netlink_ext_ack *extack)
3112 {
3113 struct mv88e6xxx_chip *chip = ds->priv;
3114 int err;
3115
3116 if (tree_index != ds->dst->index)
3117 return 0;
3118
3119 mv88e6xxx_reg_lock(chip);
3120 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3121 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3122 mv88e6xxx_reg_unlock(chip);
3123
3124 return err;
3125 }
3126
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)3127 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3128 int tree_index, int sw_index,
3129 int port, struct dsa_bridge bridge)
3130 {
3131 struct mv88e6xxx_chip *chip = ds->priv;
3132
3133 if (tree_index != ds->dst->index)
3134 return;
3135
3136 mv88e6xxx_reg_lock(chip);
3137 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3138 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3139 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3140 mv88e6xxx_reg_unlock(chip);
3141 }
3142
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)3143 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3144 {
3145 if (chip->info->ops->reset)
3146 return chip->info->ops->reset(chip);
3147
3148 return 0;
3149 }
3150
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3151 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3152 {
3153 struct gpio_desc *gpiod = chip->reset;
3154 int err;
3155
3156 /* If there is a GPIO connected to the reset pin, toggle it */
3157 if (gpiod) {
3158 /* If the switch has just been reset and not yet completed
3159 * loading EEPROM, the reset may interrupt the I2C transaction
3160 * mid-byte, causing the first EEPROM read after the reset
3161 * from the wrong location resulting in the switch booting
3162 * to wrong mode and inoperable.
3163 * For this reason, switch families with EEPROM support
3164 * generally wait for EEPROM loads to complete as their pre-
3165 * and post-reset handlers.
3166 */
3167 if (chip->info->ops->hardware_reset_pre) {
3168 err = chip->info->ops->hardware_reset_pre(chip);
3169 if (err)
3170 dev_err(chip->dev, "pre-reset error: %d\n", err);
3171 }
3172
3173 gpiod_set_value_cansleep(gpiod, 1);
3174 usleep_range(10000, 20000);
3175 gpiod_set_value_cansleep(gpiod, 0);
3176 usleep_range(10000, 20000);
3177
3178 if (chip->info->ops->hardware_reset_post) {
3179 err = chip->info->ops->hardware_reset_post(chip);
3180 if (err)
3181 dev_err(chip->dev, "post-reset error: %d\n", err);
3182 }
3183 }
3184 }
3185
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)3186 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3187 {
3188 int i, err;
3189
3190 /* Set all ports to the Disabled state */
3191 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3192 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3193 if (err)
3194 return err;
3195 }
3196
3197 /* Wait for transmit queues to drain,
3198 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3199 */
3200 usleep_range(2000, 4000);
3201
3202 return 0;
3203 }
3204
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3205 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3206 {
3207 int err;
3208
3209 err = mv88e6xxx_disable_ports(chip);
3210 if (err)
3211 return err;
3212
3213 mv88e6xxx_hardware_reset(chip);
3214
3215 return mv88e6xxx_software_reset(chip);
3216 }
3217
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)3218 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3219 enum mv88e6xxx_frame_mode frame,
3220 enum mv88e6xxx_egress_mode egress, u16 etype)
3221 {
3222 int err;
3223
3224 if (!chip->info->ops->port_set_frame_mode)
3225 return -EOPNOTSUPP;
3226
3227 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3228 if (err)
3229 return err;
3230
3231 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3232 if (err)
3233 return err;
3234
3235 if (chip->info->ops->port_set_ether_type)
3236 return chip->info->ops->port_set_ether_type(chip, port, etype);
3237
3238 return 0;
3239 }
3240
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)3241 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3242 {
3243 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3244 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3245 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3246 }
3247
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)3248 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3249 {
3250 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3251 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3252 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3253 }
3254
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)3255 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3256 {
3257 return mv88e6xxx_set_port_mode(chip, port,
3258 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3259 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3260 ETH_P_EDSA);
3261 }
3262
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)3263 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3264 {
3265 if (dsa_is_dsa_port(chip->ds, port))
3266 return mv88e6xxx_set_port_mode_dsa(chip, port);
3267
3268 if (dsa_is_user_port(chip->ds, port))
3269 return mv88e6xxx_set_port_mode_normal(chip, port);
3270
3271 /* Setup CPU port mode depending on its supported tag format */
3272 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3273 return mv88e6xxx_set_port_mode_dsa(chip, port);
3274
3275 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3276 return mv88e6xxx_set_port_mode_edsa(chip, port);
3277
3278 return -EINVAL;
3279 }
3280
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3281 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3282 {
3283 bool message = dsa_is_dsa_port(chip->ds, port);
3284
3285 return mv88e6xxx_port_set_message_port(chip, port, message);
3286 }
3287
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3288 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3289 {
3290 int err;
3291
3292 if (chip->info->ops->port_set_ucast_flood) {
3293 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3294 if (err)
3295 return err;
3296 }
3297 if (chip->info->ops->port_set_mcast_flood) {
3298 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3299 if (err)
3300 return err;
3301 }
3302
3303 return 0;
3304 }
3305
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)3306 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3307 enum mv88e6xxx_egress_direction direction,
3308 int port)
3309 {
3310 int err;
3311
3312 if (!chip->info->ops->set_egress_port)
3313 return -EOPNOTSUPP;
3314
3315 err = chip->info->ops->set_egress_port(chip, direction, port);
3316 if (err)
3317 return err;
3318
3319 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3320 chip->ingress_dest_port = port;
3321 else
3322 chip->egress_dest_port = port;
3323
3324 return 0;
3325 }
3326
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3327 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3328 {
3329 struct dsa_switch *ds = chip->ds;
3330 int upstream_port;
3331 int err;
3332
3333 upstream_port = dsa_upstream_port(ds, port);
3334 if (chip->info->ops->port_set_upstream_port) {
3335 err = chip->info->ops->port_set_upstream_port(chip, port,
3336 upstream_port);
3337 if (err)
3338 return err;
3339 }
3340
3341 if (port == upstream_port) {
3342 if (chip->info->ops->set_cpu_port) {
3343 err = chip->info->ops->set_cpu_port(chip,
3344 upstream_port);
3345 if (err)
3346 return err;
3347 }
3348
3349 err = mv88e6xxx_set_egress_port(chip,
3350 MV88E6XXX_EGRESS_DIR_INGRESS,
3351 upstream_port);
3352 if (err && err != -EOPNOTSUPP)
3353 return err;
3354
3355 err = mv88e6xxx_set_egress_port(chip,
3356 MV88E6XXX_EGRESS_DIR_EGRESS,
3357 upstream_port);
3358 if (err && err != -EOPNOTSUPP)
3359 return err;
3360 }
3361
3362 return 0;
3363 }
3364
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3365 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3366 {
3367 struct device_node *phy_handle = NULL;
3368 struct fwnode_handle *ports_fwnode;
3369 struct fwnode_handle *port_fwnode;
3370 struct dsa_switch *ds = chip->ds;
3371 struct mv88e6xxx_port *p;
3372 struct dsa_port *dp;
3373 int tx_amp;
3374 int err;
3375 u16 reg;
3376 u32 val;
3377
3378 p = &chip->ports[port];
3379 p->chip = chip;
3380 p->port = port;
3381
3382 /* Look up corresponding fwnode if any */
3383 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports");
3384 if (!ports_fwnode)
3385 ports_fwnode = device_get_named_child_node(chip->dev, "ports");
3386 if (ports_fwnode) {
3387 fwnode_for_each_child_node(ports_fwnode, port_fwnode) {
3388 if (fwnode_property_read_u32(port_fwnode, "reg", &val))
3389 continue;
3390 if (val == port) {
3391 p->fwnode = port_fwnode;
3392 p->fiber = fwnode_property_present(port_fwnode, "sfp");
3393 break;
3394 }
3395 }
3396 fwnode_handle_put(ports_fwnode);
3397 } else {
3398 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n");
3399 }
3400
3401 if (chip->info->ops->port_setup_leds) {
3402 err = chip->info->ops->port_setup_leds(chip, port);
3403 if (err && err != -EOPNOTSUPP)
3404 return err;
3405 }
3406
3407 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3408 SPEED_UNFORCED, DUPLEX_UNFORCED,
3409 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3410 if (err)
3411 return err;
3412
3413 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3414 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3415 * tunneling, determine priority by looking at 802.1p and IP
3416 * priority fields (IP prio has precedence), and set STP state
3417 * to Forwarding.
3418 *
3419 * If this is the CPU link, use DSA or EDSA tagging depending
3420 * on which tagging mode was configured.
3421 *
3422 * If this is a link to another switch, use DSA tagging mode.
3423 *
3424 * If this is the upstream port for this switch, enable
3425 * forwarding of unknown unicasts and multicasts.
3426 */
3427 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3428 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3429 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3430 * by a USER port to the CPU port to allow snooping.
3431 */
3432 if (dsa_is_user_port(ds, port))
3433 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3434
3435 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3436 if (err)
3437 return err;
3438
3439 err = mv88e6xxx_setup_port_mode(chip, port);
3440 if (err)
3441 return err;
3442
3443 err = mv88e6xxx_setup_egress_floods(chip, port);
3444 if (err)
3445 return err;
3446
3447 /* Port Control 2: don't force a good FCS, set the MTU size to
3448 * 10222 bytes, disable 802.1q tags checking, don't discard
3449 * tagged or untagged frames on this port, skip destination
3450 * address lookup on user ports, disable ARP mirroring and don't
3451 * send a copy of all transmitted/received frames on this port
3452 * to the CPU.
3453 */
3454 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3455 if (err)
3456 return err;
3457
3458 err = mv88e6xxx_setup_upstream_port(chip, port);
3459 if (err)
3460 return err;
3461
3462 /* On chips that support it, set all downstream DSA ports'
3463 * VLAN policy to TRAP. In combination with loading
3464 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3465 * provides a better isolation barrier between standalone
3466 * ports, as the ATU is bypassed on any intermediate switches
3467 * between the incoming port and the CPU.
3468 */
3469 if (dsa_is_downstream_port(ds, port) &&
3470 chip->info->ops->port_set_policy) {
3471 err = chip->info->ops->port_set_policy(chip, port,
3472 MV88E6XXX_POLICY_MAPPING_VTU,
3473 MV88E6XXX_POLICY_ACTION_TRAP);
3474 if (err)
3475 return err;
3476 }
3477
3478 /* User ports start out in standalone mode and 802.1Q is
3479 * therefore disabled. On DSA ports, all valid VIDs are always
3480 * loaded in the VTU - therefore, enable 802.1Q in order to take
3481 * advantage of VLAN policy on chips that supports it.
3482 */
3483 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3484 dsa_is_user_port(ds, port) ?
3485 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3486 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3487 if (err)
3488 return err;
3489
3490 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3491 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3492 * the first free FID. This will be used as the private PVID for
3493 * unbridged ports. Shared (DSA and CPU) ports must also be
3494 * members of this VID, in order to trap all frames assigned to
3495 * it to the CPU.
3496 */
3497 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3498 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3499 false);
3500 if (err)
3501 return err;
3502
3503 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3504 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3505 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3506 * as the private PVID on ports under a VLAN-unaware bridge.
3507 * Shared (DSA and CPU) ports must also be members of it, to translate
3508 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3509 * relying on their port default FID.
3510 */
3511 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3512 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3513 false);
3514 if (err)
3515 return err;
3516
3517 if (chip->info->ops->port_set_jumbo_size) {
3518 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3519 if (err)
3520 return err;
3521 }
3522
3523 /* Port Association Vector: disable automatic address learning
3524 * on all user ports since they start out in standalone
3525 * mode. When joining a bridge, learning will be configured to
3526 * match the bridge port settings. Enable learning on all
3527 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3528 * learning process.
3529 *
3530 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3531 * and RefreshLocked. I.e. setup standard automatic learning.
3532 */
3533 if (dsa_is_user_port(ds, port))
3534 reg = 0;
3535 else
3536 reg = 1 << port;
3537
3538 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3539 reg);
3540 if (err)
3541 return err;
3542
3543 /* Egress rate control 2: disable egress rate control. */
3544 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3545 0x0000);
3546 if (err)
3547 return err;
3548
3549 if (chip->info->ops->port_pause_limit) {
3550 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3551 if (err)
3552 return err;
3553 }
3554
3555 if (chip->info->ops->port_disable_learn_limit) {
3556 err = chip->info->ops->port_disable_learn_limit(chip, port);
3557 if (err)
3558 return err;
3559 }
3560
3561 if (chip->info->ops->port_disable_pri_override) {
3562 err = chip->info->ops->port_disable_pri_override(chip, port);
3563 if (err)
3564 return err;
3565 }
3566
3567 if (chip->info->ops->port_tag_remap) {
3568 err = chip->info->ops->port_tag_remap(chip, port);
3569 if (err)
3570 return err;
3571 }
3572
3573 if (chip->info->ops->port_egress_rate_limiting) {
3574 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3575 if (err)
3576 return err;
3577 }
3578
3579 if (chip->info->ops->port_setup_message_port) {
3580 err = chip->info->ops->port_setup_message_port(chip, port);
3581 if (err)
3582 return err;
3583 }
3584
3585 if (chip->info->ops->serdes_set_tx_amplitude) {
3586 dp = dsa_to_port(ds, port);
3587 if (dp)
3588 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3589
3590 if (phy_handle && !of_property_read_u32(phy_handle,
3591 "tx-p2p-microvolt",
3592 &tx_amp))
3593 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3594 port, tx_amp);
3595 if (phy_handle) {
3596 of_node_put(phy_handle);
3597 if (err)
3598 return err;
3599 }
3600 }
3601
3602 /* Port based VLAN map: give each port the same default address
3603 * database, and allow bidirectional communication between the
3604 * CPU and DSA port(s), and the other ports.
3605 */
3606 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3607 if (err)
3608 return err;
3609
3610 err = mv88e6xxx_port_vlan_map(chip, port);
3611 if (err)
3612 return err;
3613
3614 /* Default VLAN ID and priority: don't set a default VLAN
3615 * ID, and set the default packet priority to zero.
3616 */
3617 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3618 }
3619
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3620 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3621 {
3622 struct mv88e6xxx_chip *chip = ds->priv;
3623
3624 if (chip->info->ops->port_set_jumbo_size)
3625 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3626 else if (chip->info->ops->set_max_frame_size)
3627 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3628 return ETH_DATA_LEN;
3629 }
3630
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3631 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3632 {
3633 struct mv88e6xxx_chip *chip = ds->priv;
3634 int ret = 0;
3635
3636 /* For families where we don't know how to alter the MTU,
3637 * just accept any value up to ETH_DATA_LEN
3638 */
3639 if (!chip->info->ops->port_set_jumbo_size &&
3640 !chip->info->ops->set_max_frame_size) {
3641 if (new_mtu > ETH_DATA_LEN)
3642 return -EINVAL;
3643
3644 return 0;
3645 }
3646
3647 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3648 new_mtu += EDSA_HLEN;
3649
3650 mv88e6xxx_reg_lock(chip);
3651 if (chip->info->ops->port_set_jumbo_size)
3652 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3653 else if (chip->info->ops->set_max_frame_size &&
3654 dsa_is_cpu_port(ds, port))
3655 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3656 mv88e6xxx_reg_unlock(chip);
3657
3658 return ret;
3659 }
3660
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3661 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3662 unsigned int ageing_time)
3663 {
3664 struct mv88e6xxx_chip *chip = ds->priv;
3665 int err;
3666
3667 mv88e6xxx_reg_lock(chip);
3668 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3669 mv88e6xxx_reg_unlock(chip);
3670
3671 return err;
3672 }
3673
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3674 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3675 {
3676 int err;
3677
3678 /* Initialize the statistics unit */
3679 if (chip->info->ops->stats_set_histogram) {
3680 err = chip->info->ops->stats_set_histogram(chip);
3681 if (err)
3682 return err;
3683 }
3684
3685 return mv88e6xxx_g1_stats_clear(chip);
3686 }
3687
mv88e6320_setup_errata(struct mv88e6xxx_chip * chip)3688 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip)
3689 {
3690 u16 dummy;
3691 int err;
3692
3693 /* Workaround for erratum
3694 * 3.3 RGMII timing may be out of spec when transmit delay is enabled
3695 */
3696 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000);
3697 if (err)
3698 return err;
3699
3700 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy);
3701 }
3702
3703 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3704 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3705 {
3706 int port;
3707 int err;
3708 u16 val;
3709
3710 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3711 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3712 if (err) {
3713 dev_err(chip->dev,
3714 "Error reading hidden register: %d\n", err);
3715 return false;
3716 }
3717 if (val != 0x01c0)
3718 return false;
3719 }
3720
3721 return true;
3722 }
3723
3724 /* The 6390 copper ports have an errata which require poking magic
3725 * values into undocumented hidden registers and then performing a
3726 * software reset.
3727 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3728 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3729 {
3730 int port;
3731 int err;
3732
3733 if (mv88e6390_setup_errata_applied(chip))
3734 return 0;
3735
3736 /* Set the ports into blocking mode */
3737 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3738 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3739 if (err)
3740 return err;
3741 }
3742
3743 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3744 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3745 if (err)
3746 return err;
3747 }
3748
3749 return mv88e6xxx_software_reset(chip);
3750 }
3751
3752 /* prod_id for switch families which do not have a PHY model number */
3753 static const u16 family_prod_id_table[] = {
3754 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3755 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3756 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3757 };
3758
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3759 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3760 {
3761 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3762 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3763 u16 prod_id;
3764 u16 val;
3765 int err;
3766
3767 if (!chip->info->ops->phy_read)
3768 return -EOPNOTSUPP;
3769
3770 mv88e6xxx_reg_lock(chip);
3771 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3772 mv88e6xxx_reg_unlock(chip);
3773
3774 /* Some internal PHYs don't have a model number. */
3775 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3776 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3777 prod_id = family_prod_id_table[chip->info->family];
3778 if (prod_id)
3779 val |= prod_id >> 4;
3780 }
3781
3782 return err ? err : val;
3783 }
3784
mv88e6xxx_mdio_read_c45(struct mii_bus * bus,int phy,int devad,int reg)3785 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3786 int reg)
3787 {
3788 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3789 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3790 u16 val;
3791 int err;
3792
3793 if (!chip->info->ops->phy_read_c45)
3794 return -ENODEV;
3795
3796 mv88e6xxx_reg_lock(chip);
3797 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3798 mv88e6xxx_reg_unlock(chip);
3799
3800 return err ? err : val;
3801 }
3802
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3803 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3804 {
3805 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3806 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3807 int err;
3808
3809 if (!chip->info->ops->phy_write)
3810 return -EOPNOTSUPP;
3811
3812 mv88e6xxx_reg_lock(chip);
3813 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3814 mv88e6xxx_reg_unlock(chip);
3815
3816 return err;
3817 }
3818
mv88e6xxx_mdio_write_c45(struct mii_bus * bus,int phy,int devad,int reg,u16 val)3819 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3820 int reg, u16 val)
3821 {
3822 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3823 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3824 int err;
3825
3826 if (!chip->info->ops->phy_write_c45)
3827 return -EOPNOTSUPP;
3828
3829 mv88e6xxx_reg_lock(chip);
3830 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3831 mv88e6xxx_reg_unlock(chip);
3832
3833 return err;
3834 }
3835
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3836 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3837 struct device_node *np,
3838 bool external)
3839 {
3840 static int index;
3841 struct mv88e6xxx_mdio_bus *mdio_bus;
3842 struct mii_bus *bus;
3843 int err;
3844
3845 if (external) {
3846 mv88e6xxx_reg_lock(chip);
3847 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3848 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3849 else
3850 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3851 mv88e6xxx_reg_unlock(chip);
3852
3853 if (err)
3854 return err;
3855 }
3856
3857 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3858 if (!bus)
3859 return -ENOMEM;
3860
3861 mdio_bus = bus->priv;
3862 mdio_bus->bus = bus;
3863 mdio_bus->chip = chip;
3864 INIT_LIST_HEAD(&mdio_bus->list);
3865 mdio_bus->external = external;
3866
3867 if (np) {
3868 bus->name = np->full_name;
3869 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3870 } else {
3871 bus->name = "mv88e6xxx SMI";
3872 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3873 }
3874
3875 bus->read = mv88e6xxx_mdio_read;
3876 bus->write = mv88e6xxx_mdio_write;
3877 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3878 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3879 bus->parent = chip->dev;
3880 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3881 mv88e6xxx_num_ports(chip) - 1,
3882 chip->info->phy_base_addr);
3883
3884 if (!external) {
3885 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3886 if (err)
3887 goto out;
3888 }
3889
3890 err = of_mdiobus_register(bus, np);
3891 if (err) {
3892 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3893 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3894 goto out;
3895 }
3896
3897 if (external)
3898 list_add_tail(&mdio_bus->list, &chip->mdios);
3899 else
3900 list_add(&mdio_bus->list, &chip->mdios);
3901
3902 return 0;
3903
3904 out:
3905 mdiobus_free(bus);
3906 return err;
3907 }
3908
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3909 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3910
3911 {
3912 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3913 struct mii_bus *bus;
3914
3915 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3916 bus = mdio_bus->bus;
3917
3918 if (!mdio_bus->external)
3919 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3920
3921 mdiobus_unregister(bus);
3922 mdiobus_free(bus);
3923 }
3924 }
3925
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip)3926 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3927 {
3928 struct device_node *np = chip->dev->of_node;
3929 struct device_node *child;
3930 int err;
3931
3932 /* Always register one mdio bus for the internal/default mdio
3933 * bus. This maybe represented in the device tree, but is
3934 * optional.
3935 */
3936 child = of_get_child_by_name(np, "mdio");
3937 err = mv88e6xxx_mdio_register(chip, child, false);
3938 of_node_put(child);
3939 if (err)
3940 return err;
3941
3942 /* Walk the device tree, and see if there are any other nodes
3943 * which say they are compatible with the external mdio
3944 * bus.
3945 */
3946 for_each_available_child_of_node(np, child) {
3947 if (of_device_is_compatible(
3948 child, "marvell,mv88e6xxx-mdio-external")) {
3949 err = mv88e6xxx_mdio_register(chip, child, true);
3950 if (err) {
3951 mv88e6xxx_mdios_unregister(chip);
3952 of_node_put(child);
3953 return err;
3954 }
3955 }
3956 }
3957
3958 return 0;
3959 }
3960
mv88e6xxx_teardown(struct dsa_switch * ds)3961 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3962 {
3963 struct mv88e6xxx_chip *chip = ds->priv;
3964
3965 mv88e6xxx_teardown_devlink_params(ds);
3966 dsa_devlink_resources_unregister(ds);
3967 mv88e6xxx_teardown_devlink_regions_global(ds);
3968 mv88e6xxx_mdios_unregister(chip);
3969 }
3970
mv88e6xxx_setup(struct dsa_switch * ds)3971 static int mv88e6xxx_setup(struct dsa_switch *ds)
3972 {
3973 struct mv88e6xxx_chip *chip = ds->priv;
3974 u8 cmode;
3975 int err;
3976 int i;
3977
3978 err = mv88e6xxx_mdios_register(chip);
3979 if (err)
3980 return err;
3981
3982 chip->ds = ds;
3983 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3984
3985 /* Since virtual bridges are mapped in the PVT, the number we support
3986 * depends on the physical switch topology. We need to let DSA figure
3987 * that out and therefore we cannot set this at dsa_register_switch()
3988 * time.
3989 */
3990 if (mv88e6xxx_has_pvt(chip))
3991 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3992 ds->dst->last_switch - 1;
3993
3994 mv88e6xxx_reg_lock(chip);
3995
3996 if (chip->info->ops->setup_errata) {
3997 err = chip->info->ops->setup_errata(chip);
3998 if (err)
3999 goto unlock;
4000 }
4001
4002 /* Cache the cmode of each port. */
4003 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4004 if (chip->info->ops->port_get_cmode) {
4005 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
4006 if (err)
4007 goto unlock;
4008
4009 chip->ports[i].cmode = cmode;
4010 }
4011 }
4012
4013 err = mv88e6xxx_vtu_setup(chip);
4014 if (err)
4015 goto unlock;
4016
4017 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
4018 * VTU, thereby also flushing the STU).
4019 */
4020 err = mv88e6xxx_stu_setup(chip);
4021 if (err)
4022 goto unlock;
4023
4024 /* Setup Switch Port Registers */
4025 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4026 if (dsa_is_unused_port(ds, i))
4027 continue;
4028
4029 /* Prevent the use of an invalid port. */
4030 if (mv88e6xxx_is_invalid_port(chip, i)) {
4031 dev_err(chip->dev, "port %d is invalid\n", i);
4032 err = -EINVAL;
4033 goto unlock;
4034 }
4035
4036 err = mv88e6xxx_setup_port(chip, i);
4037 if (err)
4038 goto unlock;
4039 }
4040
4041 err = mv88e6xxx_irl_setup(chip);
4042 if (err)
4043 goto unlock;
4044
4045 err = mv88e6xxx_mac_setup(chip);
4046 if (err)
4047 goto unlock;
4048
4049 err = mv88e6xxx_phy_setup(chip);
4050 if (err)
4051 goto unlock;
4052
4053 err = mv88e6xxx_pvt_setup(chip);
4054 if (err)
4055 goto unlock;
4056
4057 err = mv88e6xxx_atu_setup(chip);
4058 if (err)
4059 goto unlock;
4060
4061 err = mv88e6xxx_broadcast_setup(chip, 0);
4062 if (err)
4063 goto unlock;
4064
4065 err = mv88e6xxx_pot_setup(chip);
4066 if (err)
4067 goto unlock;
4068
4069 err = mv88e6xxx_rmu_setup(chip);
4070 if (err)
4071 goto unlock;
4072
4073 err = mv88e6xxx_rsvd2cpu_setup(chip);
4074 if (err)
4075 goto unlock;
4076
4077 err = mv88e6xxx_trunk_setup(chip);
4078 if (err)
4079 goto unlock;
4080
4081 err = mv88e6xxx_devmap_setup(chip);
4082 if (err)
4083 goto unlock;
4084
4085 err = mv88e6xxx_pri_setup(chip);
4086 if (err)
4087 goto unlock;
4088
4089 /* Setup PTP Hardware Clock and timestamping */
4090 if (chip->info->ptp_support) {
4091 err = mv88e6xxx_ptp_setup(chip);
4092 if (err)
4093 goto unlock;
4094
4095 err = mv88e6xxx_hwtstamp_setup(chip);
4096 if (err)
4097 goto unlock;
4098 }
4099
4100 err = mv88e6xxx_stats_setup(chip);
4101 if (err)
4102 goto unlock;
4103
4104 unlock:
4105 mv88e6xxx_reg_unlock(chip);
4106
4107 if (err)
4108 goto out_mdios;
4109
4110 /* Have to be called without holding the register lock, since
4111 * they take the devlink lock, and we later take the locks in
4112 * the reverse order when getting/setting parameters or
4113 * resource occupancy.
4114 */
4115 err = mv88e6xxx_setup_devlink_resources(ds);
4116 if (err)
4117 goto out_mdios;
4118
4119 err = mv88e6xxx_setup_devlink_params(ds);
4120 if (err)
4121 goto out_resources;
4122
4123 err = mv88e6xxx_setup_devlink_regions_global(ds);
4124 if (err)
4125 goto out_params;
4126
4127 return 0;
4128
4129 out_params:
4130 mv88e6xxx_teardown_devlink_params(ds);
4131 out_resources:
4132 dsa_devlink_resources_unregister(ds);
4133 out_mdios:
4134 mv88e6xxx_mdios_unregister(chip);
4135
4136 return err;
4137 }
4138
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)4139 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4140 {
4141 struct mv88e6xxx_chip *chip = ds->priv;
4142 int err;
4143
4144 if (chip->info->ops->pcs_ops &&
4145 chip->info->ops->pcs_ops->pcs_init) {
4146 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4147 if (err)
4148 return err;
4149 }
4150
4151 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4152 }
4153
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)4154 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4155 {
4156 struct mv88e6xxx_chip *chip = ds->priv;
4157
4158 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4159
4160 if (chip->info->ops->pcs_ops &&
4161 chip->info->ops->pcs_ops->pcs_teardown)
4162 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4163 }
4164
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)4165 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4166 {
4167 struct mv88e6xxx_chip *chip = ds->priv;
4168
4169 return chip->eeprom_len;
4170 }
4171
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4172 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4173 struct ethtool_eeprom *eeprom, u8 *data)
4174 {
4175 struct mv88e6xxx_chip *chip = ds->priv;
4176 int err;
4177
4178 if (!chip->info->ops->get_eeprom)
4179 return -EOPNOTSUPP;
4180
4181 mv88e6xxx_reg_lock(chip);
4182 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4183 mv88e6xxx_reg_unlock(chip);
4184
4185 if (err)
4186 return err;
4187
4188 eeprom->magic = 0xc3ec4951;
4189
4190 return 0;
4191 }
4192
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4193 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4194 struct ethtool_eeprom *eeprom, u8 *data)
4195 {
4196 struct mv88e6xxx_chip *chip = ds->priv;
4197 int err;
4198
4199 if (!chip->info->ops->set_eeprom)
4200 return -EOPNOTSUPP;
4201
4202 if (eeprom->magic != 0xc3ec4951)
4203 return -EINVAL;
4204
4205 mv88e6xxx_reg_lock(chip);
4206 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4207 mv88e6xxx_reg_unlock(chip);
4208
4209 return err;
4210 }
4211
4212 static const struct mv88e6xxx_ops mv88e6085_ops = {
4213 /* MV88E6XXX_FAMILY_6097 */
4214 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4215 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4216 .irl_init_all = mv88e6352_g2_irl_init_all,
4217 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4218 .phy_read = mv88e6185_phy_ppu_read,
4219 .phy_write = mv88e6185_phy_ppu_write,
4220 .port_set_link = mv88e6xxx_port_set_link,
4221 .port_sync_link = mv88e6xxx_port_sync_link,
4222 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4223 .port_tag_remap = mv88e6095_port_tag_remap,
4224 .port_set_policy = mv88e6352_port_set_policy,
4225 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4226 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4227 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4228 .port_set_ether_type = mv88e6351_port_set_ether_type,
4229 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4230 .port_pause_limit = mv88e6097_port_pause_limit,
4231 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4232 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4233 .port_get_cmode = mv88e6185_port_get_cmode,
4234 .port_setup_message_port = mv88e6xxx_setup_message_port,
4235 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4236 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4237 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4238 .stats_get_strings = mv88e6095_stats_get_strings,
4239 .stats_get_stat = mv88e6095_stats_get_stat,
4240 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4241 .set_egress_port = mv88e6095_g1_set_egress_port,
4242 .watchdog_ops = &mv88e6097_watchdog_ops,
4243 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4244 .pot_clear = mv88e6xxx_g2_pot_clear,
4245 .ppu_enable = mv88e6185_g1_ppu_enable,
4246 .ppu_disable = mv88e6185_g1_ppu_disable,
4247 .reset = mv88e6185_g1_reset,
4248 .rmu_disable = mv88e6085_g1_rmu_disable,
4249 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4250 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4251 .stu_getnext = mv88e6352_g1_stu_getnext,
4252 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4253 .phylink_get_caps = mv88e6185_phylink_get_caps,
4254 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4255 };
4256
4257 static const struct mv88e6xxx_ops mv88e6095_ops = {
4258 /* MV88E6XXX_FAMILY_6095 */
4259 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4260 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4261 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4262 .phy_read = mv88e6185_phy_ppu_read,
4263 .phy_write = mv88e6185_phy_ppu_write,
4264 .port_set_link = mv88e6xxx_port_set_link,
4265 .port_sync_link = mv88e6185_port_sync_link,
4266 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4267 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4268 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4269 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4270 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4271 .port_get_cmode = mv88e6185_port_get_cmode,
4272 .port_setup_message_port = mv88e6xxx_setup_message_port,
4273 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4274 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4275 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4276 .stats_get_strings = mv88e6095_stats_get_strings,
4277 .stats_get_stat = mv88e6095_stats_get_stat,
4278 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4279 .ppu_enable = mv88e6185_g1_ppu_enable,
4280 .ppu_disable = mv88e6185_g1_ppu_disable,
4281 .reset = mv88e6185_g1_reset,
4282 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4283 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4284 .phylink_get_caps = mv88e6095_phylink_get_caps,
4285 .pcs_ops = &mv88e6185_pcs_ops,
4286 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4287 };
4288
4289 static const struct mv88e6xxx_ops mv88e6097_ops = {
4290 /* MV88E6XXX_FAMILY_6097 */
4291 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4292 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4293 .irl_init_all = mv88e6352_g2_irl_init_all,
4294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4295 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4296 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4297 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4298 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4299 .port_set_link = mv88e6xxx_port_set_link,
4300 .port_sync_link = mv88e6185_port_sync_link,
4301 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4302 .port_tag_remap = mv88e6095_port_tag_remap,
4303 .port_set_policy = mv88e6352_port_set_policy,
4304 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4305 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4306 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4307 .port_set_ether_type = mv88e6351_port_set_ether_type,
4308 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4309 .port_pause_limit = mv88e6097_port_pause_limit,
4310 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4311 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4312 .port_get_cmode = mv88e6185_port_get_cmode,
4313 .port_setup_message_port = mv88e6xxx_setup_message_port,
4314 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4315 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4316 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4317 .stats_get_strings = mv88e6095_stats_get_strings,
4318 .stats_get_stat = mv88e6095_stats_get_stat,
4319 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4320 .set_egress_port = mv88e6095_g1_set_egress_port,
4321 .watchdog_ops = &mv88e6097_watchdog_ops,
4322 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4323 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4324 .pot_clear = mv88e6xxx_g2_pot_clear,
4325 .reset = mv88e6352_g1_reset,
4326 .rmu_disable = mv88e6085_g1_rmu_disable,
4327 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4329 .phylink_get_caps = mv88e6095_phylink_get_caps,
4330 .pcs_ops = &mv88e6185_pcs_ops,
4331 .stu_getnext = mv88e6352_g1_stu_getnext,
4332 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4333 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4334 };
4335
4336 static const struct mv88e6xxx_ops mv88e6123_ops = {
4337 /* MV88E6XXX_FAMILY_6165 */
4338 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4339 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4340 .irl_init_all = mv88e6352_g2_irl_init_all,
4341 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4342 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4343 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4344 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4345 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4346 .port_set_link = mv88e6xxx_port_set_link,
4347 .port_sync_link = mv88e6xxx_port_sync_link,
4348 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4349 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4350 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4351 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4354 .port_get_cmode = mv88e6185_port_get_cmode,
4355 .port_setup_message_port = mv88e6xxx_setup_message_port,
4356 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4357 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4358 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4359 .stats_get_strings = mv88e6095_stats_get_strings,
4360 .stats_get_stat = mv88e6095_stats_get_stat,
4361 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4362 .set_egress_port = mv88e6095_g1_set_egress_port,
4363 .watchdog_ops = &mv88e6097_watchdog_ops,
4364 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4365 .pot_clear = mv88e6xxx_g2_pot_clear,
4366 .reset = mv88e6352_g1_reset,
4367 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4368 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4369 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4370 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4371 .stu_getnext = mv88e6352_g1_stu_getnext,
4372 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4373 .phylink_get_caps = mv88e6185_phylink_get_caps,
4374 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4375 };
4376
4377 static const struct mv88e6xxx_ops mv88e6131_ops = {
4378 /* MV88E6XXX_FAMILY_6185 */
4379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4380 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4381 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4382 .phy_read = mv88e6185_phy_ppu_read,
4383 .phy_write = mv88e6185_phy_ppu_write,
4384 .port_set_link = mv88e6xxx_port_set_link,
4385 .port_sync_link = mv88e6xxx_port_sync_link,
4386 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4387 .port_tag_remap = mv88e6095_port_tag_remap,
4388 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4389 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4390 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4391 .port_set_ether_type = mv88e6351_port_set_ether_type,
4392 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4395 .port_pause_limit = mv88e6097_port_pause_limit,
4396 .port_set_pause = mv88e6185_port_set_pause,
4397 .port_get_cmode = mv88e6185_port_get_cmode,
4398 .port_setup_message_port = mv88e6xxx_setup_message_port,
4399 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4400 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4401 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4402 .stats_get_strings = mv88e6095_stats_get_strings,
4403 .stats_get_stat = mv88e6095_stats_get_stat,
4404 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4405 .set_egress_port = mv88e6095_g1_set_egress_port,
4406 .watchdog_ops = &mv88e6097_watchdog_ops,
4407 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4408 .ppu_enable = mv88e6185_g1_ppu_enable,
4409 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4410 .ppu_disable = mv88e6185_g1_ppu_disable,
4411 .reset = mv88e6185_g1_reset,
4412 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4413 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4414 .phylink_get_caps = mv88e6185_phylink_get_caps,
4415 };
4416
4417 static const struct mv88e6xxx_ops mv88e6141_ops = {
4418 /* MV88E6XXX_FAMILY_6341 */
4419 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4420 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4421 .irl_init_all = mv88e6352_g2_irl_init_all,
4422 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4423 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4424 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4425 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4426 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4427 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4428 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4429 .port_set_link = mv88e6xxx_port_set_link,
4430 .port_sync_link = mv88e6xxx_port_sync_link,
4431 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4432 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4433 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4434 .port_tag_remap = mv88e6095_port_tag_remap,
4435 .port_set_policy = mv88e6352_port_set_policy,
4436 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4437 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4438 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4439 .port_set_ether_type = mv88e6351_port_set_ether_type,
4440 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4441 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4442 .port_pause_limit = mv88e6097_port_pause_limit,
4443 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4444 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4445 .port_get_cmode = mv88e6352_port_get_cmode,
4446 .port_set_cmode = mv88e6341_port_set_cmode,
4447 .port_setup_message_port = mv88e6xxx_setup_message_port,
4448 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4449 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4450 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4451 .stats_get_strings = mv88e6320_stats_get_strings,
4452 .stats_get_stat = mv88e6390_stats_get_stat,
4453 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4454 .set_egress_port = mv88e6390_g1_set_egress_port,
4455 .watchdog_ops = &mv88e6390_watchdog_ops,
4456 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4457 .pot_clear = mv88e6xxx_g2_pot_clear,
4458 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4459 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4460 .reset = mv88e6352_g1_reset,
4461 .rmu_disable = mv88e6390_g1_rmu_disable,
4462 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4463 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4464 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4465 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4466 .stu_getnext = mv88e6352_g1_stu_getnext,
4467 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4468 .serdes_get_lane = mv88e6341_serdes_get_lane,
4469 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4470 .gpio_ops = &mv88e6352_gpio_ops,
4471 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4472 .serdes_get_strings = mv88e6390_serdes_get_strings,
4473 .serdes_get_stats = mv88e6390_serdes_get_stats,
4474 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4475 .serdes_get_regs = mv88e6390_serdes_get_regs,
4476 .phylink_get_caps = mv88e6341_phylink_get_caps,
4477 .pcs_ops = &mv88e6390_pcs_ops,
4478 };
4479
4480 static const struct mv88e6xxx_ops mv88e6161_ops = {
4481 /* MV88E6XXX_FAMILY_6165 */
4482 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4483 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4484 .irl_init_all = mv88e6352_g2_irl_init_all,
4485 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4486 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4487 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4488 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4489 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4490 .port_set_link = mv88e6xxx_port_set_link,
4491 .port_sync_link = mv88e6xxx_port_sync_link,
4492 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4493 .port_tag_remap = mv88e6095_port_tag_remap,
4494 .port_set_policy = mv88e6352_port_set_policy,
4495 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4496 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4497 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4498 .port_set_ether_type = mv88e6351_port_set_ether_type,
4499 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4500 .port_pause_limit = mv88e6097_port_pause_limit,
4501 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4502 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4503 .port_get_cmode = mv88e6185_port_get_cmode,
4504 .port_setup_message_port = mv88e6xxx_setup_message_port,
4505 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4506 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4507 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4508 .stats_get_strings = mv88e6095_stats_get_strings,
4509 .stats_get_stat = mv88e6095_stats_get_stat,
4510 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4511 .set_egress_port = mv88e6095_g1_set_egress_port,
4512 .watchdog_ops = &mv88e6097_watchdog_ops,
4513 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4514 .pot_clear = mv88e6xxx_g2_pot_clear,
4515 .reset = mv88e6352_g1_reset,
4516 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4517 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4518 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4519 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4520 .stu_getnext = mv88e6352_g1_stu_getnext,
4521 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4522 .avb_ops = &mv88e6165_avb_ops,
4523 .ptp_ops = &mv88e6165_ptp_ops,
4524 .phylink_get_caps = mv88e6185_phylink_get_caps,
4525 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4526 };
4527
4528 static const struct mv88e6xxx_ops mv88e6165_ops = {
4529 /* MV88E6XXX_FAMILY_6165 */
4530 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4531 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4532 .irl_init_all = mv88e6352_g2_irl_init_all,
4533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4534 .phy_read = mv88e6165_phy_read,
4535 .phy_write = mv88e6165_phy_write,
4536 .port_set_link = mv88e6xxx_port_set_link,
4537 .port_sync_link = mv88e6xxx_port_sync_link,
4538 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4539 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4540 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4541 .port_get_cmode = mv88e6185_port_get_cmode,
4542 .port_setup_message_port = mv88e6xxx_setup_message_port,
4543 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4544 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4545 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4546 .stats_get_strings = mv88e6095_stats_get_strings,
4547 .stats_get_stat = mv88e6095_stats_get_stat,
4548 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4549 .set_egress_port = mv88e6095_g1_set_egress_port,
4550 .watchdog_ops = &mv88e6097_watchdog_ops,
4551 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4552 .pot_clear = mv88e6xxx_g2_pot_clear,
4553 .reset = mv88e6352_g1_reset,
4554 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4555 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4556 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4557 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4558 .stu_getnext = mv88e6352_g1_stu_getnext,
4559 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4560 .avb_ops = &mv88e6165_avb_ops,
4561 .ptp_ops = &mv88e6165_ptp_ops,
4562 .phylink_get_caps = mv88e6185_phylink_get_caps,
4563 };
4564
4565 static const struct mv88e6xxx_ops mv88e6171_ops = {
4566 /* MV88E6XXX_FAMILY_6351 */
4567 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4568 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4569 .irl_init_all = mv88e6352_g2_irl_init_all,
4570 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4571 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4572 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4573 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4574 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4575 .port_set_link = mv88e6xxx_port_set_link,
4576 .port_sync_link = mv88e6xxx_port_sync_link,
4577 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4578 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4579 .port_tag_remap = mv88e6095_port_tag_remap,
4580 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4581 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4582 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4583 .port_set_ether_type = mv88e6351_port_set_ether_type,
4584 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4585 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4586 .port_pause_limit = mv88e6097_port_pause_limit,
4587 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4588 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4589 .port_get_cmode = mv88e6352_port_get_cmode,
4590 .port_setup_message_port = mv88e6xxx_setup_message_port,
4591 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4592 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4593 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4594 .stats_get_strings = mv88e6095_stats_get_strings,
4595 .stats_get_stat = mv88e6095_stats_get_stat,
4596 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4597 .set_egress_port = mv88e6095_g1_set_egress_port,
4598 .watchdog_ops = &mv88e6097_watchdog_ops,
4599 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4600 .pot_clear = mv88e6xxx_g2_pot_clear,
4601 .reset = mv88e6352_g1_reset,
4602 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4603 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4604 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4605 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4606 .stu_getnext = mv88e6352_g1_stu_getnext,
4607 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4608 .phylink_get_caps = mv88e6351_phylink_get_caps,
4609 };
4610
4611 static const struct mv88e6xxx_ops mv88e6172_ops = {
4612 /* MV88E6XXX_FAMILY_6352 */
4613 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4614 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4615 .irl_init_all = mv88e6352_g2_irl_init_all,
4616 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4617 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4619 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4620 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4621 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4622 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4623 .port_set_link = mv88e6xxx_port_set_link,
4624 .port_sync_link = mv88e6xxx_port_sync_link,
4625 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4626 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4627 .port_tag_remap = mv88e6095_port_tag_remap,
4628 .port_set_policy = mv88e6352_port_set_policy,
4629 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4630 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4631 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4632 .port_set_ether_type = mv88e6351_port_set_ether_type,
4633 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4634 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4635 .port_pause_limit = mv88e6097_port_pause_limit,
4636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4638 .port_get_cmode = mv88e6352_port_get_cmode,
4639 .port_setup_leds = mv88e6xxx_port_setup_leds,
4640 .port_setup_message_port = mv88e6xxx_setup_message_port,
4641 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4642 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4643 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4644 .stats_get_strings = mv88e6095_stats_get_strings,
4645 .stats_get_stat = mv88e6095_stats_get_stat,
4646 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4647 .set_egress_port = mv88e6095_g1_set_egress_port,
4648 .watchdog_ops = &mv88e6097_watchdog_ops,
4649 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4650 .pot_clear = mv88e6xxx_g2_pot_clear,
4651 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4652 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4653 .reset = mv88e6352_g1_reset,
4654 .rmu_disable = mv88e6352_g1_rmu_disable,
4655 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4656 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4657 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4658 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4659 .stu_getnext = mv88e6352_g1_stu_getnext,
4660 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4661 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4662 .serdes_get_regs = mv88e6352_serdes_get_regs,
4663 .gpio_ops = &mv88e6352_gpio_ops,
4664 .phylink_get_caps = mv88e6352_phylink_get_caps,
4665 .pcs_ops = &mv88e6352_pcs_ops,
4666 };
4667
4668 static const struct mv88e6xxx_ops mv88e6175_ops = {
4669 /* MV88E6XXX_FAMILY_6351 */
4670 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4671 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4672 .irl_init_all = mv88e6352_g2_irl_init_all,
4673 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4674 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4675 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4676 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4677 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4678 .port_set_link = mv88e6xxx_port_set_link,
4679 .port_sync_link = mv88e6xxx_port_sync_link,
4680 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4681 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4682 .port_tag_remap = mv88e6095_port_tag_remap,
4683 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4684 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4685 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4686 .port_set_ether_type = mv88e6351_port_set_ether_type,
4687 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4688 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4689 .port_pause_limit = mv88e6097_port_pause_limit,
4690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4692 .port_get_cmode = mv88e6352_port_get_cmode,
4693 .port_setup_message_port = mv88e6xxx_setup_message_port,
4694 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4695 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4696 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4697 .stats_get_strings = mv88e6095_stats_get_strings,
4698 .stats_get_stat = mv88e6095_stats_get_stat,
4699 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4700 .set_egress_port = mv88e6095_g1_set_egress_port,
4701 .watchdog_ops = &mv88e6097_watchdog_ops,
4702 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4703 .pot_clear = mv88e6xxx_g2_pot_clear,
4704 .reset = mv88e6352_g1_reset,
4705 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4706 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4707 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4708 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4709 .stu_getnext = mv88e6352_g1_stu_getnext,
4710 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4711 .phylink_get_caps = mv88e6351_phylink_get_caps,
4712 };
4713
4714 static const struct mv88e6xxx_ops mv88e6176_ops = {
4715 /* MV88E6XXX_FAMILY_6352 */
4716 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4717 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4718 .irl_init_all = mv88e6352_g2_irl_init_all,
4719 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4720 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4721 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4722 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4723 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4724 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4725 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4726 .port_set_link = mv88e6xxx_port_set_link,
4727 .port_sync_link = mv88e6xxx_port_sync_link,
4728 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4729 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4730 .port_tag_remap = mv88e6095_port_tag_remap,
4731 .port_set_policy = mv88e6352_port_set_policy,
4732 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4733 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4734 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4735 .port_set_ether_type = mv88e6351_port_set_ether_type,
4736 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4737 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4738 .port_pause_limit = mv88e6097_port_pause_limit,
4739 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4740 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4741 .port_get_cmode = mv88e6352_port_get_cmode,
4742 .port_setup_leds = mv88e6xxx_port_setup_leds,
4743 .port_setup_message_port = mv88e6xxx_setup_message_port,
4744 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4745 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4746 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4747 .stats_get_strings = mv88e6095_stats_get_strings,
4748 .stats_get_stat = mv88e6095_stats_get_stat,
4749 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4750 .set_egress_port = mv88e6095_g1_set_egress_port,
4751 .watchdog_ops = &mv88e6097_watchdog_ops,
4752 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4753 .pot_clear = mv88e6xxx_g2_pot_clear,
4754 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4755 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4756 .reset = mv88e6352_g1_reset,
4757 .rmu_disable = mv88e6352_g1_rmu_disable,
4758 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4759 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4760 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4761 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4762 .stu_getnext = mv88e6352_g1_stu_getnext,
4763 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4764 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4765 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4766 .serdes_get_regs = mv88e6352_serdes_get_regs,
4767 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4768 .gpio_ops = &mv88e6352_gpio_ops,
4769 .phylink_get_caps = mv88e6352_phylink_get_caps,
4770 .pcs_ops = &mv88e6352_pcs_ops,
4771 };
4772
4773 static const struct mv88e6xxx_ops mv88e6185_ops = {
4774 /* MV88E6XXX_FAMILY_6185 */
4775 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4776 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4777 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4778 .phy_read = mv88e6185_phy_ppu_read,
4779 .phy_write = mv88e6185_phy_ppu_write,
4780 .port_set_link = mv88e6xxx_port_set_link,
4781 .port_sync_link = mv88e6185_port_sync_link,
4782 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4783 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4784 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4785 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4786 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4787 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4788 .port_set_pause = mv88e6185_port_set_pause,
4789 .port_get_cmode = mv88e6185_port_get_cmode,
4790 .port_setup_message_port = mv88e6xxx_setup_message_port,
4791 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4792 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4793 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4794 .stats_get_strings = mv88e6095_stats_get_strings,
4795 .stats_get_stat = mv88e6095_stats_get_stat,
4796 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4797 .set_egress_port = mv88e6095_g1_set_egress_port,
4798 .watchdog_ops = &mv88e6097_watchdog_ops,
4799 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4800 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4801 .ppu_enable = mv88e6185_g1_ppu_enable,
4802 .ppu_disable = mv88e6185_g1_ppu_disable,
4803 .reset = mv88e6185_g1_reset,
4804 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4805 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4806 .phylink_get_caps = mv88e6185_phylink_get_caps,
4807 .pcs_ops = &mv88e6185_pcs_ops,
4808 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4809 };
4810
4811 static const struct mv88e6xxx_ops mv88e6190_ops = {
4812 /* MV88E6XXX_FAMILY_6390 */
4813 .setup_errata = mv88e6390_setup_errata,
4814 .irl_init_all = mv88e6390_g2_irl_init_all,
4815 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4816 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4817 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4818 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4819 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4820 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4821 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4822 .port_set_link = mv88e6xxx_port_set_link,
4823 .port_sync_link = mv88e6xxx_port_sync_link,
4824 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4825 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4826 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4827 .port_tag_remap = mv88e6390_port_tag_remap,
4828 .port_set_policy = mv88e6352_port_set_policy,
4829 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4830 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4831 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4832 .port_set_ether_type = mv88e6351_port_set_ether_type,
4833 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4834 .port_pause_limit = mv88e6390_port_pause_limit,
4835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4837 .port_get_cmode = mv88e6352_port_get_cmode,
4838 .port_set_cmode = mv88e6390_port_set_cmode,
4839 .port_setup_message_port = mv88e6xxx_setup_message_port,
4840 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4841 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4842 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4843 .stats_get_strings = mv88e6320_stats_get_strings,
4844 .stats_get_stat = mv88e6390_stats_get_stat,
4845 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4846 .set_egress_port = mv88e6390_g1_set_egress_port,
4847 .watchdog_ops = &mv88e6390_watchdog_ops,
4848 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4849 .pot_clear = mv88e6xxx_g2_pot_clear,
4850 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4851 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4852 .reset = mv88e6352_g1_reset,
4853 .rmu_disable = mv88e6390_g1_rmu_disable,
4854 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4855 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4856 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4857 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4858 .stu_getnext = mv88e6390_g1_stu_getnext,
4859 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4860 .serdes_get_lane = mv88e6390_serdes_get_lane,
4861 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4862 .serdes_get_strings = mv88e6390_serdes_get_strings,
4863 .serdes_get_stats = mv88e6390_serdes_get_stats,
4864 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4865 .serdes_get_regs = mv88e6390_serdes_get_regs,
4866 .gpio_ops = &mv88e6352_gpio_ops,
4867 .phylink_get_caps = mv88e6390_phylink_get_caps,
4868 .pcs_ops = &mv88e6390_pcs_ops,
4869 };
4870
4871 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4872 /* MV88E6XXX_FAMILY_6390 */
4873 .setup_errata = mv88e6390_setup_errata,
4874 .irl_init_all = mv88e6390_g2_irl_init_all,
4875 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4876 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4877 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4878 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4879 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4880 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4881 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4882 .port_set_link = mv88e6xxx_port_set_link,
4883 .port_sync_link = mv88e6xxx_port_sync_link,
4884 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4885 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4886 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4887 .port_tag_remap = mv88e6390_port_tag_remap,
4888 .port_set_policy = mv88e6352_port_set_policy,
4889 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4890 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4891 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4892 .port_set_ether_type = mv88e6351_port_set_ether_type,
4893 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4894 .port_pause_limit = mv88e6390_port_pause_limit,
4895 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4896 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4897 .port_get_cmode = mv88e6352_port_get_cmode,
4898 .port_set_cmode = mv88e6390x_port_set_cmode,
4899 .port_setup_message_port = mv88e6xxx_setup_message_port,
4900 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4901 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4902 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4903 .stats_get_strings = mv88e6320_stats_get_strings,
4904 .stats_get_stat = mv88e6390_stats_get_stat,
4905 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4906 .set_egress_port = mv88e6390_g1_set_egress_port,
4907 .watchdog_ops = &mv88e6390_watchdog_ops,
4908 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4909 .pot_clear = mv88e6xxx_g2_pot_clear,
4910 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4911 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4912 .reset = mv88e6352_g1_reset,
4913 .rmu_disable = mv88e6390_g1_rmu_disable,
4914 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4915 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4916 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4917 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4918 .stu_getnext = mv88e6390_g1_stu_getnext,
4919 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4920 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4921 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4922 .serdes_get_strings = mv88e6390_serdes_get_strings,
4923 .serdes_get_stats = mv88e6390_serdes_get_stats,
4924 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4925 .serdes_get_regs = mv88e6390_serdes_get_regs,
4926 .gpio_ops = &mv88e6352_gpio_ops,
4927 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4928 .pcs_ops = &mv88e6390_pcs_ops,
4929 };
4930
4931 static const struct mv88e6xxx_ops mv88e6191_ops = {
4932 /* MV88E6XXX_FAMILY_6390 */
4933 .setup_errata = mv88e6390_setup_errata,
4934 .irl_init_all = mv88e6390_g2_irl_init_all,
4935 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4936 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4937 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4938 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4939 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4940 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4941 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4942 .port_set_link = mv88e6xxx_port_set_link,
4943 .port_sync_link = mv88e6xxx_port_sync_link,
4944 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4945 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4946 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4947 .port_tag_remap = mv88e6390_port_tag_remap,
4948 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4949 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4950 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4951 .port_set_ether_type = mv88e6351_port_set_ether_type,
4952 .port_pause_limit = mv88e6390_port_pause_limit,
4953 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4954 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4955 .port_get_cmode = mv88e6352_port_get_cmode,
4956 .port_set_cmode = mv88e6390_port_set_cmode,
4957 .port_setup_message_port = mv88e6xxx_setup_message_port,
4958 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4959 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4960 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4961 .stats_get_strings = mv88e6320_stats_get_strings,
4962 .stats_get_stat = mv88e6390_stats_get_stat,
4963 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4964 .set_egress_port = mv88e6390_g1_set_egress_port,
4965 .watchdog_ops = &mv88e6390_watchdog_ops,
4966 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4967 .pot_clear = mv88e6xxx_g2_pot_clear,
4968 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4969 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4970 .reset = mv88e6352_g1_reset,
4971 .rmu_disable = mv88e6390_g1_rmu_disable,
4972 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4973 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4974 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4975 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4976 .stu_getnext = mv88e6390_g1_stu_getnext,
4977 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4978 .serdes_get_lane = mv88e6390_serdes_get_lane,
4979 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4980 .serdes_get_strings = mv88e6390_serdes_get_strings,
4981 .serdes_get_stats = mv88e6390_serdes_get_stats,
4982 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4983 .serdes_get_regs = mv88e6390_serdes_get_regs,
4984 .avb_ops = &mv88e6390_avb_ops,
4985 .ptp_ops = &mv88e6352_ptp_ops,
4986 .phylink_get_caps = mv88e6390_phylink_get_caps,
4987 .pcs_ops = &mv88e6390_pcs_ops,
4988 };
4989
4990 static const struct mv88e6xxx_ops mv88e6240_ops = {
4991 /* MV88E6XXX_FAMILY_6352 */
4992 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4993 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4994 .irl_init_all = mv88e6352_g2_irl_init_all,
4995 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4996 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4998 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4999 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5000 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5001 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5002 .port_set_link = mv88e6xxx_port_set_link,
5003 .port_sync_link = mv88e6xxx_port_sync_link,
5004 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5005 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5006 .port_tag_remap = mv88e6095_port_tag_remap,
5007 .port_set_policy = mv88e6352_port_set_policy,
5008 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5009 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5010 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5011 .port_set_ether_type = mv88e6351_port_set_ether_type,
5012 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5013 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5014 .port_pause_limit = mv88e6097_port_pause_limit,
5015 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5016 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5017 .port_get_cmode = mv88e6352_port_get_cmode,
5018 .port_setup_leds = mv88e6xxx_port_setup_leds,
5019 .port_setup_message_port = mv88e6xxx_setup_message_port,
5020 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5021 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5022 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5023 .stats_get_strings = mv88e6095_stats_get_strings,
5024 .stats_get_stat = mv88e6095_stats_get_stat,
5025 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5026 .set_egress_port = mv88e6095_g1_set_egress_port,
5027 .watchdog_ops = &mv88e6097_watchdog_ops,
5028 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5029 .pot_clear = mv88e6xxx_g2_pot_clear,
5030 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5031 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5032 .reset = mv88e6352_g1_reset,
5033 .rmu_disable = mv88e6352_g1_rmu_disable,
5034 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5035 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5036 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5037 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5038 .stu_getnext = mv88e6352_g1_stu_getnext,
5039 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5040 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5041 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5042 .serdes_get_regs = mv88e6352_serdes_get_regs,
5043 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5044 .gpio_ops = &mv88e6352_gpio_ops,
5045 .avb_ops = &mv88e6352_avb_ops,
5046 .ptp_ops = &mv88e6352_ptp_ops,
5047 .phylink_get_caps = mv88e6352_phylink_get_caps,
5048 .pcs_ops = &mv88e6352_pcs_ops,
5049 };
5050
5051 static const struct mv88e6xxx_ops mv88e6250_ops = {
5052 /* MV88E6XXX_FAMILY_6250 */
5053 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5054 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5055 .irl_init_all = mv88e6352_g2_irl_init_all,
5056 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5057 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5058 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5059 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5060 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5061 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5062 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5063 .port_set_link = mv88e6xxx_port_set_link,
5064 .port_sync_link = mv88e6xxx_port_sync_link,
5065 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5066 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5067 .port_tag_remap = mv88e6095_port_tag_remap,
5068 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5069 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5070 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5071 .port_set_ether_type = mv88e6351_port_set_ether_type,
5072 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5073 .port_pause_limit = mv88e6097_port_pause_limit,
5074 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5075 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5076 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5077 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5078 .stats_get_strings = mv88e6250_stats_get_strings,
5079 .stats_get_stat = mv88e6250_stats_get_stat,
5080 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5081 .set_egress_port = mv88e6095_g1_set_egress_port,
5082 .watchdog_ops = &mv88e6250_watchdog_ops,
5083 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5084 .pot_clear = mv88e6xxx_g2_pot_clear,
5085 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
5086 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
5087 .reset = mv88e6250_g1_reset,
5088 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5089 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5090 .avb_ops = &mv88e6352_avb_ops,
5091 .ptp_ops = &mv88e6250_ptp_ops,
5092 .phylink_get_caps = mv88e6250_phylink_get_caps,
5093 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
5094 };
5095
5096 static const struct mv88e6xxx_ops mv88e6290_ops = {
5097 /* MV88E6XXX_FAMILY_6390 */
5098 .setup_errata = mv88e6390_setup_errata,
5099 .irl_init_all = mv88e6390_g2_irl_init_all,
5100 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5101 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5102 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5103 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5104 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5105 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5106 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5107 .port_set_link = mv88e6xxx_port_set_link,
5108 .port_sync_link = mv88e6xxx_port_sync_link,
5109 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5110 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5111 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5112 .port_tag_remap = mv88e6390_port_tag_remap,
5113 .port_set_policy = mv88e6352_port_set_policy,
5114 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5115 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5116 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5117 .port_set_ether_type = mv88e6351_port_set_ether_type,
5118 .port_pause_limit = mv88e6390_port_pause_limit,
5119 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5120 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5121 .port_get_cmode = mv88e6352_port_get_cmode,
5122 .port_set_cmode = mv88e6390_port_set_cmode,
5123 .port_setup_message_port = mv88e6xxx_setup_message_port,
5124 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5125 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5126 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5127 .stats_get_strings = mv88e6320_stats_get_strings,
5128 .stats_get_stat = mv88e6390_stats_get_stat,
5129 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5130 .set_egress_port = mv88e6390_g1_set_egress_port,
5131 .watchdog_ops = &mv88e6390_watchdog_ops,
5132 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5133 .pot_clear = mv88e6xxx_g2_pot_clear,
5134 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5135 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5136 .reset = mv88e6352_g1_reset,
5137 .rmu_disable = mv88e6390_g1_rmu_disable,
5138 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5139 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5140 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5141 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5142 .stu_getnext = mv88e6390_g1_stu_getnext,
5143 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5144 .serdes_get_lane = mv88e6390_serdes_get_lane,
5145 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5146 .serdes_get_strings = mv88e6390_serdes_get_strings,
5147 .serdes_get_stats = mv88e6390_serdes_get_stats,
5148 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5149 .serdes_get_regs = mv88e6390_serdes_get_regs,
5150 .gpio_ops = &mv88e6352_gpio_ops,
5151 .avb_ops = &mv88e6390_avb_ops,
5152 .ptp_ops = &mv88e6390_ptp_ops,
5153 .phylink_get_caps = mv88e6390_phylink_get_caps,
5154 .pcs_ops = &mv88e6390_pcs_ops,
5155 };
5156
5157 static const struct mv88e6xxx_ops mv88e6320_ops = {
5158 /* MV88E6XXX_FAMILY_6320 */
5159 .setup_errata = mv88e6320_setup_errata,
5160 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5161 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5162 .irl_init_all = mv88e6352_g2_irl_init_all,
5163 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5164 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5165 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5166 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5167 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5168 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5169 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5170 .port_set_link = mv88e6xxx_port_set_link,
5171 .port_sync_link = mv88e6xxx_port_sync_link,
5172 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5173 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5174 .port_tag_remap = mv88e6095_port_tag_remap,
5175 .port_set_policy = mv88e6352_port_set_policy,
5176 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5177 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5178 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5179 .port_set_ether_type = mv88e6351_port_set_ether_type,
5180 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5181 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5182 .port_pause_limit = mv88e6097_port_pause_limit,
5183 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5184 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5185 .port_get_cmode = mv88e6352_port_get_cmode,
5186 .port_setup_message_port = mv88e6xxx_setup_message_port,
5187 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5188 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5189 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5190 .stats_get_strings = mv88e6320_stats_get_strings,
5191 .stats_get_stat = mv88e6320_stats_get_stat,
5192 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5193 .set_egress_port = mv88e6095_g1_set_egress_port,
5194 .watchdog_ops = &mv88e6390_watchdog_ops,
5195 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5196 .pot_clear = mv88e6xxx_g2_pot_clear,
5197 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5198 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5199 .reset = mv88e6352_g1_reset,
5200 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5201 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5202 .stu_getnext = mv88e6352_g1_stu_getnext,
5203 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5204 .gpio_ops = &mv88e6352_gpio_ops,
5205 .avb_ops = &mv88e6352_avb_ops,
5206 .ptp_ops = &mv88e6352_ptp_ops,
5207 .phylink_get_caps = mv88e632x_phylink_get_caps,
5208 };
5209
5210 static const struct mv88e6xxx_ops mv88e6321_ops = {
5211 /* MV88E6XXX_FAMILY_6320 */
5212 .setup_errata = mv88e6320_setup_errata,
5213 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5214 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5215 .irl_init_all = mv88e6352_g2_irl_init_all,
5216 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5217 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5219 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5220 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5221 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5222 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5223 .port_set_link = mv88e6xxx_port_set_link,
5224 .port_sync_link = mv88e6xxx_port_sync_link,
5225 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5227 .port_tag_remap = mv88e6095_port_tag_remap,
5228 .port_set_policy = mv88e6352_port_set_policy,
5229 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5230 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5231 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5232 .port_set_ether_type = mv88e6351_port_set_ether_type,
5233 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5234 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5235 .port_pause_limit = mv88e6097_port_pause_limit,
5236 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5237 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5238 .port_get_cmode = mv88e6352_port_get_cmode,
5239 .port_setup_message_port = mv88e6xxx_setup_message_port,
5240 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5241 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5242 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5243 .stats_get_strings = mv88e6320_stats_get_strings,
5244 .stats_get_stat = mv88e6320_stats_get_stat,
5245 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5246 .set_egress_port = mv88e6095_g1_set_egress_port,
5247 .watchdog_ops = &mv88e6390_watchdog_ops,
5248 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5249 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5250 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5251 .reset = mv88e6352_g1_reset,
5252 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5253 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5254 .stu_getnext = mv88e6352_g1_stu_getnext,
5255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5256 .gpio_ops = &mv88e6352_gpio_ops,
5257 .avb_ops = &mv88e6352_avb_ops,
5258 .ptp_ops = &mv88e6352_ptp_ops,
5259 .phylink_get_caps = mv88e632x_phylink_get_caps,
5260 };
5261
5262 static const struct mv88e6xxx_ops mv88e6341_ops = {
5263 /* MV88E6XXX_FAMILY_6341 */
5264 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5265 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5266 .irl_init_all = mv88e6352_g2_irl_init_all,
5267 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5268 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5270 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5271 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5272 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5273 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5274 .port_set_link = mv88e6xxx_port_set_link,
5275 .port_sync_link = mv88e6xxx_port_sync_link,
5276 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5277 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5278 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5279 .port_tag_remap = mv88e6095_port_tag_remap,
5280 .port_set_policy = mv88e6352_port_set_policy,
5281 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5282 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5283 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5284 .port_set_ether_type = mv88e6351_port_set_ether_type,
5285 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5286 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5287 .port_pause_limit = mv88e6097_port_pause_limit,
5288 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5289 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5290 .port_get_cmode = mv88e6352_port_get_cmode,
5291 .port_set_cmode = mv88e6341_port_set_cmode,
5292 .port_setup_message_port = mv88e6xxx_setup_message_port,
5293 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5294 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5295 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5296 .stats_get_strings = mv88e6320_stats_get_strings,
5297 .stats_get_stat = mv88e6390_stats_get_stat,
5298 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5299 .set_egress_port = mv88e6390_g1_set_egress_port,
5300 .watchdog_ops = &mv88e6390_watchdog_ops,
5301 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5302 .pot_clear = mv88e6xxx_g2_pot_clear,
5303 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5304 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5305 .reset = mv88e6352_g1_reset,
5306 .rmu_disable = mv88e6390_g1_rmu_disable,
5307 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5308 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5309 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5310 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5311 .stu_getnext = mv88e6352_g1_stu_getnext,
5312 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5313 .serdes_get_lane = mv88e6341_serdes_get_lane,
5314 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5315 .gpio_ops = &mv88e6352_gpio_ops,
5316 .avb_ops = &mv88e6390_avb_ops,
5317 .ptp_ops = &mv88e6352_ptp_ops,
5318 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5319 .serdes_get_strings = mv88e6390_serdes_get_strings,
5320 .serdes_get_stats = mv88e6390_serdes_get_stats,
5321 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5322 .serdes_get_regs = mv88e6390_serdes_get_regs,
5323 .phylink_get_caps = mv88e6341_phylink_get_caps,
5324 .pcs_ops = &mv88e6390_pcs_ops,
5325 };
5326
5327 static const struct mv88e6xxx_ops mv88e6350_ops = {
5328 /* MV88E6XXX_FAMILY_6351 */
5329 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5330 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5331 .irl_init_all = mv88e6352_g2_irl_init_all,
5332 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5333 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5334 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5335 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5336 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5337 .port_set_link = mv88e6xxx_port_set_link,
5338 .port_sync_link = mv88e6xxx_port_sync_link,
5339 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5340 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5341 .port_tag_remap = mv88e6095_port_tag_remap,
5342 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5343 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5344 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5345 .port_set_ether_type = mv88e6351_port_set_ether_type,
5346 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5347 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5348 .port_pause_limit = mv88e6097_port_pause_limit,
5349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5351 .port_get_cmode = mv88e6352_port_get_cmode,
5352 .port_setup_message_port = mv88e6xxx_setup_message_port,
5353 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5354 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5355 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5356 .stats_get_strings = mv88e6095_stats_get_strings,
5357 .stats_get_stat = mv88e6095_stats_get_stat,
5358 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5359 .set_egress_port = mv88e6095_g1_set_egress_port,
5360 .watchdog_ops = &mv88e6097_watchdog_ops,
5361 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5362 .pot_clear = mv88e6xxx_g2_pot_clear,
5363 .reset = mv88e6352_g1_reset,
5364 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5365 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5366 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5367 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5368 .stu_getnext = mv88e6352_g1_stu_getnext,
5369 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5370 .phylink_get_caps = mv88e6351_phylink_get_caps,
5371 };
5372
5373 static const struct mv88e6xxx_ops mv88e6351_ops = {
5374 /* MV88E6XXX_FAMILY_6351 */
5375 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5376 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5377 .irl_init_all = mv88e6352_g2_irl_init_all,
5378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5379 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5380 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5381 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5382 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5383 .port_set_link = mv88e6xxx_port_set_link,
5384 .port_sync_link = mv88e6xxx_port_sync_link,
5385 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5386 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5387 .port_tag_remap = mv88e6095_port_tag_remap,
5388 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5389 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5390 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5391 .port_set_ether_type = mv88e6351_port_set_ether_type,
5392 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5393 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5394 .port_pause_limit = mv88e6097_port_pause_limit,
5395 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5396 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5397 .port_get_cmode = mv88e6352_port_get_cmode,
5398 .port_setup_message_port = mv88e6xxx_setup_message_port,
5399 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5400 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5401 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5402 .stats_get_strings = mv88e6095_stats_get_strings,
5403 .stats_get_stat = mv88e6095_stats_get_stat,
5404 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5405 .set_egress_port = mv88e6095_g1_set_egress_port,
5406 .watchdog_ops = &mv88e6097_watchdog_ops,
5407 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5408 .pot_clear = mv88e6xxx_g2_pot_clear,
5409 .reset = mv88e6352_g1_reset,
5410 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5411 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5412 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5413 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5414 .stu_getnext = mv88e6352_g1_stu_getnext,
5415 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5416 .avb_ops = &mv88e6352_avb_ops,
5417 .ptp_ops = &mv88e6352_ptp_ops,
5418 .phylink_get_caps = mv88e6351_phylink_get_caps,
5419 };
5420
5421 static const struct mv88e6xxx_ops mv88e6352_ops = {
5422 /* MV88E6XXX_FAMILY_6352 */
5423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5424 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5425 .irl_init_all = mv88e6352_g2_irl_init_all,
5426 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5427 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5429 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5430 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5431 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5432 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5433 .port_set_link = mv88e6xxx_port_set_link,
5434 .port_sync_link = mv88e6xxx_port_sync_link,
5435 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5436 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5437 .port_tag_remap = mv88e6095_port_tag_remap,
5438 .port_set_policy = mv88e6352_port_set_policy,
5439 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5440 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5441 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5442 .port_set_ether_type = mv88e6351_port_set_ether_type,
5443 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5444 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5445 .port_pause_limit = mv88e6097_port_pause_limit,
5446 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5447 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5448 .port_get_cmode = mv88e6352_port_get_cmode,
5449 .port_setup_leds = mv88e6xxx_port_setup_leds,
5450 .port_setup_message_port = mv88e6xxx_setup_message_port,
5451 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5452 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5453 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5454 .stats_get_strings = mv88e6095_stats_get_strings,
5455 .stats_get_stat = mv88e6095_stats_get_stat,
5456 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5457 .set_egress_port = mv88e6095_g1_set_egress_port,
5458 .watchdog_ops = &mv88e6097_watchdog_ops,
5459 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5460 .pot_clear = mv88e6xxx_g2_pot_clear,
5461 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5462 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5463 .reset = mv88e6352_g1_reset,
5464 .rmu_disable = mv88e6352_g1_rmu_disable,
5465 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5466 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5467 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5468 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5469 .stu_getnext = mv88e6352_g1_stu_getnext,
5470 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5471 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5472 .gpio_ops = &mv88e6352_gpio_ops,
5473 .avb_ops = &mv88e6352_avb_ops,
5474 .ptp_ops = &mv88e6352_ptp_ops,
5475 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5476 .serdes_get_strings = mv88e6352_serdes_get_strings,
5477 .serdes_get_stats = mv88e6352_serdes_get_stats,
5478 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5479 .serdes_get_regs = mv88e6352_serdes_get_regs,
5480 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5481 .phylink_get_caps = mv88e6352_phylink_get_caps,
5482 .pcs_ops = &mv88e6352_pcs_ops,
5483 };
5484
5485 static const struct mv88e6xxx_ops mv88e6390_ops = {
5486 /* MV88E6XXX_FAMILY_6390 */
5487 .setup_errata = mv88e6390_setup_errata,
5488 .irl_init_all = mv88e6390_g2_irl_init_all,
5489 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5490 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5491 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5492 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5493 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5494 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5495 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5496 .port_set_link = mv88e6xxx_port_set_link,
5497 .port_sync_link = mv88e6xxx_port_sync_link,
5498 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5499 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5500 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5501 .port_tag_remap = mv88e6390_port_tag_remap,
5502 .port_set_policy = mv88e6352_port_set_policy,
5503 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5504 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5505 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5506 .port_set_ether_type = mv88e6351_port_set_ether_type,
5507 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5508 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5509 .port_pause_limit = mv88e6390_port_pause_limit,
5510 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5511 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5512 .port_get_cmode = mv88e6352_port_get_cmode,
5513 .port_set_cmode = mv88e6390_port_set_cmode,
5514 .port_setup_message_port = mv88e6xxx_setup_message_port,
5515 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5516 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5517 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5518 .stats_get_strings = mv88e6320_stats_get_strings,
5519 .stats_get_stat = mv88e6390_stats_get_stat,
5520 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5521 .set_egress_port = mv88e6390_g1_set_egress_port,
5522 .watchdog_ops = &mv88e6390_watchdog_ops,
5523 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5524 .pot_clear = mv88e6xxx_g2_pot_clear,
5525 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5526 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5527 .reset = mv88e6352_g1_reset,
5528 .rmu_disable = mv88e6390_g1_rmu_disable,
5529 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5530 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5531 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5532 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5533 .stu_getnext = mv88e6390_g1_stu_getnext,
5534 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5535 .serdes_get_lane = mv88e6390_serdes_get_lane,
5536 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5537 .gpio_ops = &mv88e6352_gpio_ops,
5538 .avb_ops = &mv88e6390_avb_ops,
5539 .ptp_ops = &mv88e6390_ptp_ops,
5540 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5541 .serdes_get_strings = mv88e6390_serdes_get_strings,
5542 .serdes_get_stats = mv88e6390_serdes_get_stats,
5543 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5544 .serdes_get_regs = mv88e6390_serdes_get_regs,
5545 .phylink_get_caps = mv88e6390_phylink_get_caps,
5546 .pcs_ops = &mv88e6390_pcs_ops,
5547 };
5548
5549 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5550 /* MV88E6XXX_FAMILY_6390 */
5551 .setup_errata = mv88e6390_setup_errata,
5552 .irl_init_all = mv88e6390_g2_irl_init_all,
5553 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5554 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5556 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5557 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5558 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5559 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5560 .port_set_link = mv88e6xxx_port_set_link,
5561 .port_sync_link = mv88e6xxx_port_sync_link,
5562 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5563 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5564 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5565 .port_tag_remap = mv88e6390_port_tag_remap,
5566 .port_set_policy = mv88e6352_port_set_policy,
5567 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5568 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5569 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5570 .port_set_ether_type = mv88e6351_port_set_ether_type,
5571 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5573 .port_pause_limit = mv88e6390_port_pause_limit,
5574 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5575 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5576 .port_get_cmode = mv88e6352_port_get_cmode,
5577 .port_set_cmode = mv88e6390x_port_set_cmode,
5578 .port_setup_message_port = mv88e6xxx_setup_message_port,
5579 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5581 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5582 .stats_get_strings = mv88e6320_stats_get_strings,
5583 .stats_get_stat = mv88e6390_stats_get_stat,
5584 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5585 .set_egress_port = mv88e6390_g1_set_egress_port,
5586 .watchdog_ops = &mv88e6390_watchdog_ops,
5587 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5588 .pot_clear = mv88e6xxx_g2_pot_clear,
5589 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5590 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5591 .reset = mv88e6352_g1_reset,
5592 .rmu_disable = mv88e6390_g1_rmu_disable,
5593 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5594 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5595 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5596 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5597 .stu_getnext = mv88e6390_g1_stu_getnext,
5598 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5599 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5600 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5601 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5602 .serdes_get_strings = mv88e6390_serdes_get_strings,
5603 .serdes_get_stats = mv88e6390_serdes_get_stats,
5604 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5605 .serdes_get_regs = mv88e6390_serdes_get_regs,
5606 .gpio_ops = &mv88e6352_gpio_ops,
5607 .avb_ops = &mv88e6390_avb_ops,
5608 .ptp_ops = &mv88e6390_ptp_ops,
5609 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5610 .pcs_ops = &mv88e6390_pcs_ops,
5611 };
5612
5613 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5614 /* MV88E6XXX_FAMILY_6393 */
5615 .irl_init_all = mv88e6390_g2_irl_init_all,
5616 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5617 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5619 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5620 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5621 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5622 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5623 .port_set_link = mv88e6xxx_port_set_link,
5624 .port_sync_link = mv88e6xxx_port_sync_link,
5625 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5626 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5627 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5628 .port_tag_remap = mv88e6390_port_tag_remap,
5629 .port_set_policy = mv88e6393x_port_set_policy,
5630 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5633 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5636 .port_pause_limit = mv88e6390_port_pause_limit,
5637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5639 .port_get_cmode = mv88e6352_port_get_cmode,
5640 .port_set_cmode = mv88e6393x_port_set_cmode,
5641 .port_setup_message_port = mv88e6xxx_setup_message_port,
5642 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5643 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5644 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5645 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5646 .stats_get_strings = mv88e6320_stats_get_strings,
5647 .stats_get_stat = mv88e6390_stats_get_stat,
5648 /* .set_cpu_port is missing because this family does not support a global
5649 * CPU port, only per port CPU port which is set via
5650 * .port_set_upstream_port method.
5651 */
5652 .set_egress_port = mv88e6393x_set_egress_port,
5653 .watchdog_ops = &mv88e6393x_watchdog_ops,
5654 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5655 .pot_clear = mv88e6xxx_g2_pot_clear,
5656 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5657 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5658 .reset = mv88e6352_g1_reset,
5659 .rmu_disable = mv88e6390_g1_rmu_disable,
5660 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5661 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5662 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5663 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5664 .stu_getnext = mv88e6390_g1_stu_getnext,
5665 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5666 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5667 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5668 /* TODO: serdes stats */
5669 .gpio_ops = &mv88e6352_gpio_ops,
5670 .avb_ops = &mv88e6390_avb_ops,
5671 .ptp_ops = &mv88e6352_ptp_ops,
5672 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5673 .pcs_ops = &mv88e6393x_pcs_ops,
5674 };
5675
5676 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5677 [MV88E6020] = {
5678 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5679 .family = MV88E6XXX_FAMILY_6250,
5680 .name = "Marvell 88E6020",
5681 .num_databases = 64,
5682 /* Ports 2-4 are not routed to pins
5683 * => usable ports 0, 1, 5, 6
5684 */
5685 .num_ports = 7,
5686 .num_internal_phys = 2,
5687 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5688 .max_vid = 4095,
5689 .port_base_addr = 0x8,
5690 .phy_base_addr = 0x0,
5691 .global1_addr = 0xf,
5692 .global2_addr = 0x7,
5693 .age_time_coeff = 15000,
5694 .g1_irqs = 9,
5695 .g2_irqs = 5,
5696 .stats_type = STATS_TYPE_BANK0,
5697 .atu_move_port_mask = 0xf,
5698 .dual_chip = true,
5699 .ops = &mv88e6250_ops,
5700 },
5701
5702 [MV88E6071] = {
5703 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5704 .family = MV88E6XXX_FAMILY_6250,
5705 .name = "Marvell 88E6071",
5706 .num_databases = 64,
5707 .num_ports = 7,
5708 .num_internal_phys = 5,
5709 .max_vid = 4095,
5710 .port_base_addr = 0x08,
5711 .phy_base_addr = 0x00,
5712 .global1_addr = 0x0f,
5713 .global2_addr = 0x07,
5714 .age_time_coeff = 15000,
5715 .g1_irqs = 9,
5716 .g2_irqs = 5,
5717 .stats_type = STATS_TYPE_BANK0,
5718 .atu_move_port_mask = 0xf,
5719 .dual_chip = true,
5720 .ops = &mv88e6250_ops,
5721 },
5722
5723 [MV88E6085] = {
5724 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5725 .family = MV88E6XXX_FAMILY_6097,
5726 .name = "Marvell 88E6085",
5727 .num_databases = 4096,
5728 .num_macs = 8192,
5729 .num_ports = 10,
5730 .num_internal_phys = 5,
5731 .max_vid = 4095,
5732 .max_sid = 63,
5733 .port_base_addr = 0x10,
5734 .phy_base_addr = 0x0,
5735 .global1_addr = 0x1b,
5736 .global2_addr = 0x1c,
5737 .age_time_coeff = 15000,
5738 .g1_irqs = 8,
5739 .g2_irqs = 10,
5740 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5741 .atu_move_port_mask = 0xf,
5742 .pvt = true,
5743 .multi_chip = true,
5744 .ops = &mv88e6085_ops,
5745 },
5746
5747 [MV88E6095] = {
5748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5749 .family = MV88E6XXX_FAMILY_6095,
5750 .name = "Marvell 88E6095/88E6095F",
5751 .num_databases = 256,
5752 .num_macs = 8192,
5753 .num_ports = 11,
5754 .num_internal_phys = 0,
5755 .max_vid = 4095,
5756 .port_base_addr = 0x10,
5757 .phy_base_addr = 0x0,
5758 .global1_addr = 0x1b,
5759 .global2_addr = 0x1c,
5760 .age_time_coeff = 15000,
5761 .g1_irqs = 8,
5762 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5763 .atu_move_port_mask = 0xf,
5764 .multi_chip = true,
5765 .ops = &mv88e6095_ops,
5766 },
5767
5768 [MV88E6097] = {
5769 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5770 .family = MV88E6XXX_FAMILY_6097,
5771 .name = "Marvell 88E6097/88E6097F",
5772 .num_databases = 4096,
5773 .num_macs = 8192,
5774 .num_ports = 11,
5775 .num_internal_phys = 8,
5776 .max_vid = 4095,
5777 .max_sid = 63,
5778 .port_base_addr = 0x10,
5779 .phy_base_addr = 0x0,
5780 .global1_addr = 0x1b,
5781 .global2_addr = 0x1c,
5782 .age_time_coeff = 15000,
5783 .g1_irqs = 8,
5784 .g2_irqs = 10,
5785 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5786 .atu_move_port_mask = 0xf,
5787 .pvt = true,
5788 .multi_chip = true,
5789 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5790 .ops = &mv88e6097_ops,
5791 },
5792
5793 [MV88E6123] = {
5794 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5795 .family = MV88E6XXX_FAMILY_6165,
5796 .name = "Marvell 88E6123",
5797 .num_databases = 4096,
5798 .num_macs = 1024,
5799 .num_ports = 3,
5800 .num_internal_phys = 5,
5801 .max_vid = 4095,
5802 .max_sid = 63,
5803 .port_base_addr = 0x10,
5804 .phy_base_addr = 0x0,
5805 .global1_addr = 0x1b,
5806 .global2_addr = 0x1c,
5807 .age_time_coeff = 15000,
5808 .g1_irqs = 9,
5809 .g2_irqs = 10,
5810 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5811 .atu_move_port_mask = 0xf,
5812 .pvt = true,
5813 .multi_chip = true,
5814 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5815 .ops = &mv88e6123_ops,
5816 },
5817
5818 [MV88E6131] = {
5819 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5820 .family = MV88E6XXX_FAMILY_6185,
5821 .name = "Marvell 88E6131",
5822 .num_databases = 256,
5823 .num_macs = 8192,
5824 .num_ports = 8,
5825 .num_internal_phys = 0,
5826 .max_vid = 4095,
5827 .port_base_addr = 0x10,
5828 .phy_base_addr = 0x0,
5829 .global1_addr = 0x1b,
5830 .global2_addr = 0x1c,
5831 .age_time_coeff = 15000,
5832 .g1_irqs = 9,
5833 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5834 .atu_move_port_mask = 0xf,
5835 .multi_chip = true,
5836 .ops = &mv88e6131_ops,
5837 },
5838
5839 [MV88E6141] = {
5840 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5841 .family = MV88E6XXX_FAMILY_6341,
5842 .name = "Marvell 88E6141",
5843 .num_databases = 256,
5844 .num_macs = 2048,
5845 .num_ports = 6,
5846 .num_internal_phys = 5,
5847 .num_gpio = 11,
5848 .max_vid = 4095,
5849 .max_sid = 63,
5850 .port_base_addr = 0x10,
5851 .phy_base_addr = 0x10,
5852 .global1_addr = 0x1b,
5853 .global2_addr = 0x1c,
5854 .age_time_coeff = 3750,
5855 .atu_move_port_mask = 0xf,
5856 .g1_irqs = 9,
5857 .g2_irqs = 10,
5858 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
5859 .pvt = true,
5860 .multi_chip = true,
5861 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5862 .ops = &mv88e6141_ops,
5863 },
5864
5865 [MV88E6161] = {
5866 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5867 .family = MV88E6XXX_FAMILY_6165,
5868 .name = "Marvell 88E6161",
5869 .num_databases = 4096,
5870 .num_macs = 1024,
5871 .num_ports = 6,
5872 .num_internal_phys = 5,
5873 .max_vid = 4095,
5874 .max_sid = 63,
5875 .port_base_addr = 0x10,
5876 .phy_base_addr = 0x0,
5877 .global1_addr = 0x1b,
5878 .global2_addr = 0x1c,
5879 .age_time_coeff = 15000,
5880 .g1_irqs = 9,
5881 .g2_irqs = 10,
5882 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5883 .atu_move_port_mask = 0xf,
5884 .pvt = true,
5885 .multi_chip = true,
5886 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5887 .ptp_support = true,
5888 .ops = &mv88e6161_ops,
5889 },
5890
5891 [MV88E6165] = {
5892 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5893 .family = MV88E6XXX_FAMILY_6165,
5894 .name = "Marvell 88E6165",
5895 .num_databases = 4096,
5896 .num_macs = 8192,
5897 .num_ports = 6,
5898 .num_internal_phys = 0,
5899 .max_vid = 4095,
5900 .max_sid = 63,
5901 .port_base_addr = 0x10,
5902 .phy_base_addr = 0x0,
5903 .global1_addr = 0x1b,
5904 .global2_addr = 0x1c,
5905 .age_time_coeff = 15000,
5906 .g1_irqs = 9,
5907 .g2_irqs = 10,
5908 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5909 .atu_move_port_mask = 0xf,
5910 .pvt = true,
5911 .multi_chip = true,
5912 .ptp_support = true,
5913 .ops = &mv88e6165_ops,
5914 },
5915
5916 [MV88E6171] = {
5917 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5918 .family = MV88E6XXX_FAMILY_6351,
5919 .name = "Marvell 88E6171",
5920 .num_databases = 4096,
5921 .num_macs = 8192,
5922 .num_ports = 7,
5923 .num_internal_phys = 5,
5924 .max_vid = 4095,
5925 .max_sid = 63,
5926 .port_base_addr = 0x10,
5927 .phy_base_addr = 0x0,
5928 .global1_addr = 0x1b,
5929 .global2_addr = 0x1c,
5930 .age_time_coeff = 15000,
5931 .g1_irqs = 9,
5932 .g2_irqs = 10,
5933 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
5934 .atu_move_port_mask = 0xf,
5935 .pvt = true,
5936 .multi_chip = true,
5937 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5938 .ops = &mv88e6171_ops,
5939 },
5940
5941 [MV88E6172] = {
5942 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5943 .family = MV88E6XXX_FAMILY_6352,
5944 .name = "Marvell 88E6172",
5945 .num_databases = 4096,
5946 .num_macs = 8192,
5947 .num_ports = 7,
5948 .num_internal_phys = 5,
5949 .num_gpio = 15,
5950 .max_vid = 4095,
5951 .max_sid = 63,
5952 .port_base_addr = 0x10,
5953 .phy_base_addr = 0x0,
5954 .global1_addr = 0x1b,
5955 .global2_addr = 0x1c,
5956 .age_time_coeff = 15000,
5957 .g1_irqs = 9,
5958 .g2_irqs = 10,
5959 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5960 .atu_move_port_mask = 0xf,
5961 .pvt = true,
5962 .multi_chip = true,
5963 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5964 .ops = &mv88e6172_ops,
5965 },
5966
5967 [MV88E6175] = {
5968 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5969 .family = MV88E6XXX_FAMILY_6351,
5970 .name = "Marvell 88E6175",
5971 .num_databases = 4096,
5972 .num_macs = 8192,
5973 .num_ports = 7,
5974 .num_internal_phys = 5,
5975 .max_vid = 4095,
5976 .max_sid = 63,
5977 .port_base_addr = 0x10,
5978 .phy_base_addr = 0x0,
5979 .global1_addr = 0x1b,
5980 .global2_addr = 0x1c,
5981 .age_time_coeff = 15000,
5982 .g1_irqs = 9,
5983 .g2_irqs = 10,
5984 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
5985 .atu_move_port_mask = 0xf,
5986 .pvt = true,
5987 .multi_chip = true,
5988 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5989 .ops = &mv88e6175_ops,
5990 },
5991
5992 [MV88E6176] = {
5993 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5994 .family = MV88E6XXX_FAMILY_6352,
5995 .name = "Marvell 88E6176",
5996 .num_databases = 4096,
5997 .num_macs = 8192,
5998 .num_ports = 7,
5999 .num_internal_phys = 5,
6000 .num_gpio = 15,
6001 .max_vid = 4095,
6002 .max_sid = 63,
6003 .port_base_addr = 0x10,
6004 .phy_base_addr = 0x0,
6005 .global1_addr = 0x1b,
6006 .global2_addr = 0x1c,
6007 .age_time_coeff = 15000,
6008 .g1_irqs = 9,
6009 .g2_irqs = 10,
6010 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6011 .atu_move_port_mask = 0xf,
6012 .pvt = true,
6013 .multi_chip = true,
6014 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6015 .ops = &mv88e6176_ops,
6016 },
6017
6018 [MV88E6185] = {
6019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
6020 .family = MV88E6XXX_FAMILY_6185,
6021 .name = "Marvell 88E6185",
6022 .num_databases = 256,
6023 .num_macs = 8192,
6024 .num_ports = 10,
6025 .num_internal_phys = 0,
6026 .max_vid = 4095,
6027 .port_base_addr = 0x10,
6028 .phy_base_addr = 0x0,
6029 .global1_addr = 0x1b,
6030 .global2_addr = 0x1c,
6031 .age_time_coeff = 15000,
6032 .g1_irqs = 8,
6033 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6034 .atu_move_port_mask = 0xf,
6035 .multi_chip = true,
6036 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6037 .ops = &mv88e6185_ops,
6038 },
6039
6040 [MV88E6190] = {
6041 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
6042 .family = MV88E6XXX_FAMILY_6390,
6043 .name = "Marvell 88E6190",
6044 .num_databases = 4096,
6045 .num_macs = 16384,
6046 .num_ports = 11, /* 10 + Z80 */
6047 .num_internal_phys = 9,
6048 .num_gpio = 16,
6049 .max_vid = 8191,
6050 .max_sid = 63,
6051 .port_base_addr = 0x0,
6052 .phy_base_addr = 0x0,
6053 .global1_addr = 0x1b,
6054 .global2_addr = 0x1c,
6055 .age_time_coeff = 3750,
6056 .g1_irqs = 9,
6057 .g2_irqs = 14,
6058 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6059 .pvt = true,
6060 .multi_chip = true,
6061 .atu_move_port_mask = 0x1f,
6062 .ops = &mv88e6190_ops,
6063 },
6064
6065 [MV88E6190X] = {
6066 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
6067 .family = MV88E6XXX_FAMILY_6390,
6068 .name = "Marvell 88E6190X",
6069 .num_databases = 4096,
6070 .num_macs = 16384,
6071 .num_ports = 11, /* 10 + Z80 */
6072 .num_internal_phys = 9,
6073 .num_gpio = 16,
6074 .max_vid = 8191,
6075 .max_sid = 63,
6076 .port_base_addr = 0x0,
6077 .phy_base_addr = 0x0,
6078 .global1_addr = 0x1b,
6079 .global2_addr = 0x1c,
6080 .age_time_coeff = 3750,
6081 .g1_irqs = 9,
6082 .g2_irqs = 14,
6083 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6084 .atu_move_port_mask = 0x1f,
6085 .pvt = true,
6086 .multi_chip = true,
6087 .ops = &mv88e6190x_ops,
6088 },
6089
6090 [MV88E6191] = {
6091 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
6092 .family = MV88E6XXX_FAMILY_6390,
6093 .name = "Marvell 88E6191",
6094 .num_databases = 4096,
6095 .num_macs = 16384,
6096 .num_ports = 11, /* 10 + Z80 */
6097 .num_internal_phys = 9,
6098 .max_vid = 8191,
6099 .max_sid = 63,
6100 .port_base_addr = 0x0,
6101 .phy_base_addr = 0x0,
6102 .global1_addr = 0x1b,
6103 .global2_addr = 0x1c,
6104 .age_time_coeff = 3750,
6105 .g1_irqs = 9,
6106 .g2_irqs = 14,
6107 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6108 .atu_move_port_mask = 0x1f,
6109 .pvt = true,
6110 .multi_chip = true,
6111 .ptp_support = true,
6112 .ops = &mv88e6191_ops,
6113 },
6114
6115 [MV88E6191X] = {
6116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6117 .family = MV88E6XXX_FAMILY_6393,
6118 .name = "Marvell 88E6191X",
6119 .num_databases = 4096,
6120 .num_ports = 11, /* 10 + Z80 */
6121 .num_internal_phys = 8,
6122 .internal_phys_offset = 1,
6123 .max_vid = 8191,
6124 .max_sid = 63,
6125 .port_base_addr = 0x0,
6126 .phy_base_addr = 0x0,
6127 .global1_addr = 0x1b,
6128 .global2_addr = 0x1c,
6129 .age_time_coeff = 3750,
6130 .g1_irqs = 10,
6131 .g2_irqs = 14,
6132 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6133 .atu_move_port_mask = 0x1f,
6134 .pvt = true,
6135 .multi_chip = true,
6136 .ptp_support = true,
6137 .ops = &mv88e6393x_ops,
6138 },
6139
6140 [MV88E6193X] = {
6141 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6142 .family = MV88E6XXX_FAMILY_6393,
6143 .name = "Marvell 88E6193X",
6144 .num_databases = 4096,
6145 .num_ports = 11, /* 10 + Z80 */
6146 .num_internal_phys = 8,
6147 .internal_phys_offset = 1,
6148 .max_vid = 8191,
6149 .max_sid = 63,
6150 .port_base_addr = 0x0,
6151 .phy_base_addr = 0x0,
6152 .global1_addr = 0x1b,
6153 .global2_addr = 0x1c,
6154 .age_time_coeff = 3750,
6155 .g1_irqs = 10,
6156 .g2_irqs = 14,
6157 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6158 .atu_move_port_mask = 0x1f,
6159 .pvt = true,
6160 .multi_chip = true,
6161 .ptp_support = true,
6162 .ops = &mv88e6393x_ops,
6163 },
6164
6165 [MV88E6220] = {
6166 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6167 .family = MV88E6XXX_FAMILY_6250,
6168 .name = "Marvell 88E6220",
6169 .num_databases = 64,
6170
6171 /* Ports 2-4 are not routed to pins
6172 * => usable ports 0, 1, 5, 6
6173 */
6174 .num_ports = 7,
6175 .num_internal_phys = 2,
6176 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6177 .max_vid = 4095,
6178 .port_base_addr = 0x08,
6179 .phy_base_addr = 0x00,
6180 .global1_addr = 0x0f,
6181 .global2_addr = 0x07,
6182 .age_time_coeff = 15000,
6183 .g1_irqs = 9,
6184 .g2_irqs = 10,
6185 .stats_type = STATS_TYPE_BANK0,
6186 .atu_move_port_mask = 0xf,
6187 .dual_chip = true,
6188 .ptp_support = true,
6189 .ops = &mv88e6250_ops,
6190 },
6191
6192 [MV88E6240] = {
6193 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6194 .family = MV88E6XXX_FAMILY_6352,
6195 .name = "Marvell 88E6240",
6196 .num_databases = 4096,
6197 .num_macs = 8192,
6198 .num_ports = 7,
6199 .num_internal_phys = 5,
6200 .num_gpio = 15,
6201 .max_vid = 4095,
6202 .max_sid = 63,
6203 .port_base_addr = 0x10,
6204 .phy_base_addr = 0x0,
6205 .global1_addr = 0x1b,
6206 .global2_addr = 0x1c,
6207 .age_time_coeff = 15000,
6208 .g1_irqs = 9,
6209 .g2_irqs = 10,
6210 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6211 .atu_move_port_mask = 0xf,
6212 .pvt = true,
6213 .multi_chip = true,
6214 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6215 .ptp_support = true,
6216 .ops = &mv88e6240_ops,
6217 },
6218
6219 [MV88E6250] = {
6220 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6221 .family = MV88E6XXX_FAMILY_6250,
6222 .name = "Marvell 88E6250",
6223 .num_databases = 64,
6224 .num_ports = 7,
6225 .num_internal_phys = 5,
6226 .max_vid = 4095,
6227 .port_base_addr = 0x08,
6228 .phy_base_addr = 0x00,
6229 .global1_addr = 0x0f,
6230 .global2_addr = 0x07,
6231 .age_time_coeff = 15000,
6232 .g1_irqs = 9,
6233 .g2_irqs = 10,
6234 .stats_type = STATS_TYPE_BANK0,
6235 .atu_move_port_mask = 0xf,
6236 .dual_chip = true,
6237 .ptp_support = true,
6238 .ops = &mv88e6250_ops,
6239 },
6240
6241 [MV88E6290] = {
6242 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6243 .family = MV88E6XXX_FAMILY_6390,
6244 .name = "Marvell 88E6290",
6245 .num_databases = 4096,
6246 .num_ports = 11, /* 10 + Z80 */
6247 .num_internal_phys = 9,
6248 .num_gpio = 16,
6249 .max_vid = 8191,
6250 .max_sid = 63,
6251 .port_base_addr = 0x0,
6252 .phy_base_addr = 0x0,
6253 .global1_addr = 0x1b,
6254 .global2_addr = 0x1c,
6255 .age_time_coeff = 3750,
6256 .g1_irqs = 9,
6257 .g2_irqs = 14,
6258 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6259 .atu_move_port_mask = 0x1f,
6260 .pvt = true,
6261 .multi_chip = true,
6262 .ptp_support = true,
6263 .ops = &mv88e6290_ops,
6264 },
6265
6266 [MV88E6320] = {
6267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6268 .family = MV88E6XXX_FAMILY_6320,
6269 .name = "Marvell 88E6320",
6270 .num_databases = 4096,
6271 .num_macs = 8192,
6272 .num_ports = 7,
6273 .num_internal_phys = 2,
6274 .internal_phys_offset = 3,
6275 .num_gpio = 15,
6276 .max_vid = 4095,
6277 .max_sid = 63,
6278 .port_base_addr = 0x10,
6279 .phy_base_addr = 0x0,
6280 .global1_addr = 0x1b,
6281 .global2_addr = 0x1c,
6282 .age_time_coeff = 15000,
6283 .g1_irqs = 8,
6284 .g2_irqs = 10,
6285 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6286 .atu_move_port_mask = 0xf,
6287 .pvt = true,
6288 .multi_chip = true,
6289 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6290 .ptp_support = true,
6291 .ops = &mv88e6320_ops,
6292 },
6293
6294 [MV88E6321] = {
6295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6296 .family = MV88E6XXX_FAMILY_6320,
6297 .name = "Marvell 88E6321",
6298 .num_databases = 4096,
6299 .num_macs = 8192,
6300 .num_ports = 7,
6301 .num_internal_phys = 2,
6302 .internal_phys_offset = 3,
6303 .num_gpio = 15,
6304 .max_vid = 4095,
6305 .max_sid = 63,
6306 .port_base_addr = 0x10,
6307 .phy_base_addr = 0x0,
6308 .global1_addr = 0x1b,
6309 .global2_addr = 0x1c,
6310 .age_time_coeff = 15000,
6311 .g1_irqs = 8,
6312 .g2_irqs = 10,
6313 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6314 .atu_move_port_mask = 0xf,
6315 .pvt = true,
6316 .multi_chip = true,
6317 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6318 .ptp_support = true,
6319 .ops = &mv88e6321_ops,
6320 },
6321
6322 [MV88E6341] = {
6323 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6324 .family = MV88E6XXX_FAMILY_6341,
6325 .name = "Marvell 88E6341",
6326 .num_databases = 256,
6327 .num_macs = 2048,
6328 .num_internal_phys = 5,
6329 .num_ports = 6,
6330 .num_gpio = 11,
6331 .max_vid = 4095,
6332 .max_sid = 63,
6333 .port_base_addr = 0x10,
6334 .phy_base_addr = 0x10,
6335 .global1_addr = 0x1b,
6336 .global2_addr = 0x1c,
6337 .age_time_coeff = 3750,
6338 .atu_move_port_mask = 0xf,
6339 .g1_irqs = 9,
6340 .g2_irqs = 10,
6341 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6342 .pvt = true,
6343 .multi_chip = true,
6344 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6345 .ptp_support = true,
6346 .ops = &mv88e6341_ops,
6347 },
6348
6349 [MV88E6350] = {
6350 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6351 .family = MV88E6XXX_FAMILY_6351,
6352 .name = "Marvell 88E6350",
6353 .num_databases = 4096,
6354 .num_macs = 8192,
6355 .num_ports = 7,
6356 .num_internal_phys = 5,
6357 .max_vid = 4095,
6358 .max_sid = 63,
6359 .port_base_addr = 0x10,
6360 .phy_base_addr = 0x0,
6361 .global1_addr = 0x1b,
6362 .global2_addr = 0x1c,
6363 .age_time_coeff = 15000,
6364 .g1_irqs = 9,
6365 .g2_irqs = 10,
6366 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6367 .atu_move_port_mask = 0xf,
6368 .pvt = true,
6369 .multi_chip = true,
6370 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6371 .ops = &mv88e6350_ops,
6372 },
6373
6374 [MV88E6351] = {
6375 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6376 .family = MV88E6XXX_FAMILY_6351,
6377 .name = "Marvell 88E6351",
6378 .num_databases = 4096,
6379 .num_macs = 8192,
6380 .num_ports = 7,
6381 .num_internal_phys = 5,
6382 .max_vid = 4095,
6383 .max_sid = 63,
6384 .port_base_addr = 0x10,
6385 .phy_base_addr = 0x0,
6386 .global1_addr = 0x1b,
6387 .global2_addr = 0x1c,
6388 .age_time_coeff = 15000,
6389 .g1_irqs = 9,
6390 .g2_irqs = 10,
6391 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6392 .atu_move_port_mask = 0xf,
6393 .pvt = true,
6394 .multi_chip = true,
6395 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6396 .ops = &mv88e6351_ops,
6397 },
6398
6399 [MV88E6352] = {
6400 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6401 .family = MV88E6XXX_FAMILY_6352,
6402 .name = "Marvell 88E6352",
6403 .num_databases = 4096,
6404 .num_macs = 8192,
6405 .num_ports = 7,
6406 .num_internal_phys = 5,
6407 .num_gpio = 15,
6408 .max_vid = 4095,
6409 .max_sid = 63,
6410 .port_base_addr = 0x10,
6411 .phy_base_addr = 0x0,
6412 .global1_addr = 0x1b,
6413 .global2_addr = 0x1c,
6414 .age_time_coeff = 15000,
6415 .g1_irqs = 9,
6416 .g2_irqs = 10,
6417 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT,
6418 .atu_move_port_mask = 0xf,
6419 .pvt = true,
6420 .multi_chip = true,
6421 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6422 .ptp_support = true,
6423 .ops = &mv88e6352_ops,
6424 },
6425 [MV88E6361] = {
6426 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6427 .family = MV88E6XXX_FAMILY_6393,
6428 .name = "Marvell 88E6361",
6429 .num_databases = 4096,
6430 .num_macs = 16384,
6431 .num_ports = 11,
6432 /* Ports 1, 2 and 8 are not routed */
6433 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6434 .num_internal_phys = 5,
6435 .internal_phys_offset = 3,
6436 .max_vid = 8191,
6437 .max_sid = 63,
6438 .port_base_addr = 0x0,
6439 .phy_base_addr = 0x0,
6440 .global1_addr = 0x1b,
6441 .global2_addr = 0x1c,
6442 .age_time_coeff = 3750,
6443 .g1_irqs = 10,
6444 .g2_irqs = 14,
6445 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6446 .atu_move_port_mask = 0x1f,
6447 .pvt = true,
6448 .multi_chip = true,
6449 .ptp_support = true,
6450 .ops = &mv88e6393x_ops,
6451 },
6452 [MV88E6390] = {
6453 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6454 .family = MV88E6XXX_FAMILY_6390,
6455 .name = "Marvell 88E6390",
6456 .num_databases = 4096,
6457 .num_macs = 16384,
6458 .num_ports = 11, /* 10 + Z80 */
6459 .num_internal_phys = 9,
6460 .num_gpio = 16,
6461 .max_vid = 8191,
6462 .max_sid = 63,
6463 .port_base_addr = 0x0,
6464 .phy_base_addr = 0x0,
6465 .global1_addr = 0x1b,
6466 .global2_addr = 0x1c,
6467 .age_time_coeff = 3750,
6468 .g1_irqs = 9,
6469 .g2_irqs = 14,
6470 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6471 .atu_move_port_mask = 0x1f,
6472 .pvt = true,
6473 .multi_chip = true,
6474 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6475 .ptp_support = true,
6476 .ops = &mv88e6390_ops,
6477 },
6478 [MV88E6390X] = {
6479 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6480 .family = MV88E6XXX_FAMILY_6390,
6481 .name = "Marvell 88E6390X",
6482 .num_databases = 4096,
6483 .num_macs = 16384,
6484 .num_ports = 11, /* 10 + Z80 */
6485 .num_internal_phys = 9,
6486 .num_gpio = 16,
6487 .max_vid = 8191,
6488 .max_sid = 63,
6489 .port_base_addr = 0x0,
6490 .phy_base_addr = 0x0,
6491 .global1_addr = 0x1b,
6492 .global2_addr = 0x1c,
6493 .age_time_coeff = 3750,
6494 .g1_irqs = 9,
6495 .g2_irqs = 14,
6496 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6497 .atu_move_port_mask = 0x1f,
6498 .pvt = true,
6499 .multi_chip = true,
6500 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6501 .ptp_support = true,
6502 .ops = &mv88e6390x_ops,
6503 },
6504
6505 [MV88E6393X] = {
6506 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6507 .family = MV88E6XXX_FAMILY_6393,
6508 .name = "Marvell 88E6393X",
6509 .num_databases = 4096,
6510 .num_ports = 11, /* 10 + Z80 */
6511 .num_internal_phys = 8,
6512 .internal_phys_offset = 1,
6513 .max_vid = 8191,
6514 .max_sid = 63,
6515 .port_base_addr = 0x0,
6516 .phy_base_addr = 0x0,
6517 .global1_addr = 0x1b,
6518 .global2_addr = 0x1c,
6519 .age_time_coeff = 3750,
6520 .g1_irqs = 10,
6521 .g2_irqs = 14,
6522 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
6523 .atu_move_port_mask = 0x1f,
6524 .pvt = true,
6525 .multi_chip = true,
6526 .ptp_support = true,
6527 .ops = &mv88e6393x_ops,
6528 },
6529 };
6530
mv88e6xxx_lookup_info(unsigned int prod_num)6531 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6532 {
6533 int i;
6534
6535 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6536 if (mv88e6xxx_table[i].prod_num == prod_num)
6537 return &mv88e6xxx_table[i];
6538
6539 return NULL;
6540 }
6541
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6542 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6543 {
6544 const struct mv88e6xxx_info *info;
6545 unsigned int prod_num, rev;
6546 u16 id;
6547 int err;
6548
6549 mv88e6xxx_reg_lock(chip);
6550 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6551 mv88e6xxx_reg_unlock(chip);
6552 if (err)
6553 return err;
6554
6555 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6556 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6557
6558 info = mv88e6xxx_lookup_info(prod_num);
6559 if (!info)
6560 return -ENODEV;
6561
6562 /* Update the compatible info with the probed one */
6563 chip->info = info;
6564
6565 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6566 chip->info->prod_num, chip->info->name, rev);
6567
6568 return 0;
6569 }
6570
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)6571 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6572 struct mdio_device *mdiodev)
6573 {
6574 int err;
6575
6576 /* dual_chip takes precedence over single/multi-chip modes */
6577 if (chip->info->dual_chip)
6578 return -EINVAL;
6579
6580 /* If the mdio addr is 16 indicating the first port address of a switch
6581 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6582 * configured in single chip addressing mode. Setup the smi access as
6583 * single chip addressing mode and attempt to detect the model of the
6584 * switch, if this fails the device is not configured in single chip
6585 * addressing mode.
6586 */
6587 if (mdiodev->addr != 16)
6588 return -EINVAL;
6589
6590 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6591 if (err)
6592 return err;
6593
6594 return mv88e6xxx_detect(chip);
6595 }
6596
mv88e6xxx_alloc_chip(struct device * dev)6597 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6598 {
6599 struct mv88e6xxx_chip *chip;
6600
6601 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6602 if (!chip)
6603 return NULL;
6604
6605 chip->dev = dev;
6606
6607 mutex_init(&chip->reg_lock);
6608 INIT_LIST_HEAD(&chip->mdios);
6609 idr_init(&chip->policies);
6610 INIT_LIST_HEAD(&chip->msts);
6611
6612 return chip;
6613 }
6614
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)6615 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6616 int port,
6617 enum dsa_tag_protocol m)
6618 {
6619 struct mv88e6xxx_chip *chip = ds->priv;
6620
6621 return chip->tag_protocol;
6622 }
6623
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6624 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6625 enum dsa_tag_protocol proto)
6626 {
6627 struct mv88e6xxx_chip *chip = ds->priv;
6628 enum dsa_tag_protocol old_protocol;
6629 struct dsa_port *cpu_dp;
6630 int err;
6631
6632 switch (proto) {
6633 case DSA_TAG_PROTO_EDSA:
6634 switch (chip->info->edsa_support) {
6635 case MV88E6XXX_EDSA_UNSUPPORTED:
6636 return -EPROTONOSUPPORT;
6637 case MV88E6XXX_EDSA_UNDOCUMENTED:
6638 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6639 fallthrough;
6640 case MV88E6XXX_EDSA_SUPPORTED:
6641 break;
6642 }
6643 break;
6644 case DSA_TAG_PROTO_DSA:
6645 break;
6646 default:
6647 return -EPROTONOSUPPORT;
6648 }
6649
6650 old_protocol = chip->tag_protocol;
6651 chip->tag_protocol = proto;
6652
6653 mv88e6xxx_reg_lock(chip);
6654 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6655 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6656 if (err) {
6657 mv88e6xxx_reg_unlock(chip);
6658 goto unwind;
6659 }
6660 }
6661 mv88e6xxx_reg_unlock(chip);
6662
6663 return 0;
6664
6665 unwind:
6666 chip->tag_protocol = old_protocol;
6667
6668 mv88e6xxx_reg_lock(chip);
6669 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6670 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6671 mv88e6xxx_reg_unlock(chip);
6672
6673 return err;
6674 }
6675
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6676 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6677 const struct switchdev_obj_port_mdb *mdb,
6678 struct dsa_db db)
6679 {
6680 struct mv88e6xxx_chip *chip = ds->priv;
6681 int err;
6682
6683 mv88e6xxx_reg_lock(chip);
6684 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6685 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6686 if (err)
6687 goto out;
6688
6689 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid))
6690 err = -ENOSPC;
6691
6692 out:
6693 mv88e6xxx_reg_unlock(chip);
6694
6695 return err;
6696 }
6697
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6698 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6699 const struct switchdev_obj_port_mdb *mdb,
6700 struct dsa_db db)
6701 {
6702 struct mv88e6xxx_chip *chip = ds->priv;
6703 int err;
6704
6705 mv88e6xxx_reg_lock(chip);
6706 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6707 mv88e6xxx_reg_unlock(chip);
6708
6709 return err;
6710 }
6711
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6712 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6713 struct dsa_mall_mirror_tc_entry *mirror,
6714 bool ingress,
6715 struct netlink_ext_ack *extack)
6716 {
6717 enum mv88e6xxx_egress_direction direction = ingress ?
6718 MV88E6XXX_EGRESS_DIR_INGRESS :
6719 MV88E6XXX_EGRESS_DIR_EGRESS;
6720 struct mv88e6xxx_chip *chip = ds->priv;
6721 bool other_mirrors = false;
6722 int i;
6723 int err;
6724
6725 mutex_lock(&chip->reg_lock);
6726 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6727 mirror->to_local_port) {
6728 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6729 other_mirrors |= ingress ?
6730 chip->ports[i].mirror_ingress :
6731 chip->ports[i].mirror_egress;
6732
6733 /* Can't change egress port when other mirror is active */
6734 if (other_mirrors) {
6735 err = -EBUSY;
6736 goto out;
6737 }
6738
6739 err = mv88e6xxx_set_egress_port(chip, direction,
6740 mirror->to_local_port);
6741 if (err)
6742 goto out;
6743 }
6744
6745 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6746 out:
6747 mutex_unlock(&chip->reg_lock);
6748
6749 return err;
6750 }
6751
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6752 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6753 struct dsa_mall_mirror_tc_entry *mirror)
6754 {
6755 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6756 MV88E6XXX_EGRESS_DIR_INGRESS :
6757 MV88E6XXX_EGRESS_DIR_EGRESS;
6758 struct mv88e6xxx_chip *chip = ds->priv;
6759 bool other_mirrors = false;
6760 int i;
6761
6762 mutex_lock(&chip->reg_lock);
6763 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6764 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6765
6766 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6767 other_mirrors |= mirror->ingress ?
6768 chip->ports[i].mirror_ingress :
6769 chip->ports[i].mirror_egress;
6770
6771 /* Reset egress port when no other mirror is active */
6772 if (!other_mirrors) {
6773 if (mv88e6xxx_set_egress_port(chip, direction,
6774 dsa_upstream_port(ds, port)))
6775 dev_err(ds->dev, "failed to set egress port\n");
6776 }
6777
6778 mutex_unlock(&chip->reg_lock);
6779 }
6780
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6781 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6782 struct switchdev_brport_flags flags,
6783 struct netlink_ext_ack *extack)
6784 {
6785 struct mv88e6xxx_chip *chip = ds->priv;
6786 const struct mv88e6xxx_ops *ops;
6787
6788 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6789 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6790 return -EINVAL;
6791
6792 ops = chip->info->ops;
6793
6794 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6795 return -EINVAL;
6796
6797 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6798 return -EINVAL;
6799
6800 return 0;
6801 }
6802
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6803 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6804 struct switchdev_brport_flags flags,
6805 struct netlink_ext_ack *extack)
6806 {
6807 struct mv88e6xxx_chip *chip = ds->priv;
6808 int err = 0;
6809
6810 mv88e6xxx_reg_lock(chip);
6811
6812 if (flags.mask & BR_LEARNING) {
6813 bool learning = !!(flags.val & BR_LEARNING);
6814 u16 pav = learning ? (1 << port) : 0;
6815
6816 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6817 if (err)
6818 goto out;
6819 }
6820
6821 if (flags.mask & BR_FLOOD) {
6822 bool unicast = !!(flags.val & BR_FLOOD);
6823
6824 err = chip->info->ops->port_set_ucast_flood(chip, port,
6825 unicast);
6826 if (err)
6827 goto out;
6828 }
6829
6830 if (flags.mask & BR_MCAST_FLOOD) {
6831 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6832
6833 err = chip->info->ops->port_set_mcast_flood(chip, port,
6834 multicast);
6835 if (err)
6836 goto out;
6837 }
6838
6839 if (flags.mask & BR_BCAST_FLOOD) {
6840 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6841
6842 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6843 if (err)
6844 goto out;
6845 }
6846
6847 if (flags.mask & BR_PORT_MAB) {
6848 bool mab = !!(flags.val & BR_PORT_MAB);
6849
6850 mv88e6xxx_port_set_mab(chip, port, mab);
6851 }
6852
6853 if (flags.mask & BR_PORT_LOCKED) {
6854 bool locked = !!(flags.val & BR_PORT_LOCKED);
6855
6856 err = mv88e6xxx_port_set_lock(chip, port, locked);
6857 if (err)
6858 goto out;
6859 }
6860 out:
6861 mv88e6xxx_reg_unlock(chip);
6862
6863 return err;
6864 }
6865
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6866 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6867 struct dsa_lag lag,
6868 struct netdev_lag_upper_info *info,
6869 struct netlink_ext_ack *extack)
6870 {
6871 struct mv88e6xxx_chip *chip = ds->priv;
6872 struct dsa_port *dp;
6873 int members = 0;
6874
6875 if (!mv88e6xxx_has_lag(chip)) {
6876 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6877 return false;
6878 }
6879
6880 if (!lag.id)
6881 return false;
6882
6883 dsa_lag_foreach_port(dp, ds->dst, &lag)
6884 /* Includes the port joining the LAG */
6885 members++;
6886
6887 if (members > 8) {
6888 NL_SET_ERR_MSG_MOD(extack,
6889 "Cannot offload more than 8 LAG ports");
6890 return false;
6891 }
6892
6893 /* We could potentially relax this to include active
6894 * backup in the future.
6895 */
6896 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6897 NL_SET_ERR_MSG_MOD(extack,
6898 "Can only offload LAG using hash TX type");
6899 return false;
6900 }
6901
6902 /* Ideally we would also validate that the hash type matches
6903 * the hardware. Alas, this is always set to unknown on team
6904 * interfaces.
6905 */
6906 return true;
6907 }
6908
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6909 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6910 {
6911 struct mv88e6xxx_chip *chip = ds->priv;
6912 struct dsa_port *dp;
6913 u16 map = 0;
6914 int id;
6915
6916 /* DSA LAG IDs are one-based, hardware is zero-based */
6917 id = lag.id - 1;
6918
6919 /* Build the map of all ports to distribute flows destined for
6920 * this LAG. This can be either a local user port, or a DSA
6921 * port if the LAG port is on a remote chip.
6922 */
6923 dsa_lag_foreach_port(dp, ds->dst, &lag)
6924 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6925
6926 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6927 }
6928
6929 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6930 /* Row number corresponds to the number of active members in a
6931 * LAG. Each column states which of the eight hash buckets are
6932 * mapped to the column:th port in the LAG.
6933 *
6934 * Example: In a LAG with three active ports, the second port
6935 * ([2][1]) would be selected for traffic mapped to buckets
6936 * 3,4,5 (0x38).
6937 */
6938 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6939 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6940 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6941 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6942 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6943 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6944 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6945 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6946 };
6947
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6948 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6949 int num_tx, int nth)
6950 {
6951 u8 active = 0;
6952 int i;
6953
6954 num_tx = num_tx <= 8 ? num_tx : 8;
6955 if (nth < num_tx)
6956 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6957
6958 for (i = 0; i < 8; i++) {
6959 if (BIT(i) & active)
6960 mask[i] |= BIT(port);
6961 }
6962 }
6963
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6964 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6965 {
6966 struct mv88e6xxx_chip *chip = ds->priv;
6967 unsigned int id, num_tx;
6968 struct dsa_port *dp;
6969 struct dsa_lag *lag;
6970 int i, err, nth;
6971 u16 mask[8];
6972 u16 ivec;
6973
6974 /* Assume no port is a member of any LAG. */
6975 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6976
6977 /* Disable all masks for ports that _are_ members of a LAG. */
6978 dsa_switch_for_each_port(dp, ds) {
6979 if (!dp->lag)
6980 continue;
6981
6982 ivec &= ~BIT(dp->index);
6983 }
6984
6985 for (i = 0; i < 8; i++)
6986 mask[i] = ivec;
6987
6988 /* Enable the correct subset of masks for all LAG ports that
6989 * are in the Tx set.
6990 */
6991 dsa_lags_foreach_id(id, ds->dst) {
6992 lag = dsa_lag_by_id(ds->dst, id);
6993 if (!lag)
6994 continue;
6995
6996 num_tx = 0;
6997 dsa_lag_foreach_port(dp, ds->dst, lag) {
6998 if (dp->lag_tx_enabled)
6999 num_tx++;
7000 }
7001
7002 if (!num_tx)
7003 continue;
7004
7005 nth = 0;
7006 dsa_lag_foreach_port(dp, ds->dst, lag) {
7007 if (!dp->lag_tx_enabled)
7008 continue;
7009
7010 if (dp->ds == ds)
7011 mv88e6xxx_lag_set_port_mask(mask, dp->index,
7012 num_tx, nth);
7013
7014 nth++;
7015 }
7016 }
7017
7018 for (i = 0; i < 8; i++) {
7019 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
7020 if (err)
7021 return err;
7022 }
7023
7024 return 0;
7025 }
7026
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)7027 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
7028 struct dsa_lag lag)
7029 {
7030 int err;
7031
7032 err = mv88e6xxx_lag_sync_masks(ds);
7033
7034 if (!err)
7035 err = mv88e6xxx_lag_sync_map(ds, lag);
7036
7037 return err;
7038 }
7039
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)7040 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
7041 {
7042 struct mv88e6xxx_chip *chip = ds->priv;
7043 int err;
7044
7045 mv88e6xxx_reg_lock(chip);
7046 err = mv88e6xxx_lag_sync_masks(ds);
7047 mv88e6xxx_reg_unlock(chip);
7048 return err;
7049 }
7050
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)7051 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
7052 struct dsa_lag lag,
7053 struct netdev_lag_upper_info *info,
7054 struct netlink_ext_ack *extack)
7055 {
7056 struct mv88e6xxx_chip *chip = ds->priv;
7057 int err, id;
7058
7059 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7060 return -EOPNOTSUPP;
7061
7062 /* DSA LAG IDs are one-based */
7063 id = lag.id - 1;
7064
7065 mv88e6xxx_reg_lock(chip);
7066
7067 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
7068 if (err)
7069 goto err_unlock;
7070
7071 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7072 if (err)
7073 goto err_clear_trunk;
7074
7075 mv88e6xxx_reg_unlock(chip);
7076 return 0;
7077
7078 err_clear_trunk:
7079 mv88e6xxx_port_set_trunk(chip, port, false, 0);
7080 err_unlock:
7081 mv88e6xxx_reg_unlock(chip);
7082 return err;
7083 }
7084
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)7085 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
7086 struct dsa_lag lag)
7087 {
7088 struct mv88e6xxx_chip *chip = ds->priv;
7089 int err_sync, err_trunk;
7090
7091 mv88e6xxx_reg_lock(chip);
7092 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7093 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7094 mv88e6xxx_reg_unlock(chip);
7095 return err_sync ? : err_trunk;
7096 }
7097
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)7098 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
7099 int port)
7100 {
7101 struct mv88e6xxx_chip *chip = ds->priv;
7102 int err;
7103
7104 mv88e6xxx_reg_lock(chip);
7105 err = mv88e6xxx_lag_sync_masks(ds);
7106 mv88e6xxx_reg_unlock(chip);
7107 return err;
7108 }
7109
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)7110 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
7111 int port, struct dsa_lag lag,
7112 struct netdev_lag_upper_info *info,
7113 struct netlink_ext_ack *extack)
7114 {
7115 struct mv88e6xxx_chip *chip = ds->priv;
7116 int err;
7117
7118 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7119 return -EOPNOTSUPP;
7120
7121 mv88e6xxx_reg_lock(chip);
7122
7123 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7124 if (err)
7125 goto unlock;
7126
7127 err = mv88e6xxx_pvt_map(chip, sw_index, port);
7128
7129 unlock:
7130 mv88e6xxx_reg_unlock(chip);
7131 return err;
7132 }
7133
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)7134 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
7135 int port, struct dsa_lag lag)
7136 {
7137 struct mv88e6xxx_chip *chip = ds->priv;
7138 int err_sync, err_pvt;
7139
7140 mv88e6xxx_reg_lock(chip);
7141 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7142 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7143 mv88e6xxx_reg_unlock(chip);
7144 return err_sync ? : err_pvt;
7145 }
7146
7147 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = {
7148 .mac_select_pcs = mv88e6xxx_mac_select_pcs,
7149 .mac_prepare = mv88e6xxx_mac_prepare,
7150 .mac_config = mv88e6xxx_mac_config,
7151 .mac_finish = mv88e6xxx_mac_finish,
7152 .mac_link_down = mv88e6xxx_mac_link_down,
7153 .mac_link_up = mv88e6xxx_mac_link_up,
7154 };
7155
7156 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7157 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
7158 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
7159 .setup = mv88e6xxx_setup,
7160 .teardown = mv88e6xxx_teardown,
7161 .port_setup = mv88e6xxx_port_setup,
7162 .port_teardown = mv88e6xxx_port_teardown,
7163 .phylink_get_caps = mv88e6xxx_get_caps,
7164 .get_strings = mv88e6xxx_get_strings,
7165 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7166 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
7167 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
7168 .get_sset_count = mv88e6xxx_get_sset_count,
7169 .port_max_mtu = mv88e6xxx_get_max_mtu,
7170 .port_change_mtu = mv88e6xxx_change_mtu,
7171 .support_eee = dsa_supports_eee,
7172 .set_mac_eee = mv88e6xxx_set_mac_eee,
7173 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7174 .get_eeprom = mv88e6xxx_get_eeprom,
7175 .set_eeprom = mv88e6xxx_set_eeprom,
7176 .get_regs_len = mv88e6xxx_get_regs_len,
7177 .get_regs = mv88e6xxx_get_regs,
7178 .get_rxnfc = mv88e6xxx_get_rxnfc,
7179 .set_rxnfc = mv88e6xxx_set_rxnfc,
7180 .set_ageing_time = mv88e6xxx_set_ageing_time,
7181 .port_bridge_join = mv88e6xxx_port_bridge_join,
7182 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7183 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7184 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7185 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7186 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7187 .port_fast_age = mv88e6xxx_port_fast_age,
7188 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7189 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7190 .port_vlan_add = mv88e6xxx_port_vlan_add,
7191 .port_vlan_del = mv88e6xxx_port_vlan_del,
7192 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7193 .port_fdb_add = mv88e6xxx_port_fdb_add,
7194 .port_fdb_del = mv88e6xxx_port_fdb_del,
7195 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7196 .port_mdb_add = mv88e6xxx_port_mdb_add,
7197 .port_mdb_del = mv88e6xxx_port_mdb_del,
7198 .port_mirror_add = mv88e6xxx_port_mirror_add,
7199 .port_mirror_del = mv88e6xxx_port_mirror_del,
7200 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7201 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7202 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7203 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7204 .port_txtstamp = mv88e6xxx_port_txtstamp,
7205 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7206 .get_ts_info = mv88e6xxx_get_ts_info,
7207 .devlink_param_get = mv88e6xxx_devlink_param_get,
7208 .devlink_param_set = mv88e6xxx_devlink_param_set,
7209 .devlink_info_get = mv88e6xxx_devlink_info_get,
7210 .port_lag_change = mv88e6xxx_port_lag_change,
7211 .port_lag_join = mv88e6xxx_port_lag_join,
7212 .port_lag_leave = mv88e6xxx_port_lag_leave,
7213 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7214 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7215 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7216 };
7217
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)7218 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7219 {
7220 struct device *dev = chip->dev;
7221 struct dsa_switch *ds;
7222
7223 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7224 if (!ds)
7225 return -ENOMEM;
7226
7227 ds->dev = dev;
7228 ds->num_ports = mv88e6xxx_num_ports(chip);
7229 ds->priv = chip;
7230 ds->dev = dev;
7231 ds->ops = &mv88e6xxx_switch_ops;
7232 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops;
7233 ds->ageing_time_min = chip->info->age_time_coeff;
7234 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7235
7236 /* Some chips support up to 32, but that requires enabling the
7237 * 5-bit port mode, which we do not support. 640k^W16 ought to
7238 * be enough for anyone.
7239 */
7240 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7241
7242 dev_set_drvdata(dev, ds);
7243
7244 return dsa_register_switch(ds);
7245 }
7246
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7247 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7248 {
7249 dsa_unregister_switch(chip->ds);
7250 }
7251
pdata_device_get_match_data(struct device * dev)7252 static const void *pdata_device_get_match_data(struct device *dev)
7253 {
7254 const struct of_device_id *matches = dev->driver->of_match_table;
7255 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7256
7257 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7258 matches++) {
7259 if (!strcmp(pdata->compatible, matches->compatible))
7260 return matches->data;
7261 }
7262 return NULL;
7263 }
7264
7265 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7266 * would be lost after a power cycle so prevent it to be suspended.
7267 */
mv88e6xxx_suspend(struct device * dev)7268 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7269 {
7270 return -EOPNOTSUPP;
7271 }
7272
mv88e6xxx_resume(struct device * dev)7273 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7274 {
7275 return 0;
7276 }
7277
7278 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7279
mv88e6xxx_probe(struct mdio_device * mdiodev)7280 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7281 {
7282 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7283 const struct mv88e6xxx_info *compat_info = NULL;
7284 struct device *dev = &mdiodev->dev;
7285 struct device_node *np = dev->of_node;
7286 struct mv88e6xxx_chip *chip;
7287 int port;
7288 int err;
7289
7290 if (!np && !pdata)
7291 return -EINVAL;
7292
7293 if (np)
7294 compat_info = of_device_get_match_data(dev);
7295
7296 if (pdata) {
7297 compat_info = pdata_device_get_match_data(dev);
7298
7299 if (!pdata->netdev)
7300 return -EINVAL;
7301
7302 for (port = 0; port < DSA_MAX_PORTS; port++) {
7303 if (!(pdata->enabled_ports & (1 << port)))
7304 continue;
7305 if (strcmp(pdata->cd.port_names[port], "cpu"))
7306 continue;
7307 pdata->cd.netdev[port] = &pdata->netdev->dev;
7308 break;
7309 }
7310 }
7311
7312 if (!compat_info)
7313 return -EINVAL;
7314
7315 chip = mv88e6xxx_alloc_chip(dev);
7316 if (!chip) {
7317 err = -ENOMEM;
7318 goto out;
7319 }
7320
7321 chip->info = compat_info;
7322
7323 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7324 if (IS_ERR(chip->reset)) {
7325 err = PTR_ERR(chip->reset);
7326 goto out;
7327 }
7328 if (chip->reset)
7329 usleep_range(10000, 20000);
7330
7331 /* Detect if the device is configured in single chip addressing mode,
7332 * otherwise continue with address specific smi init/detection.
7333 */
7334 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7335 if (err) {
7336 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7337 if (err)
7338 goto out;
7339
7340 err = mv88e6xxx_detect(chip);
7341 if (err)
7342 goto out;
7343 }
7344
7345 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7346 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7347 else
7348 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7349
7350 mv88e6xxx_phy_init(chip);
7351
7352 if (chip->info->ops->get_eeprom) {
7353 if (np)
7354 of_property_read_u32(np, "eeprom-length",
7355 &chip->eeprom_len);
7356 else
7357 chip->eeprom_len = pdata->eeprom_len;
7358 }
7359
7360 mv88e6xxx_reg_lock(chip);
7361 err = mv88e6xxx_switch_reset(chip);
7362 mv88e6xxx_reg_unlock(chip);
7363 if (err)
7364 goto out_phy;
7365
7366 if (np) {
7367 chip->irq = of_irq_get(np, 0);
7368 if (chip->irq == -EPROBE_DEFER) {
7369 err = chip->irq;
7370 goto out_phy;
7371 }
7372 }
7373
7374 if (pdata)
7375 chip->irq = pdata->irq;
7376
7377 /* Has to be performed before the MDIO bus is created, because
7378 * the PHYs will link their interrupts to these interrupt
7379 * controllers
7380 */
7381 mv88e6xxx_reg_lock(chip);
7382 if (chip->irq > 0)
7383 err = mv88e6xxx_g1_irq_setup(chip);
7384 else
7385 err = mv88e6xxx_irq_poll_setup(chip);
7386 mv88e6xxx_reg_unlock(chip);
7387
7388 if (err)
7389 goto out_phy;
7390
7391 if (chip->info->g2_irqs > 0) {
7392 err = mv88e6xxx_g2_irq_setup(chip);
7393 if (err)
7394 goto out_g1_irq;
7395 }
7396
7397 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7398 if (err)
7399 goto out_g2_irq;
7400
7401 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7402 if (err)
7403 goto out_g1_atu_prob_irq;
7404
7405 err = mv88e6xxx_register_switch(chip);
7406 if (err)
7407 goto out_g1_vtu_prob_irq;
7408
7409 return 0;
7410
7411 out_g1_vtu_prob_irq:
7412 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7413 out_g1_atu_prob_irq:
7414 mv88e6xxx_g1_atu_prob_irq_free(chip);
7415 out_g2_irq:
7416 if (chip->info->g2_irqs > 0)
7417 mv88e6xxx_g2_irq_free(chip);
7418 out_g1_irq:
7419 if (chip->irq > 0)
7420 mv88e6xxx_g1_irq_free(chip);
7421 else
7422 mv88e6xxx_irq_poll_free(chip);
7423 out_phy:
7424 mv88e6xxx_phy_destroy(chip);
7425 out:
7426 if (pdata)
7427 dev_put(pdata->netdev);
7428
7429 return err;
7430 }
7431
mv88e6xxx_remove(struct mdio_device * mdiodev)7432 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7433 {
7434 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7435 struct mv88e6xxx_chip *chip;
7436
7437 if (!ds)
7438 return;
7439
7440 chip = ds->priv;
7441
7442 if (chip->info->ptp_support) {
7443 mv88e6xxx_hwtstamp_free(chip);
7444 mv88e6xxx_ptp_free(chip);
7445 }
7446
7447 mv88e6xxx_unregister_switch(chip);
7448
7449 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7450 mv88e6xxx_g1_atu_prob_irq_free(chip);
7451
7452 if (chip->info->g2_irqs > 0)
7453 mv88e6xxx_g2_irq_free(chip);
7454
7455 if (chip->irq > 0)
7456 mv88e6xxx_g1_irq_free(chip);
7457 else
7458 mv88e6xxx_irq_poll_free(chip);
7459
7460 mv88e6xxx_phy_destroy(chip);
7461 }
7462
mv88e6xxx_shutdown(struct mdio_device * mdiodev)7463 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7464 {
7465 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7466
7467 if (!ds)
7468 return;
7469
7470 dsa_switch_shutdown(ds);
7471
7472 dev_set_drvdata(&mdiodev->dev, NULL);
7473 }
7474
7475 static const struct of_device_id mv88e6xxx_of_match[] = {
7476 {
7477 .compatible = "marvell,mv88e6085",
7478 .data = &mv88e6xxx_table[MV88E6085],
7479 },
7480 {
7481 .compatible = "marvell,mv88e6190",
7482 .data = &mv88e6xxx_table[MV88E6190],
7483 },
7484 {
7485 .compatible = "marvell,mv88e6250",
7486 .data = &mv88e6xxx_table[MV88E6250],
7487 },
7488 { /* sentinel */ },
7489 };
7490
7491 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7492
7493 static struct mdio_driver mv88e6xxx_driver = {
7494 .probe = mv88e6xxx_probe,
7495 .remove = mv88e6xxx_remove,
7496 .shutdown = mv88e6xxx_shutdown,
7497 .mdiodrv.driver = {
7498 .name = "mv88e6085",
7499 .of_match_table = mv88e6xxx_of_match,
7500 .pm = &mv88e6xxx_pm_ops,
7501 },
7502 };
7503
7504 mdio_module_driver(mv88e6xxx_driver);
7505
7506 MODULE_AUTHOR("Lennert Buytenhek <[email protected]>");
7507 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7508 MODULE_LICENSE("GPL");
7509