1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 *
7 * Authors: Younghwan Joo <[email protected]>
8 * Sylwester Nawrocki <[email protected]>
9 */
10 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
11
12 #include <linux/bitops.h>
13 #include <linux/bug.h>
14 #include <linux/device.h>
15 #include <linux/errno.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include <linux/videodev2.h>
22
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-ioctl.h>
25
26 #include "fimc-is.h"
27 #include "fimc-is-command.h"
28 #include "fimc-is-errno.h"
29 #include "fimc-is-param.h"
30 #include "fimc-is-regs.h"
31 #include "fimc-is-sensor.h"
32
__hw_param_copy(void * dst,void * src)33 static void __hw_param_copy(void *dst, void *src)
34 {
35 memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
36 }
37
__fimc_is_hw_update_param_global_shotmode(struct fimc_is * is)38 static void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
39 {
40 struct param_global_shotmode *dst, *src;
41
42 dst = &is->is_p_region->parameter.global.shotmode;
43 src = &is->config[is->config_index].global.shotmode;
44 __hw_param_copy(dst, src);
45 }
46
__fimc_is_hw_update_param_sensor_framerate(struct fimc_is * is)47 static void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
48 {
49 struct param_sensor_framerate *dst, *src;
50
51 dst = &is->is_p_region->parameter.sensor.frame_rate;
52 src = &is->config[is->config_index].sensor.frame_rate;
53 __hw_param_copy(dst, src);
54 }
55
__fimc_is_hw_update_param(struct fimc_is * is,u32 offset)56 int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
57 {
58 struct is_param_region *par = &is->is_p_region->parameter;
59 struct chain_config *cfg = &is->config[is->config_index];
60
61 switch (offset) {
62 case PARAM_ISP_CONTROL:
63 __hw_param_copy(&par->isp.control, &cfg->isp.control);
64 break;
65
66 case PARAM_ISP_OTF_INPUT:
67 __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
68 break;
69
70 case PARAM_ISP_DMA1_INPUT:
71 __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
72 break;
73
74 case PARAM_ISP_DMA2_INPUT:
75 __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
76 break;
77
78 case PARAM_ISP_AA:
79 __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
80 break;
81
82 case PARAM_ISP_FLASH:
83 __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
84 break;
85
86 case PARAM_ISP_AWB:
87 __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
88 break;
89
90 case PARAM_ISP_IMAGE_EFFECT:
91 __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
92 break;
93
94 case PARAM_ISP_ISO:
95 __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
96 break;
97
98 case PARAM_ISP_ADJUST:
99 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
100 break;
101
102 case PARAM_ISP_METERING:
103 __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
104 break;
105
106 case PARAM_ISP_AFC:
107 __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
108 break;
109
110 case PARAM_ISP_OTF_OUTPUT:
111 __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
112 break;
113
114 case PARAM_ISP_DMA1_OUTPUT:
115 __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
116 break;
117
118 case PARAM_ISP_DMA2_OUTPUT:
119 __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
120 break;
121
122 case PARAM_DRC_CONTROL:
123 __hw_param_copy(&par->drc.control, &cfg->drc.control);
124 break;
125
126 case PARAM_DRC_OTF_INPUT:
127 __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
128 break;
129
130 case PARAM_DRC_DMA_INPUT:
131 __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
132 break;
133
134 case PARAM_DRC_OTF_OUTPUT:
135 __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
136 break;
137
138 case PARAM_FD_CONTROL:
139 __hw_param_copy(&par->fd.control, &cfg->fd.control);
140 break;
141
142 case PARAM_FD_OTF_INPUT:
143 __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input);
144 break;
145
146 case PARAM_FD_DMA_INPUT:
147 __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input);
148 break;
149
150 case PARAM_FD_CONFIG:
151 __hw_param_copy(&par->fd.config, &cfg->fd.config);
152 break;
153
154 default:
155 return -EINVAL;
156 }
157
158 return 0;
159 }
160
__get_pending_param_count(struct fimc_is * is)161 unsigned int __get_pending_param_count(struct fimc_is *is)
162 {
163 struct chain_config *config = &is->config[is->config_index];
164 unsigned long flags;
165 unsigned int count;
166
167 spin_lock_irqsave(&is->slock, flags);
168 count = hweight32(config->p_region_index[0]);
169 count += hweight32(config->p_region_index[1]);
170 spin_unlock_irqrestore(&is->slock, flags);
171
172 return count;
173 }
174
__is_hw_update_params(struct fimc_is * is)175 int __is_hw_update_params(struct fimc_is *is)
176 {
177 unsigned long *p_index;
178 int i, id, ret = 0;
179
180 id = is->config_index;
181 p_index = &is->config[id].p_region_index[0];
182
183 if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index))
184 __fimc_is_hw_update_param_global_shotmode(is);
185
186 if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index))
187 __fimc_is_hw_update_param_sensor_framerate(is);
188
189 for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) {
190 if (test_bit(i, p_index))
191 ret = __fimc_is_hw_update_param(is, i);
192 }
193
194 for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) {
195 if (test_bit(i, p_index))
196 ret = __fimc_is_hw_update_param(is, i);
197 }
198
199 for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) {
200 if (test_bit(i, p_index))
201 ret = __fimc_is_hw_update_param(is, i);
202 }
203
204 return ret;
205 }
206
__is_set_frame_size(struct fimc_is * is,struct v4l2_mbus_framefmt * mf)207 void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
208 {
209 unsigned int index = is->config_index;
210 struct isp_param *isp;
211 struct drc_param *drc;
212 struct fd_param *fd;
213
214 isp = &is->config[index].isp;
215 drc = &is->config[index].drc;
216 fd = &is->config[index].fd;
217
218 /* Update isp size info (OTF only) */
219 isp->otf_input.width = mf->width;
220 isp->otf_input.height = mf->height;
221 isp->otf_output.width = mf->width;
222 isp->otf_output.height = mf->height;
223 /* Update drc size info (OTF only) */
224 drc->otf_input.width = mf->width;
225 drc->otf_input.height = mf->height;
226 drc->otf_output.width = mf->width;
227 drc->otf_output.height = mf->height;
228 /* Update fd size info (OTF only) */
229 fd->otf_input.width = mf->width;
230 fd->otf_input.height = mf->height;
231
232 if (test_bit(PARAM_ISP_OTF_INPUT,
233 &is->config[index].p_region_index[0]))
234 return;
235
236 /* Update field */
237 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
238 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
239 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
240 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
241 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
242 }
243
fimc_is_hw_get_sensor_max_framerate(struct fimc_is * is)244 int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is)
245 {
246 switch (is->sensor->drvdata->id) {
247 case FIMC_IS_SENSOR_ID_S5K6A3:
248 return 30;
249 default:
250 return 15;
251 }
252 }
253
__is_set_sensor(struct fimc_is * is,int fps)254 void __is_set_sensor(struct fimc_is *is, int fps)
255 {
256 unsigned int index = is->config_index;
257 struct sensor_param *sensor;
258 struct isp_param *isp;
259
260 sensor = &is->config[index].sensor;
261 isp = &is->config[index].isp;
262
263 if (fps == 0) {
264 sensor->frame_rate.frame_rate =
265 fimc_is_hw_get_sensor_max_framerate(is);
266 isp->otf_input.frametime_min = 0;
267 isp->otf_input.frametime_max = 66666;
268 } else {
269 sensor->frame_rate.frame_rate = fps;
270 isp->otf_input.frametime_min = 0;
271 isp->otf_input.frametime_max = (u32)1000000 / fps;
272 }
273
274 fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE);
275 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
276 }
277
__is_set_init_isp_aa(struct fimc_is * is)278 static void __maybe_unused __is_set_init_isp_aa(struct fimc_is *is)
279 {
280 struct isp_param *isp;
281
282 isp = &is->config[is->config_index].isp;
283
284 isp->aa.cmd = ISP_AA_COMMAND_START;
285 isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
286 ISP_AA_TARGET_AWB;
287 isp->aa.mode = 0;
288 isp->aa.scene = 0;
289 isp->aa.sleep = 0;
290 isp->aa.face = 0;
291 isp->aa.touch_x = 0;
292 isp->aa.touch_y = 0;
293 isp->aa.manual_af_setting = 0;
294 isp->aa.err = ISP_AF_ERROR_NONE;
295
296 fimc_is_set_param_bit(is, PARAM_ISP_AA);
297 }
298
__is_set_isp_flash(struct fimc_is * is,u32 cmd,u32 redeye)299 void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye)
300 {
301 unsigned int index = is->config_index;
302 struct isp_param *isp = &is->config[index].isp;
303
304 isp->flash.cmd = cmd;
305 isp->flash.redeye = redeye;
306 isp->flash.err = ISP_FLASH_ERROR_NONE;
307
308 fimc_is_set_param_bit(is, PARAM_ISP_FLASH);
309 }
310
__is_set_isp_awb(struct fimc_is * is,u32 cmd,u32 val)311 void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val)
312 {
313 unsigned int index = is->config_index;
314 struct isp_param *isp;
315
316 isp = &is->config[index].isp;
317
318 isp->awb.cmd = cmd;
319 isp->awb.illumination = val;
320 isp->awb.err = ISP_AWB_ERROR_NONE;
321
322 fimc_is_set_param_bit(is, PARAM_ISP_AWB);
323 }
324
__is_set_isp_effect(struct fimc_is * is,u32 cmd)325 void __is_set_isp_effect(struct fimc_is *is, u32 cmd)
326 {
327 unsigned int index = is->config_index;
328 struct isp_param *isp;
329
330 isp = &is->config[index].isp;
331
332 isp->effect.cmd = cmd;
333 isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE;
334
335 fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT);
336 }
337
__is_set_isp_iso(struct fimc_is * is,u32 cmd,u32 val)338 void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val)
339 {
340 unsigned int index = is->config_index;
341 struct isp_param *isp;
342
343 isp = &is->config[index].isp;
344
345 isp->iso.cmd = cmd;
346 isp->iso.value = val;
347 isp->iso.err = ISP_ISO_ERROR_NONE;
348
349 fimc_is_set_param_bit(is, PARAM_ISP_ISO);
350 }
351
__is_set_isp_adjust(struct fimc_is * is,u32 cmd,u32 val)352 void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val)
353 {
354 unsigned int index = is->config_index;
355 unsigned long *p_index;
356 struct isp_param *isp;
357
358 p_index = &is->config[index].p_region_index[0];
359 isp = &is->config[index].isp;
360
361 switch (cmd) {
362 case ISP_ADJUST_COMMAND_MANUAL_CONTRAST:
363 isp->adjust.contrast = val;
364 break;
365 case ISP_ADJUST_COMMAND_MANUAL_SATURATION:
366 isp->adjust.saturation = val;
367 break;
368 case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS:
369 isp->adjust.sharpness = val;
370 break;
371 case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE:
372 isp->adjust.exposure = val;
373 break;
374 case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS:
375 isp->adjust.brightness = val;
376 break;
377 case ISP_ADJUST_COMMAND_MANUAL_HUE:
378 isp->adjust.hue = val;
379 break;
380 case ISP_ADJUST_COMMAND_AUTO:
381 isp->adjust.contrast = 0;
382 isp->adjust.saturation = 0;
383 isp->adjust.sharpness = 0;
384 isp->adjust.exposure = 0;
385 isp->adjust.brightness = 0;
386 isp->adjust.hue = 0;
387 break;
388 }
389
390 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
391 isp->adjust.cmd = cmd;
392 isp->adjust.err = ISP_ADJUST_ERROR_NONE;
393 fimc_is_set_param_bit(is, PARAM_ISP_ADJUST);
394 } else {
395 isp->adjust.cmd |= cmd;
396 }
397 }
398
__is_set_isp_metering(struct fimc_is * is,u32 id,u32 val)399 void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val)
400 {
401 unsigned int index = is->config_index;
402 struct isp_param *isp;
403 unsigned long *p_index;
404
405 p_index = &is->config[index].p_region_index[0];
406 isp = &is->config[index].isp;
407
408 switch (id) {
409 case IS_METERING_CONFIG_CMD:
410 isp->metering.cmd = val;
411 break;
412 case IS_METERING_CONFIG_WIN_POS_X:
413 isp->metering.win_pos_x = val;
414 break;
415 case IS_METERING_CONFIG_WIN_POS_Y:
416 isp->metering.win_pos_y = val;
417 break;
418 case IS_METERING_CONFIG_WIN_WIDTH:
419 isp->metering.win_width = val;
420 break;
421 case IS_METERING_CONFIG_WIN_HEIGHT:
422 isp->metering.win_height = val;
423 break;
424 default:
425 return;
426 }
427
428 if (!test_bit(PARAM_ISP_METERING, p_index)) {
429 isp->metering.err = ISP_METERING_ERROR_NONE;
430 fimc_is_set_param_bit(is, PARAM_ISP_METERING);
431 }
432 }
433
__is_set_isp_afc(struct fimc_is * is,u32 cmd,u32 val)434 void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val)
435 {
436 unsigned int index = is->config_index;
437 struct isp_param *isp;
438
439 isp = &is->config[index].isp;
440
441 isp->afc.cmd = cmd;
442 isp->afc.manual = val;
443 isp->afc.err = ISP_AFC_ERROR_NONE;
444
445 fimc_is_set_param_bit(is, PARAM_ISP_AFC);
446 }
447
__is_set_drc_control(struct fimc_is * is,u32 val)448 void __is_set_drc_control(struct fimc_is *is, u32 val)
449 {
450 unsigned int index = is->config_index;
451 struct drc_param *drc;
452
453 drc = &is->config[index].drc;
454
455 drc->control.bypass = val;
456
457 fimc_is_set_param_bit(is, PARAM_DRC_CONTROL);
458 }
459
__is_set_fd_control(struct fimc_is * is,u32 val)460 void __is_set_fd_control(struct fimc_is *is, u32 val)
461 {
462 unsigned int index = is->config_index;
463 struct fd_param *fd;
464 unsigned long *p_index;
465
466 p_index = &is->config[index].p_region_index[1];
467 fd = &is->config[index].fd;
468
469 fd->control.cmd = val;
470
471 if (!test_bit((PARAM_FD_CONFIG - 32), p_index))
472 fimc_is_set_param_bit(is, PARAM_FD_CONTROL);
473 }
474
__is_set_fd_config_maxface(struct fimc_is * is,u32 val)475 void __is_set_fd_config_maxface(struct fimc_is *is, u32 val)
476 {
477 unsigned int index = is->config_index;
478 struct fd_param *fd;
479 unsigned long *p_index;
480
481 p_index = &is->config[index].p_region_index[1];
482 fd = &is->config[index].fd;
483
484 fd->config.max_number = val;
485
486 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
487 fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
488 fd->config.err = ERROR_FD_NONE;
489 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
490 } else {
491 fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
492 }
493 }
494
__is_set_fd_config_rollangle(struct fimc_is * is,u32 val)495 void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val)
496 {
497 unsigned int index = is->config_index;
498 struct fd_param *fd;
499 unsigned long *p_index;
500
501 p_index = &is->config[index].p_region_index[1];
502 fd = &is->config[index].fd;
503
504 fd->config.roll_angle = val;
505
506 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
507 fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE;
508 fd->config.err = ERROR_FD_NONE;
509 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
510 } else {
511 fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE;
512 }
513 }
514
__is_set_fd_config_yawangle(struct fimc_is * is,u32 val)515 void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val)
516 {
517 unsigned int index = is->config_index;
518 struct fd_param *fd;
519 unsigned long *p_index;
520
521 p_index = &is->config[index].p_region_index[1];
522 fd = &is->config[index].fd;
523
524 fd->config.yaw_angle = val;
525
526 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
527 fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE;
528 fd->config.err = ERROR_FD_NONE;
529 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
530 } else {
531 fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE;
532 }
533 }
534
__is_set_fd_config_smilemode(struct fimc_is * is,u32 val)535 void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val)
536 {
537 unsigned int index = is->config_index;
538 struct fd_param *fd;
539 unsigned long *p_index;
540
541 p_index = &is->config[index].p_region_index[1];
542 fd = &is->config[index].fd;
543
544 fd->config.smile_mode = val;
545
546 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
547 fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE;
548 fd->config.err = ERROR_FD_NONE;
549 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
550 } else {
551 fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE;
552 }
553 }
554
__is_set_fd_config_blinkmode(struct fimc_is * is,u32 val)555 void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val)
556 {
557 unsigned int index = is->config_index;
558 struct fd_param *fd;
559 unsigned long *p_index;
560
561 p_index = &is->config[index].p_region_index[1];
562 fd = &is->config[index].fd;
563
564 fd->config.blink_mode = val;
565
566 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
567 fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE;
568 fd->config.err = ERROR_FD_NONE;
569 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
570 } else {
571 fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE;
572 }
573 }
574
__is_set_fd_config_eyedetect(struct fimc_is * is,u32 val)575 void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val)
576 {
577 unsigned int index = is->config_index;
578 struct fd_param *fd;
579 unsigned long *p_index;
580
581 p_index = &is->config[index].p_region_index[1];
582 fd = &is->config[index].fd;
583
584 fd->config.eye_detect = val;
585
586 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
587 fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT;
588 fd->config.err = ERROR_FD_NONE;
589 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
590 } else {
591 fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT;
592 }
593 }
594
__is_set_fd_config_mouthdetect(struct fimc_is * is,u32 val)595 void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val)
596 {
597 unsigned int index = is->config_index;
598 struct fd_param *fd;
599 unsigned long *p_index;
600
601 p_index = &is->config[index].p_region_index[1];
602 fd = &is->config[index].fd;
603
604 fd->config.mouth_detect = val;
605
606 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
607 fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT;
608 fd->config.err = ERROR_FD_NONE;
609 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
610 } else {
611 fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT;
612 }
613 }
614
__is_set_fd_config_orientation(struct fimc_is * is,u32 val)615 void __is_set_fd_config_orientation(struct fimc_is *is, u32 val)
616 {
617 unsigned int index = is->config_index;
618 struct fd_param *fd;
619 unsigned long *p_index;
620
621 p_index = &is->config[index].p_region_index[1];
622 fd = &is->config[index].fd;
623
624 fd->config.orientation = val;
625
626 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
627 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION;
628 fd->config.err = ERROR_FD_NONE;
629 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
630 } else {
631 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION;
632 }
633 }
634
__is_set_fd_config_orientation_val(struct fimc_is * is,u32 val)635 void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val)
636 {
637 unsigned int index = is->config_index;
638 struct fd_param *fd;
639 unsigned long *p_index;
640
641 p_index = &is->config[index].p_region_index[1];
642 fd = &is->config[index].fd;
643
644 fd->config.orientation_value = val;
645
646 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
647 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE;
648 fd->config.err = ERROR_FD_NONE;
649 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
650 } else {
651 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE;
652 }
653 }
654
fimc_is_set_initial_params(struct fimc_is * is)655 void fimc_is_set_initial_params(struct fimc_is *is)
656 {
657 struct global_param *global;
658 struct isp_param *isp;
659 struct drc_param *drc;
660 struct fd_param *fd;
661 unsigned long *p_index;
662 unsigned int index;
663
664 index = is->config_index;
665 global = &is->config[index].global;
666 isp = &is->config[index].isp;
667 drc = &is->config[index].drc;
668 fd = &is->config[index].fd;
669 p_index = &is->config[index].p_region_index[0];
670
671 /* Global */
672 global->shotmode.cmd = 1;
673 fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE);
674
675 /* ISP */
676 isp->control.cmd = CONTROL_COMMAND_START;
677 isp->control.bypass = CONTROL_BYPASS_DISABLE;
678 isp->control.err = CONTROL_ERROR_NONE;
679 fimc_is_set_param_bit(is, PARAM_ISP_CONTROL);
680
681 isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
682 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index)) {
683 isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
684 isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
685 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
686 }
687 if (is->sensor->test_pattern)
688 isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER;
689 else
690 isp->otf_input.format = OTF_INPUT_FORMAT_BAYER;
691 isp->otf_input.bitwidth = 10;
692 isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG;
693 isp->otf_input.crop_offset_x = 0;
694 isp->otf_input.crop_offset_y = 0;
695 isp->otf_input.err = OTF_INPUT_ERROR_NONE;
696
697 isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE;
698 isp->dma1_input.width = 0;
699 isp->dma1_input.height = 0;
700 isp->dma1_input.format = 0;
701 isp->dma1_input.bitwidth = 0;
702 isp->dma1_input.plane = 0;
703 isp->dma1_input.order = 0;
704 isp->dma1_input.buffer_number = 0;
705 isp->dma1_input.width = 0;
706 isp->dma1_input.err = DMA_INPUT_ERROR_NONE;
707 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT);
708
709 isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE;
710 isp->dma2_input.width = 0;
711 isp->dma2_input.height = 0;
712 isp->dma2_input.format = 0;
713 isp->dma2_input.bitwidth = 0;
714 isp->dma2_input.plane = 0;
715 isp->dma2_input.order = 0;
716 isp->dma2_input.buffer_number = 0;
717 isp->dma2_input.width = 0;
718 isp->dma2_input.err = DMA_INPUT_ERROR_NONE;
719 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT);
720
721 isp->aa.cmd = ISP_AA_COMMAND_START;
722 isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB;
723 fimc_is_set_param_bit(is, PARAM_ISP_AA);
724
725 if (!test_bit(PARAM_ISP_FLASH, p_index))
726 __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE,
727 ISP_FLASH_REDEYE_DISABLE);
728
729 if (!test_bit(PARAM_ISP_AWB, p_index))
730 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
731
732 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index))
733 __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE);
734
735 if (!test_bit(PARAM_ISP_ISO, p_index))
736 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
737
738 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
739 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0);
740 __is_set_isp_adjust(is,
741 ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0);
742 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0);
743 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0);
744 __is_set_isp_adjust(is,
745 ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0);
746 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0);
747 }
748
749 if (!test_bit(PARAM_ISP_METERING, p_index)) {
750 __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER);
751 __is_set_isp_metering(is, 1, 0);
752 __is_set_isp_metering(is, 2, 0);
753 __is_set_isp_metering(is, 3, 0);
754 __is_set_isp_metering(is, 4, 0);
755 }
756
757 if (!test_bit(PARAM_ISP_AFC, p_index))
758 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
759
760 isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
761 if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index)) {
762 isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
763 isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
764 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
765 }
766 isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
767 isp->otf_output.bitwidth = 12;
768 isp->otf_output.order = 0;
769 isp->otf_output.err = OTF_OUTPUT_ERROR_NONE;
770
771 if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index)) {
772 isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
773 isp->dma1_output.width = 0;
774 isp->dma1_output.height = 0;
775 isp->dma1_output.format = 0;
776 isp->dma1_output.bitwidth = 0;
777 isp->dma1_output.plane = 0;
778 isp->dma1_output.order = 0;
779 isp->dma1_output.buffer_number = 0;
780 isp->dma1_output.buffer_address = 0;
781 isp->dma1_output.notify_dma_done = 0;
782 isp->dma1_output.dma_out_mask = 0;
783 isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE;
784 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT);
785 }
786
787 if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index)) {
788 isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
789 isp->dma2_output.width = 0;
790 isp->dma2_output.height = 0;
791 isp->dma2_output.format = 0;
792 isp->dma2_output.bitwidth = 0;
793 isp->dma2_output.plane = 0;
794 isp->dma2_output.order = 0;
795 isp->dma2_output.buffer_number = 0;
796 isp->dma2_output.buffer_address = 0;
797 isp->dma2_output.notify_dma_done = 0;
798 isp->dma2_output.dma_out_mask = 0;
799 isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE;
800 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
801 }
802
803 /* Sensor */
804 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index)) {
805 if (is->config_index == 0)
806 __is_set_sensor(is, 0);
807 }
808
809 /* DRC */
810 drc->control.cmd = CONTROL_COMMAND_START;
811 __is_set_drc_control(is, CONTROL_BYPASS_ENABLE);
812
813 drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
814 if (!test_bit(PARAM_DRC_OTF_INPUT, p_index)) {
815 drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
816 drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
817 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
818 }
819 drc->otf_input.format = OTF_INPUT_FORMAT_YUV444;
820 drc->otf_input.bitwidth = 12;
821 drc->otf_input.order = 0;
822 drc->otf_input.err = OTF_INPUT_ERROR_NONE;
823
824 drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
825 drc->dma_input.width = 0;
826 drc->dma_input.height = 0;
827 drc->dma_input.format = 0;
828 drc->dma_input.bitwidth = 0;
829 drc->dma_input.plane = 0;
830 drc->dma_input.order = 0;
831 drc->dma_input.buffer_number = 0;
832 drc->dma_input.width = 0;
833 drc->dma_input.err = DMA_INPUT_ERROR_NONE;
834 fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT);
835
836 drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
837 if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index)) {
838 drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
839 drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
840 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
841 }
842 drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
843 drc->otf_output.bitwidth = 8;
844 drc->otf_output.order = 0;
845 drc->otf_output.err = OTF_OUTPUT_ERROR_NONE;
846
847 /* FD */
848 __is_set_fd_control(is, CONTROL_COMMAND_STOP);
849 fd->control.bypass = CONTROL_BYPASS_DISABLE;
850
851 fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
852 if (!test_bit(PARAM_FD_OTF_INPUT, p_index)) {
853 fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
854 fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
855 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
856 }
857
858 fd->otf_input.format = OTF_INPUT_FORMAT_YUV444;
859 fd->otf_input.bitwidth = 8;
860 fd->otf_input.order = 0;
861 fd->otf_input.err = OTF_INPUT_ERROR_NONE;
862
863 fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
864 fd->dma_input.width = 0;
865 fd->dma_input.height = 0;
866 fd->dma_input.format = 0;
867 fd->dma_input.bitwidth = 0;
868 fd->dma_input.plane = 0;
869 fd->dma_input.order = 0;
870 fd->dma_input.buffer_number = 0;
871 fd->dma_input.width = 0;
872 fd->dma_input.err = DMA_INPUT_ERROR_NONE;
873 fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT);
874
875 __is_set_fd_config_maxface(is, 5);
876 __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL);
877 __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90);
878 __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE);
879 __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE);
880 __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE);
881 __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE);
882 __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE);
883 __is_set_fd_config_orientation_val(is, 0);
884 }
885