1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * camss-csiphy.h
4  *
5  * Qualcomm MSM Camera Subsystem - CSIPHY Module
6  *
7  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8  * Copyright (C) 2016-2018 Linaro Ltd.
9  */
10 #ifndef QC_MSM_CAMSS_CSIPHY_H
11 #define QC_MSM_CAMSS_CSIPHY_H
12 
13 #include <linux/clk.h>
14 #include <linux/interrupt.h>
15 #include <media/media-entity.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-mediabus.h>
18 #include <media/v4l2-subdev.h>
19 
20 #define MSM_CSIPHY_PAD_SINK 0
21 #define MSM_CSIPHY_PAD_SRC 1
22 #define MSM_CSIPHY_PADS_NUM 2
23 
24 struct csiphy_lane {
25 	u8 pos;
26 	u8 pol;
27 };
28 
29 /**
30  * struct csiphy_lanes_cfg - CSIPHY lanes configuration
31  * @num_data: number of data lanes
32  * @data:     data lanes configuration
33  * @clk:      clock lane configuration (only for D-PHY)
34  */
35 struct csiphy_lanes_cfg {
36 	int num_data;
37 	struct csiphy_lane *data;
38 	struct csiphy_lane clk;
39 };
40 
41 struct csiphy_csi2_cfg {
42 	struct csiphy_lanes_cfg lane_cfg;
43 };
44 
45 struct csiphy_config {
46 	u8 combo_mode;
47 	u8 csid_id;
48 	struct csiphy_csi2_cfg *csi2;
49 };
50 
51 struct csiphy_format_info {
52 	u32 code;
53 	u8 bpp;
54 };
55 
56 struct csiphy_formats {
57 	unsigned int nformats;
58 	const struct csiphy_format_info *formats;
59 };
60 
61 struct csiphy_device;
62 
63 struct csiphy_hw_ops {
64 	/*
65 	 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
66 	 * @lane_cfg - CSI2 lane configuration
67 	 *
68 	 * Return lane mask
69 	 */
70 	u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
71 	void (*hw_version_read)(struct csiphy_device *csiphy,
72 				struct device *dev);
73 	void (*reset)(struct csiphy_device *csiphy);
74 	void (*lanes_enable)(struct csiphy_device *csiphy,
75 			     struct csiphy_config *cfg,
76 			     s64 link_freq, u8 lane_mask);
77 	void (*lanes_disable)(struct csiphy_device *csiphy,
78 			      struct csiphy_config *cfg);
79 	irqreturn_t (*isr)(int irq, void *dev);
80 };
81 
82 struct csiphy_subdev_resources {
83 	const struct csiphy_hw_ops *hw_ops;
84 	const struct csiphy_formats *formats;
85 };
86 
87 struct csiphy_device {
88 	struct camss *camss;
89 	u8 id;
90 	struct v4l2_subdev subdev;
91 	struct media_pad pads[MSM_CSIPHY_PADS_NUM];
92 	void __iomem *base;
93 	void __iomem *base_clk_mux;
94 	u32 irq;
95 	char irq_name[30];
96 	struct camss_clock *clock;
97 	bool *rate_set;
98 	int nclocks;
99 	u32 timer_clk_rate;
100 	struct regulator_bulk_data *supplies;
101 	int num_supplies;
102 	struct csiphy_config cfg;
103 	struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
104 	const struct csiphy_subdev_resources *res;
105 };
106 
107 struct camss_subdev_resources;
108 
109 int msm_csiphy_subdev_init(struct camss *camss,
110 			   struct csiphy_device *csiphy,
111 			   const struct camss_subdev_resources *res, u8 id);
112 
113 int msm_csiphy_register_entity(struct csiphy_device *csiphy,
114 			       struct v4l2_device *v4l2_dev);
115 
116 void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
117 
118 extern const struct csiphy_formats csiphy_formats_8x16;
119 extern const struct csiphy_formats csiphy_formats_8x96;
120 extern const struct csiphy_formats csiphy_formats_sc7280;
121 extern const struct csiphy_formats csiphy_formats_sdm845;
122 
123 extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
124 extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
125 
126 #endif /* QC_MSM_CAMSS_CSIPHY_H */
127