1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019-2020 NXP
4 */
5
6 #include <linux/clk.h>
7 #include <linux/device.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/property.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
19 #include <linux/types.h>
20
21 #include <media/media-device.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-mc.h>
25
26 #include "imx8-isi-core.h"
27
28 /* -----------------------------------------------------------------------------
29 * V4L2 async subdevs
30 */
31
32 struct mxc_isi_async_subdev {
33 struct v4l2_async_connection asd;
34 unsigned int port;
35 };
36
37 static inline struct mxc_isi_async_subdev *
asd_to_mxc_isi_async_subdev(struct v4l2_async_connection * asd)38 asd_to_mxc_isi_async_subdev(struct v4l2_async_connection *asd)
39 {
40 return container_of(asd, struct mxc_isi_async_subdev, asd);
41 };
42
43 static inline struct mxc_isi_dev *
notifier_to_mxc_isi_dev(struct v4l2_async_notifier * n)44 notifier_to_mxc_isi_dev(struct v4l2_async_notifier *n)
45 {
46 return container_of(n, struct mxc_isi_dev, notifier);
47 };
48
mxc_isi_async_notifier_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_connection * asc)49 static int mxc_isi_async_notifier_bound(struct v4l2_async_notifier *notifier,
50 struct v4l2_subdev *sd,
51 struct v4l2_async_connection *asc)
52 {
53 const unsigned int link_flags = MEDIA_LNK_FL_IMMUTABLE
54 | MEDIA_LNK_FL_ENABLED;
55 struct mxc_isi_dev *isi = notifier_to_mxc_isi_dev(notifier);
56 struct mxc_isi_async_subdev *masd = asd_to_mxc_isi_async_subdev(asc);
57 struct media_pad *pad = &isi->crossbar.pads[masd->port];
58 struct device_link *link;
59
60 dev_dbg(isi->dev, "Bound subdev %s to crossbar input %u\n", sd->name,
61 masd->port);
62
63 /*
64 * Enforce suspend/resume ordering between the source (supplier) and
65 * the ISI (consumer). The source will be suspended before and resume
66 * after the ISI.
67 */
68 link = device_link_add(isi->dev, sd->dev, DL_FLAG_STATELESS);
69 if (!link) {
70 dev_err(isi->dev,
71 "Failed to create device link to source %s\n", sd->name);
72 return -EINVAL;
73 }
74
75 return v4l2_create_fwnode_links_to_pad(sd, pad, link_flags);
76 }
77
mxc_isi_async_notifier_complete(struct v4l2_async_notifier * notifier)78 static int mxc_isi_async_notifier_complete(struct v4l2_async_notifier *notifier)
79 {
80 struct mxc_isi_dev *isi = notifier_to_mxc_isi_dev(notifier);
81 int ret;
82
83 dev_dbg(isi->dev, "All subdevs bound\n");
84
85 ret = v4l2_device_register_subdev_nodes(&isi->v4l2_dev);
86 if (ret < 0) {
87 dev_err(isi->dev,
88 "Failed to register subdev nodes: %d\n", ret);
89 return ret;
90 }
91
92 return media_device_register(&isi->media_dev);
93 }
94
95 static const struct v4l2_async_notifier_operations mxc_isi_async_notifier_ops = {
96 .bound = mxc_isi_async_notifier_bound,
97 .complete = mxc_isi_async_notifier_complete,
98 };
99
mxc_isi_pipe_register(struct mxc_isi_pipe * pipe)100 static int mxc_isi_pipe_register(struct mxc_isi_pipe *pipe)
101 {
102 int ret;
103
104 ret = v4l2_device_register_subdev(&pipe->isi->v4l2_dev, &pipe->sd);
105 if (ret < 0)
106 return ret;
107
108 return mxc_isi_video_register(pipe, &pipe->isi->v4l2_dev);
109 }
110
mxc_isi_pipe_unregister(struct mxc_isi_pipe * pipe)111 static void mxc_isi_pipe_unregister(struct mxc_isi_pipe *pipe)
112 {
113 mxc_isi_video_unregister(pipe);
114 }
115
mxc_isi_v4l2_init(struct mxc_isi_dev * isi)116 static int mxc_isi_v4l2_init(struct mxc_isi_dev *isi)
117 {
118 struct fwnode_handle *node = dev_fwnode(isi->dev);
119 struct media_device *media_dev = &isi->media_dev;
120 struct v4l2_device *v4l2_dev = &isi->v4l2_dev;
121 unsigned int i;
122 int ret;
123
124 /* Initialize the media device. */
125 strscpy(media_dev->model, "FSL Capture Media Device",
126 sizeof(media_dev->model));
127 media_dev->dev = isi->dev;
128
129 media_device_init(media_dev);
130
131 /* Initialize and register the V4L2 device. */
132 v4l2_dev->mdev = media_dev;
133 strscpy(v4l2_dev->name, "mx8-img-md", sizeof(v4l2_dev->name));
134
135 ret = v4l2_device_register(isi->dev, v4l2_dev);
136 if (ret < 0) {
137 dev_err(isi->dev,
138 "Failed to register V4L2 device: %d\n", ret);
139 goto err_media;
140 }
141
142 /* Register the crossbar switch subdev. */
143 ret = mxc_isi_crossbar_register(&isi->crossbar);
144 if (ret < 0) {
145 dev_err(isi->dev, "Failed to register crossbar: %d\n", ret);
146 goto err_v4l2;
147 }
148
149 /* Register the pipeline subdevs and link them to the crossbar switch. */
150 for (i = 0; i < isi->pdata->num_channels; ++i) {
151 struct mxc_isi_pipe *pipe = &isi->pipes[i];
152
153 ret = mxc_isi_pipe_register(pipe);
154 if (ret < 0) {
155 dev_err(isi->dev, "Failed to register pipe%u: %d\n", i,
156 ret);
157 goto err_v4l2;
158 }
159
160 ret = media_create_pad_link(&isi->crossbar.sd.entity,
161 isi->crossbar.num_sinks + i,
162 &pipe->sd.entity,
163 MXC_ISI_PIPE_PAD_SINK,
164 MEDIA_LNK_FL_IMMUTABLE |
165 MEDIA_LNK_FL_ENABLED);
166 if (ret < 0)
167 goto err_v4l2;
168 }
169
170 /* Register the M2M device. */
171 ret = mxc_isi_m2m_register(isi, v4l2_dev);
172 if (ret < 0) {
173 dev_err(isi->dev, "Failed to register M2M device: %d\n", ret);
174 goto err_v4l2;
175 }
176
177 /* Initialize, fill and register the async notifier. */
178 v4l2_async_nf_init(&isi->notifier, v4l2_dev);
179 isi->notifier.ops = &mxc_isi_async_notifier_ops;
180
181 for (i = 0; i < isi->pdata->num_ports; ++i) {
182 struct mxc_isi_async_subdev *masd;
183 struct fwnode_handle *ep;
184
185 ep = fwnode_graph_get_endpoint_by_id(node, i, 0,
186 FWNODE_GRAPH_ENDPOINT_NEXT);
187
188 if (!ep)
189 continue;
190
191 masd = v4l2_async_nf_add_fwnode_remote(&isi->notifier, ep,
192 struct mxc_isi_async_subdev);
193 fwnode_handle_put(ep);
194
195 if (IS_ERR(masd)) {
196 ret = PTR_ERR(masd);
197 goto err_m2m;
198 }
199
200 masd->port = i;
201 }
202
203 ret = v4l2_async_nf_register(&isi->notifier);
204 if (ret < 0) {
205 dev_err(isi->dev,
206 "Failed to register async notifier: %d\n", ret);
207 goto err_m2m;
208 }
209
210 return 0;
211
212 err_m2m:
213 mxc_isi_m2m_unregister(isi);
214 v4l2_async_nf_cleanup(&isi->notifier);
215 err_v4l2:
216 v4l2_device_unregister(v4l2_dev);
217 err_media:
218 media_device_cleanup(media_dev);
219 return ret;
220 }
221
mxc_isi_v4l2_cleanup(struct mxc_isi_dev * isi)222 static void mxc_isi_v4l2_cleanup(struct mxc_isi_dev *isi)
223 {
224 unsigned int i;
225
226 v4l2_async_nf_unregister(&isi->notifier);
227 v4l2_async_nf_cleanup(&isi->notifier);
228
229 v4l2_device_unregister(&isi->v4l2_dev);
230 media_device_unregister(&isi->media_dev);
231
232 mxc_isi_m2m_unregister(isi);
233
234 for (i = 0; i < isi->pdata->num_channels; ++i)
235 mxc_isi_pipe_unregister(&isi->pipes[i]);
236
237 mxc_isi_crossbar_unregister(&isi->crossbar);
238
239 media_device_cleanup(&isi->media_dev);
240 }
241
242 /* -----------------------------------------------------------------------------
243 * Device information
244 */
245
246 /* Panic will assert when the buffers are 50% full */
247
248 /* For i.MX8QXP C0 and i.MX8MN ISI IER version */
249 static const struct mxc_isi_ier_reg mxc_imx8_isi_ier_v1 = {
250 .oflw_y_buf_en = { .offset = 19, .mask = 0x80000 },
251 .oflw_u_buf_en = { .offset = 21, .mask = 0x200000 },
252 .oflw_v_buf_en = { .offset = 23, .mask = 0x800000 },
253
254 .panic_y_buf_en = {.offset = 20, .mask = 0x100000 },
255 .panic_u_buf_en = {.offset = 22, .mask = 0x400000 },
256 .panic_v_buf_en = {.offset = 24, .mask = 0x1000000 },
257 };
258
259 /* For i.MX8MP ISI IER version */
260 static const struct mxc_isi_ier_reg mxc_imx8_isi_ier_v2 = {
261 .oflw_y_buf_en = { .offset = 18, .mask = 0x40000 },
262 .oflw_u_buf_en = { .offset = 20, .mask = 0x100000 },
263 .oflw_v_buf_en = { .offset = 22, .mask = 0x400000 },
264
265 .panic_y_buf_en = {.offset = 19, .mask = 0x80000 },
266 .panic_u_buf_en = {.offset = 21, .mask = 0x200000 },
267 .panic_v_buf_en = {.offset = 23, .mask = 0x800000 },
268 };
269
270 /* Panic will assert when the buffers are 50% full */
271 static const struct mxc_isi_set_thd mxc_imx8_isi_thd_v1 = {
272 .panic_set_thd_y = { .mask = 0x0000f, .offset = 0, .threshold = 0x7 },
273 .panic_set_thd_u = { .mask = 0x00f00, .offset = 8, .threshold = 0x7 },
274 .panic_set_thd_v = { .mask = 0xf0000, .offset = 16, .threshold = 0x7 },
275 };
276
277 static const struct clk_bulk_data mxc_imx8mn_clks[] = {
278 { .id = "axi" },
279 { .id = "apb" },
280 };
281
282 static const struct mxc_isi_plat_data mxc_imx8mn_data = {
283 .model = MXC_ISI_IMX8MN,
284 .num_ports = 1,
285 .num_channels = 1,
286 .reg_offset = 0,
287 .ier_reg = &mxc_imx8_isi_ier_v1,
288 .set_thd = &mxc_imx8_isi_thd_v1,
289 .clks = mxc_imx8mn_clks,
290 .num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
291 .buf_active_reverse = false,
292 .gasket_ops = &mxc_imx8_gasket_ops,
293 .has_36bit_dma = false,
294 };
295
296 static const struct mxc_isi_plat_data mxc_imx8mp_data = {
297 .model = MXC_ISI_IMX8MP,
298 .num_ports = 2,
299 .num_channels = 2,
300 .reg_offset = 0x2000,
301 .ier_reg = &mxc_imx8_isi_ier_v2,
302 .set_thd = &mxc_imx8_isi_thd_v1,
303 .clks = mxc_imx8mn_clks,
304 .num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
305 .buf_active_reverse = true,
306 .gasket_ops = &mxc_imx8_gasket_ops,
307 .has_36bit_dma = true,
308 };
309
310 static const struct mxc_isi_plat_data mxc_imx8ulp_data = {
311 .model = MXC_ISI_IMX8ULP,
312 .num_ports = 1,
313 .num_channels = 1,
314 .reg_offset = 0x0,
315 .ier_reg = &mxc_imx8_isi_ier_v2,
316 .set_thd = &mxc_imx8_isi_thd_v1,
317 .clks = mxc_imx8mn_clks,
318 .num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
319 .buf_active_reverse = true,
320 .has_36bit_dma = false,
321 };
322
323 static const struct mxc_isi_plat_data mxc_imx93_data = {
324 .model = MXC_ISI_IMX93,
325 .num_ports = 1,
326 .num_channels = 1,
327 .reg_offset = 0,
328 .ier_reg = &mxc_imx8_isi_ier_v2,
329 .set_thd = &mxc_imx8_isi_thd_v1,
330 .clks = mxc_imx8mn_clks,
331 .num_clks = ARRAY_SIZE(mxc_imx8mn_clks),
332 .buf_active_reverse = true,
333 .gasket_ops = &mxc_imx93_gasket_ops,
334 .has_36bit_dma = false,
335 };
336
337 /* -----------------------------------------------------------------------------
338 * Power management
339 */
340
mxc_isi_pm_suspend(struct device * dev)341 static int mxc_isi_pm_suspend(struct device *dev)
342 {
343 struct mxc_isi_dev *isi = dev_get_drvdata(dev);
344 unsigned int i;
345
346 for (i = 0; i < isi->pdata->num_channels; ++i) {
347 struct mxc_isi_pipe *pipe = &isi->pipes[i];
348
349 mxc_isi_video_suspend(pipe);
350 }
351
352 return pm_runtime_force_suspend(dev);
353 }
354
mxc_isi_pm_resume(struct device * dev)355 static int mxc_isi_pm_resume(struct device *dev)
356 {
357 struct mxc_isi_dev *isi = dev_get_drvdata(dev);
358 unsigned int i;
359 int err = 0;
360 int ret;
361
362 ret = pm_runtime_force_resume(dev);
363 if (ret < 0)
364 return ret;
365
366 for (i = 0; i < isi->pdata->num_channels; ++i) {
367 struct mxc_isi_pipe *pipe = &isi->pipes[i];
368
369 ret = mxc_isi_video_resume(pipe);
370 if (ret) {
371 dev_err(dev, "Failed to resume pipeline %u (%d)\n", i,
372 ret);
373 /*
374 * Record the last error as it's as meaningful as any,
375 * and continue resuming the other pipelines.
376 */
377 err = ret;
378 }
379 }
380
381 return err;
382 }
383
mxc_isi_runtime_suspend(struct device * dev)384 static int mxc_isi_runtime_suspend(struct device *dev)
385 {
386 struct mxc_isi_dev *isi = dev_get_drvdata(dev);
387
388 clk_bulk_disable_unprepare(isi->pdata->num_clks, isi->clks);
389
390 return 0;
391 }
392
mxc_isi_runtime_resume(struct device * dev)393 static int mxc_isi_runtime_resume(struct device *dev)
394 {
395 struct mxc_isi_dev *isi = dev_get_drvdata(dev);
396 int ret;
397
398 ret = clk_bulk_prepare_enable(isi->pdata->num_clks, isi->clks);
399 if (ret) {
400 dev_err(dev, "Failed to enable clocks (%d)\n", ret);
401 return ret;
402 }
403
404 return 0;
405 }
406
407 static const struct dev_pm_ops mxc_isi_pm_ops = {
408 SYSTEM_SLEEP_PM_OPS(mxc_isi_pm_suspend, mxc_isi_pm_resume)
409 RUNTIME_PM_OPS(mxc_isi_runtime_suspend, mxc_isi_runtime_resume, NULL)
410 };
411
412 /* -----------------------------------------------------------------------------
413 * Probe, remove & driver
414 */
415
mxc_isi_clk_get(struct mxc_isi_dev * isi)416 static int mxc_isi_clk_get(struct mxc_isi_dev *isi)
417 {
418 unsigned int size = isi->pdata->num_clks
419 * sizeof(*isi->clks);
420 int ret;
421
422 isi->clks = devm_kmemdup(isi->dev, isi->pdata->clks, size, GFP_KERNEL);
423 if (!isi->clks)
424 return -ENOMEM;
425
426 ret = devm_clk_bulk_get(isi->dev, isi->pdata->num_clks,
427 isi->clks);
428 if (ret < 0) {
429 dev_err(isi->dev, "Failed to acquire clocks: %d\n",
430 ret);
431 return ret;
432 }
433
434 return 0;
435 }
436
mxc_isi_probe(struct platform_device * pdev)437 static int mxc_isi_probe(struct platform_device *pdev)
438 {
439 struct device *dev = &pdev->dev;
440 struct mxc_isi_dev *isi;
441 unsigned int dma_size;
442 unsigned int i;
443 int ret = 0;
444
445 isi = devm_kzalloc(dev, sizeof(*isi), GFP_KERNEL);
446 if (!isi)
447 return -ENOMEM;
448
449 isi->dev = dev;
450 platform_set_drvdata(pdev, isi);
451
452 isi->pdata = of_device_get_match_data(dev);
453
454 isi->pipes = kcalloc(isi->pdata->num_channels, sizeof(isi->pipes[0]),
455 GFP_KERNEL);
456 if (!isi->pipes)
457 return -ENOMEM;
458
459 ret = mxc_isi_clk_get(isi);
460 if (ret < 0) {
461 dev_err(dev, "Failed to get clocks\n");
462 return ret;
463 }
464
465 isi->regs = devm_platform_ioremap_resource(pdev, 0);
466 if (IS_ERR(isi->regs)) {
467 dev_err(dev, "Failed to get ISI register map\n");
468 return PTR_ERR(isi->regs);
469 }
470
471 if (isi->pdata->gasket_ops) {
472 isi->gasket = syscon_regmap_lookup_by_phandle(dev->of_node,
473 "fsl,blk-ctrl");
474 if (IS_ERR(isi->gasket)) {
475 ret = PTR_ERR(isi->gasket);
476 dev_err(dev, "failed to get gasket: %d\n", ret);
477 return ret;
478 }
479 }
480
481 dma_size = isi->pdata->has_36bit_dma ? 36 : 32;
482 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_size));
483 if (ret) {
484 dev_err(dev, "failed to set DMA mask\n");
485 return ret;
486 }
487
488 pm_runtime_enable(dev);
489
490 ret = mxc_isi_crossbar_init(isi);
491 if (ret) {
492 dev_err(dev, "Failed to initialize crossbar: %d\n", ret);
493 goto err_pm;
494 }
495
496 for (i = 0; i < isi->pdata->num_channels; ++i) {
497 ret = mxc_isi_pipe_init(isi, i);
498 if (ret < 0) {
499 dev_err(dev, "Failed to initialize pipe%u: %d\n", i,
500 ret);
501 goto err_xbar;
502 }
503 }
504
505 ret = mxc_isi_v4l2_init(isi);
506 if (ret < 0) {
507 dev_err(dev, "Failed to initialize V4L2: %d\n", ret);
508 goto err_xbar;
509 }
510
511 mxc_isi_debug_init(isi);
512
513 return 0;
514
515 err_xbar:
516 mxc_isi_crossbar_cleanup(&isi->crossbar);
517 err_pm:
518 pm_runtime_disable(isi->dev);
519 return ret;
520 }
521
mxc_isi_remove(struct platform_device * pdev)522 static void mxc_isi_remove(struct platform_device *pdev)
523 {
524 struct mxc_isi_dev *isi = platform_get_drvdata(pdev);
525 unsigned int i;
526
527 mxc_isi_debug_cleanup(isi);
528
529 for (i = 0; i < isi->pdata->num_channels; ++i) {
530 struct mxc_isi_pipe *pipe = &isi->pipes[i];
531
532 mxc_isi_pipe_cleanup(pipe);
533 }
534
535 mxc_isi_crossbar_cleanup(&isi->crossbar);
536 mxc_isi_v4l2_cleanup(isi);
537
538 pm_runtime_disable(isi->dev);
539 }
540
541 static const struct of_device_id mxc_isi_of_match[] = {
542 { .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
543 { .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data },
544 { .compatible = "fsl,imx8ulp-isi", .data = &mxc_imx8ulp_data },
545 { .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data },
546 { /* sentinel */ },
547 };
548 MODULE_DEVICE_TABLE(of, mxc_isi_of_match);
549
550 static struct platform_driver mxc_isi_driver = {
551 .probe = mxc_isi_probe,
552 .remove = mxc_isi_remove,
553 .driver = {
554 .of_match_table = mxc_isi_of_match,
555 .name = MXC_ISI_DRIVER_NAME,
556 .pm = pm_ptr(&mxc_isi_pm_ops),
557 }
558 };
559 module_platform_driver(mxc_isi_driver);
560
561 MODULE_ALIAS("ISI");
562 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
563 MODULE_DESCRIPTION("IMX8 Image Sensing Interface driver");
564 MODULE_LICENSE("GPL");
565