1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig MAILBOX
3	bool "Mailbox Hardware Support"
4	help
5	  Mailbox is a framework to control hardware communication between
6	  on-chip processors through queued messages and interrupt driven
7	  signals. Say Y if your platform supports hardware mailboxes.
8
9if MAILBOX
10
11config ARM_MHU
12	tristate "ARM MHU Mailbox"
13	depends on ARM_AMBA
14	help
15	  Say Y here if you want to build the ARM MHU controller driver.
16	  The controller has 3 mailbox channels, the last of which can be
17	  used in Secure mode only.
18
19config ARM_MHU_V2
20	tristate "ARM MHUv2 Mailbox"
21	depends on ARM_AMBA
22	help
23	  Say Y here if you want to build the ARM MHUv2 controller driver,
24	  which provides unidirectional mailboxes between processing elements.
25
26config ARM_MHU_V3
27	tristate "ARM MHUv3 Mailbox"
28	depends on ARM64 || COMPILE_TEST
29	depends on HAS_IOMEM || COMPILE_TEST
30	depends on OF
31	help
32	  Say Y here if you want to build the ARM MHUv3 controller driver,
33	  which provides unidirectional mailboxes between processing elements.
34
35	  ARM MHUv3 controllers can implement a varying number of extensions
36	  that provides different means of transports: supported extensions
37	  will be discovered and possibly managed at probe-time.
38
39config EXYNOS_MBOX
40	tristate "Exynos Mailbox"
41	depends on ARCH_EXYNOS || COMPILE_TEST
42	help
43	  Say Y here if you want to build the Samsung Exynos Mailbox controller
44	  driver. The controller has 16 flag bits for hardware interrupt
45	  generation and a shared register for passing mailbox messages.
46	  When the controller is used by the ACPM interface the shared register
47	  is ignored and the mailbox controller acts as a doorbell that raises
48	  the interrupt to the ACPM firmware.
49
50config IMX_MBOX
51	tristate "i.MX Mailbox"
52	depends on ARCH_MXC || COMPILE_TEST
53	help
54	  Mailbox implementation for i.MX Messaging Unit (MU).
55
56config PLATFORM_MHU
57	tristate "Platform MHU Mailbox"
58	depends on OF
59	depends on HAS_IOMEM
60	help
61	  Say Y here if you want to build a platform specific variant MHU
62	  controller driver.
63	  The controller has a maximum of 3 mailbox channels, the last of
64	  which can be used in Secure mode only.
65
66config PL320_MBOX
67	bool "ARM PL320 Mailbox"
68	depends on ARM_AMBA
69	help
70	  An implementation of the ARM PL320 Interprocessor Communication
71	  Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
72	  send short messages between Highbank's A9 cores and the EnergyCore
73	  Management Engine, primarily for cpufreq. Say Y here if you want
74	  to use the PL320 IPCM support.
75
76config ARMADA_37XX_RWTM_MBOX
77	tristate "Armada 37xx rWTM BIU Mailbox"
78	depends on ARCH_MVEBU || COMPILE_TEST
79	depends on OF
80	help
81	  Mailbox implementation for communication with the the firmware
82	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
83	  SOC. Say Y here if you are building for such a device (for example
84	  the Turris Mox router).
85
86config OMAP2PLUS_MBOX
87	tristate "OMAP2+ Mailbox framework support"
88	depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
89	help
90	  Mailbox implementation for OMAP family chips with hardware for
91	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
92	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
93	  want to use OMAP2+ Mailbox framework support.
94
95config ROCKCHIP_MBOX
96	bool "Rockchip Soc Integrated Mailbox Support"
97	depends on ARCH_ROCKCHIP || COMPILE_TEST
98	help
99	  This driver provides support for inter-processor communication
100	  between CPU cores and MCU processor on Some Rockchip SOCs.
101	  Please check it that the Soc you use have Mailbox hardware.
102	  Say Y here if you want to use the Rockchip Mailbox support.
103
104config PCC
105	bool "Platform Communication Channel Driver"
106	depends on ACPI
107	default n
108	help
109	  ACPI 5.0+ spec defines a generic mode of communication
110	  between the OS and a platform such as the BMC. This medium
111	  (PCC) is typically used by CPPC (ACPI CPU Performance management),
112	  RAS (ACPI reliability protocol) and MPST (ACPI Memory power
113	  states). Select this driver if your platform implements the
114	  PCC clients mentioned above.
115
116config ALTERA_MBOX
117	tristate "Altera Mailbox"
118	depends on HAS_IOMEM
119	help
120	  An implementation of the Altera Mailbox soft core. It is used
121	  to send message between processors. Say Y here if you want to use the
122	  Altera mailbox support.
123
124config BCM2835_MBOX
125	tristate "BCM2835 Mailbox"
126	depends on ARCH_BCM2835
127	help
128	  An implementation of the BCM2385 Mailbox.  It is used to invoke
129	  the services of the Videocore. Say Y here if you want to use the
130	  BCM2835 Mailbox.
131
132config STI_MBOX
133	tristate "STI Mailbox framework support"
134	depends on ARCH_STI && OF
135	help
136	  Mailbox implementation for STMicroelectonics family chips with
137	  hardware for interprocessor communication.
138
139config TI_MESSAGE_MANAGER
140	tristate "Texas Instruments Message Manager Driver"
141	depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
142	default ARCH_K3
143	help
144	  An implementation of Message Manager slave driver for Keystone
145	  and K3 architecture SoCs from Texas Instruments. Message Manager
146	  is a communication entity found on few of Texas Instrument's keystone
147	  and K3 architecture SoCs. These may be used for communication between
148	  multiple processors within the SoC. Select this driver if your
149	  platform has support for the hardware block.
150
151config HI3660_MBOX
152	tristate "Hi3660 Mailbox" if EXPERT
153	depends on (ARCH_HISI || COMPILE_TEST)
154	depends on OF
155	default ARCH_HISI
156	help
157	  An implementation of the hi3660 mailbox. It is used to send message
158	  between application processors and other processors/MCU/DSP. Select
159	  Y here if you want to use Hi3660 mailbox controller.
160
161config HI6220_MBOX
162	tristate "Hi6220 Mailbox" if EXPERT
163	depends on (ARCH_HISI || COMPILE_TEST)
164	depends on OF
165	default ARCH_HISI
166	help
167	  An implementation of the hi6220 mailbox. It is used to send message
168	  between application processors and MCU. Say Y here if you want to
169	  build Hi6220 mailbox controller driver.
170
171config MAILBOX_TEST
172	tristate "Mailbox Test Client"
173	depends on OF
174	depends on HAS_IOMEM
175	help
176	  Test client to help with testing new Controller driver
177	  implementations.
178
179config POLARFIRE_SOC_MAILBOX
180	tristate "PolarFire SoC (MPFS) Mailbox"
181	depends on HAS_IOMEM
182	depends on MFD_SYSCON
183	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
184	help
185	  This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
186
187	  To compile this driver as a module, choose M here. the
188	  module will be called mailbox-mpfs.
189
190	  If unsure, say N.
191
192config MCHP_SBI_IPC_MBOX
193	tristate "Microchip Inter-processor Communication (IPC) SBI driver"
194	depends on RISCV_SBI || COMPILE_TEST
195	depends on ARCH_MICROCHIP
196	help
197	  Mailbox implementation for Microchip devices with an
198	  Inter-process communication (IPC) controller.
199
200	  To compile this driver as a module, choose M here. the
201	  module will be called mailbox-mchp-ipc-sbi.
202
203	  If unsure, say N.
204
205config QCOM_APCS_IPC
206	tristate "Qualcomm APCS IPC driver"
207	depends on ARCH_QCOM || COMPILE_TEST
208	help
209	  Say y here to enable support for the APCS IPC mailbox driver,
210	  providing an interface for invoking the inter-process communication
211	  signals from the application processor to other masters.
212
213config TEGRA_HSP_MBOX
214	bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
215	depends on ARCH_TEGRA
216	help
217	  The Tegra HSP driver is used for the interprocessor communication
218	  between different remote processors and host processors on Tegra186
219	  and later SoCs. Say Y here if you want to have this support.
220	  If unsure say N.
221
222config XGENE_SLIMPRO_MBOX
223	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
224	depends on ARCH_XGENE
225	help
226	  An implementation of the APM X-Gene Interprocessor Communication
227	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
228	  It is used to send short messages between ARM64-bit cores and
229	  the SLIMpro Management Engine, primarily for PM. Say Y here if you
230	  want to use the APM X-Gene SLIMpro IPCM support.
231
232config BCM_PDC_MBOX
233	tristate "Broadcom FlexSparx DMA Mailbox"
234	depends on ARCH_BCM_IPROC || COMPILE_TEST
235	help
236	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
237	  which provides access to various offload engines on Broadcom
238	  SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
239
240config BCM_FLEXRM_MBOX
241	tristate "Broadcom FlexRM Mailbox"
242	depends on ARM64
243	depends on ARCH_BCM_IPROC || COMPILE_TEST
244	select GENERIC_MSI_IRQ
245	default m if ARCH_BCM_IPROC
246	help
247	  Mailbox implementation of the Broadcom FlexRM ring manager,
248	  which provides access to various offload engines on Broadcom
249	  SoCs. Say Y here if you want to use the Broadcom FlexRM.
250
251config STM32_IPCC
252	tristate "STM32 IPCC Mailbox"
253	depends on MACH_STM32MP157 || COMPILE_TEST
254	help
255	  Mailbox implementation for STMicroelectonics STM32 family chips
256	  with hardware for Inter-Processor Communication Controller (IPCC)
257	  between processors. Say Y here if you want to have this support.
258
259config MTK_ADSP_MBOX
260	tristate "MediaTek ADSP Mailbox Controller"
261	depends on ARCH_MEDIATEK || COMPILE_TEST
262	help
263          Say yes here to add support for "MediaTek ADSP Mailbox Controller.
264          This mailbox driver is used to send notification or short message
265          between processors with ADSP. It will place the message to share
266	  buffer and will access the ipc control.
267
268config MTK_CMDQ_MBOX
269	tristate "MediaTek CMDQ Mailbox Support"
270	depends on ARCH_MEDIATEK || COMPILE_TEST
271	select MTK_INFRACFG
272	help
273	  Say yes here to add support for the MediaTek Command Queue (CMDQ)
274	  mailbox driver. The CMDQ is used to help read/write registers with
275	  critical time limitation, such as updating display configuration
276	  during the vblank.
277
278config ZYNQMP_IPI_MBOX
279	tristate "Xilinx ZynqMP IPI Mailbox"
280	depends on ARCH_ZYNQMP && OF
281	help
282	  Say yes here to add support for Xilinx IPI mailbox driver.
283	  This mailbox driver is used to send notification or short message
284	  between processors with Xilinx ZynqMP IPI. It will place the
285	  message to the IPI buffer and will access the IPI control
286	  registers to kick the other processor or enquire status.
287
288config SUN6I_MSGBOX
289	tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
290	depends on ARCH_SUNXI || COMPILE_TEST
291	default ARCH_SUNXI
292	help
293	  Mailbox implementation for the hardware message box present in
294	  various Allwinner SoCs. This mailbox is used for communication
295	  between the application CPUs and the power management coprocessor.
296
297config SPRD_MBOX
298	tristate "Spreadtrum Mailbox"
299	depends on ARCH_SPRD || COMPILE_TEST
300	help
301	  Mailbox driver implementation for the Spreadtrum platform. It is used
302	  to send message between application processors and MCU. Say Y here if
303	  you want to build the Spreatrum mailbox controller driver.
304
305config QCOM_CPUCP_MBOX
306	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
307	depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
308	help
309	  Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
310	  controller driver enables communication between AP and CPUCP. Say
311	  Y here if you want to build this driver.
312
313config QCOM_IPCC
314	tristate "Qualcomm Technologies, Inc. IPCC driver"
315	depends on ARCH_QCOM || COMPILE_TEST
316	help
317	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller
318	  (IPCC) driver for MSM devices. The driver provides mailbox support for
319	  sending interrupts to the clients. On the other hand, the driver also
320	  acts as an interrupt controller for receiving interrupts from clients.
321	  Say Y here if you want to build this driver.
322
323config THEAD_TH1520_MBOX
324	tristate "T-head TH1520 Mailbox"
325	depends on ARCH_THEAD || COMPILE_TEST
326	help
327	  Mailbox driver implementation for the Thead TH-1520 platform. Enables
328	  two cores within the SoC to communicate and coordinate by passing
329	  messages. Could be used to communicate between E910 core, on which the
330	  kernel is running, and E902 core used for power management among other
331	  things.
332
333endif
334