1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
13
14 #include "bcm-voter.h"
15 #include "icc-rpmh.h"
16
17 #define SM8750_MASTER_GPU_TCU 0
18 #define SM8750_MASTER_SYS_TCU 1
19 #define SM8750_MASTER_APPSS_PROC 2
20 #define SM8750_MASTER_LLCC 3
21 #define SM8750_MASTER_QDSS_BAM 4
22 #define SM8750_MASTER_QSPI_0 5
23 #define SM8750_MASTER_QUP_1 6
24 #define SM8750_MASTER_QUP_2 7
25 #define SM8750_MASTER_A1NOC_SNOC 8
26 #define SM8750_MASTER_A2NOC_SNOC 9
27 #define SM8750_MASTER_CAMNOC_HF 10
28 #define SM8750_MASTER_CAMNOC_NRT_ICP_SF 11
29 #define SM8750_MASTER_CAMNOC_RT_CDM_SF 12
30 #define SM8750_MASTER_CAMNOC_SF 13
31 #define SM8750_MASTER_GEM_NOC_CNOC 14
32 #define SM8750_MASTER_GEM_NOC_PCIE_SNOC 15
33 #define SM8750_MASTER_GFX3D 16
34 #define SM8750_MASTER_LPASS_GEM_NOC 17
35 #define SM8750_MASTER_LPASS_LPINOC 18
36 #define SM8750_MASTER_LPIAON_NOC 19
37 #define SM8750_MASTER_LPASS_PROC 20
38 #define SM8750_MASTER_MDP 21
39 #define SM8750_MASTER_MSS_PROC 22
40 #define SM8750_MASTER_MNOC_HF_MEM_NOC 23
41 #define SM8750_MASTER_MNOC_SF_MEM_NOC 24
42 #define SM8750_MASTER_CDSP_PROC 25
43 #define SM8750_MASTER_COMPUTE_NOC 26
44 #define SM8750_MASTER_ANOC_PCIE_GEM_NOC 27
45 #define SM8750_MASTER_SNOC_SF_MEM_NOC 28
46 #define SM8750_MASTER_UBWC_P 29
47 #define SM8750_MASTER_CDSP_HCP 30
48 #define SM8750_MASTER_VIDEO_CV_PROC 31
49 #define SM8750_MASTER_VIDEO_EVA 32
50 #define SM8750_MASTER_VIDEO_MVP 33
51 #define SM8750_MASTER_VIDEO_V_PROC 34
52 #define SM8750_MASTER_CNOC_CFG 35
53 #define SM8750_MASTER_CNOC_MNOC_CFG 36
54 #define SM8750_MASTER_PCIE_ANOC_CFG 37
55 #define SM8750_MASTER_QUP_CORE_0 38
56 #define SM8750_MASTER_QUP_CORE_1 39
57 #define SM8750_MASTER_QUP_CORE_2 40
58 #define SM8750_MASTER_CRYPTO 41
59 #define SM8750_MASTER_IPA 42
60 #define SM8750_MASTER_QUP_3 43
61 #define SM8750_MASTER_SOCCP_AGGR_NOC 44
62 #define SM8750_MASTER_SP 45
63 #define SM8750_MASTER_GIC 46
64 #define SM8750_MASTER_PCIE_0 47
65 #define SM8750_MASTER_QDSS_ETR 48
66 #define SM8750_MASTER_QDSS_ETR_1 49
67 #define SM8750_MASTER_SDCC_2 50
68 #define SM8750_MASTER_SDCC_4 51
69 #define SM8750_MASTER_UFS_MEM 52
70 #define SM8750_MASTER_USB3_0 53
71 #define SM8750_SLAVE_UBWC_P 54
72 #define SM8750_SLAVE_EBI1 55
73 #define SM8750_SLAVE_AHB2PHY_SOUTH 56
74 #define SM8750_SLAVE_AHB2PHY_NORTH 57
75 #define SM8750_SLAVE_AOSS 58
76 #define SM8750_SLAVE_CAMERA_CFG 59
77 #define SM8750_SLAVE_CLK_CTL 60
78 #define SM8750_SLAVE_CRYPTO_0_CFG 61
79 #define SM8750_SLAVE_DISPLAY_CFG 62
80 #define SM8750_SLAVE_EVA_CFG 63
81 #define SM8750_SLAVE_GFX3D_CFG 64
82 #define SM8750_SLAVE_I2C 65
83 #define SM8750_SLAVE_I3C_IBI0_CFG 66
84 #define SM8750_SLAVE_I3C_IBI1_CFG 67
85 #define SM8750_SLAVE_IMEM_CFG 68
86 #define SM8750_SLAVE_IPA_CFG 69
87 #define SM8750_SLAVE_IPC_ROUTER_CFG 70
88 #define SM8750_SLAVE_CNOC_MSS 71
89 #define SM8750_SLAVE_PCIE_CFG 72
90 #define SM8750_SLAVE_PRNG 73
91 #define SM8750_SLAVE_QDSS_CFG 74
92 #define SM8750_SLAVE_QSPI_0 75
93 #define SM8750_SLAVE_QUP_3 76
94 #define SM8750_SLAVE_QUP_1 77
95 #define SM8750_SLAVE_QUP_2 78
96 #define SM8750_SLAVE_SDCC_2 79
97 #define SM8750_SLAVE_SDCC_4 80
98 #define SM8750_SLAVE_SOCCP 81
99 #define SM8750_SLAVE_SPSS_CFG 82
100 #define SM8750_SLAVE_TCSR 83
101 #define SM8750_SLAVE_TLMM 84
102 #define SM8750_SLAVE_TME_CFG 85
103 #define SM8750_SLAVE_UFS_MEM_CFG 86
104 #define SM8750_SLAVE_USB3_0 87
105 #define SM8750_SLAVE_VENUS_CFG 88
106 #define SM8750_SLAVE_VSENSE_CTRL_CFG 89
107 #define SM8750_SLAVE_A1NOC_SNOC 90
108 #define SM8750_SLAVE_A2NOC_SNOC 91
109 #define SM8750_SLAVE_APPSS 92
110 #define SM8750_SLAVE_GEM_NOC_CNOC 93
111 #define SM8750_SLAVE_SNOC_GEM_NOC_SF 94
112 #define SM8750_SLAVE_LLCC 95
113 #define SM8750_SLAVE_LPASS_GEM_NOC 96
114 #define SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC 97
115 #define SM8750_SLAVE_LPICX_NOC_LPIAON_NOC 98
116 #define SM8750_SLAVE_MNOC_HF_MEM_NOC 99
117 #define SM8750_SLAVE_MNOC_SF_MEM_NOC 100
118 #define SM8750_SLAVE_CDSP_MEM_NOC 101
119 #define SM8750_SLAVE_MEM_NOC_PCIE_SNOC 102
120 #define SM8750_SLAVE_ANOC_PCIE_GEM_NOC 103
121 #define SM8750_SLAVE_CNOC_CFG 104
122 #define SM8750_SLAVE_DDRSS_CFG 105
123 #define SM8750_SLAVE_CNOC_MNOC_CFG 106
124 #define SM8750_SLAVE_PCIE_ANOC_CFG 107
125 #define SM8750_SLAVE_QUP_CORE_0 108
126 #define SM8750_SLAVE_QUP_CORE_1 109
127 #define SM8750_SLAVE_QUP_CORE_2 110
128 #define SM8750_SLAVE_BOOT_IMEM 111
129 #define SM8750_SLAVE_IMEM 112
130 #define SM8750_SLAVE_BOOT_IMEM_2 113
131 #define SM8750_SLAVE_SERVICE_CNOC 114
132 #define SM8750_SLAVE_SERVICE_MNOC 115
133 #define SM8750_SLAVE_SERVICE_PCIE_ANOC 116
134 #define SM8750_SLAVE_PCIE_0 117
135 #define SM8750_SLAVE_QDSS_STM 118
136 #define SM8750_SLAVE_TCU 119
137
138 static struct qcom_icc_node qhm_qspi = {
139 .name = "qhm_qspi",
140 .id = SM8750_MASTER_QSPI_0,
141 .channels = 1,
142 .buswidth = 4,
143 .num_links = 1,
144 .links = { SM8750_SLAVE_A1NOC_SNOC },
145 };
146
147 static struct qcom_icc_node qhm_qup1 = {
148 .name = "qhm_qup1",
149 .id = SM8750_MASTER_QUP_1,
150 .channels = 1,
151 .buswidth = 4,
152 .num_links = 1,
153 .links = { SM8750_SLAVE_A1NOC_SNOC },
154 };
155
156 static struct qcom_icc_node qxm_qup02 = {
157 .name = "qxm_qup02",
158 .id = SM8750_MASTER_QUP_3,
159 .channels = 1,
160 .buswidth = 8,
161 .num_links = 1,
162 .links = { SM8750_SLAVE_A1NOC_SNOC },
163 };
164
165 static struct qcom_icc_node xm_sdc4 = {
166 .name = "xm_sdc4",
167 .id = SM8750_MASTER_SDCC_4,
168 .channels = 1,
169 .buswidth = 8,
170 .num_links = 1,
171 .links = { SM8750_SLAVE_A1NOC_SNOC },
172 };
173
174 static struct qcom_icc_node xm_ufs_mem = {
175 .name = "xm_ufs_mem",
176 .id = SM8750_MASTER_UFS_MEM,
177 .channels = 1,
178 .buswidth = 16,
179 .num_links = 1,
180 .links = { SM8750_SLAVE_A1NOC_SNOC },
181 };
182
183 static struct qcom_icc_node xm_usb3_0 = {
184 .name = "xm_usb3_0",
185 .id = SM8750_MASTER_USB3_0,
186 .channels = 1,
187 .buswidth = 8,
188 .num_links = 1,
189 .links = { SM8750_SLAVE_A1NOC_SNOC },
190 };
191
192 static struct qcom_icc_node qhm_qdss_bam = {
193 .name = "qhm_qdss_bam",
194 .id = SM8750_MASTER_QDSS_BAM,
195 .channels = 1,
196 .buswidth = 4,
197 .num_links = 1,
198 .links = { SM8750_SLAVE_A2NOC_SNOC },
199 };
200
201 static struct qcom_icc_node qhm_qup2 = {
202 .name = "qhm_qup2",
203 .id = SM8750_MASTER_QUP_2,
204 .channels = 1,
205 .buswidth = 4,
206 .num_links = 1,
207 .links = { SM8750_SLAVE_A2NOC_SNOC },
208 };
209
210 static struct qcom_icc_node qxm_crypto = {
211 .name = "qxm_crypto",
212 .id = SM8750_MASTER_CRYPTO,
213 .channels = 1,
214 .buswidth = 8,
215 .num_links = 1,
216 .links = { SM8750_SLAVE_A2NOC_SNOC },
217 };
218
219 static struct qcom_icc_node qxm_ipa = {
220 .name = "qxm_ipa",
221 .id = SM8750_MASTER_IPA,
222 .channels = 1,
223 .buswidth = 8,
224 .num_links = 1,
225 .links = { SM8750_SLAVE_A2NOC_SNOC },
226 };
227
228 static struct qcom_icc_node qxm_soccp = {
229 .name = "qxm_soccp",
230 .id = SM8750_MASTER_SOCCP_AGGR_NOC,
231 .channels = 1,
232 .buswidth = 8,
233 .num_links = 1,
234 .links = { SM8750_SLAVE_A2NOC_SNOC },
235 };
236
237 static struct qcom_icc_node qxm_sp = {
238 .name = "qxm_sp",
239 .id = SM8750_MASTER_SP,
240 .channels = 1,
241 .buswidth = 8,
242 .num_links = 1,
243 .links = { SM8750_SLAVE_A2NOC_SNOC },
244 };
245
246 static struct qcom_icc_node xm_qdss_etr_0 = {
247 .name = "xm_qdss_etr_0",
248 .id = SM8750_MASTER_QDSS_ETR,
249 .channels = 1,
250 .buswidth = 8,
251 .num_links = 1,
252 .links = { SM8750_SLAVE_A2NOC_SNOC },
253 };
254
255 static struct qcom_icc_node xm_qdss_etr_1 = {
256 .name = "xm_qdss_etr_1",
257 .id = SM8750_MASTER_QDSS_ETR_1,
258 .channels = 1,
259 .buswidth = 8,
260 .num_links = 1,
261 .links = { SM8750_SLAVE_A2NOC_SNOC },
262 };
263
264 static struct qcom_icc_node xm_sdc2 = {
265 .name = "xm_sdc2",
266 .id = SM8750_MASTER_SDCC_2,
267 .channels = 1,
268 .buswidth = 8,
269 .num_links = 1,
270 .links = { SM8750_SLAVE_A2NOC_SNOC },
271 };
272
273 static struct qcom_icc_node qup0_core_master = {
274 .name = "qup0_core_master",
275 .id = SM8750_MASTER_QUP_CORE_0,
276 .channels = 1,
277 .buswidth = 4,
278 .num_links = 1,
279 .links = { SM8750_SLAVE_QUP_CORE_0 },
280 };
281
282 static struct qcom_icc_node qup1_core_master = {
283 .name = "qup1_core_master",
284 .id = SM8750_MASTER_QUP_CORE_1,
285 .channels = 1,
286 .buswidth = 4,
287 .num_links = 1,
288 .links = { SM8750_SLAVE_QUP_CORE_1 },
289 };
290
291 static struct qcom_icc_node qup2_core_master = {
292 .name = "qup2_core_master",
293 .id = SM8750_MASTER_QUP_CORE_2,
294 .channels = 1,
295 .buswidth = 4,
296 .num_links = 1,
297 .links = { SM8750_SLAVE_QUP_CORE_2 },
298 };
299
300 static struct qcom_icc_node qsm_cfg = {
301 .name = "qsm_cfg",
302 .id = SM8750_MASTER_CNOC_CFG,
303 .channels = 1,
304 .buswidth = 4,
305 .num_links = 33,
306 .links = { SM8750_SLAVE_AHB2PHY_SOUTH, SM8750_SLAVE_AHB2PHY_NORTH,
307 SM8750_SLAVE_CAMERA_CFG, SM8750_SLAVE_CLK_CTL,
308 SM8750_SLAVE_CRYPTO_0_CFG, SM8750_SLAVE_DISPLAY_CFG,
309 SM8750_SLAVE_EVA_CFG, SM8750_SLAVE_GFX3D_CFG,
310 SM8750_SLAVE_I2C, SM8750_SLAVE_I3C_IBI0_CFG,
311 SM8750_SLAVE_I3C_IBI1_CFG, SM8750_SLAVE_IMEM_CFG,
312 SM8750_SLAVE_CNOC_MSS, SM8750_SLAVE_PCIE_CFG,
313 SM8750_SLAVE_PRNG, SM8750_SLAVE_QDSS_CFG,
314 SM8750_SLAVE_QSPI_0, SM8750_SLAVE_QUP_3,
315 SM8750_SLAVE_QUP_1, SM8750_SLAVE_QUP_2,
316 SM8750_SLAVE_SDCC_2, SM8750_SLAVE_SDCC_4,
317 SM8750_SLAVE_SPSS_CFG, SM8750_SLAVE_TCSR,
318 SM8750_SLAVE_TLMM, SM8750_SLAVE_UFS_MEM_CFG,
319 SM8750_SLAVE_USB3_0, SM8750_SLAVE_VENUS_CFG,
320 SM8750_SLAVE_VSENSE_CTRL_CFG, SM8750_SLAVE_CNOC_MNOC_CFG,
321 SM8750_SLAVE_PCIE_ANOC_CFG, SM8750_SLAVE_QDSS_STM,
322 SM8750_SLAVE_TCU },
323 };
324
325 static struct qcom_icc_node qnm_gemnoc_cnoc = {
326 .name = "qnm_gemnoc_cnoc",
327 .id = SM8750_MASTER_GEM_NOC_CNOC,
328 .channels = 1,
329 .buswidth = 16,
330 .num_links = 12,
331 .links = { SM8750_SLAVE_AOSS, SM8750_SLAVE_IPA_CFG,
332 SM8750_SLAVE_IPC_ROUTER_CFG, SM8750_SLAVE_SOCCP,
333 SM8750_SLAVE_TME_CFG, SM8750_SLAVE_APPSS,
334 SM8750_SLAVE_CNOC_CFG, SM8750_SLAVE_DDRSS_CFG,
335 SM8750_SLAVE_BOOT_IMEM, SM8750_SLAVE_IMEM,
336 SM8750_SLAVE_BOOT_IMEM_2, SM8750_SLAVE_SERVICE_CNOC },
337 };
338
339 static struct qcom_icc_node qnm_gemnoc_pcie = {
340 .name = "qnm_gemnoc_pcie",
341 .id = SM8750_MASTER_GEM_NOC_PCIE_SNOC,
342 .channels = 1,
343 .buswidth = 8,
344 .num_links = 1,
345 .links = { SM8750_SLAVE_PCIE_0 },
346 };
347
348 static struct qcom_icc_node alm_gpu_tcu = {
349 .name = "alm_gpu_tcu",
350 .id = SM8750_MASTER_GPU_TCU,
351 .channels = 1,
352 .buswidth = 8,
353 .num_links = 2,
354 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
355 };
356
357 static struct qcom_icc_node alm_sys_tcu = {
358 .name = "alm_sys_tcu",
359 .id = SM8750_MASTER_SYS_TCU,
360 .channels = 1,
361 .buswidth = 8,
362 .num_links = 2,
363 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
364 };
365
366 static struct qcom_icc_node chm_apps = {
367 .name = "chm_apps",
368 .id = SM8750_MASTER_APPSS_PROC,
369 .channels = 4,
370 .buswidth = 32,
371 .num_links = 4,
372 .links = { SM8750_SLAVE_UBWC_P, SM8750_SLAVE_GEM_NOC_CNOC,
373 SM8750_SLAVE_LLCC, SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
374 };
375
376 static struct qcom_icc_node qnm_gpu = {
377 .name = "qnm_gpu",
378 .id = SM8750_MASTER_GFX3D,
379 .channels = 2,
380 .buswidth = 32,
381 .num_links = 2,
382 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
383 };
384
385 static struct qcom_icc_node qnm_lpass_gemnoc = {
386 .name = "qnm_lpass_gemnoc",
387 .id = SM8750_MASTER_LPASS_GEM_NOC,
388 .channels = 1,
389 .buswidth = 16,
390 .num_links = 3,
391 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
392 SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
393 };
394
395 static struct qcom_icc_node qnm_mdsp = {
396 .name = "qnm_mdsp",
397 .id = SM8750_MASTER_MSS_PROC,
398 .channels = 1,
399 .buswidth = 16,
400 .num_links = 3,
401 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
402 SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
403 };
404
405 static struct qcom_icc_node qnm_mnoc_hf = {
406 .name = "qnm_mnoc_hf",
407 .id = SM8750_MASTER_MNOC_HF_MEM_NOC,
408 .channels = 2,
409 .buswidth = 32,
410 .num_links = 2,
411 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
412 };
413
414 static struct qcom_icc_node qnm_mnoc_sf = {
415 .name = "qnm_mnoc_sf",
416 .id = SM8750_MASTER_MNOC_SF_MEM_NOC,
417 .channels = 2,
418 .buswidth = 32,
419 .num_links = 2,
420 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
421 };
422
423 static struct qcom_icc_node qnm_nsp_gemnoc = {
424 .name = "qnm_nsp_gemnoc",
425 .id = SM8750_MASTER_COMPUTE_NOC,
426 .channels = 2,
427 .buswidth = 32,
428 .num_links = 3,
429 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
430 SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
431 };
432
433 static struct qcom_icc_node qnm_pcie = {
434 .name = "qnm_pcie",
435 .id = SM8750_MASTER_ANOC_PCIE_GEM_NOC,
436 .channels = 1,
437 .buswidth = 8,
438 .num_links = 2,
439 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC },
440 };
441
442 static struct qcom_icc_node qnm_snoc_sf = {
443 .name = "qnm_snoc_sf",
444 .id = SM8750_MASTER_SNOC_SF_MEM_NOC,
445 .channels = 1,
446 .buswidth = 16,
447 .num_links = 3,
448 .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC,
449 SM8750_SLAVE_MEM_NOC_PCIE_SNOC },
450 };
451
452 static struct qcom_icc_node qnm_ubwc_p = {
453 .name = "qnm_ubwc_p",
454 .id = SM8750_MASTER_UBWC_P,
455 .channels = 1,
456 .buswidth = 32,
457 .num_links = 1,
458 .links = { SM8750_SLAVE_LLCC },
459 };
460
461 static struct qcom_icc_node xm_gic = {
462 .name = "xm_gic",
463 .id = SM8750_MASTER_GIC,
464 .channels = 1,
465 .buswidth = 8,
466 .num_links = 1,
467 .links = { SM8750_SLAVE_LLCC },
468 };
469
470 static struct qcom_icc_node qnm_lpiaon_noc = {
471 .name = "qnm_lpiaon_noc",
472 .id = SM8750_MASTER_LPIAON_NOC,
473 .channels = 1,
474 .buswidth = 16,
475 .num_links = 1,
476 .links = { SM8750_SLAVE_LPASS_GEM_NOC },
477 };
478
479 static struct qcom_icc_node qnm_lpass_lpinoc = {
480 .name = "qnm_lpass_lpinoc",
481 .id = SM8750_MASTER_LPASS_LPINOC,
482 .channels = 1,
483 .buswidth = 16,
484 .num_links = 1,
485 .links = { SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
486 };
487
488 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
489 .name = "qnm_lpinoc_dsp_qns4m",
490 .id = SM8750_MASTER_LPASS_PROC,
491 .channels = 1,
492 .buswidth = 16,
493 .num_links = 1,
494 .links = { SM8750_SLAVE_LPICX_NOC_LPIAON_NOC },
495 };
496
497 static struct qcom_icc_node llcc_mc = {
498 .name = "llcc_mc",
499 .id = SM8750_MASTER_LLCC,
500 .channels = 4,
501 .buswidth = 4,
502 .num_links = 1,
503 .links = { SM8750_SLAVE_EBI1 },
504 };
505
506 static struct qcom_icc_node qnm_camnoc_hf = {
507 .name = "qnm_camnoc_hf",
508 .id = SM8750_MASTER_CAMNOC_HF,
509 .channels = 2,
510 .buswidth = 32,
511 .num_links = 1,
512 .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC },
513 };
514
515 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
516 .name = "qnm_camnoc_nrt_icp_sf",
517 .id = SM8750_MASTER_CAMNOC_NRT_ICP_SF,
518 .channels = 1,
519 .buswidth = 8,
520 .num_links = 1,
521 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
522 };
523
524 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
525 .name = "qnm_camnoc_rt_cdm_sf",
526 .id = SM8750_MASTER_CAMNOC_RT_CDM_SF,
527 .channels = 1,
528 .buswidth = 8,
529 .num_links = 1,
530 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
531 };
532
533 static struct qcom_icc_node qnm_camnoc_sf = {
534 .name = "qnm_camnoc_sf",
535 .id = SM8750_MASTER_CAMNOC_SF,
536 .channels = 2,
537 .buswidth = 32,
538 .num_links = 1,
539 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
540 };
541
542 static struct qcom_icc_node qnm_mdp = {
543 .name = "qnm_mdp",
544 .id = SM8750_MASTER_MDP,
545 .channels = 2,
546 .buswidth = 32,
547 .num_links = 1,
548 .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC },
549 };
550
551 static struct qcom_icc_node qnm_vapss_hcp = {
552 .name = "qnm_vapss_hcp",
553 .id = SM8750_MASTER_CDSP_HCP,
554 .channels = 1,
555 .buswidth = 32,
556 .num_links = 1,
557 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
558 };
559
560 static struct qcom_icc_node qnm_video_cv_cpu = {
561 .name = "qnm_video_cv_cpu",
562 .id = SM8750_MASTER_VIDEO_CV_PROC,
563 .channels = 1,
564 .buswidth = 8,
565 .num_links = 1,
566 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
567 };
568
569 static struct qcom_icc_node qnm_video_eva = {
570 .name = "qnm_video_eva",
571 .id = SM8750_MASTER_VIDEO_EVA,
572 .channels = 2,
573 .buswidth = 32,
574 .num_links = 1,
575 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
576 };
577
578 static struct qcom_icc_node qnm_video_mvp = {
579 .name = "qnm_video_mvp",
580 .id = SM8750_MASTER_VIDEO_MVP,
581 .channels = 2,
582 .buswidth = 32,
583 .num_links = 1,
584 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
585 };
586
587 static struct qcom_icc_node qnm_video_v_cpu = {
588 .name = "qnm_video_v_cpu",
589 .id = SM8750_MASTER_VIDEO_V_PROC,
590 .channels = 1,
591 .buswidth = 8,
592 .num_links = 1,
593 .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC },
594 };
595
596 static struct qcom_icc_node qsm_mnoc_cfg = {
597 .name = "qsm_mnoc_cfg",
598 .id = SM8750_MASTER_CNOC_MNOC_CFG,
599 .channels = 1,
600 .buswidth = 4,
601 .num_links = 1,
602 .links = { SM8750_SLAVE_SERVICE_MNOC },
603 };
604
605 static struct qcom_icc_node qnm_nsp = {
606 .name = "qnm_nsp",
607 .id = SM8750_MASTER_CDSP_PROC,
608 .channels = 2,
609 .buswidth = 32,
610 .num_links = 1,
611 .links = { SM8750_SLAVE_CDSP_MEM_NOC },
612 };
613
614 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
615 .name = "qsm_pcie_anoc_cfg",
616 .id = SM8750_MASTER_PCIE_ANOC_CFG,
617 .channels = 1,
618 .buswidth = 4,
619 .num_links = 1,
620 .links = { SM8750_SLAVE_SERVICE_PCIE_ANOC },
621 };
622
623 static struct qcom_icc_node xm_pcie3 = {
624 .name = "xm_pcie3",
625 .id = SM8750_MASTER_PCIE_0,
626 .channels = 1,
627 .buswidth = 8,
628 .num_links = 1,
629 .links = { SM8750_SLAVE_ANOC_PCIE_GEM_NOC },
630 };
631
632 static struct qcom_icc_node qnm_aggre1_noc = {
633 .name = "qnm_aggre1_noc",
634 .id = SM8750_MASTER_A1NOC_SNOC,
635 .channels = 1,
636 .buswidth = 16,
637 .num_links = 1,
638 .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF },
639 };
640
641 static struct qcom_icc_node qnm_aggre2_noc = {
642 .name = "qnm_aggre2_noc",
643 .id = SM8750_MASTER_A2NOC_SNOC,
644 .channels = 1,
645 .buswidth = 16,
646 .num_links = 1,
647 .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF },
648 };
649
650 static struct qcom_icc_node qns_a1noc_snoc = {
651 .name = "qns_a1noc_snoc",
652 .id = SM8750_SLAVE_A1NOC_SNOC,
653 .channels = 1,
654 .buswidth = 16,
655 .num_links = 1,
656 .links = { SM8750_MASTER_A1NOC_SNOC },
657 };
658
659 static struct qcom_icc_node qns_a2noc_snoc = {
660 .name = "qns_a2noc_snoc",
661 .id = SM8750_SLAVE_A2NOC_SNOC,
662 .channels = 1,
663 .buswidth = 16,
664 .num_links = 1,
665 .links = { SM8750_MASTER_A2NOC_SNOC },
666 };
667
668 static struct qcom_icc_node qup0_core_slave = {
669 .name = "qup0_core_slave",
670 .id = SM8750_SLAVE_QUP_CORE_0,
671 .channels = 1,
672 .buswidth = 4,
673 .num_links = 0,
674 };
675
676 static struct qcom_icc_node qup1_core_slave = {
677 .name = "qup1_core_slave",
678 .id = SM8750_SLAVE_QUP_CORE_1,
679 .channels = 1,
680 .buswidth = 4,
681 .num_links = 0,
682 };
683
684 static struct qcom_icc_node qup2_core_slave = {
685 .name = "qup2_core_slave",
686 .id = SM8750_SLAVE_QUP_CORE_2,
687 .channels = 1,
688 .buswidth = 4,
689 .num_links = 0,
690 };
691
692 static struct qcom_icc_node qhs_ahb2phy0 = {
693 .name = "qhs_ahb2phy0",
694 .id = SM8750_SLAVE_AHB2PHY_SOUTH,
695 .channels = 1,
696 .buswidth = 4,
697 .num_links = 0,
698 };
699
700 static struct qcom_icc_node qhs_ahb2phy1 = {
701 .name = "qhs_ahb2phy1",
702 .id = SM8750_SLAVE_AHB2PHY_NORTH,
703 .channels = 1,
704 .buswidth = 4,
705 .num_links = 0,
706 };
707
708 static struct qcom_icc_node qhs_camera_cfg = {
709 .name = "qhs_camera_cfg",
710 .id = SM8750_SLAVE_CAMERA_CFG,
711 .channels = 1,
712 .buswidth = 4,
713 .num_links = 0,
714 };
715
716 static struct qcom_icc_node qhs_clk_ctl = {
717 .name = "qhs_clk_ctl",
718 .id = SM8750_SLAVE_CLK_CTL,
719 .channels = 1,
720 .buswidth = 4,
721 .num_links = 0,
722 };
723
724 static struct qcom_icc_node qhs_crypto0_cfg = {
725 .name = "qhs_crypto0_cfg",
726 .id = SM8750_SLAVE_CRYPTO_0_CFG,
727 .channels = 1,
728 .buswidth = 4,
729 .num_links = 0,
730 };
731
732 static struct qcom_icc_node qhs_display_cfg = {
733 .name = "qhs_display_cfg",
734 .id = SM8750_SLAVE_DISPLAY_CFG,
735 .channels = 1,
736 .buswidth = 4,
737 .num_links = 0,
738 };
739
740 static struct qcom_icc_node qhs_eva_cfg = {
741 .name = "qhs_eva_cfg",
742 .id = SM8750_SLAVE_EVA_CFG,
743 .channels = 1,
744 .buswidth = 4,
745 .num_links = 0,
746 };
747
748 static struct qcom_icc_node qhs_gpuss_cfg = {
749 .name = "qhs_gpuss_cfg",
750 .id = SM8750_SLAVE_GFX3D_CFG,
751 .channels = 1,
752 .buswidth = 8,
753 .num_links = 0,
754 };
755
756 static struct qcom_icc_node qhs_i2c = {
757 .name = "qhs_i2c",
758 .id = SM8750_SLAVE_I2C,
759 .channels = 1,
760 .buswidth = 4,
761 .num_links = 0,
762 };
763
764 static struct qcom_icc_node qhs_i3c_ibi0_cfg = {
765 .name = "qhs_i3c_ibi0_cfg",
766 .id = SM8750_SLAVE_I3C_IBI0_CFG,
767 .channels = 1,
768 .buswidth = 4,
769 .num_links = 0,
770 };
771
772 static struct qcom_icc_node qhs_i3c_ibi1_cfg = {
773 .name = "qhs_i3c_ibi1_cfg",
774 .id = SM8750_SLAVE_I3C_IBI1_CFG,
775 .channels = 1,
776 .buswidth = 4,
777 .num_links = 0,
778 };
779
780 static struct qcom_icc_node qhs_imem_cfg = {
781 .name = "qhs_imem_cfg",
782 .id = SM8750_SLAVE_IMEM_CFG,
783 .channels = 1,
784 .buswidth = 4,
785 .num_links = 0,
786 };
787
788 static struct qcom_icc_node qhs_mss_cfg = {
789 .name = "qhs_mss_cfg",
790 .id = SM8750_SLAVE_CNOC_MSS,
791 .channels = 1,
792 .buswidth = 4,
793 .num_links = 0,
794 };
795
796 static struct qcom_icc_node qhs_pcie_cfg = {
797 .name = "qhs_pcie_cfg",
798 .id = SM8750_SLAVE_PCIE_CFG,
799 .channels = 1,
800 .buswidth = 4,
801 .num_links = 0,
802 };
803
804 static struct qcom_icc_node qhs_prng = {
805 .name = "qhs_prng",
806 .id = SM8750_SLAVE_PRNG,
807 .channels = 1,
808 .buswidth = 4,
809 .num_links = 0,
810 };
811
812 static struct qcom_icc_node qhs_qdss_cfg = {
813 .name = "qhs_qdss_cfg",
814 .id = SM8750_SLAVE_QDSS_CFG,
815 .channels = 1,
816 .buswidth = 4,
817 .num_links = 0,
818 };
819
820 static struct qcom_icc_node qhs_qspi = {
821 .name = "qhs_qspi",
822 .id = SM8750_SLAVE_QSPI_0,
823 .channels = 1,
824 .buswidth = 4,
825 .num_links = 0,
826 };
827
828 static struct qcom_icc_node qhs_qup02 = {
829 .name = "qhs_qup02",
830 .id = SM8750_SLAVE_QUP_3,
831 .channels = 1,
832 .buswidth = 4,
833 .num_links = 0,
834 };
835
836 static struct qcom_icc_node qhs_qup1 = {
837 .name = "qhs_qup1",
838 .id = SM8750_SLAVE_QUP_1,
839 .channels = 1,
840 .buswidth = 4,
841 .num_links = 0,
842 };
843
844 static struct qcom_icc_node qhs_qup2 = {
845 .name = "qhs_qup2",
846 .id = SM8750_SLAVE_QUP_2,
847 .channels = 1,
848 .buswidth = 4,
849 .num_links = 0,
850 };
851
852 static struct qcom_icc_node qhs_sdc2 = {
853 .name = "qhs_sdc2",
854 .id = SM8750_SLAVE_SDCC_2,
855 .channels = 1,
856 .buswidth = 4,
857 .num_links = 0,
858 };
859
860 static struct qcom_icc_node qhs_sdc4 = {
861 .name = "qhs_sdc4",
862 .id = SM8750_SLAVE_SDCC_4,
863 .channels = 1,
864 .buswidth = 4,
865 .num_links = 0,
866 };
867
868 static struct qcom_icc_node qhs_spss_cfg = {
869 .name = "qhs_spss_cfg",
870 .id = SM8750_SLAVE_SPSS_CFG,
871 .channels = 1,
872 .buswidth = 4,
873 .num_links = 0,
874 };
875
876 static struct qcom_icc_node qhs_tcsr = {
877 .name = "qhs_tcsr",
878 .id = SM8750_SLAVE_TCSR,
879 .channels = 1,
880 .buswidth = 4,
881 .num_links = 0,
882 };
883
884 static struct qcom_icc_node qhs_tlmm = {
885 .name = "qhs_tlmm",
886 .id = SM8750_SLAVE_TLMM,
887 .channels = 1,
888 .buswidth = 4,
889 .num_links = 0,
890 };
891
892 static struct qcom_icc_node qhs_ufs_mem_cfg = {
893 .name = "qhs_ufs_mem_cfg",
894 .id = SM8750_SLAVE_UFS_MEM_CFG,
895 .channels = 1,
896 .buswidth = 4,
897 .num_links = 0,
898 };
899
900 static struct qcom_icc_node qhs_usb3_0 = {
901 .name = "qhs_usb3_0",
902 .id = SM8750_SLAVE_USB3_0,
903 .channels = 1,
904 .buswidth = 4,
905 .num_links = 0,
906 };
907
908 static struct qcom_icc_node qhs_venus_cfg = {
909 .name = "qhs_venus_cfg",
910 .id = SM8750_SLAVE_VENUS_CFG,
911 .channels = 1,
912 .buswidth = 4,
913 .num_links = 0,
914 };
915
916 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
917 .name = "qhs_vsense_ctrl_cfg",
918 .id = SM8750_SLAVE_VSENSE_CTRL_CFG,
919 .channels = 1,
920 .buswidth = 4,
921 .num_links = 0,
922 };
923
924 static struct qcom_icc_node qss_mnoc_cfg = {
925 .name = "qss_mnoc_cfg",
926 .id = SM8750_SLAVE_CNOC_MNOC_CFG,
927 .channels = 1,
928 .buswidth = 4,
929 .num_links = 1,
930 .links = { SM8750_MASTER_CNOC_MNOC_CFG },
931 };
932
933 static struct qcom_icc_node qss_pcie_anoc_cfg = {
934 .name = "qss_pcie_anoc_cfg",
935 .id = SM8750_SLAVE_PCIE_ANOC_CFG,
936 .channels = 1,
937 .buswidth = 4,
938 .num_links = 1,
939 .links = { SM8750_MASTER_PCIE_ANOC_CFG },
940 };
941
942 static struct qcom_icc_node xs_qdss_stm = {
943 .name = "xs_qdss_stm",
944 .id = SM8750_SLAVE_QDSS_STM,
945 .channels = 1,
946 .buswidth = 4,
947 .num_links = 0,
948 };
949
950 static struct qcom_icc_node xs_sys_tcu_cfg = {
951 .name = "xs_sys_tcu_cfg",
952 .id = SM8750_SLAVE_TCU,
953 .channels = 1,
954 .buswidth = 8,
955 .num_links = 0,
956 };
957
958 static struct qcom_icc_node qhs_aoss = {
959 .name = "qhs_aoss",
960 .id = SM8750_SLAVE_AOSS,
961 .channels = 1,
962 .buswidth = 4,
963 .num_links = 0,
964 };
965
966 static struct qcom_icc_node qhs_ipa = {
967 .name = "qhs_ipa",
968 .id = SM8750_SLAVE_IPA_CFG,
969 .channels = 1,
970 .buswidth = 4,
971 .num_links = 0,
972 };
973
974 static struct qcom_icc_node qhs_ipc_router = {
975 .name = "qhs_ipc_router",
976 .id = SM8750_SLAVE_IPC_ROUTER_CFG,
977 .channels = 1,
978 .buswidth = 4,
979 .num_links = 0,
980 };
981
982 static struct qcom_icc_node qhs_soccp = {
983 .name = "qhs_soccp",
984 .id = SM8750_SLAVE_SOCCP,
985 .channels = 1,
986 .buswidth = 4,
987 .num_links = 0,
988 };
989
990 static struct qcom_icc_node qhs_tme_cfg = {
991 .name = "qhs_tme_cfg",
992 .id = SM8750_SLAVE_TME_CFG,
993 .channels = 1,
994 .buswidth = 4,
995 .num_links = 0,
996 };
997
998 static struct qcom_icc_node qns_apss = {
999 .name = "qns_apss",
1000 .id = SM8750_SLAVE_APPSS,
1001 .channels = 1,
1002 .buswidth = 8,
1003 .num_links = 0,
1004 };
1005
1006 static struct qcom_icc_node qss_cfg = {
1007 .name = "qss_cfg",
1008 .id = SM8750_SLAVE_CNOC_CFG,
1009 .channels = 1,
1010 .buswidth = 4,
1011 .num_links = 1,
1012 .links = { SM8750_MASTER_CNOC_CFG },
1013 };
1014
1015 static struct qcom_icc_node qss_ddrss_cfg = {
1016 .name = "qss_ddrss_cfg",
1017 .id = SM8750_SLAVE_DDRSS_CFG,
1018 .channels = 1,
1019 .buswidth = 4,
1020 .num_links = 0,
1021 };
1022
1023 static struct qcom_icc_node qxs_boot_imem = {
1024 .name = "qxs_boot_imem",
1025 .id = SM8750_SLAVE_BOOT_IMEM,
1026 .channels = 1,
1027 .buswidth = 16,
1028 .num_links = 0,
1029 };
1030
1031 static struct qcom_icc_node qxs_imem = {
1032 .name = "qxs_imem",
1033 .id = SM8750_SLAVE_IMEM,
1034 .channels = 1,
1035 .buswidth = 8,
1036 .num_links = 0,
1037 };
1038
1039 static struct qcom_icc_node qxs_modem_boot_imem = {
1040 .name = "qxs_modem_boot_imem",
1041 .id = SM8750_SLAVE_BOOT_IMEM_2,
1042 .channels = 1,
1043 .buswidth = 8,
1044 .num_links = 0,
1045 };
1046
1047 static struct qcom_icc_node srvc_cnoc_main = {
1048 .name = "srvc_cnoc_main",
1049 .id = SM8750_SLAVE_SERVICE_CNOC,
1050 .channels = 1,
1051 .buswidth = 4,
1052 .num_links = 0,
1053 };
1054
1055 static struct qcom_icc_node xs_pcie = {
1056 .name = "xs_pcie",
1057 .id = SM8750_SLAVE_PCIE_0,
1058 .channels = 1,
1059 .buswidth = 8,
1060 .num_links = 0,
1061 };
1062
1063 static struct qcom_icc_node chs_ubwc_p = {
1064 .name = "chs_ubwc_p",
1065 .id = SM8750_SLAVE_UBWC_P,
1066 .channels = 1,
1067 .buswidth = 32,
1068 .num_links = 0,
1069 };
1070
1071 static struct qcom_icc_node qns_gem_noc_cnoc = {
1072 .name = "qns_gem_noc_cnoc",
1073 .id = SM8750_SLAVE_GEM_NOC_CNOC,
1074 .channels = 1,
1075 .buswidth = 16,
1076 .num_links = 1,
1077 .links = { SM8750_MASTER_GEM_NOC_CNOC },
1078 };
1079
1080 static struct qcom_icc_node qns_llcc = {
1081 .name = "qns_llcc",
1082 .id = SM8750_SLAVE_LLCC,
1083 .channels = 4,
1084 .buswidth = 16,
1085 .num_links = 1,
1086 .links = { SM8750_MASTER_LLCC },
1087 };
1088
1089 static struct qcom_icc_node qns_pcie = {
1090 .name = "qns_pcie",
1091 .id = SM8750_SLAVE_MEM_NOC_PCIE_SNOC,
1092 .channels = 1,
1093 .buswidth = 8,
1094 .num_links = 1,
1095 .links = { SM8750_MASTER_GEM_NOC_PCIE_SNOC },
1096 };
1097
1098 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1099 .name = "qns_lpass_ag_noc_gemnoc",
1100 .id = SM8750_SLAVE_LPASS_GEM_NOC,
1101 .channels = 1,
1102 .buswidth = 16,
1103 .num_links = 1,
1104 .links = { SM8750_MASTER_LPASS_GEM_NOC },
1105 };
1106
1107 static struct qcom_icc_node qns_lpass_aggnoc = {
1108 .name = "qns_lpass_aggnoc",
1109 .id = SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
1110 .channels = 1,
1111 .buswidth = 16,
1112 .num_links = 1,
1113 .links = { SM8750_MASTER_LPIAON_NOC },
1114 };
1115
1116 static struct qcom_icc_node qns_lpi_aon_noc = {
1117 .name = "qns_lpi_aon_noc",
1118 .id = SM8750_SLAVE_LPICX_NOC_LPIAON_NOC,
1119 .channels = 1,
1120 .buswidth = 16,
1121 .num_links = 1,
1122 .links = { SM8750_MASTER_LPASS_LPINOC },
1123 };
1124
1125 static struct qcom_icc_node ebi = {
1126 .name = "ebi",
1127 .id = SM8750_SLAVE_EBI1,
1128 .channels = 4,
1129 .buswidth = 4,
1130 .num_links = 0,
1131 };
1132
1133 static struct qcom_icc_node qns_mem_noc_hf = {
1134 .name = "qns_mem_noc_hf",
1135 .id = SM8750_SLAVE_MNOC_HF_MEM_NOC,
1136 .channels = 2,
1137 .buswidth = 32,
1138 .num_links = 1,
1139 .links = { SM8750_MASTER_MNOC_HF_MEM_NOC },
1140 };
1141
1142 static struct qcom_icc_node qns_mem_noc_sf = {
1143 .name = "qns_mem_noc_sf",
1144 .id = SM8750_SLAVE_MNOC_SF_MEM_NOC,
1145 .channels = 2,
1146 .buswidth = 32,
1147 .num_links = 1,
1148 .links = { SM8750_MASTER_MNOC_SF_MEM_NOC },
1149 };
1150
1151 static struct qcom_icc_node srvc_mnoc = {
1152 .name = "srvc_mnoc",
1153 .id = SM8750_SLAVE_SERVICE_MNOC,
1154 .channels = 1,
1155 .buswidth = 4,
1156 .num_links = 0,
1157 };
1158
1159 static struct qcom_icc_node qns_nsp_gemnoc = {
1160 .name = "qns_nsp_gemnoc",
1161 .id = SM8750_SLAVE_CDSP_MEM_NOC,
1162 .channels = 2,
1163 .buswidth = 32,
1164 .num_links = 1,
1165 .links = { SM8750_MASTER_COMPUTE_NOC },
1166 };
1167
1168 static struct qcom_icc_node qns_pcie_mem_noc = {
1169 .name = "qns_pcie_mem_noc",
1170 .id = SM8750_SLAVE_ANOC_PCIE_GEM_NOC,
1171 .channels = 1,
1172 .buswidth = 8,
1173 .num_links = 1,
1174 .links = { SM8750_MASTER_ANOC_PCIE_GEM_NOC },
1175 };
1176
1177 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1178 .name = "srvc_pcie_aggre_noc",
1179 .id = SM8750_SLAVE_SERVICE_PCIE_ANOC,
1180 .channels = 1,
1181 .buswidth = 4,
1182 .num_links = 0,
1183 };
1184
1185 static struct qcom_icc_node qns_gemnoc_sf = {
1186 .name = "qns_gemnoc_sf",
1187 .id = SM8750_SLAVE_SNOC_GEM_NOC_SF,
1188 .channels = 1,
1189 .buswidth = 16,
1190 .num_links = 1,
1191 .links = { SM8750_MASTER_SNOC_SF_MEM_NOC },
1192 };
1193
1194 static struct qcom_icc_bcm bcm_acv = {
1195 .name = "ACV",
1196 .enable_mask = BIT(0),
1197 .num_nodes = 1,
1198 .nodes = { &ebi },
1199 };
1200
1201 static struct qcom_icc_bcm bcm_ce0 = {
1202 .name = "CE0",
1203 .num_nodes = 1,
1204 .nodes = { &qxm_crypto },
1205 };
1206
1207 static struct qcom_icc_bcm bcm_cn0 = {
1208 .name = "CN0",
1209 .enable_mask = BIT(0),
1210 .keepalive = true,
1211 .num_nodes = 44,
1212 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1213 &qhs_ahb2phy1, &qhs_camera_cfg,
1214 &qhs_clk_ctl, &qhs_crypto0_cfg,
1215 &qhs_eva_cfg, &qhs_gpuss_cfg,
1216 &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg,
1217 &qhs_imem_cfg, &qhs_mss_cfg,
1218 &qhs_pcie_cfg, &qhs_prng,
1219 &qhs_qdss_cfg, &qhs_qspi,
1220 &qhs_sdc2, &qhs_sdc4,
1221 &qhs_spss_cfg, &qhs_tcsr,
1222 &qhs_tlmm, &qhs_ufs_mem_cfg,
1223 &qhs_usb3_0, &qhs_venus_cfg,
1224 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg,
1225 &qss_pcie_anoc_cfg, &xs_qdss_stm,
1226 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc,
1227 &qnm_gemnoc_pcie, &qhs_aoss,
1228 &qhs_ipa, &qhs_ipc_router,
1229 &qhs_soccp, &qhs_tme_cfg,
1230 &qns_apss, &qss_cfg,
1231 &qss_ddrss_cfg, &qxs_boot_imem,
1232 &qxs_imem, &qxs_modem_boot_imem,
1233 &srvc_cnoc_main, &xs_pcie },
1234 };
1235
1236 static struct qcom_icc_bcm bcm_cn1 = {
1237 .name = "CN1",
1238 .num_nodes = 5,
1239 .nodes = { &qhs_display_cfg, &qhs_i2c,
1240 &qhs_qup02, &qhs_qup1,
1241 &qhs_qup2 },
1242 };
1243
1244 static struct qcom_icc_bcm bcm_co0 = {
1245 .name = "CO0",
1246 .enable_mask = BIT(0),
1247 .num_nodes = 2,
1248 .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
1249 };
1250
1251 static struct qcom_icc_bcm bcm_lp0 = {
1252 .name = "LP0",
1253 .num_nodes = 2,
1254 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1255 };
1256
1257 static struct qcom_icc_bcm bcm_mc0 = {
1258 .name = "MC0",
1259 .keepalive = true,
1260 .num_nodes = 1,
1261 .nodes = { &ebi },
1262 };
1263
1264 static struct qcom_icc_bcm bcm_mm0 = {
1265 .name = "MM0",
1266 .num_nodes = 1,
1267 .nodes = { &qns_mem_noc_hf },
1268 };
1269
1270 static struct qcom_icc_bcm bcm_mm1 = {
1271 .name = "MM1",
1272 .enable_mask = BIT(0),
1273 .num_nodes = 9,
1274 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
1275 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
1276 &qnm_vapss_hcp, &qnm_video_cv_cpu,
1277 &qnm_video_mvp, &qnm_video_v_cpu,
1278 &qns_mem_noc_sf },
1279 };
1280
1281 static struct qcom_icc_bcm bcm_qup0 = {
1282 .name = "QUP0",
1283 .keepalive = true,
1284 .vote_scale = 1,
1285 .num_nodes = 1,
1286 .nodes = { &qup0_core_slave },
1287 };
1288
1289 static struct qcom_icc_bcm bcm_qup1 = {
1290 .name = "QUP1",
1291 .keepalive = true,
1292 .vote_scale = 1,
1293 .num_nodes = 1,
1294 .nodes = { &qup1_core_slave },
1295 };
1296
1297 static struct qcom_icc_bcm bcm_qup2 = {
1298 .name = "QUP2",
1299 .keepalive = true,
1300 .vote_scale = 1,
1301 .num_nodes = 1,
1302 .nodes = { &qup2_core_slave },
1303 };
1304
1305 static struct qcom_icc_bcm bcm_sh0 = {
1306 .name = "SH0",
1307 .keepalive = true,
1308 .num_nodes = 1,
1309 .nodes = { &qns_llcc },
1310 };
1311
1312 static struct qcom_icc_bcm bcm_sh1 = {
1313 .name = "SH1",
1314 .enable_mask = BIT(0),
1315 .num_nodes = 14,
1316 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1317 &chm_apps, &qnm_gpu,
1318 &qnm_mdsp, &qnm_mnoc_hf,
1319 &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1320 &qnm_pcie, &qnm_snoc_sf,
1321 &xm_gic, &chs_ubwc_p,
1322 &qns_gem_noc_cnoc, &qns_pcie },
1323 };
1324
1325 static struct qcom_icc_bcm bcm_sn0 = {
1326 .name = "SN0",
1327 .keepalive = true,
1328 .num_nodes = 1,
1329 .nodes = { &qns_gemnoc_sf },
1330 };
1331
1332 static struct qcom_icc_bcm bcm_sn2 = {
1333 .name = "SN2",
1334 .num_nodes = 1,
1335 .nodes = { &qnm_aggre1_noc },
1336 };
1337
1338 static struct qcom_icc_bcm bcm_sn3 = {
1339 .name = "SN3",
1340 .num_nodes = 1,
1341 .nodes = { &qnm_aggre2_noc },
1342 };
1343
1344 static struct qcom_icc_bcm bcm_sn4 = {
1345 .name = "SN4",
1346 .num_nodes = 1,
1347 .nodes = { &qns_pcie_mem_noc },
1348 };
1349
1350 static struct qcom_icc_bcm bcm_ubw0 = {
1351 .name = "UBW0",
1352 .num_nodes = 1,
1353 .nodes = { &qnm_ubwc_p },
1354 };
1355
1356 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1357 [MASTER_QSPI_0] = &qhm_qspi,
1358 [MASTER_QUP_1] = &qhm_qup1,
1359 [MASTER_QUP_3] = &qxm_qup02,
1360 [MASTER_SDCC_4] = &xm_sdc4,
1361 [MASTER_UFS_MEM] = &xm_ufs_mem,
1362 [MASTER_USB3_0] = &xm_usb3_0,
1363 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1364 };
1365
1366 static const struct qcom_icc_desc sm8750_aggre1_noc = {
1367 .nodes = aggre1_noc_nodes,
1368 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1369 };
1370
1371 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1372 &bcm_ce0,
1373 };
1374
1375 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1376 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1377 [MASTER_QUP_2] = &qhm_qup2,
1378 [MASTER_CRYPTO] = &qxm_crypto,
1379 [MASTER_IPA] = &qxm_ipa,
1380 [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp,
1381 [MASTER_SP] = &qxm_sp,
1382 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1383 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1384 [MASTER_SDCC_2] = &xm_sdc2,
1385 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1386 };
1387
1388 static const struct qcom_icc_desc sm8750_aggre2_noc = {
1389 .nodes = aggre2_noc_nodes,
1390 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1391 .bcms = aggre2_noc_bcms,
1392 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1393 };
1394
1395 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1396 &bcm_qup0,
1397 &bcm_qup1,
1398 &bcm_qup2,
1399 };
1400
1401 static struct qcom_icc_node * const clk_virt_nodes[] = {
1402 [MASTER_QUP_CORE_0] = &qup0_core_master,
1403 [MASTER_QUP_CORE_1] = &qup1_core_master,
1404 [MASTER_QUP_CORE_2] = &qup2_core_master,
1405 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1406 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1407 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1408 };
1409
1410 static const struct qcom_icc_desc sm8750_clk_virt = {
1411 .nodes = clk_virt_nodes,
1412 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1413 .bcms = clk_virt_bcms,
1414 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1415 };
1416
1417 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1418 &bcm_cn0,
1419 &bcm_cn1,
1420 };
1421
1422 static struct qcom_icc_node * const config_noc_nodes[] = {
1423 [MASTER_CNOC_CFG] = &qsm_cfg,
1424 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1425 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1426 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1427 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1428 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1429 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1430 [SLAVE_EVA_CFG] = &qhs_eva_cfg,
1431 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1432 [SLAVE_I2C] = &qhs_i2c,
1433 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg,
1434 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg,
1435 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1436 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1437 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
1438 [SLAVE_PRNG] = &qhs_prng,
1439 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1440 [SLAVE_QSPI_0] = &qhs_qspi,
1441 [SLAVE_QUP_3] = &qhs_qup02,
1442 [SLAVE_QUP_1] = &qhs_qup1,
1443 [SLAVE_QUP_2] = &qhs_qup2,
1444 [SLAVE_SDCC_2] = &qhs_sdc2,
1445 [SLAVE_SDCC_4] = &qhs_sdc4,
1446 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1447 [SLAVE_TCSR] = &qhs_tcsr,
1448 [SLAVE_TLMM] = &qhs_tlmm,
1449 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1450 [SLAVE_USB3_0] = &qhs_usb3_0,
1451 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1452 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1453 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1454 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1455 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1456 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1457 };
1458
1459 static const struct qcom_icc_desc sm8750_config_noc = {
1460 .nodes = config_noc_nodes,
1461 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1462 .bcms = config_noc_bcms,
1463 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1464 };
1465
1466 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1467 &bcm_cn0,
1468 };
1469
1470 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1471 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1472 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1473 [SLAVE_AOSS] = &qhs_aoss,
1474 [SLAVE_IPA_CFG] = &qhs_ipa,
1475 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1476 [SLAVE_SOCCP] = &qhs_soccp,
1477 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1478 [SLAVE_APPSS] = &qns_apss,
1479 [SLAVE_CNOC_CFG] = &qss_cfg,
1480 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1481 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1482 [SLAVE_IMEM] = &qxs_imem,
1483 [SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem,
1484 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main,
1485 [SLAVE_PCIE_0] = &xs_pcie,
1486 };
1487
1488 static const struct qcom_icc_desc sm8750_cnoc_main = {
1489 .nodes = cnoc_main_nodes,
1490 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1491 .bcms = cnoc_main_bcms,
1492 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1493 };
1494
1495 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1496 &bcm_sh0,
1497 &bcm_sh1,
1498 &bcm_ubw0,
1499 };
1500
1501 static struct qcom_icc_node * const gem_noc_nodes[] = {
1502 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1503 [MASTER_SYS_TCU] = &alm_sys_tcu,
1504 [MASTER_APPSS_PROC] = &chm_apps,
1505 [MASTER_GFX3D] = &qnm_gpu,
1506 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1507 [MASTER_MSS_PROC] = &qnm_mdsp,
1508 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1509 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1510 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1511 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1512 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1513 [MASTER_UBWC_P] = &qnm_ubwc_p,
1514 [MASTER_GIC] = &xm_gic,
1515 [SLAVE_UBWC_P] = &chs_ubwc_p,
1516 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1517 [SLAVE_LLCC] = &qns_llcc,
1518 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1519 };
1520
1521 static const struct qcom_icc_desc sm8750_gem_noc = {
1522 .nodes = gem_noc_nodes,
1523 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1524 .bcms = gem_noc_bcms,
1525 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1526 };
1527
1528 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1529 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1530 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1531 };
1532
1533 static const struct qcom_icc_desc sm8750_lpass_ag_noc = {
1534 .nodes = lpass_ag_noc_nodes,
1535 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1536 };
1537
1538 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1539 &bcm_lp0,
1540 };
1541
1542 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1543 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1544 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1545 };
1546
1547 static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = {
1548 .nodes = lpass_lpiaon_noc_nodes,
1549 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1550 .bcms = lpass_lpiaon_noc_bcms,
1551 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1552 };
1553
1554 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1555 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
1556 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1557 };
1558
1559 static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = {
1560 .nodes = lpass_lpicx_noc_nodes,
1561 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1562 };
1563
1564 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1565 &bcm_acv,
1566 &bcm_mc0,
1567 };
1568
1569 static struct qcom_icc_node * const mc_virt_nodes[] = {
1570 [MASTER_LLCC] = &llcc_mc,
1571 [SLAVE_EBI1] = &ebi,
1572 };
1573
1574 static const struct qcom_icc_desc sm8750_mc_virt = {
1575 .nodes = mc_virt_nodes,
1576 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1577 .bcms = mc_virt_bcms,
1578 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1579 };
1580
1581 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1582 &bcm_mm0,
1583 &bcm_mm1,
1584 };
1585
1586 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1587 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1588 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
1589 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
1590 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1591 [MASTER_MDP] = &qnm_mdp,
1592 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1593 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1594 [MASTER_VIDEO_EVA] = &qnm_video_eva,
1595 [MASTER_VIDEO_MVP] = &qnm_video_mvp,
1596 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1597 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1598 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1599 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1600 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1601 };
1602
1603 static const struct qcom_icc_desc sm8750_mmss_noc = {
1604 .nodes = mmss_noc_nodes,
1605 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1606 .bcms = mmss_noc_bcms,
1607 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1608 };
1609
1610 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1611 &bcm_co0,
1612 };
1613
1614 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1615 [MASTER_CDSP_PROC] = &qnm_nsp,
1616 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1617 };
1618
1619 static const struct qcom_icc_desc sm8750_nsp_noc = {
1620 .nodes = nsp_noc_nodes,
1621 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1622 .bcms = nsp_noc_bcms,
1623 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1624 };
1625
1626 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1627 &bcm_sn4,
1628 };
1629
1630 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1631 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1632 [MASTER_PCIE_0] = &xm_pcie3,
1633 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1634 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1635 };
1636
1637 static const struct qcom_icc_desc sm8750_pcie_anoc = {
1638 .nodes = pcie_anoc_nodes,
1639 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1640 .bcms = pcie_anoc_bcms,
1641 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1642 };
1643
1644 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1645 &bcm_sn0,
1646 &bcm_sn2,
1647 &bcm_sn3,
1648 };
1649
1650 static struct qcom_icc_node * const system_noc_nodes[] = {
1651 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1652 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1653 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1654 };
1655
1656 static const struct qcom_icc_desc sm8750_system_noc = {
1657 .nodes = system_noc_nodes,
1658 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1659 .bcms = system_noc_bcms,
1660 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1661 };
1662
1663 static const struct of_device_id qnoc_of_match[] = {
1664 { .compatible = "qcom,sm8750-aggre1-noc", .data = &sm8750_aggre1_noc},
1665 { .compatible = "qcom,sm8750-aggre2-noc", .data = &sm8750_aggre2_noc},
1666 { .compatible = "qcom,sm8750-clk-virt", .data = &sm8750_clk_virt},
1667 { .compatible = "qcom,sm8750-config-noc", .data = &sm8750_config_noc},
1668 { .compatible = "qcom,sm8750-cnoc-main", .data = &sm8750_cnoc_main},
1669 { .compatible = "qcom,sm8750-gem-noc", .data = &sm8750_gem_noc},
1670 { .compatible = "qcom,sm8750-lpass-ag-noc", .data = &sm8750_lpass_ag_noc},
1671 { .compatible = "qcom,sm8750-lpass-lpiaon-noc", .data = &sm8750_lpass_lpiaon_noc},
1672 { .compatible = "qcom,sm8750-lpass-lpicx-noc", .data = &sm8750_lpass_lpicx_noc},
1673 { .compatible = "qcom,sm8750-mc-virt", .data = &sm8750_mc_virt},
1674 { .compatible = "qcom,sm8750-mmss-noc", .data = &sm8750_mmss_noc},
1675 { .compatible = "qcom,sm8750-nsp-noc", .data = &sm8750_nsp_noc},
1676 { .compatible = "qcom,sm8750-pcie-anoc", .data = &sm8750_pcie_anoc},
1677 { .compatible = "qcom,sm8750-system-noc", .data = &sm8750_system_noc},
1678 { }
1679 };
1680 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1681
1682 static struct platform_driver qnoc_driver = {
1683 .probe = qcom_icc_rpmh_probe,
1684 .remove = qcom_icc_rpmh_remove,
1685 .driver = {
1686 .name = "qnoc-sm8750",
1687 .of_match_table = qnoc_of_match,
1688 .sync_state = icc_sync_state,
1689 },
1690 };
1691
qnoc_driver_init(void)1692 static int __init qnoc_driver_init(void)
1693 {
1694 return platform_driver_register(&qnoc_driver);
1695 }
1696 core_initcall(qnoc_driver_init);
1697
qnoc_driver_exit(void)1698 static void __exit qnoc_driver_exit(void)
1699 {
1700 platform_driver_unregister(&qnoc_driver);
1701 }
1702 module_exit(qnoc_driver_exit);
1703
1704 MODULE_DESCRIPTION("SM8750 NoC driver");
1705 MODULE_LICENSE("GPL");
1706