1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
13
14 #include "bcm-voter.h"
15 #include "icc-rpmh.h"
16 #include "qcs8300.h"
17
18 static struct qcom_icc_node qxm_qup3 = {
19 .name = "qxm_qup3",
20 .id = QCS8300_MASTER_QUP_3,
21 .channels = 1,
22 .buswidth = 8,
23 .num_links = 1,
24 .links = { QCS8300_SLAVE_A1NOC_SNOC },
25 };
26
27 static struct qcom_icc_node xm_emac_0 = {
28 .name = "xm_emac_0",
29 .id = QCS8300_MASTER_EMAC,
30 .channels = 1,
31 .buswidth = 8,
32 .num_links = 1,
33 .links = { QCS8300_SLAVE_A1NOC_SNOC },
34 };
35
36 static struct qcom_icc_node xm_sdc1 = {
37 .name = "xm_sdc1",
38 .id = QCS8300_MASTER_SDC,
39 .channels = 1,
40 .buswidth = 8,
41 .num_links = 1,
42 .links = { QCS8300_SLAVE_A1NOC_SNOC },
43 };
44
45 static struct qcom_icc_node xm_ufs_mem = {
46 .name = "xm_ufs_mem",
47 .id = QCS8300_MASTER_UFS_MEM,
48 .channels = 1,
49 .buswidth = 8,
50 .num_links = 1,
51 .links = { QCS8300_SLAVE_A1NOC_SNOC },
52 };
53
54 static struct qcom_icc_node xm_usb2_2 = {
55 .name = "xm_usb2_2",
56 .id = QCS8300_MASTER_USB2,
57 .channels = 1,
58 .buswidth = 8,
59 .num_links = 1,
60 .links = { QCS8300_SLAVE_A1NOC_SNOC },
61 };
62
63 static struct qcom_icc_node xm_usb3_0 = {
64 .name = "xm_usb3_0",
65 .id = QCS8300_MASTER_USB3_0,
66 .channels = 1,
67 .buswidth = 8,
68 .num_links = 1,
69 .links = { QCS8300_SLAVE_A1NOC_SNOC },
70 };
71
72 static struct qcom_icc_node qhm_qdss_bam = {
73 .name = "qhm_qdss_bam",
74 .id = QCS8300_MASTER_QDSS_BAM,
75 .channels = 1,
76 .buswidth = 4,
77 .num_links = 1,
78 .links = { QCS8300_SLAVE_A2NOC_SNOC },
79 };
80
81 static struct qcom_icc_node qhm_qup0 = {
82 .name = "qhm_qup0",
83 .id = QCS8300_MASTER_QUP_0,
84 .channels = 1,
85 .buswidth = 4,
86 .num_links = 1,
87 .links = { QCS8300_SLAVE_A2NOC_SNOC },
88 };
89
90 static struct qcom_icc_node qhm_qup1 = {
91 .name = "qhm_qup1",
92 .id = QCS8300_MASTER_QUP_1,
93 .channels = 1,
94 .buswidth = 4,
95 .num_links = 1,
96 .links = { QCS8300_SLAVE_A2NOC_SNOC },
97 };
98
99 static struct qcom_icc_node qnm_cnoc_datapath = {
100 .name = "qnm_cnoc_datapath",
101 .id = QCS8300_MASTER_CNOC_A2NOC,
102 .channels = 1,
103 .buswidth = 8,
104 .num_links = 1,
105 .links = { QCS8300_SLAVE_A2NOC_SNOC },
106 };
107
108 static struct qcom_icc_node qxm_crypto_0 = {
109 .name = "qxm_crypto_0",
110 .id = QCS8300_MASTER_CRYPTO_CORE0,
111 .channels = 1,
112 .buswidth = 8,
113 .num_links = 1,
114 .links = { QCS8300_SLAVE_A2NOC_SNOC },
115 };
116
117 static struct qcom_icc_node qxm_crypto_1 = {
118 .name = "qxm_crypto_1",
119 .id = QCS8300_MASTER_CRYPTO_CORE1,
120 .channels = 1,
121 .buswidth = 8,
122 .num_links = 1,
123 .links = { QCS8300_SLAVE_A2NOC_SNOC },
124 };
125
126 static struct qcom_icc_node qxm_ipa = {
127 .name = "qxm_ipa",
128 .id = QCS8300_MASTER_IPA,
129 .channels = 1,
130 .buswidth = 8,
131 .num_links = 1,
132 .links = { QCS8300_SLAVE_A2NOC_SNOC },
133 };
134
135 static struct qcom_icc_node xm_qdss_etr_0 = {
136 .name = "xm_qdss_etr_0",
137 .id = QCS8300_MASTER_QDSS_ETR_0,
138 .channels = 1,
139 .buswidth = 8,
140 .num_links = 1,
141 .links = { QCS8300_SLAVE_A2NOC_SNOC },
142 };
143
144 static struct qcom_icc_node xm_qdss_etr_1 = {
145 .name = "xm_qdss_etr_1",
146 .id = QCS8300_MASTER_QDSS_ETR_1,
147 .channels = 1,
148 .buswidth = 8,
149 .num_links = 1,
150 .links = { QCS8300_SLAVE_A2NOC_SNOC },
151 };
152
153 static struct qcom_icc_node qup0_core_master = {
154 .name = "qup0_core_master",
155 .id = QCS8300_MASTER_QUP_CORE_0,
156 .channels = 1,
157 .buswidth = 4,
158 .num_links = 1,
159 .links = { QCS8300_SLAVE_QUP_CORE_0 },
160 };
161
162 static struct qcom_icc_node qup1_core_master = {
163 .name = "qup1_core_master",
164 .id = QCS8300_MASTER_QUP_CORE_1,
165 .channels = 1,
166 .buswidth = 4,
167 .num_links = 1,
168 .links = { QCS8300_SLAVE_QUP_CORE_1 },
169 };
170
171 static struct qcom_icc_node qup3_core_master = {
172 .name = "qup3_core_master",
173 .id = QCS8300_MASTER_QUP_CORE_3,
174 .channels = 1,
175 .buswidth = 4,
176 .num_links = 1,
177 .links = { QCS8300_SLAVE_QUP_CORE_3 },
178 };
179
180 static struct qcom_icc_node qnm_gemnoc_cnoc = {
181 .name = "qnm_gemnoc_cnoc",
182 .id = QCS8300_MASTER_GEM_NOC_CNOC,
183 .channels = 1,
184 .buswidth = 16,
185 .num_links = 71,
186 .links = { QCS8300_SLAVE_AHB2PHY_2, QCS8300_SLAVE_AHB2PHY_3,
187 QCS8300_SLAVE_ANOC_THROTTLE_CFG, QCS8300_SLAVE_AOSS,
188 QCS8300_SLAVE_APPSS, QCS8300_SLAVE_BOOT_ROM,
189 QCS8300_SLAVE_CAMERA_CFG, QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
190 QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, QCS8300_SLAVE_CLK_CTL,
191 QCS8300_SLAVE_CDSP_CFG, QCS8300_SLAVE_RBCPR_CX_CFG,
192 QCS8300_SLAVE_RBCPR_MMCX_CFG, QCS8300_SLAVE_RBCPR_MX_CFG,
193 QCS8300_SLAVE_CPR_NSPCX, QCS8300_SLAVE_CPR_NSPHMX,
194 QCS8300_SLAVE_CRYPTO_0_CFG, QCS8300_SLAVE_CX_RDPM,
195 QCS8300_SLAVE_DISPLAY_CFG, QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
196 QCS8300_SLAVE_EMAC_CFG, QCS8300_SLAVE_GP_DSP0_CFG,
197 QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
198 QCS8300_SLAVE_GFX3D_CFG, QCS8300_SLAVE_HWKM,
199 QCS8300_SLAVE_IMEM_CFG, QCS8300_SLAVE_IPA_CFG,
200 QCS8300_SLAVE_IPC_ROUTER_CFG, QCS8300_SLAVE_LPASS,
201 QCS8300_SLAVE_LPASS_THROTTLE_CFG, QCS8300_SLAVE_MX_RDPM,
202 QCS8300_SLAVE_MXC_RDPM, QCS8300_SLAVE_PCIE_0_CFG,
203 QCS8300_SLAVE_PCIE_1_CFG, QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
204 QCS8300_SLAVE_PCIE_THROTTLE_CFG, QCS8300_SLAVE_PDM,
205 QCS8300_SLAVE_PIMEM_CFG, QCS8300_SLAVE_PKA_WRAPPER_CFG,
206 QCS8300_SLAVE_QDSS_CFG, QCS8300_SLAVE_QM_CFG,
207 QCS8300_SLAVE_QM_MPU_CFG, QCS8300_SLAVE_QUP_0,
208 QCS8300_SLAVE_QUP_1, QCS8300_SLAVE_QUP_3,
209 QCS8300_SLAVE_SAIL_THROTTLE_CFG, QCS8300_SLAVE_SDC1,
210 QCS8300_SLAVE_SECURITY, QCS8300_SLAVE_SNOC_THROTTLE_CFG,
211 QCS8300_SLAVE_TCSR, QCS8300_SLAVE_TLMM,
212 QCS8300_SLAVE_TSC_CFG, QCS8300_SLAVE_UFS_MEM_CFG,
213 QCS8300_SLAVE_USB2, QCS8300_SLAVE_USB3_0,
214 QCS8300_SLAVE_VENUS_CFG, QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
215 QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
216 QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
217 QCS8300_SLAVE_DDRSS_CFG, QCS8300_SLAVE_GPDSP_NOC_CFG,
218 QCS8300_SLAVE_CNOC_MNOC_HF_CFG, QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
219 QCS8300_SLAVE_PCIE_ANOC_CFG, QCS8300_SLAVE_SNOC_CFG,
220 QCS8300_SLAVE_BOOT_IMEM, QCS8300_SLAVE_IMEM,
221 QCS8300_SLAVE_PIMEM, QCS8300_SLAVE_QDSS_STM,
222 QCS8300_SLAVE_TCU },
223 };
224
225 static struct qcom_icc_node qnm_gemnoc_pcie = {
226 .name = "qnm_gemnoc_pcie",
227 .id = QCS8300_MASTER_GEM_NOC_PCIE_SNOC,
228 .channels = 1,
229 .buswidth = 16,
230 .num_links = 2,
231 .links = { QCS8300_SLAVE_PCIE_0, QCS8300_SLAVE_PCIE_1 },
232 };
233
234 static struct qcom_icc_node qnm_cnoc_dc_noc = {
235 .name = "qnm_cnoc_dc_noc",
236 .id = QCS8300_MASTER_CNOC_DC_NOC,
237 .channels = 1,
238 .buswidth = 4,
239 .num_links = 2,
240 .links = { QCS8300_SLAVE_LLCC_CFG, QCS8300_SLAVE_GEM_NOC_CFG },
241 };
242
243 static struct qcom_icc_node alm_gpu_tcu = {
244 .name = "alm_gpu_tcu",
245 .id = QCS8300_MASTER_GPU_TCU,
246 .channels = 1,
247 .buswidth = 8,
248 .num_links = 2,
249 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
250 };
251
252 static struct qcom_icc_node alm_pcie_tcu = {
253 .name = "alm_pcie_tcu",
254 .id = QCS8300_MASTER_PCIE_TCU,
255 .channels = 1,
256 .buswidth = 8,
257 .num_links = 2,
258 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
259 };
260
261 static struct qcom_icc_node alm_sys_tcu = {
262 .name = "alm_sys_tcu",
263 .id = QCS8300_MASTER_SYS_TCU,
264 .channels = 1,
265 .buswidth = 8,
266 .num_links = 2,
267 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
268 };
269
270 static struct qcom_icc_node chm_apps = {
271 .name = "chm_apps",
272 .id = QCS8300_MASTER_APPSS_PROC,
273 .channels = 4,
274 .buswidth = 32,
275 .num_links = 3,
276 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
277 QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
278 };
279
280 static struct qcom_icc_node qnm_cmpnoc0 = {
281 .name = "qnm_cmpnoc0",
282 .id = QCS8300_MASTER_COMPUTE_NOC,
283 .channels = 2,
284 .buswidth = 32,
285 .num_links = 2,
286 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
287 };
288
289 static struct qcom_icc_node qnm_gemnoc_cfg = {
290 .name = "qnm_gemnoc_cfg",
291 .id = QCS8300_MASTER_GEM_NOC_CFG,
292 .channels = 1,
293 .buswidth = 4,
294 .num_links = 4,
295 .links = { QCS8300_SLAVE_SERVICE_GEM_NOC_1, QCS8300_SLAVE_SERVICE_GEM_NOC_2,
296 QCS8300_SLAVE_SERVICE_GEM_NOC, QCS8300_SLAVE_SERVICE_GEM_NOC2 },
297 };
298
299 static struct qcom_icc_node qnm_gpdsp_sail = {
300 .name = "qnm_gpdsp_sail",
301 .id = QCS8300_MASTER_GPDSP_SAIL,
302 .channels = 1,
303 .buswidth = 16,
304 .num_links = 2,
305 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
306 };
307
308 static struct qcom_icc_node qnm_gpu = {
309 .name = "qnm_gpu",
310 .id = QCS8300_MASTER_GFX3D,
311 .channels = 2,
312 .buswidth = 32,
313 .num_links = 2,
314 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
315 };
316
317 static struct qcom_icc_node qnm_mnoc_hf = {
318 .name = "qnm_mnoc_hf",
319 .id = QCS8300_MASTER_MNOC_HF_MEM_NOC,
320 .channels = 2,
321 .buswidth = 32,
322 .num_links = 2,
323 .links = { QCS8300_SLAVE_LLCC, QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
324 };
325
326 static struct qcom_icc_node qnm_mnoc_sf = {
327 .name = "qnm_mnoc_sf",
328 .id = QCS8300_MASTER_MNOC_SF_MEM_NOC,
329 .channels = 2,
330 .buswidth = 32,
331 .num_links = 3,
332 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
333 QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
334 };
335
336 static struct qcom_icc_node qnm_pcie = {
337 .name = "qnm_pcie",
338 .id = QCS8300_MASTER_ANOC_PCIE_GEM_NOC,
339 .channels = 1,
340 .buswidth = 32,
341 .num_links = 2,
342 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
343 };
344
345 static struct qcom_icc_node qnm_snoc_gc = {
346 .name = "qnm_snoc_gc",
347 .id = QCS8300_MASTER_SNOC_GC_MEM_NOC,
348 .channels = 1,
349 .buswidth = 8,
350 .num_links = 1,
351 .links = { QCS8300_SLAVE_LLCC },
352 };
353
354 static struct qcom_icc_node qnm_snoc_sf = {
355 .name = "qnm_snoc_sf",
356 .id = QCS8300_MASTER_SNOC_SF_MEM_NOC,
357 .channels = 1,
358 .buswidth = 16,
359 .num_links = 3,
360 .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
361 QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
362 };
363
364 static struct qcom_icc_node qnm_sailss_md0 = {
365 .name = "qnm_sailss_md0",
366 .id = QCS8300_MASTER_SAILSS_MD0,
367 .channels = 1,
368 .buswidth = 16,
369 .num_links = 1,
370 .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
371 };
372
373 static struct qcom_icc_node qxm_dsp0 = {
374 .name = "qxm_dsp0",
375 .id = QCS8300_MASTER_DSP0,
376 .channels = 1,
377 .buswidth = 16,
378 .num_links = 1,
379 .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
380 };
381
382 static struct qcom_icc_node qhm_config_noc = {
383 .name = "qhm_config_noc",
384 .id = QCS8300_MASTER_CNOC_LPASS_AG_NOC,
385 .channels = 1,
386 .buswidth = 4,
387 .num_links = 6,
388 .links = { QCS8300_SLAVE_LPASS_CORE_CFG, QCS8300_SLAVE_LPASS_LPI_CFG,
389 QCS8300_SLAVE_LPASS_MPU_CFG, QCS8300_SLAVE_LPASS_TOP_CFG,
390 QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
391 };
392
393 static struct qcom_icc_node qxm_lpass_dsp = {
394 .name = "qxm_lpass_dsp",
395 .id = QCS8300_MASTER_LPASS_PROC,
396 .channels = 1,
397 .buswidth = 8,
398 .num_links = 4,
399 .links = { QCS8300_SLAVE_LPASS_TOP_CFG, QCS8300_SLAVE_LPASS_SNOC,
400 QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
401 };
402
403 static struct qcom_icc_node llcc_mc = {
404 .name = "llcc_mc",
405 .id = QCS8300_MASTER_LLCC,
406 .channels = 8,
407 .buswidth = 4,
408 .num_links = 1,
409 .links = { QCS8300_SLAVE_EBI1 },
410 };
411
412 static struct qcom_icc_node qnm_camnoc_hf = {
413 .name = "qnm_camnoc_hf",
414 .id = QCS8300_MASTER_CAMNOC_HF,
415 .channels = 1,
416 .buswidth = 32,
417 .num_links = 1,
418 .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
419 };
420
421 static struct qcom_icc_node qnm_camnoc_icp = {
422 .name = "qnm_camnoc_icp",
423 .id = QCS8300_MASTER_CAMNOC_ICP,
424 .channels = 1,
425 .buswidth = 8,
426 .num_links = 1,
427 .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
428 };
429
430 static struct qcom_icc_node qnm_camnoc_sf = {
431 .name = "qnm_camnoc_sf",
432 .id = QCS8300_MASTER_CAMNOC_SF,
433 .channels = 1,
434 .buswidth = 32,
435 .num_links = 1,
436 .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
437 };
438
439 static struct qcom_icc_node qnm_mdp0_0 = {
440 .name = "qnm_mdp0_0",
441 .id = QCS8300_MASTER_MDP0,
442 .channels = 1,
443 .buswidth = 32,
444 .num_links = 1,
445 .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
446 };
447
448 static struct qcom_icc_node qnm_mdp0_1 = {
449 .name = "qnm_mdp0_1",
450 .id = QCS8300_MASTER_MDP1,
451 .channels = 1,
452 .buswidth = 32,
453 .num_links = 1,
454 .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
455 };
456
457 static struct qcom_icc_node qnm_mnoc_hf_cfg = {
458 .name = "qnm_mnoc_hf_cfg",
459 .id = QCS8300_MASTER_CNOC_MNOC_HF_CFG,
460 .channels = 1,
461 .buswidth = 4,
462 .num_links = 1,
463 .links = { QCS8300_SLAVE_SERVICE_MNOC_HF },
464 };
465
466 static struct qcom_icc_node qnm_mnoc_sf_cfg = {
467 .name = "qnm_mnoc_sf_cfg",
468 .id = QCS8300_MASTER_CNOC_MNOC_SF_CFG,
469 .channels = 1,
470 .buswidth = 4,
471 .num_links = 1,
472 .links = { QCS8300_SLAVE_SERVICE_MNOC_SF },
473 };
474
475 static struct qcom_icc_node qnm_video0 = {
476 .name = "qnm_video0",
477 .id = QCS8300_MASTER_VIDEO_P0,
478 .channels = 1,
479 .buswidth = 32,
480 .num_links = 1,
481 .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
482 };
483
484 static struct qcom_icc_node qnm_video_cvp = {
485 .name = "qnm_video_cvp",
486 .id = QCS8300_MASTER_VIDEO_PROC,
487 .channels = 1,
488 .buswidth = 32,
489 .num_links = 1,
490 .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
491 };
492
493 static struct qcom_icc_node qnm_video_v_cpu = {
494 .name = "qnm_video_v_cpu",
495 .id = QCS8300_MASTER_VIDEO_V_PROC,
496 .channels = 1,
497 .buswidth = 8,
498 .num_links = 1,
499 .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
500 };
501
502 static struct qcom_icc_node qhm_nsp_noc_config = {
503 .name = "qhm_nsp_noc_config",
504 .id = QCS8300_MASTER_CDSP_NOC_CFG,
505 .channels = 1,
506 .buswidth = 4,
507 .num_links = 1,
508 .links = { QCS8300_SLAVE_SERVICE_NSP_NOC },
509 };
510
511 static struct qcom_icc_node qxm_nsp = {
512 .name = "qxm_nsp",
513 .id = QCS8300_MASTER_CDSP_PROC,
514 .channels = 2,
515 .buswidth = 32,
516 .num_links = 2,
517 .links = { QCS8300_SLAVE_HCP_A, QCS8300_SLAVE_CDSP_MEM_NOC },
518 };
519
520 static struct qcom_icc_node xm_pcie3_0 = {
521 .name = "xm_pcie3_0",
522 .id = QCS8300_MASTER_PCIE_0,
523 .channels = 1,
524 .buswidth = 16,
525 .num_links = 1,
526 .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
527 };
528
529 static struct qcom_icc_node xm_pcie3_1 = {
530 .name = "xm_pcie3_1",
531 .id = QCS8300_MASTER_PCIE_1,
532 .channels = 1,
533 .buswidth = 32,
534 .num_links = 1,
535 .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
536 };
537
538 static struct qcom_icc_node qhm_gic = {
539 .name = "qhm_gic",
540 .id = QCS8300_MASTER_GIC_AHB,
541 .channels = 1,
542 .buswidth = 4,
543 .num_links = 1,
544 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
545 };
546
547 static struct qcom_icc_node qnm_aggre1_noc = {
548 .name = "qnm_aggre1_noc",
549 .id = QCS8300_MASTER_A1NOC_SNOC,
550 .channels = 1,
551 .buswidth = 32,
552 .num_links = 1,
553 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
554 };
555
556 static struct qcom_icc_node qnm_aggre2_noc = {
557 .name = "qnm_aggre2_noc",
558 .id = QCS8300_MASTER_A2NOC_SNOC,
559 .channels = 1,
560 .buswidth = 16,
561 .num_links = 1,
562 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
563 };
564
565 static struct qcom_icc_node qnm_lpass_noc = {
566 .name = "qnm_lpass_noc",
567 .id = QCS8300_MASTER_LPASS_ANOC,
568 .channels = 1,
569 .buswidth = 16,
570 .num_links = 1,
571 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
572 };
573
574 static struct qcom_icc_node qnm_snoc_cfg = {
575 .name = "qnm_snoc_cfg",
576 .id = QCS8300_MASTER_SNOC_CFG,
577 .channels = 1,
578 .buswidth = 4,
579 .num_links = 1,
580 .links = { QCS8300_SLAVE_SERVICE_SNOC },
581 };
582
583 static struct qcom_icc_node qxm_pimem = {
584 .name = "qxm_pimem",
585 .id = QCS8300_MASTER_PIMEM,
586 .channels = 1,
587 .buswidth = 8,
588 .num_links = 1,
589 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
590 };
591
592 static struct qcom_icc_node xm_gic = {
593 .name = "xm_gic",
594 .id = QCS8300_MASTER_GIC,
595 .channels = 1,
596 .buswidth = 8,
597 .num_links = 1,
598 .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
599 };
600
601 static struct qcom_icc_node qns_a1noc_snoc = {
602 .name = "qns_a1noc_snoc",
603 .id = QCS8300_SLAVE_A1NOC_SNOC,
604 .channels = 1,
605 .buswidth = 32,
606 .num_links = 1,
607 .links = { QCS8300_MASTER_A1NOC_SNOC },
608 };
609
610 static struct qcom_icc_node qns_a2noc_snoc = {
611 .name = "qns_a2noc_snoc",
612 .id = QCS8300_SLAVE_A2NOC_SNOC,
613 .channels = 1,
614 .buswidth = 16,
615 .num_links = 1,
616 .links = { QCS8300_MASTER_A2NOC_SNOC },
617 };
618
619 static struct qcom_icc_node qup0_core_slave = {
620 .name = "qup0_core_slave",
621 .id = QCS8300_SLAVE_QUP_CORE_0,
622 .channels = 1,
623 .buswidth = 4,
624 .num_links = 0,
625 };
626
627 static struct qcom_icc_node qup1_core_slave = {
628 .name = "qup1_core_slave",
629 .id = QCS8300_SLAVE_QUP_CORE_1,
630 .channels = 1,
631 .buswidth = 4,
632 .num_links = 0,
633 };
634
635 static struct qcom_icc_node qup3_core_slave = {
636 .name = "qup3_core_slave",
637 .id = QCS8300_SLAVE_QUP_CORE_3,
638 .channels = 1,
639 .buswidth = 4,
640 .num_links = 0,
641 };
642
643 static struct qcom_icc_node qhs_ahb2phy2 = {
644 .name = "qhs_ahb2phy2",
645 .id = QCS8300_SLAVE_AHB2PHY_2,
646 .channels = 1,
647 .buswidth = 4,
648 .num_links = 0,
649 };
650
651 static struct qcom_icc_node qhs_ahb2phy3 = {
652 .name = "qhs_ahb2phy3",
653 .id = QCS8300_SLAVE_AHB2PHY_3,
654 .channels = 1,
655 .buswidth = 4,
656 .num_links = 0,
657 };
658
659 static struct qcom_icc_node qhs_anoc_throttle_cfg = {
660 .name = "qhs_anoc_throttle_cfg",
661 .id = QCS8300_SLAVE_ANOC_THROTTLE_CFG,
662 .channels = 1,
663 .buswidth = 4,
664 .num_links = 0,
665 };
666
667 static struct qcom_icc_node qhs_aoss = {
668 .name = "qhs_aoss",
669 .id = QCS8300_SLAVE_AOSS,
670 .channels = 1,
671 .buswidth = 4,
672 .num_links = 0,
673 };
674
675 static struct qcom_icc_node qhs_apss = {
676 .name = "qhs_apss",
677 .id = QCS8300_SLAVE_APPSS,
678 .channels = 1,
679 .buswidth = 8,
680 .num_links = 0,
681 };
682
683 static struct qcom_icc_node qhs_boot_rom = {
684 .name = "qhs_boot_rom",
685 .id = QCS8300_SLAVE_BOOT_ROM,
686 .channels = 1,
687 .buswidth = 4,
688 .num_links = 0,
689 };
690
691 static struct qcom_icc_node qhs_camera_cfg = {
692 .name = "qhs_camera_cfg",
693 .id = QCS8300_SLAVE_CAMERA_CFG,
694 .channels = 1,
695 .buswidth = 4,
696 .num_links = 0,
697 };
698
699 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
700 .name = "qhs_camera_nrt_throttle_cfg",
701 .id = QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
702 .channels = 1,
703 .buswidth = 4,
704 .num_links = 0,
705 };
706
707 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
708 .name = "qhs_camera_rt_throttle_cfg",
709 .id = QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG,
710 .channels = 1,
711 .buswidth = 4,
712 .num_links = 0,
713 };
714
715 static struct qcom_icc_node qhs_clk_ctl = {
716 .name = "qhs_clk_ctl",
717 .id = QCS8300_SLAVE_CLK_CTL,
718 .channels = 1,
719 .buswidth = 4,
720 .num_links = 0,
721 };
722
723 static struct qcom_icc_node qhs_compute0_cfg = {
724 .name = "qhs_compute0_cfg",
725 .id = QCS8300_SLAVE_CDSP_CFG,
726 .channels = 1,
727 .buswidth = 4,
728 .num_links = 1,
729 .links = { QCS8300_MASTER_CDSP_NOC_CFG },
730 };
731
732 static struct qcom_icc_node qhs_cpr_cx = {
733 .name = "qhs_cpr_cx",
734 .id = QCS8300_SLAVE_RBCPR_CX_CFG,
735 .channels = 1,
736 .buswidth = 4,
737 .num_links = 0,
738 };
739
740 static struct qcom_icc_node qhs_cpr_mmcx = {
741 .name = "qhs_cpr_mmcx",
742 .id = QCS8300_SLAVE_RBCPR_MMCX_CFG,
743 .channels = 1,
744 .buswidth = 4,
745 .num_links = 0,
746 };
747
748 static struct qcom_icc_node qhs_cpr_mx = {
749 .name = "qhs_cpr_mx",
750 .id = QCS8300_SLAVE_RBCPR_MX_CFG,
751 .channels = 1,
752 .buswidth = 4,
753 .num_links = 0,
754 };
755
756 static struct qcom_icc_node qhs_cpr_nspcx = {
757 .name = "qhs_cpr_nspcx",
758 .id = QCS8300_SLAVE_CPR_NSPCX,
759 .channels = 1,
760 .buswidth = 4,
761 .num_links = 0,
762 };
763
764 static struct qcom_icc_node qhs_cpr_nsphmx = {
765 .name = "qhs_cpr_nsphmx",
766 .id = QCS8300_SLAVE_CPR_NSPHMX,
767 .channels = 1,
768 .buswidth = 4,
769 .num_links = 0,
770 };
771
772 static struct qcom_icc_node qhs_crypto0_cfg = {
773 .name = "qhs_crypto0_cfg",
774 .id = QCS8300_SLAVE_CRYPTO_0_CFG,
775 .channels = 1,
776 .buswidth = 4,
777 .num_links = 0,
778 };
779
780 static struct qcom_icc_node qhs_cx_rdpm = {
781 .name = "qhs_cx_rdpm",
782 .id = QCS8300_SLAVE_CX_RDPM,
783 .channels = 1,
784 .buswidth = 4,
785 .num_links = 0,
786 };
787
788 static struct qcom_icc_node qhs_display0_cfg = {
789 .name = "qhs_display0_cfg",
790 .id = QCS8300_SLAVE_DISPLAY_CFG,
791 .channels = 1,
792 .buswidth = 4,
793 .num_links = 0,
794 };
795
796 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
797 .name = "qhs_display0_rt_throttle_cfg",
798 .id = QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
799 .channels = 1,
800 .buswidth = 4,
801 .num_links = 0,
802 };
803
804 static struct qcom_icc_node qhs_emac0_cfg = {
805 .name = "qhs_emac0_cfg",
806 .id = QCS8300_SLAVE_EMAC_CFG,
807 .channels = 1,
808 .buswidth = 4,
809 .num_links = 0,
810 };
811
812 static struct qcom_icc_node qhs_gp_dsp0_cfg = {
813 .name = "qhs_gp_dsp0_cfg",
814 .id = QCS8300_SLAVE_GP_DSP0_CFG,
815 .channels = 1,
816 .buswidth = 4,
817 .num_links = 0,
818 };
819
820 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
821 .name = "qhs_gpdsp0_throttle_cfg",
822 .id = QCS8300_SLAVE_GPDSP0_THROTTLE_CFG,
823 .channels = 1,
824 .buswidth = 4,
825 .num_links = 0,
826 };
827
828 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
829 .name = "qhs_gpu_tcu_throttle_cfg",
830 .id = QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
831 .channels = 1,
832 .buswidth = 4,
833 .num_links = 0,
834 };
835
836 static struct qcom_icc_node qhs_gpuss_cfg = {
837 .name = "qhs_gpuss_cfg",
838 .id = QCS8300_SLAVE_GFX3D_CFG,
839 .channels = 1,
840 .buswidth = 8,
841 .num_links = 0,
842 };
843
844 static struct qcom_icc_node qhs_hwkm = {
845 .name = "qhs_hwkm",
846 .id = QCS8300_SLAVE_HWKM,
847 .channels = 1,
848 .buswidth = 4,
849 .num_links = 0,
850 };
851
852 static struct qcom_icc_node qhs_imem_cfg = {
853 .name = "qhs_imem_cfg",
854 .id = QCS8300_SLAVE_IMEM_CFG,
855 .channels = 1,
856 .buswidth = 4,
857 .num_links = 0,
858 };
859
860 static struct qcom_icc_node qhs_ipa = {
861 .name = "qhs_ipa",
862 .id = QCS8300_SLAVE_IPA_CFG,
863 .channels = 1,
864 .buswidth = 4,
865 .num_links = 0,
866 };
867
868 static struct qcom_icc_node qhs_ipc_router = {
869 .name = "qhs_ipc_router",
870 .id = QCS8300_SLAVE_IPC_ROUTER_CFG,
871 .channels = 1,
872 .buswidth = 4,
873 .num_links = 0,
874 };
875
876 static struct qcom_icc_node qhs_lpass_cfg = {
877 .name = "qhs_lpass_cfg",
878 .id = QCS8300_SLAVE_LPASS,
879 .channels = 1,
880 .buswidth = 4,
881 .num_links = 1,
882 .links = { QCS8300_MASTER_CNOC_LPASS_AG_NOC },
883 };
884
885 static struct qcom_icc_node qhs_lpass_throttle_cfg = {
886 .name = "qhs_lpass_throttle_cfg",
887 .id = QCS8300_SLAVE_LPASS_THROTTLE_CFG,
888 .channels = 1,
889 .buswidth = 4,
890 .num_links = 0,
891 };
892
893 static struct qcom_icc_node qhs_mx_rdpm = {
894 .name = "qhs_mx_rdpm",
895 .id = QCS8300_SLAVE_MX_RDPM,
896 .channels = 1,
897 .buswidth = 4,
898 .num_links = 0,
899 };
900
901 static struct qcom_icc_node qhs_mxc_rdpm = {
902 .name = "qhs_mxc_rdpm",
903 .id = QCS8300_SLAVE_MXC_RDPM,
904 .channels = 1,
905 .buswidth = 4,
906 .num_links = 0,
907 };
908
909 static struct qcom_icc_node qhs_pcie0_cfg = {
910 .name = "qhs_pcie0_cfg",
911 .id = QCS8300_SLAVE_PCIE_0_CFG,
912 .channels = 1,
913 .buswidth = 4,
914 .num_links = 0,
915 };
916
917 static struct qcom_icc_node qhs_pcie1_cfg = {
918 .name = "qhs_pcie1_cfg",
919 .id = QCS8300_SLAVE_PCIE_1_CFG,
920 .channels = 1,
921 .buswidth = 4,
922 .num_links = 0,
923 };
924
925 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
926 .name = "qhs_pcie_tcu_throttle_cfg",
927 .id = QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
928 .channels = 1,
929 .buswidth = 4,
930 .num_links = 0,
931 };
932
933 static struct qcom_icc_node qhs_pcie_throttle_cfg = {
934 .name = "qhs_pcie_throttle_cfg",
935 .id = QCS8300_SLAVE_PCIE_THROTTLE_CFG,
936 .channels = 1,
937 .buswidth = 4,
938 .num_links = 0,
939 };
940
941 static struct qcom_icc_node qhs_pdm = {
942 .name = "qhs_pdm",
943 .id = QCS8300_SLAVE_PDM,
944 .channels = 1,
945 .buswidth = 4,
946 .num_links = 0,
947 };
948
949 static struct qcom_icc_node qhs_pimem_cfg = {
950 .name = "qhs_pimem_cfg",
951 .id = QCS8300_SLAVE_PIMEM_CFG,
952 .channels = 1,
953 .buswidth = 4,
954 .num_links = 0,
955 };
956
957 static struct qcom_icc_node qhs_pke_wrapper_cfg = {
958 .name = "qhs_pke_wrapper_cfg",
959 .id = QCS8300_SLAVE_PKA_WRAPPER_CFG,
960 .channels = 1,
961 .buswidth = 4,
962 .num_links = 0,
963 };
964
965 static struct qcom_icc_node qhs_qdss_cfg = {
966 .name = "qhs_qdss_cfg",
967 .id = QCS8300_SLAVE_QDSS_CFG,
968 .channels = 1,
969 .buswidth = 4,
970 .num_links = 0,
971 };
972
973 static struct qcom_icc_node qhs_qm_cfg = {
974 .name = "qhs_qm_cfg",
975 .id = QCS8300_SLAVE_QM_CFG,
976 .channels = 1,
977 .buswidth = 4,
978 .num_links = 0,
979 };
980
981 static struct qcom_icc_node qhs_qm_mpu_cfg = {
982 .name = "qhs_qm_mpu_cfg",
983 .id = QCS8300_SLAVE_QM_MPU_CFG,
984 .channels = 1,
985 .buswidth = 4,
986 .num_links = 0,
987 };
988
989 static struct qcom_icc_node qhs_qup0 = {
990 .name = "qhs_qup0",
991 .id = QCS8300_SLAVE_QUP_0,
992 .channels = 1,
993 .buswidth = 4,
994 .num_links = 0,
995 };
996
997 static struct qcom_icc_node qhs_qup1 = {
998 .name = "qhs_qup1",
999 .id = QCS8300_SLAVE_QUP_1,
1000 .channels = 1,
1001 .buswidth = 4,
1002 .num_links = 0,
1003 };
1004
1005 static struct qcom_icc_node qhs_qup3 = {
1006 .name = "qhs_qup3",
1007 .id = QCS8300_SLAVE_QUP_3,
1008 .channels = 1,
1009 .buswidth = 4,
1010 .num_links = 0,
1011 };
1012
1013 static struct qcom_icc_node qhs_sail_throttle_cfg = {
1014 .name = "qhs_sail_throttle_cfg",
1015 .id = QCS8300_SLAVE_SAIL_THROTTLE_CFG,
1016 .channels = 1,
1017 .buswidth = 4,
1018 .num_links = 0,
1019 };
1020
1021 static struct qcom_icc_node qhs_sdc1 = {
1022 .name = "qhs_sdc1",
1023 .id = QCS8300_SLAVE_SDC1,
1024 .channels = 1,
1025 .buswidth = 4,
1026 .num_links = 0,
1027 };
1028
1029 static struct qcom_icc_node qhs_security = {
1030 .name = "qhs_security",
1031 .id = QCS8300_SLAVE_SECURITY,
1032 .channels = 1,
1033 .buswidth = 4,
1034 .num_links = 0,
1035 };
1036
1037 static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1038 .name = "qhs_snoc_throttle_cfg",
1039 .id = QCS8300_SLAVE_SNOC_THROTTLE_CFG,
1040 .channels = 1,
1041 .buswidth = 4,
1042 .num_links = 0,
1043 };
1044
1045 static struct qcom_icc_node qhs_tcsr = {
1046 .name = "qhs_tcsr",
1047 .id = QCS8300_SLAVE_TCSR,
1048 .channels = 1,
1049 .buswidth = 4,
1050 .num_links = 0,
1051 };
1052
1053 static struct qcom_icc_node qhs_tlmm = {
1054 .name = "qhs_tlmm",
1055 .id = QCS8300_SLAVE_TLMM,
1056 .channels = 1,
1057 .buswidth = 4,
1058 .num_links = 0,
1059 };
1060
1061 static struct qcom_icc_node qhs_tsc_cfg = {
1062 .name = "qhs_tsc_cfg",
1063 .id = QCS8300_SLAVE_TSC_CFG,
1064 .channels = 1,
1065 .buswidth = 4,
1066 .num_links = 0,
1067 };
1068
1069 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1070 .name = "qhs_ufs_mem_cfg",
1071 .id = QCS8300_SLAVE_UFS_MEM_CFG,
1072 .channels = 1,
1073 .buswidth = 4,
1074 .num_links = 0,
1075 };
1076
1077 static struct qcom_icc_node qhs_usb2_0 = {
1078 .name = "qhs_usb2_0",
1079 .id = QCS8300_SLAVE_USB2,
1080 .channels = 1,
1081 .buswidth = 4,
1082 .num_links = 0,
1083 };
1084
1085 static struct qcom_icc_node qhs_usb3_0 = {
1086 .name = "qhs_usb3_0",
1087 .id = QCS8300_SLAVE_USB3_0,
1088 .channels = 1,
1089 .buswidth = 4,
1090 .num_links = 0,
1091 };
1092
1093 static struct qcom_icc_node qhs_venus_cfg = {
1094 .name = "qhs_venus_cfg",
1095 .id = QCS8300_SLAVE_VENUS_CFG,
1096 .channels = 1,
1097 .buswidth = 4,
1098 .num_links = 0,
1099 };
1100
1101 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1102 .name = "qhs_venus_cvp_throttle_cfg",
1103 .id = QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
1104 .channels = 1,
1105 .buswidth = 4,
1106 .num_links = 0,
1107 };
1108
1109 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1110 .name = "qhs_venus_v_cpu_throttle_cfg",
1111 .id = QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
1112 .channels = 1,
1113 .buswidth = 4,
1114 .num_links = 0,
1115 };
1116
1117 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1118 .name = "qhs_venus_vcodec_throttle_cfg",
1119 .id = QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
1120 .channels = 1,
1121 .buswidth = 4,
1122 .num_links = 0,
1123 };
1124
1125 static struct qcom_icc_node qns_ddrss_cfg = {
1126 .name = "qns_ddrss_cfg",
1127 .id = QCS8300_SLAVE_DDRSS_CFG,
1128 .channels = 1,
1129 .buswidth = 4,
1130 .num_links = 1,
1131 .links = { QCS8300_MASTER_CNOC_DC_NOC },
1132 };
1133
1134 static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1135 .name = "qns_gpdsp_noc_cfg",
1136 .id = QCS8300_SLAVE_GPDSP_NOC_CFG,
1137 .channels = 1,
1138 .buswidth = 4,
1139 .num_links = 0,
1140 };
1141
1142 static struct qcom_icc_node qns_mnoc_hf_cfg = {
1143 .name = "qns_mnoc_hf_cfg",
1144 .id = QCS8300_SLAVE_CNOC_MNOC_HF_CFG,
1145 .channels = 1,
1146 .buswidth = 4,
1147 .num_links = 1,
1148 .links = { QCS8300_MASTER_CNOC_MNOC_HF_CFG },
1149 };
1150
1151 static struct qcom_icc_node qns_mnoc_sf_cfg = {
1152 .name = "qns_mnoc_sf_cfg",
1153 .id = QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
1154 .channels = 1,
1155 .buswidth = 4,
1156 .num_links = 1,
1157 .links = { QCS8300_MASTER_CNOC_MNOC_SF_CFG },
1158 };
1159
1160 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1161 .name = "qns_pcie_anoc_cfg",
1162 .id = QCS8300_SLAVE_PCIE_ANOC_CFG,
1163 .channels = 1,
1164 .buswidth = 4,
1165 .num_links = 0,
1166 };
1167
1168 static struct qcom_icc_node qns_snoc_cfg = {
1169 .name = "qns_snoc_cfg",
1170 .id = QCS8300_SLAVE_SNOC_CFG,
1171 .channels = 1,
1172 .buswidth = 4,
1173 .num_links = 1,
1174 .links = { QCS8300_MASTER_SNOC_CFG },
1175 };
1176
1177 static struct qcom_icc_node qxs_boot_imem = {
1178 .name = "qxs_boot_imem",
1179 .id = QCS8300_SLAVE_BOOT_IMEM,
1180 .channels = 1,
1181 .buswidth = 16,
1182 .num_links = 0,
1183 };
1184
1185 static struct qcom_icc_node qxs_imem = {
1186 .name = "qxs_imem",
1187 .id = QCS8300_SLAVE_IMEM,
1188 .channels = 1,
1189 .buswidth = 8,
1190 .num_links = 0,
1191 };
1192
1193 static struct qcom_icc_node qxs_pimem = {
1194 .name = "qxs_pimem",
1195 .id = QCS8300_SLAVE_PIMEM,
1196 .channels = 1,
1197 .buswidth = 8,
1198 .num_links = 0,
1199 };
1200
1201 static struct qcom_icc_node xs_pcie_0 = {
1202 .name = "xs_pcie_0",
1203 .id = QCS8300_SLAVE_PCIE_0,
1204 .channels = 1,
1205 .buswidth = 16,
1206 .num_links = 0,
1207 };
1208
1209 static struct qcom_icc_node xs_pcie_1 = {
1210 .name = "xs_pcie_1",
1211 .id = QCS8300_SLAVE_PCIE_1,
1212 .channels = 1,
1213 .buswidth = 32,
1214 .num_links = 0,
1215 };
1216
1217 static struct qcom_icc_node xs_qdss_stm = {
1218 .name = "xs_qdss_stm",
1219 .id = QCS8300_SLAVE_QDSS_STM,
1220 .channels = 1,
1221 .buswidth = 4,
1222 .num_links = 0,
1223 };
1224
1225 static struct qcom_icc_node xs_sys_tcu_cfg = {
1226 .name = "xs_sys_tcu_cfg",
1227 .id = QCS8300_SLAVE_TCU,
1228 .channels = 1,
1229 .buswidth = 8,
1230 .num_links = 0,
1231 };
1232
1233 static struct qcom_icc_node qhs_llcc = {
1234 .name = "qhs_llcc",
1235 .id = QCS8300_SLAVE_LLCC_CFG,
1236 .channels = 1,
1237 .buswidth = 4,
1238 .num_links = 0,
1239 };
1240
1241 static struct qcom_icc_node qns_gemnoc = {
1242 .name = "qns_gemnoc",
1243 .id = QCS8300_SLAVE_GEM_NOC_CFG,
1244 .channels = 1,
1245 .buswidth = 4,
1246 .num_links = 1,
1247 .links = { QCS8300_MASTER_GEM_NOC_CFG },
1248 };
1249
1250 static struct qcom_icc_node qns_gem_noc_cnoc = {
1251 .name = "qns_gem_noc_cnoc",
1252 .id = QCS8300_SLAVE_GEM_NOC_CNOC,
1253 .channels = 1,
1254 .buswidth = 16,
1255 .num_links = 1,
1256 .links = { QCS8300_MASTER_GEM_NOC_CNOC },
1257 };
1258
1259 static struct qcom_icc_node qns_llcc = {
1260 .name = "qns_llcc",
1261 .id = QCS8300_SLAVE_LLCC,
1262 .channels = 4,
1263 .buswidth = 16,
1264 .num_links = 1,
1265 .links = { QCS8300_MASTER_LLCC },
1266 };
1267
1268 static struct qcom_icc_node qns_pcie = {
1269 .name = "qns_pcie",
1270 .id = QCS8300_SLAVE_GEM_NOC_PCIE_CNOC,
1271 .channels = 1,
1272 .buswidth = 16,
1273 .num_links = 1,
1274 .links = { QCS8300_MASTER_GEM_NOC_PCIE_SNOC },
1275 };
1276
1277 static struct qcom_icc_node srvc_even_gemnoc = {
1278 .name = "srvc_even_gemnoc",
1279 .id = QCS8300_SLAVE_SERVICE_GEM_NOC_1,
1280 .channels = 1,
1281 .buswidth = 4,
1282 .num_links = 0,
1283 };
1284
1285 static struct qcom_icc_node srvc_odd_gemnoc = {
1286 .name = "srvc_odd_gemnoc",
1287 .id = QCS8300_SLAVE_SERVICE_GEM_NOC_2,
1288 .channels = 1,
1289 .buswidth = 4,
1290 .num_links = 0,
1291 };
1292
1293 static struct qcom_icc_node srvc_sys_gemnoc = {
1294 .name = "srvc_sys_gemnoc",
1295 .id = QCS8300_SLAVE_SERVICE_GEM_NOC,
1296 .channels = 1,
1297 .buswidth = 4,
1298 .num_links = 0,
1299 };
1300
1301 static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1302 .name = "srvc_sys_gemnoc_2",
1303 .id = QCS8300_SLAVE_SERVICE_GEM_NOC2,
1304 .channels = 1,
1305 .buswidth = 4,
1306 .num_links = 0,
1307 };
1308
1309 static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1310 .name = "qns_gp_dsp_sail_noc",
1311 .id = QCS8300_SLAVE_GP_DSP_SAIL_NOC,
1312 .channels = 1,
1313 .buswidth = 16,
1314 .num_links = 1,
1315 .links = { QCS8300_MASTER_GPDSP_SAIL },
1316 };
1317
1318 static struct qcom_icc_node qhs_lpass_core = {
1319 .name = "qhs_lpass_core",
1320 .id = QCS8300_SLAVE_LPASS_CORE_CFG,
1321 .channels = 1,
1322 .buswidth = 4,
1323 .num_links = 0,
1324 };
1325
1326 static struct qcom_icc_node qhs_lpass_lpi = {
1327 .name = "qhs_lpass_lpi",
1328 .id = QCS8300_SLAVE_LPASS_LPI_CFG,
1329 .channels = 1,
1330 .buswidth = 4,
1331 .num_links = 0,
1332 };
1333
1334 static struct qcom_icc_node qhs_lpass_mpu = {
1335 .name = "qhs_lpass_mpu",
1336 .id = QCS8300_SLAVE_LPASS_MPU_CFG,
1337 .channels = 1,
1338 .buswidth = 4,
1339 .num_links = 0,
1340 };
1341
1342 static struct qcom_icc_node qhs_lpass_top = {
1343 .name = "qhs_lpass_top",
1344 .id = QCS8300_SLAVE_LPASS_TOP_CFG,
1345 .channels = 1,
1346 .buswidth = 4,
1347 .num_links = 0,
1348 };
1349
1350 static struct qcom_icc_node qns_sysnoc = {
1351 .name = "qns_sysnoc",
1352 .id = QCS8300_SLAVE_LPASS_SNOC,
1353 .channels = 1,
1354 .buswidth = 16,
1355 .num_links = 1,
1356 .links = { QCS8300_MASTER_LPASS_ANOC },
1357 };
1358
1359 static struct qcom_icc_node srvc_niu_aml_noc = {
1360 .name = "srvc_niu_aml_noc",
1361 .id = QCS8300_SLAVE_SERVICES_LPASS_AML_NOC,
1362 .channels = 1,
1363 .buswidth = 4,
1364 .num_links = 0,
1365 };
1366
1367 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1368 .name = "srvc_niu_lpass_agnoc",
1369 .id = QCS8300_SLAVE_SERVICE_LPASS_AG_NOC,
1370 .channels = 1,
1371 .buswidth = 4,
1372 .num_links = 0,
1373 };
1374
1375 static struct qcom_icc_node ebi = {
1376 .name = "ebi",
1377 .id = QCS8300_SLAVE_EBI1,
1378 .channels = 8,
1379 .buswidth = 4,
1380 .num_links = 0,
1381 };
1382
1383 static struct qcom_icc_node qns_mem_noc_hf = {
1384 .name = "qns_mem_noc_hf",
1385 .id = QCS8300_SLAVE_MNOC_HF_MEM_NOC,
1386 .channels = 2,
1387 .buswidth = 32,
1388 .num_links = 1,
1389 .links = { QCS8300_MASTER_MNOC_HF_MEM_NOC },
1390 };
1391
1392 static struct qcom_icc_node qns_mem_noc_sf = {
1393 .name = "qns_mem_noc_sf",
1394 .id = QCS8300_SLAVE_MNOC_SF_MEM_NOC,
1395 .channels = 2,
1396 .buswidth = 32,
1397 .num_links = 1,
1398 .links = { QCS8300_MASTER_MNOC_SF_MEM_NOC },
1399 };
1400
1401 static struct qcom_icc_node srvc_mnoc_hf = {
1402 .name = "srvc_mnoc_hf",
1403 .id = QCS8300_SLAVE_SERVICE_MNOC_HF,
1404 .channels = 1,
1405 .buswidth = 4,
1406 .num_links = 0,
1407 };
1408
1409 static struct qcom_icc_node srvc_mnoc_sf = {
1410 .name = "srvc_mnoc_sf",
1411 .id = QCS8300_SLAVE_SERVICE_MNOC_SF,
1412 .channels = 1,
1413 .buswidth = 4,
1414 .num_links = 0,
1415 };
1416
1417 static struct qcom_icc_node qns_hcp = {
1418 .name = "qns_hcp",
1419 .id = QCS8300_SLAVE_HCP_A,
1420 .channels = 2,
1421 .buswidth = 32,
1422 .num_links = 0,
1423 };
1424
1425 static struct qcom_icc_node qns_nsp_gemnoc = {
1426 .name = "qns_nsp_gemnoc",
1427 .id = QCS8300_SLAVE_CDSP_MEM_NOC,
1428 .channels = 2,
1429 .buswidth = 32,
1430 .num_links = 1,
1431 .links = { QCS8300_MASTER_COMPUTE_NOC },
1432 };
1433
1434 static struct qcom_icc_node service_nsp_noc = {
1435 .name = "service_nsp_noc",
1436 .id = QCS8300_SLAVE_SERVICE_NSP_NOC,
1437 .channels = 1,
1438 .buswidth = 4,
1439 .num_links = 0,
1440 };
1441
1442 static struct qcom_icc_node qns_pcie_mem_noc = {
1443 .name = "qns_pcie_mem_noc",
1444 .id = QCS8300_SLAVE_ANOC_PCIE_GEM_NOC,
1445 .channels = 1,
1446 .buswidth = 32,
1447 .num_links = 1,
1448 .links = { QCS8300_MASTER_ANOC_PCIE_GEM_NOC },
1449 };
1450
1451 static struct qcom_icc_node qns_gemnoc_gc = {
1452 .name = "qns_gemnoc_gc",
1453 .id = QCS8300_SLAVE_SNOC_GEM_NOC_GC,
1454 .channels = 1,
1455 .buswidth = 8,
1456 .num_links = 1,
1457 .links = { QCS8300_MASTER_SNOC_GC_MEM_NOC },
1458 };
1459
1460 static struct qcom_icc_node qns_gemnoc_sf = {
1461 .name = "qns_gemnoc_sf",
1462 .id = QCS8300_SLAVE_SNOC_GEM_NOC_SF,
1463 .channels = 1,
1464 .buswidth = 16,
1465 .num_links = 1,
1466 .links = { QCS8300_MASTER_SNOC_SF_MEM_NOC },
1467 };
1468
1469 static struct qcom_icc_node srvc_snoc = {
1470 .name = "srvc_snoc",
1471 .id = QCS8300_SLAVE_SERVICE_SNOC,
1472 .channels = 1,
1473 .buswidth = 4,
1474 .num_links = 0,
1475 };
1476
1477 static struct qcom_icc_bcm bcm_acv = {
1478 .name = "ACV",
1479 .enable_mask = BIT(3),
1480 .num_nodes = 1,
1481 .nodes = { &ebi },
1482 };
1483
1484 static struct qcom_icc_bcm bcm_ce0 = {
1485 .name = "CE0",
1486 .num_nodes = 2,
1487 .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1488 };
1489
1490 static struct qcom_icc_bcm bcm_cn0 = {
1491 .name = "CN0",
1492 .keepalive = true,
1493 .num_nodes = 2,
1494 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1495 };
1496
1497 static struct qcom_icc_bcm bcm_cn1 = {
1498 .name = "CN1",
1499 .num_nodes = 66,
1500 .nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
1501 &qhs_anoc_throttle_cfg, &qhs_aoss,
1502 &qhs_apss, &qhs_boot_rom,
1503 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1504 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1505 &qhs_compute0_cfg, &qhs_cpr_cx,
1506 &qhs_cpr_mmcx, &qhs_cpr_mx,
1507 &qhs_cpr_nspcx, &qhs_cpr_nsphmx,
1508 &qhs_crypto0_cfg, &qhs_cx_rdpm,
1509 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1510 &qhs_emac0_cfg, &qhs_gp_dsp0_cfg,
1511 &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg,
1512 &qhs_gpuss_cfg, &qhs_hwkm,
1513 &qhs_imem_cfg, &qhs_ipa,
1514 &qhs_ipc_router, &qhs_lpass_cfg,
1515 &qhs_lpass_throttle_cfg, &qhs_mx_rdpm,
1516 &qhs_mxc_rdpm, &qhs_pcie0_cfg,
1517 &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg,
1518 &qhs_pcie_throttle_cfg, &qhs_pdm,
1519 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1520 &qhs_qdss_cfg, &qhs_qm_cfg,
1521 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1522 &qhs_sdc1, &qhs_security,
1523 &qhs_snoc_throttle_cfg, &qhs_tcsr,
1524 &qhs_tlmm, &qhs_tsc_cfg,
1525 &qhs_ufs_mem_cfg, &qhs_usb2_0,
1526 &qhs_usb3_0, &qhs_venus_cfg,
1527 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1528 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1529 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1530 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1531 &qns_snoc_cfg, &qxs_boot_imem,
1532 &qxs_imem, &xs_sys_tcu_cfg },
1533 };
1534
1535 static struct qcom_icc_bcm bcm_cn2 = {
1536 .name = "CN2",
1537 .num_nodes = 3,
1538 .nodes = { &qhs_qup0, &qhs_qup1,
1539 &qhs_qup3 },
1540 };
1541
1542 static struct qcom_icc_bcm bcm_cn3 = {
1543 .name = "CN3",
1544 .num_nodes = 2,
1545 .nodes = { &xs_pcie_0, &xs_pcie_1 },
1546 };
1547
1548 static struct qcom_icc_bcm bcm_gna0 = {
1549 .name = "GNA0",
1550 .num_nodes = 1,
1551 .nodes = { &qxm_dsp0 },
1552 };
1553
1554 static struct qcom_icc_bcm bcm_mc0 = {
1555 .name = "MC0",
1556 .keepalive = true,
1557 .num_nodes = 1,
1558 .nodes = { &ebi },
1559 };
1560
1561 static struct qcom_icc_bcm bcm_mm0 = {
1562 .name = "MM0",
1563 .keepalive = true,
1564 .num_nodes = 4,
1565 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1566 &qnm_mdp0_1, &qns_mem_noc_hf },
1567 };
1568
1569 static struct qcom_icc_bcm bcm_mm1 = {
1570 .name = "MM1",
1571 .num_nodes = 6,
1572 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1573 &qnm_video0, &qnm_video_cvp,
1574 &qnm_video_v_cpu, &qns_mem_noc_sf },
1575 };
1576
1577 static struct qcom_icc_bcm bcm_nsa0 = {
1578 .name = "NSA0",
1579 .num_nodes = 2,
1580 .nodes = { &qns_hcp, &qns_nsp_gemnoc },
1581 };
1582
1583 static struct qcom_icc_bcm bcm_nsa1 = {
1584 .name = "NSA1",
1585 .num_nodes = 1,
1586 .nodes = { &qxm_nsp },
1587 };
1588
1589 static struct qcom_icc_bcm bcm_pci0 = {
1590 .name = "PCI0",
1591 .num_nodes = 1,
1592 .nodes = { &qns_pcie_mem_noc },
1593 };
1594
1595 static struct qcom_icc_bcm bcm_qup0 = {
1596 .name = "QUP0",
1597 .vote_scale = 1,
1598 .keepalive = true,
1599 .num_nodes = 1,
1600 .nodes = { &qup0_core_slave },
1601 };
1602
1603 static struct qcom_icc_bcm bcm_qup1 = {
1604 .name = "QUP1",
1605 .vote_scale = 1,
1606 .keepalive = true,
1607 .num_nodes = 1,
1608 .nodes = { &qup1_core_slave },
1609 };
1610
1611 static struct qcom_icc_bcm bcm_qup2 = {
1612 .name = "QUP2",
1613 .vote_scale = 1,
1614 .keepalive = true,
1615 .num_nodes = 1,
1616 .nodes = { &qup3_core_slave },
1617 };
1618
1619 static struct qcom_icc_bcm bcm_sh0 = {
1620 .name = "SH0",
1621 .keepalive = true,
1622 .num_nodes = 1,
1623 .nodes = { &qns_llcc },
1624 };
1625
1626 static struct qcom_icc_bcm bcm_sh2 = {
1627 .name = "SH2",
1628 .num_nodes = 1,
1629 .nodes = { &chm_apps },
1630 };
1631
1632 static struct qcom_icc_bcm bcm_sn0 = {
1633 .name = "SN0",
1634 .keepalive = true,
1635 .num_nodes = 1,
1636 .nodes = { &qns_gemnoc_sf },
1637 };
1638
1639 static struct qcom_icc_bcm bcm_sn1 = {
1640 .name = "SN1",
1641 .num_nodes = 1,
1642 .nodes = { &qns_gemnoc_gc },
1643 };
1644
1645 static struct qcom_icc_bcm bcm_sn2 = {
1646 .name = "SN2",
1647 .num_nodes = 1,
1648 .nodes = { &qxs_pimem },
1649 };
1650
1651 static struct qcom_icc_bcm bcm_sn3 = {
1652 .name = "SN3",
1653 .num_nodes = 2,
1654 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
1655 };
1656
1657 static struct qcom_icc_bcm bcm_sn4 = {
1658 .name = "SN4",
1659 .num_nodes = 2,
1660 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
1661 };
1662
1663 static struct qcom_icc_bcm bcm_sn9 = {
1664 .name = "SN9",
1665 .num_nodes = 2,
1666 .nodes = { &qns_sysnoc, &qnm_lpass_noc },
1667 };
1668
1669 static struct qcom_icc_bcm bcm_sn10 = {
1670 .name = "SN10",
1671 .num_nodes = 1,
1672 .nodes = { &xs_qdss_stm },
1673 };
1674
1675 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1676 &bcm_sn3,
1677 };
1678
1679 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1680 [MASTER_QUP_3] = &qxm_qup3,
1681 [MASTER_EMAC] = &xm_emac_0,
1682 [MASTER_SDC] = &xm_sdc1,
1683 [MASTER_UFS_MEM] = &xm_ufs_mem,
1684 [MASTER_USB2] = &xm_usb2_2,
1685 [MASTER_USB3_0] = &xm_usb3_0,
1686 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1687 };
1688
1689 static const struct qcom_icc_desc qcs8300_aggre1_noc = {
1690 .nodes = aggre1_noc_nodes,
1691 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1692 .bcms = aggre1_noc_bcms,
1693 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1694 };
1695
1696 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1697 &bcm_ce0,
1698 &bcm_sn4,
1699 };
1700
1701 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1702 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1703 [MASTER_QUP_0] = &qhm_qup0,
1704 [MASTER_QUP_1] = &qhm_qup1,
1705 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1706 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
1707 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
1708 [MASTER_IPA] = &qxm_ipa,
1709 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
1710 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1711 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1712 };
1713
1714 static const struct qcom_icc_desc qcs8300_aggre2_noc = {
1715 .nodes = aggre2_noc_nodes,
1716 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1717 .bcms = aggre2_noc_bcms,
1718 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1719 };
1720
1721 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1722 &bcm_qup0,
1723 &bcm_qup1,
1724 &bcm_qup2,
1725 };
1726
1727 static struct qcom_icc_node * const clk_virt_nodes[] = {
1728 [MASTER_QUP_CORE_0] = &qup0_core_master,
1729 [MASTER_QUP_CORE_1] = &qup1_core_master,
1730 [MASTER_QUP_CORE_3] = &qup3_core_master,
1731 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1732 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1733 [SLAVE_QUP_CORE_3] = &qup3_core_slave,
1734 };
1735
1736 static const struct qcom_icc_desc qcs8300_clk_virt = {
1737 .nodes = clk_virt_nodes,
1738 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1739 .bcms = clk_virt_bcms,
1740 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1741 };
1742
1743 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1744 &bcm_cn0,
1745 &bcm_cn1,
1746 &bcm_cn2,
1747 &bcm_cn3,
1748 &bcm_sn2,
1749 &bcm_sn10,
1750 };
1751
1752 static struct qcom_icc_node * const config_noc_nodes[] = {
1753 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1754 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1755 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1756 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
1757 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
1758 [SLAVE_AOSS] = &qhs_aoss,
1759 [SLAVE_APPSS] = &qhs_apss,
1760 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1761 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1762 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1763 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1764 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1765 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
1766 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1767 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1768 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1769 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1770 [SLAVE_CPR_NSPHMX] = &qhs_cpr_nsphmx,
1771 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1772 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1773 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
1774 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
1775 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
1776 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
1777 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
1778 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
1779 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1780 [SLAVE_HWKM] = &qhs_hwkm,
1781 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1782 [SLAVE_IPA_CFG] = &qhs_ipa,
1783 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1784 [SLAVE_LPASS] = &qhs_lpass_cfg,
1785 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
1786 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1787 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
1788 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1789 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1790 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
1791 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
1792 [SLAVE_PDM] = &qhs_pdm,
1793 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1794 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
1795 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1796 [SLAVE_QM_CFG] = &qhs_qm_cfg,
1797 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1798 [SLAVE_QUP_0] = &qhs_qup0,
1799 [SLAVE_QUP_1] = &qhs_qup1,
1800 [SLAVE_QUP_3] = &qhs_qup3,
1801 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
1802 [SLAVE_SDC1] = &qhs_sdc1,
1803 [SLAVE_SECURITY] = &qhs_security,
1804 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
1805 [SLAVE_TCSR] = &qhs_tcsr,
1806 [SLAVE_TLMM] = &qhs_tlmm,
1807 [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
1808 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1809 [SLAVE_USB2] = &qhs_usb2_0,
1810 [SLAVE_USB3_0] = &qhs_usb3_0,
1811 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1812 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
1813 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
1814 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
1815 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1816 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
1817 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
1818 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
1819 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1820 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1821 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1822 [SLAVE_IMEM] = &qxs_imem,
1823 [SLAVE_PIMEM] = &qxs_pimem,
1824 [SLAVE_PCIE_0] = &xs_pcie_0,
1825 [SLAVE_PCIE_1] = &xs_pcie_1,
1826 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1827 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1828 };
1829
1830 static const struct qcom_icc_desc qcs8300_config_noc = {
1831 .nodes = config_noc_nodes,
1832 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1833 .bcms = config_noc_bcms,
1834 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1835 };
1836
1837 static struct qcom_icc_node * const dc_noc_nodes[] = {
1838 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1839 [SLAVE_LLCC_CFG] = &qhs_llcc,
1840 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1841 };
1842
1843 static const struct qcom_icc_desc qcs8300_dc_noc = {
1844 .nodes = dc_noc_nodes,
1845 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1846 };
1847
1848 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1849 &bcm_sh0,
1850 &bcm_sh2,
1851 };
1852
1853 static struct qcom_icc_node * const gem_noc_nodes[] = {
1854 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1855 [MASTER_PCIE_TCU] = &alm_pcie_tcu,
1856 [MASTER_SYS_TCU] = &alm_sys_tcu,
1857 [MASTER_APPSS_PROC] = &chm_apps,
1858 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
1859 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1860 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
1861 [MASTER_GFX3D] = &qnm_gpu,
1862 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1863 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1864 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1865 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1866 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1867 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1868 [SLAVE_LLCC] = &qns_llcc,
1869 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
1870 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1871 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1872 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1873 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
1874 };
1875
1876 static const struct qcom_icc_desc qcs8300_gem_noc = {
1877 .nodes = gem_noc_nodes,
1878 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1879 .bcms = gem_noc_bcms,
1880 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1881 };
1882
1883 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
1884 &bcm_gna0,
1885 };
1886
1887 static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
1888 [MASTER_SAILSS_MD0] = &qnm_sailss_md0,
1889 [MASTER_DSP0] = &qxm_dsp0,
1890 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
1891 };
1892
1893 static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
1894 .nodes = gpdsp_anoc_nodes,
1895 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
1896 .bcms = gpdsp_anoc_bcms,
1897 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
1898 };
1899
1900 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1901 &bcm_sn9,
1902 };
1903
1904 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1905 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1906 [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1907 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1908 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1909 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1910 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1911 [SLAVE_LPASS_SNOC] = &qns_sysnoc,
1912 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1913 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1914 };
1915
1916 static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
1917 .nodes = lpass_ag_noc_nodes,
1918 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1919 .bcms = lpass_ag_noc_bcms,
1920 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1921 };
1922
1923 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1924 &bcm_acv,
1925 &bcm_mc0,
1926 };
1927
1928 static struct qcom_icc_node * const mc_virt_nodes[] = {
1929 [MASTER_LLCC] = &llcc_mc,
1930 [SLAVE_EBI1] = &ebi,
1931 };
1932
1933 static const struct qcom_icc_desc qcs8300_mc_virt = {
1934 .nodes = mc_virt_nodes,
1935 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1936 .bcms = mc_virt_bcms,
1937 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1938 };
1939
1940 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1941 &bcm_mm0,
1942 &bcm_mm1,
1943 };
1944
1945 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1946 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1947 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1948 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1949 [MASTER_MDP0] = &qnm_mdp0_0,
1950 [MASTER_MDP1] = &qnm_mdp0_1,
1951 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
1952 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
1953 [MASTER_VIDEO_P0] = &qnm_video0,
1954 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1955 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1956 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1957 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1958 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
1959 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
1960 };
1961
1962 static const struct qcom_icc_desc qcs8300_mmss_noc = {
1963 .nodes = mmss_noc_nodes,
1964 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1965 .bcms = mmss_noc_bcms,
1966 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1967 };
1968
1969 static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
1970 &bcm_nsa0,
1971 &bcm_nsa1,
1972 };
1973
1974 static struct qcom_icc_node * const nspa_noc_nodes[] = {
1975 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1976 [MASTER_CDSP_PROC] = &qxm_nsp,
1977 [SLAVE_HCP_A] = &qns_hcp,
1978 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1979 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1980 };
1981
1982 static const struct qcom_icc_desc qcs8300_nspa_noc = {
1983 .nodes = nspa_noc_nodes,
1984 .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
1985 .bcms = nspa_noc_bcms,
1986 .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
1987 };
1988
1989 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1990 &bcm_pci0,
1991 };
1992
1993 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1994 [MASTER_PCIE_0] = &xm_pcie3_0,
1995 [MASTER_PCIE_1] = &xm_pcie3_1,
1996 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1997 };
1998
1999 static const struct qcom_icc_desc qcs8300_pcie_anoc = {
2000 .nodes = pcie_anoc_nodes,
2001 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2002 .bcms = pcie_anoc_bcms,
2003 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2004 };
2005
2006 static struct qcom_icc_bcm * const system_noc_bcms[] = {
2007 &bcm_sn0,
2008 &bcm_sn1,
2009 &bcm_sn3,
2010 &bcm_sn4,
2011 &bcm_sn9,
2012 };
2013
2014 static struct qcom_icc_node * const system_noc_nodes[] = {
2015 [MASTER_GIC_AHB] = &qhm_gic,
2016 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2017 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2018 [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2019 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2020 [MASTER_PIMEM] = &qxm_pimem,
2021 [MASTER_GIC] = &xm_gic,
2022 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2023 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2024 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2025 };
2026
2027 static const struct qcom_icc_desc qcs8300_system_noc = {
2028 .nodes = system_noc_nodes,
2029 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2030 .bcms = system_noc_bcms,
2031 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2032 };
2033
2034 static const struct of_device_id qnoc_of_match[] = {
2035 { .compatible = "qcom,qcs8300-aggre1-noc",
2036 .data = &qcs8300_aggre1_noc},
2037 { .compatible = "qcom,qcs8300-aggre2-noc",
2038 .data = &qcs8300_aggre2_noc},
2039 { .compatible = "qcom,qcs8300-clk-virt",
2040 .data = &qcs8300_clk_virt},
2041 { .compatible = "qcom,qcs8300-config-noc",
2042 .data = &qcs8300_config_noc},
2043 { .compatible = "qcom,qcs8300-dc-noc",
2044 .data = &qcs8300_dc_noc},
2045 { .compatible = "qcom,qcs8300-gem-noc",
2046 .data = &qcs8300_gem_noc},
2047 { .compatible = "qcom,qcs8300-gpdsp-anoc",
2048 .data = &qcs8300_gpdsp_anoc},
2049 { .compatible = "qcom,qcs8300-lpass-ag-noc",
2050 .data = &qcs8300_lpass_ag_noc},
2051 { .compatible = "qcom,qcs8300-mc-virt",
2052 .data = &qcs8300_mc_virt},
2053 { .compatible = "qcom,qcs8300-mmss-noc",
2054 .data = &qcs8300_mmss_noc},
2055 { .compatible = "qcom,qcs8300-nspa-noc",
2056 .data = &qcs8300_nspa_noc},
2057 { .compatible = "qcom,qcs8300-pcie-anoc",
2058 .data = &qcs8300_pcie_anoc},
2059 { .compatible = "qcom,qcs8300-system-noc",
2060 .data = &qcs8300_system_noc},
2061 { }
2062 };
2063 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2064
2065 static struct platform_driver qnoc_driver = {
2066 .probe = qcom_icc_rpmh_probe,
2067 .remove = qcom_icc_rpmh_remove,
2068 .driver = {
2069 .name = "qnoc-qcs8300",
2070 .of_match_table = qnoc_of_match,
2071 .sync_state = icc_sync_state,
2072 },
2073 };
2074
qnoc_driver_init(void)2075 static int __init qnoc_driver_init(void)
2076 {
2077 return platform_driver_register(&qnoc_driver);
2078 }
2079 core_initcall(qnoc_driver_init);
2080
qnoc_driver_exit(void)2081 static void __exit qnoc_driver_exit(void)
2082 {
2083 platform_driver_unregister(&qnoc_driver);
2084 }
2085 module_exit(qnoc_driver_exit);
2086
2087 MODULE_DESCRIPTION("QCS8300 NoC driver");
2088 MODULE_LICENSE("GPL");
2089