1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <[email protected]>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/nvmem-consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24
25 #define MESON_SAR_ADC_REG0 0x00
26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
46
47 #define MESON_SAR_ADC_CHAN_LIST 0x04
48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
50 (GENMASK(2, 0) << ((_chan) * 3))
51
52 #define MESON_SAR_ADC_AVG_CNTL 0x08
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
60 (GENMASK(1, 0) << ((_chan) * 2))
61
62 #define MESON_SAR_ADC_REG3 0x0c
63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
77
78 #define MESON_SAR_ADC_DELAY 0x10
79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
85
86 #define MESON_SAR_ADC_LAST_RD 0x14
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
89
90 #define MESON_SAR_ADC_FIFO_RD 0x18
91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
93
94 #define MESON_SAR_ADC_AUX_SW 0x1c
95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
96 (8 + (((_chan) - 2) * 3))
97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
104
105 #define MESON_SAR_ADC_CHAN_10_SW 0x20
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
122
123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
141
142 #define MESON_SAR_ADC_DELTA_10 0x28
143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
150
151 /*
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
155 */
156 #define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
158 #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6)
159 #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
160 #define MESON_SAR_ADC_REG11_EOC BIT(1)
161 #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
162
163 #define MESON_SAR_ADC_REG13 0x34
164 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
165
166 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
167 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
168 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
169 #define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL 7
170 #define MESON_SAR_ADC_TEMP_OFFSET 27
171
172 /* temperature sensor calibration information in eFuse */
173 #define MESON_SAR_ADC_EFUSE_BYTES 4
174 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
175 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
176
177 #define MESON_HHI_DPLL_TOP_0 0x318
178 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
179
180 /* for use with IIO_VAL_INT_PLUS_MICRO */
181 #define MILLION 1000000
182
183 #define MESON_SAR_ADC_CHAN(_chan) { \
184 .type = IIO_VOLTAGE, \
185 .indexed = 1, \
186 .channel = _chan, \
187 .address = _chan, \
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
189 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
190 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
191 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
192 BIT(IIO_CHAN_INFO_CALIBSCALE), \
193 .datasheet_name = "SAR_ADC_CH"#_chan, \
194 }
195
196 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
197 .type = IIO_TEMP, \
198 .channel = _chan, \
199 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
200 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
201 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
202 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
203 BIT(IIO_CHAN_INFO_SCALE), \
204 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
205 BIT(IIO_CHAN_INFO_CALIBSCALE), \
206 .datasheet_name = "TEMP_SENSOR", \
207 }
208
209 #define MESON_SAR_ADC_MUX(_chan, _sel) { \
210 .type = IIO_VOLTAGE, \
211 .channel = _chan, \
212 .indexed = 1, \
213 .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL, \
214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
215 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
217 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
218 BIT(IIO_CHAN_INFO_CALIBSCALE), \
219 .datasheet_name = "SAR_ADC_MUX_"#_sel, \
220 }
221
222 enum meson_sar_adc_vref_sel {
223 VREF_CALIBATION_VOLTAGE = 0,
224 VREF_VDDA = 1,
225 };
226
227 enum meson_sar_adc_avg_mode {
228 NO_AVERAGING = 0x0,
229 MEAN_AVERAGING = 0x1,
230 MEDIAN_AVERAGING = 0x2,
231 };
232
233 enum meson_sar_adc_num_samples {
234 ONE_SAMPLE = 0x0,
235 TWO_SAMPLES = 0x1,
236 FOUR_SAMPLES = 0x2,
237 EIGHT_SAMPLES = 0x3,
238 };
239
240 enum meson_sar_adc_chan7_mux_sel {
241 CHAN7_MUX_VSS = 0x0,
242 CHAN7_MUX_VDD_DIV4 = 0x1,
243 CHAN7_MUX_VDD_DIV2 = 0x2,
244 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
245 CHAN7_MUX_VDD = 0x4,
246 CHAN7_MUX_CH7_INPUT = 0x7,
247 };
248
249 enum meson_sar_adc_channel_index {
250 NUM_CHAN_0,
251 NUM_CHAN_1,
252 NUM_CHAN_2,
253 NUM_CHAN_3,
254 NUM_CHAN_4,
255 NUM_CHAN_5,
256 NUM_CHAN_6,
257 NUM_CHAN_7,
258 NUM_CHAN_TEMP,
259 NUM_MUX_0_VSS,
260 NUM_MUX_1_VDD_DIV4,
261 NUM_MUX_2_VDD_DIV2,
262 NUM_MUX_3_VDD_MUL3_DIV4,
263 NUM_MUX_4_VDD,
264 };
265
266 static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = {
267 CHAN7_MUX_VSS,
268 CHAN7_MUX_VDD_DIV4,
269 CHAN7_MUX_VDD_DIV2,
270 CHAN7_MUX_VDD_MUL3_DIV4,
271 CHAN7_MUX_VDD,
272 };
273
274 static const char * const chan7_mux_names[] = {
275 [CHAN7_MUX_VSS] = "gnd",
276 [CHAN7_MUX_VDD_DIV4] = "0.25vdd",
277 [CHAN7_MUX_VDD_DIV2] = "0.5vdd",
278 [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd",
279 [CHAN7_MUX_VDD] = "vdd",
280 };
281
282 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
283 MESON_SAR_ADC_CHAN(NUM_CHAN_0),
284 MESON_SAR_ADC_CHAN(NUM_CHAN_1),
285 MESON_SAR_ADC_CHAN(NUM_CHAN_2),
286 MESON_SAR_ADC_CHAN(NUM_CHAN_3),
287 MESON_SAR_ADC_CHAN(NUM_CHAN_4),
288 MESON_SAR_ADC_CHAN(NUM_CHAN_5),
289 MESON_SAR_ADC_CHAN(NUM_CHAN_6),
290 MESON_SAR_ADC_CHAN(NUM_CHAN_7),
291 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
292 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
293 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
294 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
295 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
296 };
297
298 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
299 MESON_SAR_ADC_CHAN(NUM_CHAN_0),
300 MESON_SAR_ADC_CHAN(NUM_CHAN_1),
301 MESON_SAR_ADC_CHAN(NUM_CHAN_2),
302 MESON_SAR_ADC_CHAN(NUM_CHAN_3),
303 MESON_SAR_ADC_CHAN(NUM_CHAN_4),
304 MESON_SAR_ADC_CHAN(NUM_CHAN_5),
305 MESON_SAR_ADC_CHAN(NUM_CHAN_6),
306 MESON_SAR_ADC_CHAN(NUM_CHAN_7),
307 MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP),
308 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
309 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
310 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
311 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
312 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
313 };
314
315 struct meson_sar_adc_param {
316 bool has_bl30_integration;
317 unsigned long clock_rate;
318 unsigned int resolution;
319 const struct regmap_config *regmap_config;
320 u8 temperature_trimming_bits;
321 unsigned int temperature_multiplier;
322 unsigned int temperature_divider;
323 u8 disable_ring_counter;
324 bool has_vref_select;
325 u8 vref_select;
326 u8 cmv_select;
327 u8 adc_eoc;
328 enum meson_sar_adc_vref_sel vref_voltage;
329 };
330
331 struct meson_sar_adc_data {
332 const struct meson_sar_adc_param *param;
333 const char *name;
334 };
335
336 struct meson_sar_adc_priv {
337 struct regmap *regmap;
338 struct regulator *vref;
339 const struct meson_sar_adc_param *param;
340 struct clk *clkin;
341 struct clk *core_clk;
342 struct clk *adc_sel_clk;
343 struct clk *adc_clk;
344 struct clk_gate clk_gate;
345 struct clk *adc_div_clk;
346 struct clk_divider clk_div;
347 struct completion done;
348 /* lock to protect against multiple access to the device */
349 struct mutex lock;
350 int calibbias;
351 int calibscale;
352 struct regmap *tsc_regmap;
353 bool temperature_sensor_calibrated;
354 u8 temperature_sensor_coefficient;
355 u16 temperature_sensor_adc_val;
356 enum meson_sar_adc_chan7_mux_sel chan7_mux_sel;
357 };
358
359 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
360 .reg_bits = 8,
361 .val_bits = 32,
362 .reg_stride = 4,
363 .max_register = MESON_SAR_ADC_REG13,
364 };
365
366 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
367 .reg_bits = 8,
368 .val_bits = 32,
369 .reg_stride = 4,
370 .max_register = MESON_SAR_ADC_DELTA_10,
371 };
372
373 static const struct iio_chan_spec *
find_channel_by_num(struct iio_dev * indio_dev,int num)374 find_channel_by_num(struct iio_dev *indio_dev, int num)
375 {
376 int i;
377
378 for (i = 0; i < indio_dev->num_channels; i++)
379 if (indio_dev->channels[i].channel == num)
380 return &indio_dev->channels[i];
381 return NULL;
382 }
383
meson_sar_adc_get_fifo_count(struct iio_dev * indio_dev)384 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
385 {
386 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
387 u32 regval;
388
389 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
390
391 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
392 }
393
meson_sar_adc_calib_val(struct iio_dev * indio_dev,int val)394 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
395 {
396 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
397 int tmp;
398
399 /* use val_calib = scale * val_raw + offset calibration function */
400 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
401
402 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
403 }
404
meson_sar_adc_wait_busy_clear(struct iio_dev * indio_dev)405 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
406 {
407 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
408 int val;
409
410 /*
411 * NOTE: we need a small delay before reading the status, otherwise
412 * the sample engine may not have started internally (which would
413 * seem to us that sampling is already finished).
414 */
415 udelay(1);
416 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
417 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
418 1, 10000);
419 }
420
meson_sar_adc_set_chan7_mux(struct iio_dev * indio_dev,enum meson_sar_adc_chan7_mux_sel sel)421 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
422 enum meson_sar_adc_chan7_mux_sel sel)
423 {
424 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
425 u32 regval;
426
427 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
428 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
429 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
430
431 usleep_range(10, 20);
432
433 priv->chan7_mux_sel = sel;
434 }
435
meson_sar_adc_read_raw_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)436 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
437 const struct iio_chan_spec *chan,
438 int *val)
439 {
440 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
441 struct device *dev = indio_dev->dev.parent;
442 int regval, fifo_chan, fifo_val, count;
443
444 if (!wait_for_completion_timeout(&priv->done,
445 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
446 return -ETIMEDOUT;
447
448 count = meson_sar_adc_get_fifo_count(indio_dev);
449 if (count != 1) {
450 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
451 return -EINVAL;
452 }
453
454 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
455 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
456 if (fifo_chan != chan->address) {
457 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
458 fifo_chan, chan->address);
459 return -EINVAL;
460 }
461
462 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
463 fifo_val &= GENMASK(priv->param->resolution - 1, 0);
464 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
465
466 return 0;
467 }
468
meson_sar_adc_set_averaging(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode mode,enum meson_sar_adc_num_samples samples)469 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
470 const struct iio_chan_spec *chan,
471 enum meson_sar_adc_avg_mode mode,
472 enum meson_sar_adc_num_samples samples)
473 {
474 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
475 int val, address = chan->address;
476
477 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
478 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
479 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
480 val);
481
482 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
483 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
484 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
485 }
486
meson_sar_adc_enable_channel(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)487 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
488 const struct iio_chan_spec *chan)
489 {
490 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
491 u32 regval;
492
493 /*
494 * the SAR ADC engine allows sampling multiple channels at the same
495 * time. to keep it simple we're only working with one *internal*
496 * channel, which starts counting at index 0 (which means: count = 1).
497 */
498 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
499 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
500 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
501
502 /* map channel index 0 to the channel which we want to read */
503 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
504 chan->address);
505 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
506 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
507
508 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
509 chan->address);
510 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
511 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
512 regval);
513
514 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
515 chan->address);
516 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
517 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
518 regval);
519
520 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
521 if (chan->type == IIO_TEMP)
522 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
523 else
524 regval = 0;
525
526 regmap_update_bits(priv->regmap,
527 MESON_SAR_ADC_DELTA_10,
528 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
529 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) {
530 enum meson_sar_adc_chan7_mux_sel sel;
531
532 if (chan->channel == NUM_CHAN_7)
533 sel = CHAN7_MUX_CH7_INPUT;
534 else
535 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS];
536 if (sel != priv->chan7_mux_sel)
537 meson_sar_adc_set_chan7_mux(indio_dev, sel);
538 }
539 }
540
meson_sar_adc_start_sample_engine(struct iio_dev * indio_dev)541 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
542 {
543 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
544
545 reinit_completion(&priv->done);
546
547 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
548 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
549
550 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
551 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
552
553 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
554 MESON_SAR_ADC_REG0_SAMPLING_START);
555 }
556
meson_sar_adc_stop_sample_engine(struct iio_dev * indio_dev)557 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
558 {
559 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
560
561 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
562 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
563
564 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,
565 MESON_SAR_ADC_REG0_SAMPLING_STOP);
566
567 /* wait until all modules are stopped */
568 meson_sar_adc_wait_busy_clear(indio_dev);
569
570 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
571 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
572 }
573
meson_sar_adc_lock(struct iio_dev * indio_dev)574 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
575 {
576 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
577 int val, ret;
578
579 mutex_lock(&priv->lock);
580
581 if (priv->param->has_bl30_integration) {
582 /* prevent BL30 from using the SAR ADC while we are using it */
583 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY,
584 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
585
586 udelay(1);
587
588 /*
589 * wait until BL30 releases it's lock (so we can use the SAR
590 * ADC)
591 */
592 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
593 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
594 1, 10000);
595 if (ret) {
596 mutex_unlock(&priv->lock);
597 return ret;
598 }
599 }
600
601 return 0;
602 }
603
meson_sar_adc_unlock(struct iio_dev * indio_dev)604 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
605 {
606 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
607
608 if (priv->param->has_bl30_integration)
609 /* allow BL30 to use the SAR ADC again */
610 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY,
611 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
612
613 mutex_unlock(&priv->lock);
614 }
615
meson_sar_adc_clear_fifo(struct iio_dev * indio_dev)616 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
617 {
618 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
619 unsigned int count, tmp;
620
621 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
622 if (!meson_sar_adc_get_fifo_count(indio_dev))
623 break;
624
625 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
626 }
627 }
628
meson_sar_adc_get_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode avg_mode,enum meson_sar_adc_num_samples avg_samples,int * val)629 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
630 const struct iio_chan_spec *chan,
631 enum meson_sar_adc_avg_mode avg_mode,
632 enum meson_sar_adc_num_samples avg_samples,
633 int *val)
634 {
635 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
636 struct device *dev = indio_dev->dev.parent;
637 int ret;
638
639 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
640 return -ENOTSUPP;
641
642 ret = meson_sar_adc_lock(indio_dev);
643 if (ret)
644 return ret;
645
646 /* clear the FIFO to make sure we're not reading old values */
647 meson_sar_adc_clear_fifo(indio_dev);
648
649 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
650
651 meson_sar_adc_enable_channel(indio_dev, chan);
652
653 meson_sar_adc_start_sample_engine(indio_dev);
654 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
655 meson_sar_adc_stop_sample_engine(indio_dev);
656
657 meson_sar_adc_unlock(indio_dev);
658
659 if (ret) {
660 dev_warn(dev, "failed to read sample for channel %lu: %d\n",
661 chan->address, ret);
662 return ret;
663 }
664
665 return IIO_VAL_INT;
666 }
667
meson_sar_adc_iio_info_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)668 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
669 const struct iio_chan_spec *chan,
670 int *val, int *val2, long mask)
671 {
672 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
673 struct device *dev = indio_dev->dev.parent;
674 int ret;
675
676 switch (mask) {
677 case IIO_CHAN_INFO_RAW:
678 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
679 ONE_SAMPLE, val);
680
681 case IIO_CHAN_INFO_AVERAGE_RAW:
682 return meson_sar_adc_get_sample(indio_dev, chan,
683 MEAN_AVERAGING, EIGHT_SAMPLES,
684 val);
685
686 case IIO_CHAN_INFO_SCALE:
687 if (chan->type == IIO_VOLTAGE) {
688 ret = regulator_get_voltage(priv->vref);
689 if (ret < 0) {
690 dev_err(dev, "failed to get vref voltage: %d\n", ret);
691 return ret;
692 }
693
694 *val = ret / 1000;
695 *val2 = priv->param->resolution;
696 return IIO_VAL_FRACTIONAL_LOG2;
697 } else if (chan->type == IIO_TEMP) {
698 /* SoC specific multiplier and divider */
699 *val = priv->param->temperature_multiplier;
700 *val2 = priv->param->temperature_divider;
701
702 /* celsius to millicelsius */
703 *val *= 1000;
704
705 return IIO_VAL_FRACTIONAL;
706 } else {
707 return -EINVAL;
708 }
709
710 case IIO_CHAN_INFO_CALIBBIAS:
711 *val = priv->calibbias;
712 return IIO_VAL_INT;
713
714 case IIO_CHAN_INFO_CALIBSCALE:
715 *val = priv->calibscale / MILLION;
716 *val2 = priv->calibscale % MILLION;
717 return IIO_VAL_INT_PLUS_MICRO;
718
719 case IIO_CHAN_INFO_OFFSET:
720 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
721 priv->param->temperature_divider,
722 priv->param->temperature_multiplier);
723 *val -= priv->temperature_sensor_adc_val;
724 return IIO_VAL_INT;
725
726 default:
727 return -EINVAL;
728 }
729 }
730
meson_sar_adc_clk_init(struct iio_dev * indio_dev,void __iomem * base)731 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
732 void __iomem *base)
733 {
734 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
735 struct device *dev = indio_dev->dev.parent;
736 struct clk_init_data init;
737 const char *clk_parents[1];
738
739 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
740 if (!init.name)
741 return -ENOMEM;
742
743 init.flags = 0;
744 init.ops = &clk_divider_ops;
745 clk_parents[0] = __clk_get_name(priv->clkin);
746 init.parent_names = clk_parents;
747 init.num_parents = 1;
748
749 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
750 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
751 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
752 priv->clk_div.hw.init = &init;
753 priv->clk_div.flags = 0;
754
755 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
756 if (WARN_ON(IS_ERR(priv->adc_div_clk)))
757 return PTR_ERR(priv->adc_div_clk);
758
759 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
760 if (!init.name)
761 return -ENOMEM;
762
763 init.flags = CLK_SET_RATE_PARENT;
764 init.ops = &clk_gate_ops;
765 clk_parents[0] = __clk_get_name(priv->adc_div_clk);
766 init.parent_names = clk_parents;
767 init.num_parents = 1;
768
769 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
770 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
771 priv->clk_gate.hw.init = &init;
772
773 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
774 if (WARN_ON(IS_ERR(priv->adc_clk)))
775 return PTR_ERR(priv->adc_clk);
776
777 return 0;
778 }
779
meson_sar_adc_temp_sensor_init(struct iio_dev * indio_dev)780 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
781 {
782 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
783 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
784 struct device *dev = indio_dev->dev.parent;
785 struct nvmem_cell *temperature_calib;
786 size_t read_len;
787 int ret;
788
789 temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");
790 if (IS_ERR(temperature_calib)) {
791 ret = PTR_ERR(temperature_calib);
792
793 /*
794 * leave the temperature sensor disabled if no calibration data
795 * was passed via nvmem-cells.
796 */
797 if (ret == -ENODEV)
798 return 0;
799
800 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
801 }
802
803 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
804 if (IS_ERR(priv->tsc_regmap))
805 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
806 "failed to get amlogic,hhi-sysctrl regmap\n");
807
808 read_len = MESON_SAR_ADC_EFUSE_BYTES;
809 buf = nvmem_cell_read(temperature_calib, &read_len);
810 if (IS_ERR(buf))
811 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
812 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
813 kfree(buf);
814 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
815 }
816
817 trimming_bits = priv->param->temperature_trimming_bits;
818 trimming_mask = BIT(trimming_bits) - 1;
819
820 priv->temperature_sensor_calibrated =
821 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
822 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
823
824 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
825 buf[3]);
826
827 priv->temperature_sensor_adc_val = buf[2];
828 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
829 priv->temperature_sensor_adc_val >>= trimming_bits;
830
831 kfree(buf);
832
833 return 0;
834 }
835
meson_sar_adc_init(struct iio_dev * indio_dev)836 static int meson_sar_adc_init(struct iio_dev *indio_dev)
837 {
838 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
839 struct device *dev = indio_dev->dev.parent;
840 int regval, i, ret;
841
842 /*
843 * make sure we start at CH7 input since the other muxes are only used
844 * for internal calibration.
845 */
846 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
847
848 if (priv->param->has_bl30_integration) {
849 /*
850 * leave sampling delay and the input clocks as configured by
851 * BL30 to make sure BL30 gets the values it expects when
852 * reading the temperature sensor.
853 */
854 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
855 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
856 return 0;
857 }
858
859 meson_sar_adc_stop_sample_engine(indio_dev);
860
861 /*
862 * disable this bit as seems to be only relevant for Meson6 (based
863 * on the vendor driver), which we don't support at the moment.
864 */
865 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,
866 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
867
868 /* disable all channels by default */
869 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
870
871 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
872 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE);
873 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,
874 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
875
876 /* delay between two samples = (10+1) * 1uS */
877 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
878 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
879 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
880 10));
881 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
882 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
883 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
884 0));
885
886 /* delay between two samples = (10+1) * 1uS */
887 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
888 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
889 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
890 10));
891 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
892 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
893 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
894 1));
895
896 /*
897 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
898 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
899 */
900 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
901 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
902 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
903 regval);
904 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
905 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
906 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
907 regval);
908
909 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
910 MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
911
912 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
913 MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
914
915 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
916 MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
917
918 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
919 MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
920
921 /*
922 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
923 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
924 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
925 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
926 */
927 regval = 0;
928 for (i = 2; i <= 7; i++)
929 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
930 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
931 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
932 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
933
934 if (priv->temperature_sensor_calibrated) {
935 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
936 MESON_SAR_ADC_DELTA_10_TS_REVE1);
937 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
938 MESON_SAR_ADC_DELTA_10_TS_REVE0);
939
940 /*
941 * set bits [3:0] of the TSC (temperature sensor coefficient)
942 * to get the correct values when reading the temperature.
943 */
944 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
945 priv->temperature_sensor_coefficient);
946 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
947 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
948
949 if (priv->param->temperature_trimming_bits == 5) {
950 if (priv->temperature_sensor_coefficient & BIT(4))
951 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
952 else
953 regval = 0;
954
955 /*
956 * bit [4] (the 5th bit when starting to count at 1)
957 * of the TSC is located in the HHI register area.
958 */
959 regmap_update_bits(priv->tsc_regmap,
960 MESON_HHI_DPLL_TOP_0,
961 MESON_HHI_DPLL_TOP_0_TSC_BIT4,
962 regval);
963 }
964 } else {
965 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
966 MESON_SAR_ADC_DELTA_10_TS_REVE1);
967 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
968 MESON_SAR_ADC_DELTA_10_TS_REVE0);
969 }
970
971 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
972 priv->param->disable_ring_counter);
973 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
974 MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
975 regval);
976
977 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) {
978 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
979 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
980 MESON_SAR_ADC_REG11_EOC, regval);
981
982 if (priv->param->has_vref_select) {
983 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,
984 priv->param->vref_select);
985 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
986 MESON_SAR_ADC_REG11_VREF_SEL, regval);
987 }
988
989 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
990 priv->param->vref_voltage);
991 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
992 MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
993
994 regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
995 priv->param->cmv_select);
996 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
997 MESON_SAR_ADC_REG11_CMV_SEL, regval);
998 }
999
1000 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
1001 if (ret)
1002 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
1003
1004 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
1005 if (ret)
1006 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
1007
1008 return 0;
1009 }
1010
meson_sar_adc_set_bandgap(struct iio_dev * indio_dev,bool on_off)1011 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
1012 {
1013 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1014
1015 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11)
1016 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1017 MESON_SAR_ADC_REG11_BANDGAP_EN,
1018 on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0);
1019 else
1020 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
1021 MESON_SAR_ADC_DELTA_10_TS_VBG_EN,
1022 on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0);
1023 }
1024
meson_sar_adc_hw_enable(struct iio_dev * indio_dev)1025 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
1026 {
1027 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1028 struct device *dev = indio_dev->dev.parent;
1029 int ret;
1030 u32 regval;
1031
1032 ret = meson_sar_adc_lock(indio_dev);
1033 if (ret) {
1034 dev_err(dev, "failed to lock adc\n");
1035 goto err_lock;
1036 }
1037
1038 ret = regulator_enable(priv->vref);
1039 if (ret < 0) {
1040 dev_err(dev, "failed to enable vref regulator\n");
1041 goto err_vref;
1042 }
1043
1044 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
1045 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
1046 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1047
1048 meson_sar_adc_set_bandgap(indio_dev, true);
1049
1050 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,
1051 MESON_SAR_ADC_REG3_ADC_EN);
1052
1053 udelay(5);
1054
1055 ret = clk_prepare_enable(priv->adc_clk);
1056 if (ret) {
1057 dev_err(dev, "failed to enable adc clk\n");
1058 goto err_adc_clk;
1059 }
1060
1061 meson_sar_adc_unlock(indio_dev);
1062
1063 return 0;
1064
1065 err_adc_clk:
1066 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
1067 MESON_SAR_ADC_REG3_ADC_EN);
1068 meson_sar_adc_set_bandgap(indio_dev, false);
1069 regulator_disable(priv->vref);
1070 err_vref:
1071 meson_sar_adc_unlock(indio_dev);
1072 err_lock:
1073 return ret;
1074 }
1075
meson_sar_adc_hw_disable(struct iio_dev * indio_dev)1076 static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
1077 {
1078 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1079 int ret;
1080
1081 /*
1082 * If taking the lock fails we have to assume that BL30 is broken. The
1083 * best we can do then is to release the resources anyhow.
1084 */
1085 ret = meson_sar_adc_lock(indio_dev);
1086 if (ret)
1087 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret));
1088
1089 clk_disable_unprepare(priv->adc_clk);
1090
1091 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,
1092 MESON_SAR_ADC_REG3_ADC_EN);
1093
1094 meson_sar_adc_set_bandgap(indio_dev, false);
1095
1096 regulator_disable(priv->vref);
1097
1098 if (!ret)
1099 meson_sar_adc_unlock(indio_dev);
1100 }
1101
meson_sar_adc_irq(int irq,void * data)1102 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
1103 {
1104 struct iio_dev *indio_dev = data;
1105 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1106 unsigned int cnt, threshold;
1107 u32 regval;
1108
1109 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
1110 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
1111 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1112
1113 if (cnt < threshold)
1114 return IRQ_NONE;
1115
1116 complete(&priv->done);
1117
1118 return IRQ_HANDLED;
1119 }
1120
meson_sar_adc_calib(struct iio_dev * indio_dev)1121 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1122 {
1123 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1124 int ret, nominal0, nominal1, value0, value1;
1125
1126 /* use points 25% and 75% for calibration */
1127 nominal0 = (1 << priv->param->resolution) / 4;
1128 nominal1 = (1 << priv->param->resolution) * 3 / 4;
1129
1130 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1131 usleep_range(10, 20);
1132 ret = meson_sar_adc_get_sample(indio_dev,
1133 find_channel_by_num(indio_dev,
1134 NUM_MUX_1_VDD_DIV4),
1135 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1136 if (ret < 0)
1137 goto out;
1138
1139 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1140 usleep_range(10, 20);
1141 ret = meson_sar_adc_get_sample(indio_dev,
1142 find_channel_by_num(indio_dev,
1143 NUM_MUX_3_VDD_MUL3_DIV4),
1144 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1145 if (ret < 0)
1146 goto out;
1147
1148 if (value1 <= value0) {
1149 ret = -EINVAL;
1150 goto out;
1151 }
1152
1153 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1154 value1 - value0);
1155 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1156 MILLION);
1157 ret = 0;
1158 out:
1159 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1160
1161 return ret;
1162 }
1163
read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)1164 static int read_label(struct iio_dev *indio_dev,
1165 struct iio_chan_spec const *chan,
1166 char *label)
1167 {
1168 if (chan->type == IIO_TEMP)
1169 return sprintf(label, "temp-sensor\n");
1170 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS)
1171 return sprintf(label, "%s\n",
1172 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]);
1173 if (chan->type == IIO_VOLTAGE)
1174 return sprintf(label, "channel-%d\n", chan->channel);
1175 return 0;
1176 }
1177
1178 static const struct iio_info meson_sar_adc_iio_info = {
1179 .read_raw = meson_sar_adc_iio_info_read_raw,
1180 .read_label = read_label,
1181 };
1182
1183 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1184 .has_bl30_integration = false,
1185 .clock_rate = 1150000,
1186 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1187 .resolution = 10,
1188 .temperature_trimming_bits = 4,
1189 .temperature_multiplier = 18 * 10000,
1190 .temperature_divider = 1024 * 10 * 85,
1191 };
1192
1193 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1194 .has_bl30_integration = false,
1195 .clock_rate = 1150000,
1196 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1197 .resolution = 10,
1198 .temperature_trimming_bits = 5,
1199 .temperature_multiplier = 10,
1200 .temperature_divider = 32,
1201 };
1202
1203 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1204 .has_bl30_integration = true,
1205 .clock_rate = 1200000,
1206 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1207 .resolution = 10,
1208 .vref_voltage = 1,
1209 .cmv_select = 1,
1210 };
1211
1212 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1213 .has_bl30_integration = true,
1214 .clock_rate = 1200000,
1215 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1216 .resolution = 12,
1217 .disable_ring_counter = 1,
1218 .vref_voltage = 1,
1219 .cmv_select = 1,
1220 };
1221
1222 static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
1223 .has_bl30_integration = true,
1224 .clock_rate = 1200000,
1225 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1226 .resolution = 12,
1227 .disable_ring_counter = 1,
1228 .vref_voltage = 1,
1229 .has_vref_select = true,
1230 .vref_select = VREF_VDDA,
1231 .cmv_select = 1,
1232 };
1233
1234 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
1235 .has_bl30_integration = false,
1236 .clock_rate = 1200000,
1237 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1238 .resolution = 12,
1239 .disable_ring_counter = 1,
1240 .adc_eoc = 1,
1241 .has_vref_select = true,
1242 .vref_select = VREF_VDDA,
1243 };
1244
1245 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1246 .param = &meson_sar_adc_meson8_param,
1247 .name = "meson-meson8-saradc",
1248 };
1249
1250 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1251 .param = &meson_sar_adc_meson8b_param,
1252 .name = "meson-meson8b-saradc",
1253 };
1254
1255 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1256 .param = &meson_sar_adc_meson8b_param,
1257 .name = "meson-meson8m2-saradc",
1258 };
1259
1260 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1261 .param = &meson_sar_adc_gxbb_param,
1262 .name = "meson-gxbb-saradc",
1263 };
1264
1265 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1266 .param = &meson_sar_adc_gxl_param,
1267 .name = "meson-gxl-saradc",
1268 };
1269
1270 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1271 .param = &meson_sar_adc_gxl_param,
1272 .name = "meson-gxm-saradc",
1273 };
1274
1275 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1276 .param = &meson_sar_adc_axg_param,
1277 .name = "meson-axg-saradc",
1278 };
1279
1280 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1281 .param = &meson_sar_adc_g12a_param,
1282 .name = "meson-g12a-saradc",
1283 };
1284
1285 static const struct of_device_id meson_sar_adc_of_match[] = {
1286 {
1287 .compatible = "amlogic,meson8-saradc",
1288 .data = &meson_sar_adc_meson8_data,
1289 }, {
1290 .compatible = "amlogic,meson8b-saradc",
1291 .data = &meson_sar_adc_meson8b_data,
1292 }, {
1293 .compatible = "amlogic,meson8m2-saradc",
1294 .data = &meson_sar_adc_meson8m2_data,
1295 }, {
1296 .compatible = "amlogic,meson-gxbb-saradc",
1297 .data = &meson_sar_adc_gxbb_data,
1298 }, {
1299 .compatible = "amlogic,meson-gxl-saradc",
1300 .data = &meson_sar_adc_gxl_data,
1301 }, {
1302 .compatible = "amlogic,meson-gxm-saradc",
1303 .data = &meson_sar_adc_gxm_data,
1304 }, {
1305 .compatible = "amlogic,meson-axg-saradc",
1306 .data = &meson_sar_adc_axg_data,
1307 }, {
1308 .compatible = "amlogic,meson-g12a-saradc",
1309 .data = &meson_sar_adc_g12a_data,
1310 },
1311 { /* sentinel */ }
1312 };
1313 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1314
meson_sar_adc_probe(struct platform_device * pdev)1315 static int meson_sar_adc_probe(struct platform_device *pdev)
1316 {
1317 const struct meson_sar_adc_data *match_data;
1318 struct meson_sar_adc_priv *priv;
1319 struct device *dev = &pdev->dev;
1320 struct iio_dev *indio_dev;
1321 void __iomem *base;
1322 int irq, ret;
1323
1324 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1325 if (!indio_dev)
1326 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");
1327
1328 priv = iio_priv(indio_dev);
1329 init_completion(&priv->done);
1330
1331 match_data = of_device_get_match_data(dev);
1332 if (!match_data)
1333 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
1334
1335 priv->param = match_data->param;
1336
1337 indio_dev->name = match_data->name;
1338 indio_dev->modes = INDIO_DIRECT_MODE;
1339 indio_dev->info = &meson_sar_adc_iio_info;
1340
1341 base = devm_platform_ioremap_resource(pdev, 0);
1342 if (IS_ERR(base))
1343 return PTR_ERR(base);
1344
1345 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
1346 if (IS_ERR(priv->regmap))
1347 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n");
1348
1349 irq = irq_of_parse_and_map(dev->of_node, 0);
1350 if (!irq)
1351 return dev_err_probe(dev, -EINVAL, "failed to get irq\n");
1352
1353 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
1354 if (ret)
1355 return dev_err_probe(dev, ret, "failed to request irq\n");
1356
1357 priv->clkin = devm_clk_get(dev, "clkin");
1358 if (IS_ERR(priv->clkin))
1359 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
1360
1361 priv->core_clk = devm_clk_get_enabled(dev, "core");
1362 if (IS_ERR(priv->core_clk))
1363 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
1364
1365 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
1366 if (IS_ERR(priv->adc_clk))
1367 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
1368
1369 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
1370 if (IS_ERR(priv->adc_sel_clk))
1371 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
1372
1373 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1374 if (!priv->adc_clk) {
1375 ret = meson_sar_adc_clk_init(indio_dev, base);
1376 if (ret)
1377 return dev_err_probe(dev, ret, "failed to init internal clk\n");
1378 }
1379
1380 priv->vref = devm_regulator_get(dev, "vref");
1381 if (IS_ERR(priv->vref))
1382 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
1383
1384 priv->calibscale = MILLION;
1385
1386 if (priv->param->temperature_trimming_bits) {
1387 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1388 if (ret)
1389 return ret;
1390 }
1391
1392 if (priv->temperature_sensor_calibrated) {
1393 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1394 indio_dev->num_channels =
1395 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1396 } else {
1397 indio_dev->channels = meson_sar_adc_iio_channels;
1398 indio_dev->num_channels =
1399 ARRAY_SIZE(meson_sar_adc_iio_channels);
1400 }
1401
1402 ret = meson_sar_adc_init(indio_dev);
1403 if (ret)
1404 goto err;
1405
1406 mutex_init(&priv->lock);
1407
1408 ret = meson_sar_adc_hw_enable(indio_dev);
1409 if (ret)
1410 goto err;
1411
1412 ret = meson_sar_adc_calib(indio_dev);
1413 if (ret)
1414 dev_warn(dev, "calibration failed\n");
1415
1416 platform_set_drvdata(pdev, indio_dev);
1417
1418 ret = iio_device_register(indio_dev);
1419 if (ret) {
1420 dev_err_probe(dev, ret, "failed to register iio device\n");
1421 goto err_hw;
1422 }
1423
1424 return 0;
1425
1426 err_hw:
1427 meson_sar_adc_hw_disable(indio_dev);
1428 err:
1429 return ret;
1430 }
1431
meson_sar_adc_remove(struct platform_device * pdev)1432 static void meson_sar_adc_remove(struct platform_device *pdev)
1433 {
1434 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1435
1436 iio_device_unregister(indio_dev);
1437
1438 meson_sar_adc_hw_disable(indio_dev);
1439 }
1440
meson_sar_adc_suspend(struct device * dev)1441 static int meson_sar_adc_suspend(struct device *dev)
1442 {
1443 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1444 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1445
1446 meson_sar_adc_hw_disable(indio_dev);
1447
1448 clk_disable_unprepare(priv->core_clk);
1449
1450 return 0;
1451 }
1452
meson_sar_adc_resume(struct device * dev)1453 static int meson_sar_adc_resume(struct device *dev)
1454 {
1455 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1456 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1457 int ret;
1458
1459 ret = clk_prepare_enable(priv->core_clk);
1460 if (ret) {
1461 dev_err(dev, "failed to enable core clk\n");
1462 return ret;
1463 }
1464
1465 return meson_sar_adc_hw_enable(indio_dev);
1466 }
1467
1468 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1469 meson_sar_adc_suspend, meson_sar_adc_resume);
1470
1471 static struct platform_driver meson_sar_adc_driver = {
1472 .probe = meson_sar_adc_probe,
1473 .remove = meson_sar_adc_remove,
1474 .driver = {
1475 .name = "meson-saradc",
1476 .of_match_table = meson_sar_adc_of_match,
1477 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
1478 },
1479 };
1480
1481 module_platform_driver(meson_sar_adc_driver);
1482
1483 MODULE_AUTHOR("Martin Blumenstingl <[email protected]>");
1484 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1485 MODULE_LICENSE("GPL v2");
1486