1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD717x and AD411x family SPI ADC driver
4 *
5 * Supported devices:
6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116
7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2
8 * AD7175-8/AD7176-2/AD7177-2
9 *
10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
11 */
12
13 #include <linux/array_size.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitmap.h>
16 #include <linux/container_of.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/regmap.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/math64.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/property.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/types.h>
35 #include <linux/units.h>
36
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/iio.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41
42 #include <linux/iio/adc/ad_sigma_delta.h>
43
44 #define AD7173_REG_COMMS 0x00
45 #define AD7173_REG_ADC_MODE 0x01
46 #define AD7173_REG_INTERFACE_MODE 0x02
47 #define AD7173_REG_CRC 0x03
48 #define AD7173_REG_DATA 0x04
49 #define AD7173_REG_GPIO 0x06
50 #define AD7173_REG_ID 0x07
51 #define AD7173_REG_CH(x) (0x10 + (x))
52 #define AD7173_REG_SETUP(x) (0x20 + (x))
53 #define AD7173_REG_FILTER(x) (0x28 + (x))
54 #define AD7173_REG_OFFSET(x) (0x30 + (x))
55 #define AD7173_REG_GAIN(x) (0x38 + (x))
56
57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
58
59 #define AD7173_CH_ENABLE BIT(15)
60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
63
64 #define AD7173_NO_AINS_PER_CHANNEL 2
65 #define AD7173_CH_ADDRESS(pos, neg) \
66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
68 #define AD7173_AIN_TEMP_POS 17
69 #define AD7173_AIN_TEMP_NEG 18
70 #define AD7173_AIN_POW_MON_POS 19
71 #define AD7173_AIN_POW_MON_NEG 20
72 #define AD7173_AIN_REF_POS 21
73 #define AD7173_AIN_REF_NEG 22
74
75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \
76 (x) == AD7173_AIN_REF_NEG)
77
78 #define AD7172_2_ID 0x00d0
79 #define AD7176_ID 0x0c90
80 #define AD7175_ID 0x0cd0
81 #define AD7175_2_ID 0x0cd0
82 #define AD7172_4_ID 0x2050
83 #define AD7173_ID 0x30d0
84 #define AD4111_ID AD7173_ID
85 #define AD4112_ID AD7173_ID
86 #define AD4114_ID AD7173_ID
87 #define AD4113_ID 0x31d0
88 #define AD4116_ID 0x34d0
89 #define AD4115_ID 0x38d0
90 #define AD7175_8_ID 0x3cd0
91 #define AD7177_ID 0x4fd0
92 #define AD7173_ID_MASK GENMASK(15, 4)
93
94 #define AD7173_ADC_MODE_REF_EN BIT(15)
95 #define AD7173_ADC_MODE_SING_CYC BIT(13)
96 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
97 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
98 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
99 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
100 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
101 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
102
103 #define AD7173_GPIO_PDSW BIT(14)
104 #define AD7173_GPIO_OP_EN2_3 BIT(13)
105 #define AD7173_GPIO_MUX_IO BIT(12)
106 #define AD7173_GPIO_SYNC_EN BIT(11)
107 #define AD7173_GPIO_ERR_EN BIT(10)
108 #define AD7173_GPIO_ERR_DAT BIT(9)
109 #define AD7173_GPIO_GP_DATA3 BIT(7)
110 #define AD7173_GPIO_GP_DATA2 BIT(6)
111 #define AD7173_GPIO_IP_EN1 BIT(5)
112 #define AD7173_GPIO_IP_EN0 BIT(4)
113 #define AD7173_GPIO_OP_EN1 BIT(3)
114 #define AD7173_GPIO_OP_EN0 BIT(2)
115 #define AD7173_GPIO_GP_DATA1 BIT(1)
116 #define AD7173_GPIO_GP_DATA0 BIT(0)
117
118 #define AD7173_GPO12_DATA(x) BIT((x) + 0)
119 #define AD7173_GPO23_DATA(x) BIT((x) + 4)
120 #define AD4111_GPO01_DATA(x) BIT((x) + 6)
121 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
122
123 #define AD7173_INTERFACE_DATA_STAT BIT(6)
124 #define AD7173_INTERFACE_DATA_STAT_EN(x) \
125 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
126
127 #define AD7173_SETUP_BIPOLAR BIT(12)
128 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
129 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
130
131 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
132 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
133 #define AD7173_SETUP_REF_SEL_INT_REF 0x2
134 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
135 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0
136 #define AD7173_VOLTAGE_INT_REF_uV 2500000
137 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477
138 #define AD7177_ODR_START_VALUE 0x07
139 #define AD4111_SHUNT_RESISTOR_OHM 50
140 #define AD4111_DIVIDER_RATIO 10
141 #define AD4111_CURRENT_CHAN_CUTOFF 16
142 #define AD4111_VINCOM_INPUT 0x10
143
144 /* pin < num_voltage_in is a normal voltage input */
145 /* pin >= num_voltage_in_div is a voltage input without a divider */
146 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
147 (pin2) < st->info->num_voltage_in && \
148 (pin2) >= st->info->num_voltage_in_div)
149
150 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
151 #define AD7173_MAX_CONFIGS 8
152
153 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */
154 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */
155 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */
156 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */
157
158 struct ad7173_device_info {
159 const unsigned int *sinc5_data_rates;
160 unsigned int num_sinc5_data_rates;
161 unsigned int odr_start_value;
162 /*
163 * AD4116 has both inputs with a voltage divider and without.
164 * These inputs cannot be mixed in the channel configuration.
165 * Does not include the VINCOM input.
166 */
167 unsigned int num_voltage_in_div;
168 unsigned int num_channels;
169 unsigned int num_configs;
170 unsigned int num_voltage_in;
171 unsigned int clock;
172 unsigned int id;
173 char *name;
174 bool has_current_inputs;
175 bool has_vincom_input;
176 bool has_temp;
177 /* ((AVDD1 − AVSS)/5) */
178 bool has_pow_supply_monitoring;
179 bool data_reg_only_16bit;
180 bool has_input_buf;
181 bool has_int_ref;
182 bool has_ref2;
183 bool has_internal_fs_calibration;
184 bool higher_gpio_bits;
185 u8 num_gpios;
186 };
187
188 struct ad7173_channel_config {
189 u8 cfg_slot;
190 bool live;
191
192 /*
193 * Following fields are used to compare equality. If you
194 * make adaptations in it, you most likely also have to adapt
195 * ad7173_find_live_config(), too.
196 */
197 struct_group(config_props,
198 bool bipolar;
199 bool input_buf;
200 u8 odr;
201 u8 ref_sel;
202 );
203 };
204
205 struct ad7173_channel {
206 unsigned int ain;
207 struct ad7173_channel_config cfg;
208 u8 syscalib_mode;
209 };
210
211 struct ad7173_state {
212 struct ad_sigma_delta sd;
213 struct ad_sigma_delta_info sigma_delta_info;
214 const struct ad7173_device_info *info;
215 struct ad7173_channel *channels;
216 struct regulator_bulk_data regulators[3];
217 unsigned int adc_mode;
218 unsigned int interface_mode;
219 unsigned int num_channels;
220 struct ida cfg_slots_status;
221 unsigned long long config_usage_counter;
222 unsigned long long *config_cnts;
223 struct clk *ext_clk;
224 struct clk_hw int_clk_hw;
225 #if IS_ENABLED(CONFIG_GPIOLIB)
226 struct regmap *reg_gpiocon_regmap;
227 struct gpio_regmap *gpio_regmap;
228 #endif
229 };
230
231 static unsigned int ad4115_sinc5_data_rates[] = {
232 24845000, 24845000, 20725000, 20725000, /* 0-3 */
233 15564000, 13841000, 10390000, 10390000, /* 4-7 */
234 4994000, 2499000, 1000000, 500000, /* 8-11 */
235 395500, 200000, 100000, 59890, /* 12-15 */
236 49920, 20000, 16660, 10000, /* 16-19 */
237 5000, 2500, 2500, /* 20-22 */
238 };
239
240 static unsigned int ad4116_sinc5_data_rates[] = {
241 12422360, 12422360, 12422360, 12422360, /* 0-3 */
242 10362690, 10362690, 7782100, 6290530, /* 4-7 */
243 5194800, 2496900, 1007600, 499900, /* 8-11 */
244 390600, 200300, 100000, 59750, /* 12-15 */
245 49840, 20000, 16650, 10000, /* 16-19 */
246 5000, 2500, 1250, /* 20-22 */
247 };
248
249 static const unsigned int ad7173_sinc5_data_rates[] = {
250 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
251 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
252 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
253 };
254
255 static const unsigned int ad7175_sinc5_data_rates[] = {
256 50000000, 41667000, 31250000, 27778000, /* 0-3 */
257 20833000, 17857000, 12500000, 10000000, /* 4-7 */
258 5000000, 2500000, 1000000, 500000, /* 8-11 */
259 397500, 200000, 100000, 59920, /* 12-15 */
260 49960, 20000, 16666, 10000, /* 16-19 */
261 5000, /* 20 */
262 };
263
264 static unsigned int ad4111_current_channel_config[] = {
265 /* Ain sel: pos neg */
266 0x1E8, /* 15:IIN0+ 8:IIN0− */
267 0x1C9, /* 14:IIN1+ 9:IIN1− */
268 0x1AA, /* 13:IIN2+ 10:IIN2− */
269 0x18B, /* 12:IIN3+ 11:IIN3− */
270 };
271
272 static const struct ad7173_device_info ad4111_device_info = {
273 .name = "ad4111",
274 .id = AD4111_ID,
275 .num_voltage_in_div = 8,
276 .num_channels = 16,
277 .num_configs = 8,
278 .num_voltage_in = 8,
279 .num_gpios = 2,
280 .higher_gpio_bits = true,
281 .has_temp = true,
282 .has_vincom_input = true,
283 .has_input_buf = true,
284 .has_current_inputs = true,
285 .has_int_ref = true,
286 .has_internal_fs_calibration = true,
287 .clock = 2 * HZ_PER_MHZ,
288 .sinc5_data_rates = ad7173_sinc5_data_rates,
289 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
290 };
291
292 static const struct ad7173_device_info ad4112_device_info = {
293 .name = "ad4112",
294 .id = AD4112_ID,
295 .num_voltage_in_div = 8,
296 .num_channels = 16,
297 .num_configs = 8,
298 .num_voltage_in = 8,
299 .num_gpios = 2,
300 .higher_gpio_bits = true,
301 .has_vincom_input = true,
302 .has_temp = true,
303 .has_input_buf = true,
304 .has_current_inputs = true,
305 .has_int_ref = true,
306 .has_internal_fs_calibration = true,
307 .clock = 2 * HZ_PER_MHZ,
308 .sinc5_data_rates = ad7173_sinc5_data_rates,
309 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
310 };
311
312 static const struct ad7173_device_info ad4113_device_info = {
313 .name = "ad4113",
314 .id = AD4113_ID,
315 .num_voltage_in_div = 8,
316 .num_channels = 16,
317 .num_configs = 8,
318 .num_voltage_in = 8,
319 .num_gpios = 2,
320 .data_reg_only_16bit = true,
321 .higher_gpio_bits = true,
322 .has_vincom_input = true,
323 .has_input_buf = true,
324 .has_int_ref = true,
325 .clock = 2 * HZ_PER_MHZ,
326 .sinc5_data_rates = ad7173_sinc5_data_rates,
327 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
328 };
329
330 static const struct ad7173_device_info ad4114_device_info = {
331 .name = "ad4114",
332 .id = AD4114_ID,
333 .num_voltage_in_div = 16,
334 .num_channels = 16,
335 .num_configs = 8,
336 .num_voltage_in = 16,
337 .num_gpios = 4,
338 .has_vincom_input = true,
339 .has_temp = true,
340 .has_input_buf = true,
341 .has_int_ref = true,
342 .has_internal_fs_calibration = true,
343 .clock = 2 * HZ_PER_MHZ,
344 .sinc5_data_rates = ad7173_sinc5_data_rates,
345 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
346 };
347
348 static const struct ad7173_device_info ad4115_device_info = {
349 .name = "ad4115",
350 .id = AD4115_ID,
351 .num_voltage_in_div = 16,
352 .num_channels = 16,
353 .num_configs = 8,
354 .num_voltage_in = 16,
355 .num_gpios = 4,
356 .has_vincom_input = true,
357 .has_temp = true,
358 .has_input_buf = true,
359 .has_int_ref = true,
360 .has_internal_fs_calibration = true,
361 .clock = 8 * HZ_PER_MHZ,
362 .sinc5_data_rates = ad4115_sinc5_data_rates,
363 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
364 };
365
366 static const struct ad7173_device_info ad4116_device_info = {
367 .name = "ad4116",
368 .id = AD4116_ID,
369 .num_voltage_in_div = 11,
370 .num_channels = 16,
371 .num_configs = 8,
372 .num_voltage_in = 16,
373 .num_gpios = 4,
374 .has_vincom_input = true,
375 .has_temp = true,
376 .has_input_buf = true,
377 .has_int_ref = true,
378 .has_internal_fs_calibration = true,
379 .clock = 4 * HZ_PER_MHZ,
380 .sinc5_data_rates = ad4116_sinc5_data_rates,
381 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
382 };
383
384 static const struct ad7173_device_info ad7172_2_device_info = {
385 .name = "ad7172-2",
386 .id = AD7172_2_ID,
387 .num_voltage_in = 5,
388 .num_channels = 4,
389 .num_configs = 4,
390 .num_gpios = 2,
391 .has_temp = true,
392 .has_input_buf = true,
393 .has_int_ref = true,
394 .has_pow_supply_monitoring = true,
395 .clock = 2 * HZ_PER_MHZ,
396 .sinc5_data_rates = ad7173_sinc5_data_rates,
397 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
398 };
399
400 static const struct ad7173_device_info ad7172_4_device_info = {
401 .name = "ad7172-4",
402 .id = AD7172_4_ID,
403 .num_voltage_in = 9,
404 .num_channels = 8,
405 .num_configs = 8,
406 .num_gpios = 4,
407 .has_input_buf = true,
408 .has_ref2 = true,
409 .has_pow_supply_monitoring = true,
410 .clock = 2 * HZ_PER_MHZ,
411 .sinc5_data_rates = ad7173_sinc5_data_rates,
412 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
413 };
414
415 static const struct ad7173_device_info ad7173_8_device_info = {
416 .name = "ad7173-8",
417 .id = AD7173_ID,
418 .num_voltage_in = 17,
419 .num_channels = 16,
420 .num_configs = 8,
421 .num_gpios = 4,
422 .has_temp = true,
423 .has_input_buf = true,
424 .has_int_ref = true,
425 .has_ref2 = true,
426 .clock = 2 * HZ_PER_MHZ,
427 .sinc5_data_rates = ad7173_sinc5_data_rates,
428 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
429 };
430
431 static const struct ad7173_device_info ad7175_2_device_info = {
432 .name = "ad7175-2",
433 .id = AD7175_2_ID,
434 .num_voltage_in = 5,
435 .num_channels = 4,
436 .num_configs = 4,
437 .num_gpios = 2,
438 .has_temp = true,
439 .has_input_buf = true,
440 .has_int_ref = true,
441 .has_pow_supply_monitoring = true,
442 .clock = 16 * HZ_PER_MHZ,
443 .sinc5_data_rates = ad7175_sinc5_data_rates,
444 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
445 };
446
447 static const struct ad7173_device_info ad7175_8_device_info = {
448 .name = "ad7175-8",
449 .id = AD7175_8_ID,
450 .num_voltage_in = 17,
451 .num_channels = 16,
452 .num_configs = 8,
453 .num_gpios = 4,
454 .has_temp = true,
455 .has_input_buf = true,
456 .has_int_ref = true,
457 .has_ref2 = true,
458 .has_pow_supply_monitoring = true,
459 .clock = 16 * HZ_PER_MHZ,
460 .sinc5_data_rates = ad7175_sinc5_data_rates,
461 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
462 };
463
464 static const struct ad7173_device_info ad7176_2_device_info = {
465 .name = "ad7176-2",
466 .id = AD7176_ID,
467 .num_voltage_in = 5,
468 .num_channels = 4,
469 .num_configs = 4,
470 .num_gpios = 2,
471 .has_int_ref = true,
472 .clock = 16 * HZ_PER_MHZ,
473 .sinc5_data_rates = ad7175_sinc5_data_rates,
474 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
475 };
476
477 static const struct ad7173_device_info ad7177_2_device_info = {
478 .name = "ad7177-2",
479 .id = AD7177_ID,
480 .num_voltage_in = 5,
481 .num_channels = 4,
482 .num_configs = 4,
483 .num_gpios = 2,
484 .has_temp = true,
485 .has_input_buf = true,
486 .has_int_ref = true,
487 .has_pow_supply_monitoring = true,
488 .clock = 16 * HZ_PER_MHZ,
489 .odr_start_value = AD7177_ODR_START_VALUE,
490 .sinc5_data_rates = ad7175_sinc5_data_rates,
491 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
492 };
493
494 static const char *const ad7173_ref_sel_str[] = {
495 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
496 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
497 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
498 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
499 };
500
501 static const char *const ad7173_clk_sel[] = {
502 "ext-clk", "xtal"
503 };
504
505 #if IS_ENABLED(CONFIG_GPIOLIB)
506
507 static const struct regmap_range ad7173_range_gpio[] = {
508 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
509 };
510
511 static const struct regmap_access_table ad7173_access_table = {
512 .yes_ranges = ad7173_range_gpio,
513 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
514 };
515
516 static const struct regmap_config ad7173_regmap_config = {
517 .reg_bits = 8,
518 .val_bits = 16,
519 .rd_table = &ad7173_access_table,
520 .wr_table = &ad7173_access_table,
521 .read_flag_mask = BIT(6),
522 };
523
524 enum {
525 AD7173_SYSCALIB_ZERO_SCALE,
526 AD7173_SYSCALIB_FULL_SCALE,
527 };
528
529 static const char * const ad7173_syscalib_modes[] = {
530 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale",
531 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale",
532 };
533
ad7173_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)534 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev,
535 const struct iio_chan_spec *chan,
536 unsigned int mode)
537 {
538 struct ad7173_state *st = iio_priv(indio_dev);
539
540 st->channels[chan->channel].syscalib_mode = mode;
541
542 return 0;
543 }
544
ad7173_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)545 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev,
546 const struct iio_chan_spec *chan)
547 {
548 struct ad7173_state *st = iio_priv(indio_dev);
549
550 return st->channels[chan->channel].syscalib_mode;
551 }
552
ad7173_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)553 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev,
554 uintptr_t private,
555 const struct iio_chan_spec *chan,
556 const char *buf, size_t len)
557 {
558 struct ad7173_state *st = iio_priv(indio_dev);
559 bool sys_calib;
560 int ret, mode;
561
562 ret = kstrtobool(buf, &sys_calib);
563 if (ret)
564 return ret;
565
566 if (!iio_device_claim_direct(indio_dev))
567 return -EBUSY;
568
569 mode = st->channels[chan->channel].syscalib_mode;
570 if (sys_calib) {
571 if (mode == AD7173_SYSCALIB_ZERO_SCALE)
572 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO,
573 chan->address);
574 else
575 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL,
576 chan->address);
577 }
578
579 iio_device_release_direct(indio_dev);
580
581 return ret ? : len;
582 }
583
584 static const struct iio_enum ad7173_syscalib_mode_enum = {
585 .items = ad7173_syscalib_modes,
586 .num_items = ARRAY_SIZE(ad7173_syscalib_modes),
587 .set = ad7173_set_syscalib_mode,
588 .get = ad7173_get_syscalib_mode
589 };
590
591 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = {
592 {
593 .name = "sys_calibration",
594 .write = ad7173_write_syscalib,
595 .shared = IIO_SEPARATE,
596 },
597 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
598 &ad7173_syscalib_mode_enum),
599 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
600 &ad7173_syscalib_mode_enum),
601 { }
602 };
603
ad7173_calibrate_all(struct ad7173_state * st,struct iio_dev * indio_dev)604 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev)
605 {
606 int ret;
607 int i;
608
609 for (i = 0; i < st->num_channels; i++) {
610 if (indio_dev->channels[i].type != IIO_VOLTAGE)
611 continue;
612
613 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, st->channels[i].ain);
614 if (ret < 0)
615 return ret;
616
617 if (st->info->has_internal_fs_calibration) {
618 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL,
619 st->channels[i].ain);
620 if (ret < 0)
621 return ret;
622 }
623 }
624
625 return 0;
626 }
627
ad7173_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)628 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
629 unsigned int offset, unsigned int *reg,
630 unsigned int *mask)
631 {
632 *mask = AD7173_GPO_DATA(offset);
633 *reg = base;
634 return 0;
635 }
636
ad4111_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)637 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
638 unsigned int offset, unsigned int *reg,
639 unsigned int *mask)
640 {
641 *mask = AD4111_GPO01_DATA(offset);
642 *reg = base;
643 return 0;
644 }
645
ad7173_gpio_disable(void * data)646 static void ad7173_gpio_disable(void *data)
647 {
648 struct ad7173_state *st = data;
649 unsigned int mask;
650
651 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
652 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
653 }
654
ad7173_gpio_init(struct ad7173_state * st)655 static int ad7173_gpio_init(struct ad7173_state *st)
656 {
657 struct gpio_regmap_config gpio_regmap = {};
658 struct device *dev = &st->sd.spi->dev;
659 unsigned int mask;
660 int ret;
661
662 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
663 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
664 if (ret)
665 return dev_err_probe(dev, ret, "Unable to init regmap\n");
666
667 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
668 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
669
670 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
671 if (ret)
672 return ret;
673
674 gpio_regmap.parent = dev;
675 gpio_regmap.regmap = st->reg_gpiocon_regmap;
676 gpio_regmap.ngpio = st->info->num_gpios;
677 gpio_regmap.reg_set_base = AD7173_REG_GPIO;
678 if (st->info->higher_gpio_bits)
679 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
680 else
681 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
682
683 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
684 ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
685 if (ret)
686 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
687
688 return 0;
689 }
690 #else
ad7173_gpio_init(struct ad7173_state * st)691 static int ad7173_gpio_init(struct ad7173_state *st)
692 {
693 return 0;
694 }
695 #endif /* CONFIG_GPIOLIB */
696
ad_sigma_delta_to_ad7173(struct ad_sigma_delta * sd)697 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
698 {
699 return container_of(sd, struct ad7173_state, sd);
700 }
701
clk_hw_to_ad7173(struct clk_hw * hw)702 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
703 {
704 return container_of(hw, struct ad7173_state, int_clk_hw);
705 }
706
ad7173_ida_destroy(void * data)707 static void ad7173_ida_destroy(void *data)
708 {
709 struct ad7173_state *st = data;
710
711 ida_destroy(&st->cfg_slots_status);
712 }
713
ad7173_reset_usage_cnts(struct ad7173_state * st)714 static void ad7173_reset_usage_cnts(struct ad7173_state *st)
715 {
716 memset64(st->config_cnts, 0, st->info->num_configs);
717 st->config_usage_counter = 0;
718 }
719
720 static struct ad7173_channel_config *
ad7173_find_live_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)721 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
722 {
723 struct ad7173_channel_config *cfg_aux;
724 int i;
725
726 /*
727 * This is just to make sure that the comparison is adapted after
728 * struct ad7173_channel_config was changed.
729 */
730 static_assert(sizeof_field(struct ad7173_channel_config, config_props) ==
731 sizeof(struct {
732 bool bipolar;
733 bool input_buf;
734 u8 odr;
735 u8 ref_sel;
736 }));
737
738 for (i = 0; i < st->num_channels; i++) {
739 cfg_aux = &st->channels[i].cfg;
740
741 if (cfg_aux->live &&
742 cfg->bipolar == cfg_aux->bipolar &&
743 cfg->input_buf == cfg_aux->input_buf &&
744 cfg->odr == cfg_aux->odr &&
745 cfg->ref_sel == cfg_aux->ref_sel)
746 return cfg_aux;
747 }
748 return NULL;
749 }
750
751 /* Could be replaced with a generic LRU implementation */
ad7173_free_config_slot_lru(struct ad7173_state * st)752 static int ad7173_free_config_slot_lru(struct ad7173_state *st)
753 {
754 int i, lru_position = 0;
755
756 for (i = 1; i < st->info->num_configs; i++)
757 if (st->config_cnts[i] < st->config_cnts[lru_position])
758 lru_position = i;
759
760 for (i = 0; i < st->num_channels; i++)
761 if (st->channels[i].cfg.cfg_slot == lru_position)
762 st->channels[i].cfg.live = false;
763
764 ida_free(&st->cfg_slots_status, lru_position);
765 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
766 }
767
768 /* Could be replaced with a generic LRU implementation */
ad7173_load_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)769 static int ad7173_load_config(struct ad7173_state *st,
770 struct ad7173_channel_config *cfg)
771 {
772 unsigned int config;
773 int free_cfg_slot, ret;
774
775 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
776 st->info->num_configs - 1, GFP_KERNEL);
777 if (free_cfg_slot < 0)
778 free_cfg_slot = ad7173_free_config_slot_lru(st);
779
780 cfg->cfg_slot = free_cfg_slot;
781 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
782
783 if (cfg->bipolar)
784 config |= AD7173_SETUP_BIPOLAR;
785
786 if (cfg->input_buf)
787 config |= AD7173_SETUP_AIN_BUF_MASK;
788
789 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
790 if (ret)
791 return ret;
792
793 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
794 AD7173_FILTER_ODR0_MASK & cfg->odr);
795 }
796
ad7173_config_channel(struct ad7173_state * st,int addr)797 static int ad7173_config_channel(struct ad7173_state *st, int addr)
798 {
799 struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
800 struct ad7173_channel_config *live_cfg;
801 int ret;
802
803 if (!cfg->live) {
804 live_cfg = ad7173_find_live_config(st, cfg);
805 if (live_cfg) {
806 cfg->cfg_slot = live_cfg->cfg_slot;
807 } else {
808 ret = ad7173_load_config(st, cfg);
809 if (ret)
810 return ret;
811 cfg->live = true;
812 }
813 }
814
815 if (st->config_usage_counter == U64_MAX)
816 ad7173_reset_usage_cnts(st);
817
818 st->config_usage_counter++;
819 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
820
821 return 0;
822 }
823
ad7173_set_channel(struct ad_sigma_delta * sd,unsigned int channel)824 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
825 {
826 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
827 unsigned int val;
828 int ret;
829
830 ret = ad7173_config_channel(st, channel);
831 if (ret)
832 return ret;
833
834 val = AD7173_CH_ENABLE |
835 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
836 st->channels[channel].ain;
837
838 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
839 }
840
ad7173_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)841 static int ad7173_set_mode(struct ad_sigma_delta *sd,
842 enum ad_sigma_delta_mode mode)
843 {
844 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
845
846 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
847 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
848
849 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
850 }
851
ad7173_append_status(struct ad_sigma_delta * sd,bool append)852 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
853 {
854 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
855 unsigned int interface_mode = st->interface_mode;
856 int ret;
857
858 interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
859 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
860 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
861 if (ret)
862 return ret;
863
864 st->interface_mode = interface_mode;
865
866 return 0;
867 }
868
ad7173_disable_all(struct ad_sigma_delta * sd)869 static int ad7173_disable_all(struct ad_sigma_delta *sd)
870 {
871 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
872 int ret;
873 int i;
874
875 for (i = 0; i < st->num_channels; i++) {
876 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
877 if (ret < 0)
878 return ret;
879 }
880
881 return 0;
882 }
883
ad7173_disable_one(struct ad_sigma_delta * sd,unsigned int chan)884 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
885 {
886 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
887 }
888
889 static const struct ad_sigma_delta_info ad7173_sigma_delta_info = {
890 .set_channel = ad7173_set_channel,
891 .append_status = ad7173_append_status,
892 .disable_all = ad7173_disable_all,
893 .disable_one = ad7173_disable_one,
894 .set_mode = ad7173_set_mode,
895 .has_registers = true,
896 .addr_shift = 0,
897 .read_mask = BIT(6),
898 .status_ch_mask = GENMASK(3, 0),
899 .data_reg = AD7173_REG_DATA,
900 .num_resetclks = 64,
901 };
902
ad7173_setup(struct iio_dev * indio_dev)903 static int ad7173_setup(struct iio_dev *indio_dev)
904 {
905 struct ad7173_state *st = iio_priv(indio_dev);
906 struct device *dev = &st->sd.spi->dev;
907 u8 buf[AD7173_RESET_LENGTH];
908 unsigned int id;
909 int ret;
910
911 /* reset the serial interface */
912 memset(buf, 0xff, AD7173_RESET_LENGTH);
913 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
914 if (ret < 0)
915 return ret;
916
917 /* datasheet recommends a delay of at least 500us after reset */
918 fsleep(500);
919
920 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
921 if (ret)
922 return ret;
923
924 id &= AD7173_ID_MASK;
925 if (id != st->info->id)
926 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
927 id, st->info->id);
928
929 st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
930 st->interface_mode = 0x0;
931
932 st->config_usage_counter = 0;
933 st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
934 sizeof(*st->config_cnts), GFP_KERNEL);
935 if (!st->config_cnts)
936 return -ENOMEM;
937
938 ret = ad7173_calibrate_all(st, indio_dev);
939 if (ret)
940 return ret;
941
942 /* All channels are enabled by default after a reset */
943 return ad7173_disable_all(&st->sd);
944 }
945
ad7173_get_ref_voltage_milli(struct ad7173_state * st,u8 reference_select)946 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
947 u8 reference_select)
948 {
949 int vref;
950
951 switch (reference_select) {
952 case AD7173_SETUP_REF_SEL_EXT_REF:
953 vref = regulator_get_voltage(st->regulators[0].consumer);
954 break;
955
956 case AD7173_SETUP_REF_SEL_EXT_REF2:
957 vref = regulator_get_voltage(st->regulators[1].consumer);
958 break;
959
960 case AD7173_SETUP_REF_SEL_INT_REF:
961 vref = AD7173_VOLTAGE_INT_REF_uV;
962 break;
963
964 case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
965 vref = regulator_get_voltage(st->regulators[2].consumer);
966 break;
967
968 default:
969 return -EINVAL;
970 }
971
972 if (vref < 0)
973 return vref;
974
975 return vref / (MICRO / MILLI);
976 }
977
ad7173_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)978 static int ad7173_read_raw(struct iio_dev *indio_dev,
979 struct iio_chan_spec const *chan,
980 int *val, int *val2, long info)
981 {
982 struct ad7173_state *st = iio_priv(indio_dev);
983 struct ad7173_channel *ch = &st->channels[chan->address];
984 unsigned int reg;
985 u64 temp;
986 int ret;
987
988 switch (info) {
989 case IIO_CHAN_INFO_RAW:
990 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
991 if (ret < 0)
992 return ret;
993
994 return IIO_VAL_INT;
995 case IIO_CHAN_INFO_SCALE:
996
997 switch (chan->type) {
998 case IIO_TEMP:
999 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
1000 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
1001 *val = temp;
1002 *val2 = chan->scan_type.realbits;
1003 return IIO_VAL_FRACTIONAL_LOG2;
1004 case IIO_VOLTAGE:
1005 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
1006 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
1007
1008 if (chan->channel < st->info->num_voltage_in_div)
1009 *val *= AD4111_DIVIDER_RATIO;
1010 return IIO_VAL_FRACTIONAL_LOG2;
1011 case IIO_CURRENT:
1012 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
1013 *val /= AD4111_SHUNT_RESISTOR_OHM;
1014 *val2 = chan->scan_type.realbits - ch->cfg.bipolar;
1015 return IIO_VAL_FRACTIONAL_LOG2;
1016 default:
1017 return -EINVAL;
1018 }
1019 case IIO_CHAN_INFO_OFFSET:
1020
1021 switch (chan->type) {
1022 case IIO_TEMP:
1023 /* 0 Kelvin -> raw sample */
1024 temp = -ABSOLUTE_ZERO_MILLICELSIUS;
1025 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
1026 temp <<= chan->scan_type.realbits;
1027 temp = DIV_U64_ROUND_CLOSEST(temp,
1028 AD7173_VOLTAGE_INT_REF_uV *
1029 MILLI);
1030 *val = -temp;
1031 return IIO_VAL_INT;
1032 case IIO_VOLTAGE:
1033 case IIO_CURRENT:
1034 *val = -BIT(chan->scan_type.realbits - 1);
1035 return IIO_VAL_INT;
1036 default:
1037 return -EINVAL;
1038 }
1039 case IIO_CHAN_INFO_SAMP_FREQ:
1040 reg = st->channels[chan->address].cfg.odr;
1041
1042 *val = st->info->sinc5_data_rates[reg] / MILLI;
1043 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
1044
1045 return IIO_VAL_INT_PLUS_MICRO;
1046 default:
1047 return -EINVAL;
1048 }
1049 }
1050
ad7173_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1051 static int ad7173_write_raw(struct iio_dev *indio_dev,
1052 struct iio_chan_spec const *chan,
1053 int val, int val2, long info)
1054 {
1055 struct ad7173_state *st = iio_priv(indio_dev);
1056 struct ad7173_channel_config *cfg;
1057 unsigned int freq, i;
1058 int ret;
1059
1060 ret = iio_device_claim_direct_mode(indio_dev);
1061 if (ret)
1062 return ret;
1063
1064 switch (info) {
1065 /*
1066 * This attribute sets the sampling frequency for each channel individually.
1067 * There are no issues for raw or buffered reads of an individual channel.
1068 *
1069 * When multiple channels are enabled in buffered mode, the effective
1070 * sampling rate of a channel is lowered in correlation to the number
1071 * of channels enabled and the sampling rate of the other channels.
1072 *
1073 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
1074 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
1075 * will take 100ms each.
1076 *
1077 * This will cause the reading of CH1 to be actually done once every
1078 * 200.16ms, an effective rate of 4.99sps.
1079 */
1080 case IIO_CHAN_INFO_SAMP_FREQ:
1081 freq = val * MILLI + val2 / MILLI;
1082 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
1083 if (freq >= st->info->sinc5_data_rates[i])
1084 break;
1085
1086 cfg = &st->channels[chan->address].cfg;
1087 cfg->odr = i;
1088 cfg->live = false;
1089 break;
1090
1091 default:
1092 ret = -EINVAL;
1093 break;
1094 }
1095
1096 iio_device_release_direct_mode(indio_dev);
1097 return ret;
1098 }
1099
ad7173_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1100 static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
1101 const unsigned long *scan_mask)
1102 {
1103 struct ad7173_state *st = iio_priv(indio_dev);
1104 int i, ret;
1105
1106 for (i = 0; i < indio_dev->num_channels; i++) {
1107 if (test_bit(i, scan_mask))
1108 ret = ad7173_set_channel(&st->sd, i);
1109 else
1110 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
1111 if (ret < 0)
1112 return ret;
1113 }
1114
1115 return 0;
1116 }
1117
ad7173_debug_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1118 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1119 unsigned int writeval, unsigned int *readval)
1120 {
1121 struct ad7173_state *st = iio_priv(indio_dev);
1122 u8 reg_size;
1123
1124 if (reg == AD7173_REG_COMMS)
1125 reg_size = 1;
1126 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
1127 reg >= AD7173_REG_OFFSET(0))
1128 reg_size = 3;
1129 else
1130 reg_size = 2;
1131
1132 if (readval)
1133 return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
1134
1135 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
1136 }
1137
1138 static const struct iio_info ad7173_info = {
1139 .read_raw = &ad7173_read_raw,
1140 .write_raw = &ad7173_write_raw,
1141 .debugfs_reg_access = &ad7173_debug_reg_access,
1142 .validate_trigger = ad_sd_validate_trigger,
1143 .update_scan_mode = ad7173_update_scan_mode,
1144 };
1145
1146 static const struct iio_scan_type ad4113_scan_type = {
1147 .sign = 'u',
1148 .realbits = 16,
1149 .storagebits = 16,
1150 .endianness = IIO_BE,
1151 };
1152
1153 static const struct iio_chan_spec ad7173_channel_template = {
1154 .type = IIO_VOLTAGE,
1155 .indexed = 1,
1156 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1157 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
1158 .scan_type = {
1159 .sign = 'u',
1160 .realbits = 24,
1161 .storagebits = 32,
1162 .endianness = IIO_BE,
1163 },
1164 .ext_info = ad7173_calibsys_ext_info,
1165 };
1166
1167 static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1168 .type = IIO_TEMP,
1169 .channel = AD7173_AIN_TEMP_POS,
1170 .channel2 = AD7173_AIN_TEMP_NEG,
1171 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1172 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1173 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1174 .scan_type = {
1175 .sign = 'u',
1176 .realbits = 24,
1177 .storagebits = 32,
1178 .endianness = IIO_BE,
1179 },
1180 };
1181
ad7173_disable_regulators(void * data)1182 static void ad7173_disable_regulators(void *data)
1183 {
1184 struct ad7173_state *st = data;
1185
1186 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1187 }
1188
ad7173_clk_disable_unprepare(void * clk)1189 static void ad7173_clk_disable_unprepare(void *clk)
1190 {
1191 clk_disable_unprepare(clk);
1192 }
1193
ad7173_sel_clk(struct ad7173_state * st,unsigned int clk_sel)1194 static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1195 unsigned int clk_sel)
1196 {
1197 int ret;
1198
1199 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1200 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1201 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1202
1203 return ret;
1204 }
1205
ad7173_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1206 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1207 unsigned long parent_rate)
1208 {
1209 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1210
1211 return st->info->clock / HZ_PER_KHZ;
1212 }
1213
ad7173_clk_output_is_enabled(struct clk_hw * hw)1214 static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1215 {
1216 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1217 u32 clk_sel;
1218
1219 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1220 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1221 }
1222
ad7173_clk_output_prepare(struct clk_hw * hw)1223 static int ad7173_clk_output_prepare(struct clk_hw *hw)
1224 {
1225 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1226
1227 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1228 }
1229
ad7173_clk_output_unprepare(struct clk_hw * hw)1230 static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1231 {
1232 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1233
1234 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1235 }
1236
1237 static const struct clk_ops ad7173_int_clk_ops = {
1238 .recalc_rate = ad7173_clk_recalc_rate,
1239 .is_enabled = ad7173_clk_output_is_enabled,
1240 .prepare = ad7173_clk_output_prepare,
1241 .unprepare = ad7173_clk_output_unprepare,
1242 };
1243
ad7173_register_clk_provider(struct iio_dev * indio_dev)1244 static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1245 {
1246 struct ad7173_state *st = iio_priv(indio_dev);
1247 struct device *dev = indio_dev->dev.parent;
1248 struct fwnode_handle *fwnode = dev_fwnode(dev);
1249 struct clk_init_data init = {};
1250 int ret;
1251
1252 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1253 return 0;
1254
1255 init.name = fwnode_get_name(fwnode);
1256 init.ops = &ad7173_int_clk_ops;
1257
1258 st->int_clk_hw.init = &init;
1259 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1260 if (ret)
1261 return ret;
1262
1263 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1264 &st->int_clk_hw);
1265 }
1266
ad4111_validate_current_ain(struct ad7173_state * st,const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])1267 static int ad4111_validate_current_ain(struct ad7173_state *st,
1268 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1269 {
1270 struct device *dev = &st->sd.spi->dev;
1271
1272 if (!st->info->has_current_inputs)
1273 return dev_err_probe(dev, -EINVAL,
1274 "Model %s does not support current channels\n",
1275 st->info->name);
1276
1277 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1278 return dev_err_probe(dev, -EINVAL,
1279 "For current channels single-channel must be <[0-3]>\n");
1280
1281 return 0;
1282 }
1283
ad7173_validate_voltage_ain_inputs(struct ad7173_state * st,unsigned int ain0,unsigned int ain1)1284 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1285 unsigned int ain0, unsigned int ain1)
1286 {
1287 struct device *dev = &st->sd.spi->dev;
1288 bool special_input0, special_input1;
1289
1290 /* (AVDD1-AVSS)/5 power supply monitoring */
1291 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1292 st->info->has_pow_supply_monitoring)
1293 return 0;
1294
1295 special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1296 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1297 special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1298 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1299
1300 if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1301 (ain1 >= st->info->num_voltage_in && !special_input1)) {
1302 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1303 return dev_err_probe(dev, -EINVAL,
1304 "VINCOM not supported for %s\n", st->info->name);
1305
1306 return dev_err_probe(dev, -EINVAL,
1307 "Input pin number out of range for pair (%d %d).\n",
1308 ain0, ain1);
1309 }
1310
1311 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1312 AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1313 return dev_err_probe(dev, -EINVAL,
1314 "VINCOM must be paired with inputs having divider.\n");
1315
1316 if (!special_input0 && !special_input1 &&
1317 ((ain0 >= st->info->num_voltage_in_div) !=
1318 (ain1 >= st->info->num_voltage_in_div)))
1319 return dev_err_probe(dev, -EINVAL,
1320 "Both inputs must either have a voltage divider or not have: (%d %d).\n",
1321 ain0, ain1);
1322
1323 return 0;
1324 }
1325
ad7173_validate_reference(struct ad7173_state * st,int ref_sel)1326 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1327 {
1328 struct device *dev = &st->sd.spi->dev;
1329 int ret;
1330
1331 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1332 return dev_err_probe(dev, -EINVAL,
1333 "Internal reference is not available on current model.\n");
1334
1335 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1336 return dev_err_probe(dev, -EINVAL,
1337 "External reference 2 is not available on current model.\n");
1338
1339 ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1340 if (ret < 0)
1341 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1342 ref_sel);
1343
1344 return 0;
1345 }
1346
ad7173_fw_parse_channel_config(struct iio_dev * indio_dev)1347 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1348 {
1349 struct ad7173_channel *chans_st_arr, *chan_st_priv;
1350 struct ad7173_state *st = iio_priv(indio_dev);
1351 struct device *dev = indio_dev->dev.parent;
1352 struct iio_chan_spec *chan_arr, *chan;
1353 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1354 int ref_sel, ret, num_channels;
1355
1356 num_channels = device_get_child_node_count(dev);
1357
1358 if (st->info->has_temp)
1359 num_channels++;
1360
1361 if (num_channels == 0)
1362 return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1363
1364 if (num_channels > st->info->num_channels)
1365 return dev_err_probe(dev, -EINVAL,
1366 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1367 st->info->num_channels);
1368
1369 indio_dev->num_channels = num_channels;
1370 st->num_channels = num_channels;
1371
1372 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1373 st->num_channels, GFP_KERNEL);
1374 if (!chan_arr)
1375 return -ENOMEM;
1376
1377 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1378 GFP_KERNEL);
1379 if (!chans_st_arr)
1380 return -ENOMEM;
1381
1382 indio_dev->channels = chan_arr;
1383 st->channels = chans_st_arr;
1384
1385 if (st->info->has_temp) {
1386 chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1387 chan_st_priv = &chans_st_arr[chan_index];
1388 chan_st_priv->ain =
1389 AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1390 chan_arr[chan_index].channel2);
1391 chan_st_priv->cfg.bipolar = false;
1392 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1393 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1394 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1395 if (st->info->data_reg_only_16bit)
1396 chan_arr[chan_index].scan_type = ad4113_scan_type;
1397
1398 chan_index++;
1399 }
1400
1401 device_for_each_child_node_scoped(dev, child) {
1402 bool is_current_chan = false;
1403
1404 chan = &chan_arr[chan_index];
1405 *chan = ad7173_channel_template;
1406 chan_st_priv = &chans_st_arr[chan_index];
1407 ret = fwnode_property_read_u32_array(child, "diff-channels",
1408 ain, ARRAY_SIZE(ain));
1409 if (ret) {
1410 ret = fwnode_property_read_u32(child, "single-channel",
1411 ain);
1412 if (ret)
1413 return dev_err_probe(dev, ret,
1414 "Channel must define one of diff-channels or single-channel.\n");
1415
1416 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1417 } else {
1418 chan->differential = true;
1419 }
1420
1421 if (is_current_chan) {
1422 ret = ad4111_validate_current_ain(st, ain);
1423 if (ret)
1424 return ret;
1425 } else {
1426 if (!chan->differential) {
1427 ret = fwnode_property_read_u32(child,
1428 "common-mode-channel", ain + 1);
1429 if (ret)
1430 return dev_err_probe(dev, ret,
1431 "common-mode-channel must be defined for single-ended channels.\n");
1432 }
1433 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1434 if (ret)
1435 return ret;
1436 }
1437
1438 ret = fwnode_property_match_property_string(child,
1439 "adi,reference-select",
1440 ad7173_ref_sel_str,
1441 ARRAY_SIZE(ad7173_ref_sel_str));
1442 if (ret < 0)
1443 ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1444 else
1445 ref_sel = ret;
1446
1447 ret = ad7173_validate_reference(st, ref_sel);
1448 if (ret)
1449 return ret;
1450
1451 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1452 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1453 chan_st_priv->cfg.ref_sel = ref_sel;
1454
1455 chan->address = chan_index;
1456 chan->scan_index = chan_index;
1457 chan->channel = ain[0];
1458 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1459 chan_st_priv->cfg.odr = 0;
1460
1461 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1462 if (chan_st_priv->cfg.bipolar)
1463 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1464
1465 if (is_current_chan) {
1466 chan->type = IIO_CURRENT;
1467 chan->differential = false;
1468 chan->channel2 = 0;
1469 chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1470 } else {
1471 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1472 chan->channel2 = ain[1];
1473 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1474 }
1475
1476 if (st->info->data_reg_only_16bit)
1477 chan_arr[chan_index].scan_type = ad4113_scan_type;
1478
1479 chan_index++;
1480 }
1481 return 0;
1482 }
1483
ad7173_fw_parse_device_config(struct iio_dev * indio_dev)1484 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1485 {
1486 struct ad7173_state *st = iio_priv(indio_dev);
1487 struct device *dev = indio_dev->dev.parent;
1488 int ret;
1489
1490 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1491 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1492 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1493
1494 /*
1495 * If a regulator is not available, it will be set to a dummy regulator.
1496 * Each channel reference is checked with regulator_get_voltage() before
1497 * setting attributes so if any channel uses a dummy supply the driver
1498 * probe will fail.
1499 */
1500 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1501 st->regulators);
1502 if (ret)
1503 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1504
1505 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1506 if (ret)
1507 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1508
1509 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1510 if (ret)
1511 return dev_err_probe(dev, ret,
1512 "Failed to add regulators disable action\n");
1513
1514 ret = device_property_match_property_string(dev, "clock-names",
1515 ad7173_clk_sel,
1516 ARRAY_SIZE(ad7173_clk_sel));
1517 if (ret < 0) {
1518 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1519 AD7173_ADC_MODE_CLOCKSEL_INT);
1520 ad7173_register_clk_provider(indio_dev);
1521 } else {
1522 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1523 AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1524 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
1525 if (IS_ERR(st->ext_clk))
1526 return dev_err_probe(dev, PTR_ERR(st->ext_clk),
1527 "Failed to get external clock\n");
1528
1529 ret = clk_prepare_enable(st->ext_clk);
1530 if (ret)
1531 return dev_err_probe(dev, ret,
1532 "Failed to enable external clock\n");
1533
1534 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1535 st->ext_clk);
1536 if (ret)
1537 return ret;
1538 }
1539
1540 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1541 if (ret < 0)
1542 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1543
1544 st->sigma_delta_info.irq_line = ret;
1545
1546 return ad7173_fw_parse_channel_config(indio_dev);
1547 }
1548
ad7173_probe(struct spi_device * spi)1549 static int ad7173_probe(struct spi_device *spi)
1550 {
1551 struct device *dev = &spi->dev;
1552 struct ad7173_state *st;
1553 struct iio_dev *indio_dev;
1554 int ret;
1555
1556 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1557 if (!indio_dev)
1558 return -ENOMEM;
1559
1560 st = iio_priv(indio_dev);
1561 st->info = spi_get_device_match_data(spi);
1562 if (!st->info)
1563 return -ENODEV;
1564
1565 ida_init(&st->cfg_slots_status);
1566 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1567 if (ret)
1568 return ret;
1569
1570 indio_dev->name = st->info->name;
1571 indio_dev->modes = INDIO_DIRECT_MODE;
1572 indio_dev->info = &ad7173_info;
1573
1574 spi->mode = SPI_MODE_3;
1575 spi_setup(spi);
1576
1577 st->sigma_delta_info = ad7173_sigma_delta_info;
1578 st->sigma_delta_info.num_slots = st->info->num_configs;
1579 ret = ad_sd_init(&st->sd, indio_dev, spi, &st->sigma_delta_info);
1580 if (ret)
1581 return ret;
1582
1583 ret = ad7173_fw_parse_device_config(indio_dev);
1584 if (ret)
1585 return ret;
1586
1587 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1588 if (ret)
1589 return ret;
1590
1591 ret = ad7173_setup(indio_dev);
1592 if (ret)
1593 return ret;
1594
1595 ret = devm_iio_device_register(dev, indio_dev);
1596 if (ret)
1597 return ret;
1598
1599 if (IS_ENABLED(CONFIG_GPIOLIB))
1600 return ad7173_gpio_init(st);
1601
1602 return 0;
1603 }
1604
1605 static const struct of_device_id ad7173_of_match[] = {
1606 { .compatible = "adi,ad4111", .data = &ad4111_device_info },
1607 { .compatible = "adi,ad4112", .data = &ad4112_device_info },
1608 { .compatible = "adi,ad4113", .data = &ad4113_device_info },
1609 { .compatible = "adi,ad4114", .data = &ad4114_device_info },
1610 { .compatible = "adi,ad4115", .data = &ad4115_device_info },
1611 { .compatible = "adi,ad4116", .data = &ad4116_device_info },
1612 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1613 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1614 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
1615 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
1616 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
1617 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
1618 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
1619 { }
1620 };
1621 MODULE_DEVICE_TABLE(of, ad7173_of_match);
1622
1623 static const struct spi_device_id ad7173_id_table[] = {
1624 { "ad4111", (kernel_ulong_t)&ad4111_device_info },
1625 { "ad4112", (kernel_ulong_t)&ad4112_device_info },
1626 { "ad4113", (kernel_ulong_t)&ad4113_device_info },
1627 { "ad4114", (kernel_ulong_t)&ad4114_device_info },
1628 { "ad4115", (kernel_ulong_t)&ad4115_device_info },
1629 { "ad4116", (kernel_ulong_t)&ad4116_device_info },
1630 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
1631 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
1632 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
1633 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
1634 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
1635 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
1636 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
1637 { }
1638 };
1639 MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1640
1641 static struct spi_driver ad7173_driver = {
1642 .driver = {
1643 .name = "ad7173",
1644 .of_match_table = ad7173_of_match,
1645 },
1646 .probe = ad7173_probe,
1647 .id_table = ad7173_id_table,
1648 };
1649 module_spi_driver(ad7173_driver);
1650
1651 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1652 MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
1653 MODULE_AUTHOR("Dumitru Ceclan <[email protected]>");
1654 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
1655 MODULE_LICENSE("GPL");
1656