1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI DAVINCI I2C adapter driver.
4 *
5 * Copyright (C) 2006 Texas Instruments.
6 * Copyright (C) 2007 MontaVista Software Inc.
7 *
8 * Updated by Vinod & Sudhakar Feb 2005
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * ----------------------------------------------------------------------------
13 */
14
15 #include <linux/clk.h>
16 #include <linux/cpufreq.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/property.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31
32 /* ----- global defines ----------------------------------------------- */
33
34 #define DAVINCI_I2C_TIMEOUT (1*HZ)
35 #define DAVINCI_I2C_MAX_TRIES 2
36 #define DAVINCI_I2C_OWN_ADDRESS 0x08
37 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
38 DAVINCI_I2C_IMR_ARDY | \
39 DAVINCI_I2C_IMR_NACK | \
40 DAVINCI_I2C_IMR_AL)
41
42 #define DAVINCI_I2C_OAR_REG 0x00
43 #define DAVINCI_I2C_IMR_REG 0x04
44 #define DAVINCI_I2C_STR_REG 0x08
45 #define DAVINCI_I2C_CLKL_REG 0x0c
46 #define DAVINCI_I2C_CLKH_REG 0x10
47 #define DAVINCI_I2C_CNT_REG 0x14
48 #define DAVINCI_I2C_DRR_REG 0x18
49 #define DAVINCI_I2C_SAR_REG 0x1c
50 #define DAVINCI_I2C_DXR_REG 0x20
51 #define DAVINCI_I2C_MDR_REG 0x24
52 #define DAVINCI_I2C_IVR_REG 0x28
53 #define DAVINCI_I2C_EMDR_REG 0x2c
54 #define DAVINCI_I2C_PSC_REG 0x30
55 #define DAVINCI_I2C_FUNC_REG 0x48
56 #define DAVINCI_I2C_DIR_REG 0x4c
57 #define DAVINCI_I2C_DIN_REG 0x50
58 #define DAVINCI_I2C_DOUT_REG 0x54
59 #define DAVINCI_I2C_DSET_REG 0x58
60 #define DAVINCI_I2C_DCLR_REG 0x5c
61
62 #define DAVINCI_I2C_IVR_AAS 0x07
63 #define DAVINCI_I2C_IVR_SCD 0x06
64 #define DAVINCI_I2C_IVR_XRDY 0x05
65 #define DAVINCI_I2C_IVR_RDR 0x04
66 #define DAVINCI_I2C_IVR_ARDY 0x03
67 #define DAVINCI_I2C_IVR_NACK 0x02
68 #define DAVINCI_I2C_IVR_AL 0x01
69
70 #define DAVINCI_I2C_STR_BB BIT(12)
71 #define DAVINCI_I2C_STR_RSFULL BIT(11)
72 #define DAVINCI_I2C_STR_SCD BIT(5)
73 #define DAVINCI_I2C_STR_ARDY BIT(2)
74 #define DAVINCI_I2C_STR_NACK BIT(1)
75 #define DAVINCI_I2C_STR_AL BIT(0)
76
77 #define DAVINCI_I2C_MDR_NACK BIT(15)
78 #define DAVINCI_I2C_MDR_STT BIT(13)
79 #define DAVINCI_I2C_MDR_STP BIT(11)
80 #define DAVINCI_I2C_MDR_MST BIT(10)
81 #define DAVINCI_I2C_MDR_TRX BIT(9)
82 #define DAVINCI_I2C_MDR_XA BIT(8)
83 #define DAVINCI_I2C_MDR_RM BIT(7)
84 #define DAVINCI_I2C_MDR_IRS BIT(5)
85
86 #define DAVINCI_I2C_IMR_AAS BIT(6)
87 #define DAVINCI_I2C_IMR_SCD BIT(5)
88 #define DAVINCI_I2C_IMR_XRDY BIT(4)
89 #define DAVINCI_I2C_IMR_RRDY BIT(3)
90 #define DAVINCI_I2C_IMR_ARDY BIT(2)
91 #define DAVINCI_I2C_IMR_NACK BIT(1)
92 #define DAVINCI_I2C_IMR_AL BIT(0)
93
94 /* set SDA and SCL as GPIO */
95 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
96
97 /* set SCL as output when used as GPIO*/
98 #define DAVINCI_I2C_DIR_PDIR0 BIT(0)
99 /* set SDA as output when used as GPIO*/
100 #define DAVINCI_I2C_DIR_PDIR1 BIT(1)
101
102 /* read SCL GPIO level */
103 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
104 /* read SDA GPIO level */
105 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
106
107 /*set the SCL GPIO high */
108 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
109 /*set the SDA GPIO high */
110 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
111
112 /* set the SCL GPIO low */
113 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
114 /* set the SDA GPIO low */
115 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
116
117 /* timeout for pm runtime autosuspend */
118 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */
119
120 #define DAVINCI_I2C_DEFAULT_BUS_FREQ 100
121
122 struct davinci_i2c_dev {
123 struct device *dev;
124 void __iomem *base;
125 struct completion cmd_complete;
126 struct clk *clk;
127 int cmd_err;
128 u8 *buf;
129 size_t buf_len;
130 int irq;
131 int stop;
132 u8 terminate;
133 struct i2c_adapter adapter;
134 #ifdef CONFIG_CPU_FREQ
135 struct notifier_block freq_transition;
136 #endif
137 /* standard bus frequency (kHz) */
138 unsigned int bus_freq;
139 /* Chip has a ICPFUNC register */
140 bool has_pfunc;
141 };
142
davinci_i2c_write_reg(struct davinci_i2c_dev * i2c_dev,int reg,u16 val)143 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
144 int reg, u16 val)
145 {
146 writew_relaxed(val, i2c_dev->base + reg);
147 }
148
davinci_i2c_read_reg(struct davinci_i2c_dev * i2c_dev,int reg)149 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
150 {
151 return readw_relaxed(i2c_dev->base + reg);
152 }
153
davinci_i2c_reset_ctrl(struct davinci_i2c_dev * i2c_dev,int val)154 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
155 int val)
156 {
157 u16 w;
158
159 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
160 if (!val) /* put I2C into reset */
161 w &= ~DAVINCI_I2C_MDR_IRS;
162 else /* take I2C out of reset */
163 w |= DAVINCI_I2C_MDR_IRS;
164
165 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
166 }
167
i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev * dev)168 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
169 {
170 u16 psc;
171 u32 clk;
172 u32 d;
173 u32 clkh;
174 u32 clkl;
175 u32 input_clock = clk_get_rate(dev->clk);
176
177 /* NOTE: I2C Clock divider programming info
178 * As per I2C specs the following formulas provide prescaler
179 * and low/high divider values
180 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
181 * module clk
182 *
183 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
184 *
185 * Thus,
186 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
187 *
188 * where if PSC == 0, d = 7,
189 * if PSC == 1, d = 6
190 * if PSC > 1 , d = 5
191 *
192 * Note:
193 * d is always 6 on Keystone I2C controller
194 */
195
196 /*
197 * Both Davinci and current Keystone User Guides recommend a value
198 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
199 * always produce enough margin between SDA and SCL transitions.
200 * Measurements show that the higher the module clock is, the
201 * bigger is the margin, providing more reliable communication.
202 * So we better target for 12MHz.
203 */
204 psc = (input_clock / 12000000) - 1;
205 if ((input_clock / (psc + 1)) > 12000000)
206 psc++; /* better to run under spec than over */
207 d = (psc >= 2) ? 5 : 7 - psc;
208
209 if (device_is_compatible(dev->dev, "ti,keystone-i2c"))
210 d = 6;
211
212 clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000));
213 /* Avoid driving the bus too fast because of rounding errors above */
214 if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000)
215 clk++;
216 /*
217 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
218 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
219 * to LOW ratio as 1 to 2 is more safe.
220 */
221 if (dev->bus_freq > 100)
222 clkl = (clk << 1) / 3;
223 else
224 clkl = (clk >> 1);
225 /*
226 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
227 * to minimal possible clkh in this case.
228 *
229 * Note:
230 * CLKH is not allowed to be 0, in this case I2C clock is not generated
231 * at all
232 */
233 if (clk > clkl + d) {
234 clkh = clk - clkl - d;
235 clkl -= d;
236 } else {
237 clkh = 1;
238 clkl = clk - (d << 1);
239 }
240
241 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
242 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
243 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
244
245 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
246 }
247
248 /*
249 * This function configures I2C and brings I2C out of reset.
250 * This function is called during I2C init function. This function
251 * also gets called if I2C encounters any errors.
252 */
i2c_davinci_init(struct davinci_i2c_dev * dev)253 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
254 {
255 /* put I2C into reset */
256 davinci_i2c_reset_ctrl(dev, 0);
257
258 /* compute clock dividers */
259 i2c_davinci_calc_clk_dividers(dev);
260
261 /* Respond at reserved "SMBus Host" target address" (and zero);
262 * we seem to have no option to not respond...
263 */
264 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
265
266 dev_dbg(dev->dev, "PSC = %d\n",
267 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
268 dev_dbg(dev->dev, "CLKL = %d\n",
269 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
270 dev_dbg(dev->dev, "CLKH = %d\n",
271 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
272 dev_dbg(dev->dev, "bus_freq = %dkHz\n", dev->bus_freq);
273
274
275 /* Take the I2C module out of reset: */
276 davinci_i2c_reset_ctrl(dev, 1);
277
278 /* Enable interrupts */
279 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
280
281 return 0;
282 }
283
284 /*
285 * This routine does i2c bus recovery by using i2c_generic_scl_recovery
286 * which is provided by I2C Bus recovery infrastructure.
287 */
davinci_i2c_prepare_recovery(struct i2c_adapter * adap)288 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
289 {
290 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
291
292 /* Disable interrupts */
293 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
294
295 /* put I2C into reset */
296 davinci_i2c_reset_ctrl(dev, 0);
297 }
298
davinci_i2c_unprepare_recovery(struct i2c_adapter * adap)299 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
300 {
301 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
302
303 i2c_davinci_init(dev);
304 }
305
davinci_i2c_set_scl(struct i2c_adapter * adap,int val)306 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
307 {
308 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
309
310 if (val)
311 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
312 DAVINCI_I2C_DSET_PDSET0);
313 else
314 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
315 DAVINCI_I2C_DCLR_PDCLR0);
316 }
317
davinci_i2c_get_scl(struct i2c_adapter * adap)318 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
319 {
320 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
321 int val;
322
323 /* read the state of SCL */
324 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
325 return val & DAVINCI_I2C_DIN_PDIN0;
326 }
327
davinci_i2c_get_sda(struct i2c_adapter * adap)328 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
329 {
330 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
331 int val;
332
333 /* read the state of SDA */
334 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
335 return val & DAVINCI_I2C_DIN_PDIN1;
336 }
337
davinci_i2c_scl_prepare_recovery(struct i2c_adapter * adap)338 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
339 {
340 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
341
342 davinci_i2c_prepare_recovery(adap);
343
344 /* SCL output, SDA input */
345 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
346
347 /* change to GPIO mode */
348 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
349 DAVINCI_I2C_FUNC_PFUNC0);
350 }
351
davinci_i2c_scl_unprepare_recovery(struct i2c_adapter * adap)352 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
353 {
354 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
355
356 /* change back to I2C mode */
357 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
358
359 davinci_i2c_unprepare_recovery(adap);
360 }
361
362 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
363 .recover_bus = i2c_generic_scl_recovery,
364 .set_scl = davinci_i2c_set_scl,
365 .get_scl = davinci_i2c_get_scl,
366 .get_sda = davinci_i2c_get_sda,
367 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
368 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
369 };
370
371 /*
372 * Waiting for bus not busy
373 */
i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev * dev)374 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
375 {
376 unsigned long timeout = jiffies + dev->adapter.timeout;
377
378 do {
379 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
380 return 0;
381 schedule_timeout_uninterruptible(1);
382 } while (time_before_eq(jiffies, timeout));
383
384 dev_warn(dev->dev, "timeout waiting for bus ready\n");
385 i2c_recover_bus(&dev->adapter);
386
387 /*
388 * if bus is still "busy" here, it's most probably a HW problem like
389 * short-circuit
390 */
391 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
392 return -EIO;
393
394 return 0;
395 }
396
397 /*
398 * Low level read/write transaction. This function is called from
399 * i2c_davinci_xfer.
400 */
401 static int
i2c_davinci_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)402 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
403 {
404 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
405 u32 flag;
406 u16 w;
407 unsigned long time_left;
408
409 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
410 dev_warn(dev->dev, "transfer to own address aborted\n");
411 return -EADDRNOTAVAIL;
412 }
413
414 /* set the target address */
415 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
416
417 dev->buf = msg->buf;
418 dev->buf_len = msg->len;
419 dev->stop = stop;
420
421 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
422
423 reinit_completion(&dev->cmd_complete);
424 dev->cmd_err = 0;
425
426 /* Take I2C out of reset and configure it as controller */
427 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
428
429 if (msg->flags & I2C_M_TEN)
430 flag |= DAVINCI_I2C_MDR_XA;
431 if (!(msg->flags & I2C_M_RD))
432 flag |= DAVINCI_I2C_MDR_TRX;
433 if (msg->len == 0)
434 flag |= DAVINCI_I2C_MDR_RM;
435
436 /* Enable receive or transmit interrupts */
437 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
438 if (msg->flags & I2C_M_RD)
439 w |= DAVINCI_I2C_IMR_RRDY;
440 else
441 w |= DAVINCI_I2C_IMR_XRDY;
442 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
443
444 dev->terminate = 0;
445
446 /*
447 * Write mode register first as needed for correct behaviour
448 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
449 * occurring before we have loaded DXR
450 */
451 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
452
453 /*
454 * First byte should be set here, not after interrupt,
455 * because transmit-data-ready interrupt can come before
456 * NACK-interrupt during sending of previous message and
457 * ICDXR may have wrong data
458 * It also saves us one interrupt, slightly faster
459 */
460 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
461 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
462 dev->buf_len--;
463 }
464
465 /* Set STT to begin transmit now DXR is loaded */
466 flag |= DAVINCI_I2C_MDR_STT;
467 if (stop && msg->len != 0)
468 flag |= DAVINCI_I2C_MDR_STP;
469 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
470
471 time_left = wait_for_completion_timeout(&dev->cmd_complete,
472 dev->adapter.timeout);
473 if (!time_left) {
474 i2c_recover_bus(adap);
475 dev->buf_len = 0;
476 return -ETIMEDOUT;
477 }
478 if (dev->buf_len) {
479 /* This should be 0 if all bytes were transferred
480 * or dev->cmd_err denotes an error.
481 */
482 dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
483 dev->buf_len);
484 dev->terminate = 1;
485 wmb();
486 dev->buf_len = 0;
487 return -EREMOTEIO;
488 }
489
490 /* no error */
491 if (likely(!dev->cmd_err))
492 return msg->len;
493
494 /* We have an error */
495 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
496 i2c_davinci_init(dev);
497 return -EIO;
498 }
499
500 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
501 if (msg->flags & I2C_M_IGNORE_NAK)
502 return msg->len;
503 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
504 w |= DAVINCI_I2C_MDR_STP;
505 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
506 return -EREMOTEIO;
507 }
508 return -EIO;
509 }
510
511 /*
512 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
513 */
514 static int
i2c_davinci_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)515 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
516 {
517 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
518 int i;
519 int ret;
520
521 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
522
523 ret = pm_runtime_resume_and_get(dev->dev);
524 if (ret < 0) {
525 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
526 return ret;
527 }
528
529 ret = i2c_davinci_wait_bus_not_busy(dev);
530 if (ret < 0) {
531 dev_warn(dev->dev, "timeout waiting for bus ready\n");
532 goto out;
533 }
534
535 for (i = 0; i < num; i++) {
536 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
537 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
538 ret);
539 if (ret < 0)
540 goto out;
541 }
542
543 ret = num;
544
545 out:
546 pm_runtime_mark_last_busy(dev->dev);
547 pm_runtime_put_autosuspend(dev->dev);
548
549 return ret;
550 }
551
i2c_davinci_func(struct i2c_adapter * adap)552 static u32 i2c_davinci_func(struct i2c_adapter *adap)
553 {
554 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
555 }
556
terminate_read(struct davinci_i2c_dev * dev)557 static void terminate_read(struct davinci_i2c_dev *dev)
558 {
559 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
560 w |= DAVINCI_I2C_MDR_NACK;
561 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
562
563 /* Throw away data */
564 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
565 if (!dev->terminate)
566 dev_err(dev->dev, "RDR IRQ while no data requested\n");
567 }
terminate_write(struct davinci_i2c_dev * dev)568 static void terminate_write(struct davinci_i2c_dev *dev)
569 {
570 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
571 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
572 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
573
574 if (!dev->terminate)
575 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
576 }
577
578 /*
579 * Interrupt service routine. This gets called whenever an I2C interrupt
580 * occurs.
581 */
i2c_davinci_isr(int this_irq,void * dev_id)582 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
583 {
584 struct davinci_i2c_dev *dev = dev_id;
585 u32 stat;
586 int count = 0;
587 u16 w;
588
589 if (pm_runtime_suspended(dev->dev))
590 return IRQ_NONE;
591
592 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
593 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
594 if (count++ == 100) {
595 dev_warn(dev->dev, "Too much work in one IRQ\n");
596 break;
597 }
598
599 switch (stat) {
600 case DAVINCI_I2C_IVR_AL:
601 /* Arbitration lost, must retry */
602 dev->cmd_err |= DAVINCI_I2C_STR_AL;
603 dev->buf_len = 0;
604 complete(&dev->cmd_complete);
605 break;
606
607 case DAVINCI_I2C_IVR_NACK:
608 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
609 dev->buf_len = 0;
610 complete(&dev->cmd_complete);
611 break;
612
613 case DAVINCI_I2C_IVR_ARDY:
614 davinci_i2c_write_reg(dev,
615 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
616 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
617 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
618 w = davinci_i2c_read_reg(dev,
619 DAVINCI_I2C_MDR_REG);
620 w |= DAVINCI_I2C_MDR_STP;
621 davinci_i2c_write_reg(dev,
622 DAVINCI_I2C_MDR_REG, w);
623 }
624 complete(&dev->cmd_complete);
625 break;
626
627 case DAVINCI_I2C_IVR_RDR:
628 if (dev->buf_len) {
629 *dev->buf++ =
630 davinci_i2c_read_reg(dev,
631 DAVINCI_I2C_DRR_REG);
632 dev->buf_len--;
633 if (dev->buf_len)
634 continue;
635
636 davinci_i2c_write_reg(dev,
637 DAVINCI_I2C_STR_REG,
638 DAVINCI_I2C_IMR_RRDY);
639 } else {
640 /* signal can terminate transfer */
641 terminate_read(dev);
642 }
643 break;
644
645 case DAVINCI_I2C_IVR_XRDY:
646 if (dev->buf_len) {
647 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
648 *dev->buf++);
649 dev->buf_len--;
650 if (dev->buf_len)
651 continue;
652
653 w = davinci_i2c_read_reg(dev,
654 DAVINCI_I2C_IMR_REG);
655 w &= ~DAVINCI_I2C_IMR_XRDY;
656 davinci_i2c_write_reg(dev,
657 DAVINCI_I2C_IMR_REG,
658 w);
659 } else {
660 /* signal can terminate transfer */
661 terminate_write(dev);
662 }
663 break;
664
665 case DAVINCI_I2C_IVR_SCD:
666 davinci_i2c_write_reg(dev,
667 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
668 complete(&dev->cmd_complete);
669 break;
670
671 case DAVINCI_I2C_IVR_AAS:
672 dev_dbg(dev->dev, "Address as target interrupt\n");
673 break;
674
675 default:
676 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
677 break;
678 }
679 }
680
681 return count ? IRQ_HANDLED : IRQ_NONE;
682 }
683
684 #ifdef CONFIG_CPU_FREQ
i2c_davinci_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)685 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
686 unsigned long val, void *data)
687 {
688 struct davinci_i2c_dev *dev;
689
690 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
691
692 i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
693 if (val == CPUFREQ_PRECHANGE) {
694 davinci_i2c_reset_ctrl(dev, 0);
695 } else if (val == CPUFREQ_POSTCHANGE) {
696 i2c_davinci_calc_clk_dividers(dev);
697 davinci_i2c_reset_ctrl(dev, 1);
698 }
699 i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
700
701 return 0;
702 }
703
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)704 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
705 {
706 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
707
708 return cpufreq_register_notifier(&dev->freq_transition,
709 CPUFREQ_TRANSITION_NOTIFIER);
710 }
711
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)712 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
713 {
714 cpufreq_unregister_notifier(&dev->freq_transition,
715 CPUFREQ_TRANSITION_NOTIFIER);
716 }
717 #else
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)718 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
719 {
720 return 0;
721 }
722
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)723 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
724 {
725 }
726 #endif
727
728 static const struct i2c_algorithm i2c_davinci_algo = {
729 .xfer = i2c_davinci_xfer,
730 .functionality = i2c_davinci_func,
731 };
732
733 static const struct of_device_id davinci_i2c_of_match[] = {
734 {.compatible = "ti,davinci-i2c", },
735 {.compatible = "ti,keystone-i2c", },
736 {},
737 };
738 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
739
davinci_i2c_probe(struct platform_device * pdev)740 static int davinci_i2c_probe(struct platform_device *pdev)
741 {
742 struct davinci_i2c_dev *dev;
743 struct i2c_adapter *adap;
744 int r, irq;
745 u32 prop;
746
747 irq = platform_get_irq(pdev, 0);
748 if (irq < 0)
749 return irq;
750
751 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
752 if (!dev)
753 return -ENOMEM;
754
755 init_completion(&dev->cmd_complete);
756
757 dev->dev = &pdev->dev;
758 dev->irq = irq;
759 platform_set_drvdata(pdev, dev);
760
761 r = device_property_read_u32(&pdev->dev, "clock-frequency", &prop);
762 if (r)
763 prop = DAVINCI_I2C_DEFAULT_BUS_FREQ;
764
765 dev->bus_freq = prop / 1000;
766
767 dev->has_pfunc = device_property_present(&pdev->dev, "ti,has-pfunc");
768
769 dev->clk = devm_clk_get(&pdev->dev, NULL);
770 if (IS_ERR(dev->clk))
771 return PTR_ERR(dev->clk);
772
773 dev->base = devm_platform_ioremap_resource(pdev, 0);
774 if (IS_ERR(dev->base)) {
775 return PTR_ERR(dev->base);
776 }
777
778 pm_runtime_set_autosuspend_delay(dev->dev,
779 DAVINCI_I2C_PM_TIMEOUT);
780 pm_runtime_use_autosuspend(dev->dev);
781
782 pm_runtime_enable(dev->dev);
783
784 r = pm_runtime_resume_and_get(dev->dev);
785 if (r < 0) {
786 dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
787 goto err_pm;
788 }
789
790 i2c_davinci_init(dev);
791
792 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
793 pdev->name, dev);
794 if (r) {
795 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
796 goto err_unuse_clocks;
797 }
798
799 r = i2c_davinci_cpufreq_register(dev);
800 if (r) {
801 dev_err(&pdev->dev, "failed to register cpufreq\n");
802 goto err_unuse_clocks;
803 }
804
805 adap = &dev->adapter;
806 i2c_set_adapdata(adap, dev);
807 adap->owner = THIS_MODULE;
808 adap->class = I2C_CLASS_DEPRECATED;
809 strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
810 adap->algo = &i2c_davinci_algo;
811 adap->dev.parent = &pdev->dev;
812 adap->timeout = DAVINCI_I2C_TIMEOUT;
813 adap->dev.of_node = dev_of_node(&pdev->dev);
814
815 if (dev->has_pfunc)
816 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
817
818 adap->nr = pdev->id;
819 r = i2c_add_numbered_adapter(adap);
820 if (r)
821 goto err_unuse_clocks;
822
823 pm_runtime_mark_last_busy(dev->dev);
824 pm_runtime_put_autosuspend(dev->dev);
825
826 return 0;
827
828 err_unuse_clocks:
829 pm_runtime_dont_use_autosuspend(dev->dev);
830 pm_runtime_put_sync(dev->dev);
831 err_pm:
832 pm_runtime_disable(dev->dev);
833
834 return r;
835 }
836
davinci_i2c_remove(struct platform_device * pdev)837 static void davinci_i2c_remove(struct platform_device *pdev)
838 {
839 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
840 int ret;
841
842 i2c_davinci_cpufreq_deregister(dev);
843
844 i2c_del_adapter(&dev->adapter);
845
846 ret = pm_runtime_get_sync(&pdev->dev);
847 if (ret < 0)
848 dev_err(&pdev->dev, "Failed to resume device\n");
849 else
850 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
851
852 pm_runtime_dont_use_autosuspend(dev->dev);
853 pm_runtime_put_sync(dev->dev);
854 pm_runtime_disable(dev->dev);
855 }
856
davinci_i2c_suspend(struct device * dev)857 static int davinci_i2c_suspend(struct device *dev)
858 {
859 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
860
861 /* put I2C into reset */
862 davinci_i2c_reset_ctrl(i2c_dev, 0);
863
864 return 0;
865 }
866
davinci_i2c_resume(struct device * dev)867 static int davinci_i2c_resume(struct device *dev)
868 {
869 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
870
871 /* take I2C out of reset */
872 davinci_i2c_reset_ctrl(i2c_dev, 1);
873
874 return 0;
875 }
876
877 static const struct dev_pm_ops davinci_i2c_pm = {
878 .suspend = davinci_i2c_suspend,
879 .resume = davinci_i2c_resume,
880 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
881 pm_runtime_force_resume)
882 };
883
884 static const struct platform_device_id davinci_i2c_driver_ids[] = {
885 { .name = "i2c_davinci", },
886 { /* sentinel */ }
887 };
888 MODULE_DEVICE_TABLE(platform, davinci_i2c_driver_ids);
889
890 static struct platform_driver davinci_i2c_driver = {
891 .probe = davinci_i2c_probe,
892 .remove = davinci_i2c_remove,
893 .id_table = davinci_i2c_driver_ids,
894 .driver = {
895 .name = "i2c_davinci",
896 .pm = pm_sleep_ptr(&davinci_i2c_pm),
897 .of_match_table = davinci_i2c_of_match,
898 },
899 };
900
901 /* I2C may be needed to bring up other drivers */
davinci_i2c_init_driver(void)902 static int __init davinci_i2c_init_driver(void)
903 {
904 return platform_driver_register(&davinci_i2c_driver);
905 }
906 subsys_initcall(davinci_i2c_init_driver);
907
davinci_i2c_exit_driver(void)908 static void __exit davinci_i2c_exit_driver(void)
909 {
910 platform_driver_unregister(&davinci_i2c_driver);
911 }
912 module_exit(davinci_i2c_exit_driver);
913
914 MODULE_AUTHOR("Texas Instruments India");
915 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
916 MODULE_LICENSE("GPL");
917