1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_PRIV_H
7 #define _CORESIGHT_PRIV_H
8
9 #include <linux/amba/bus.h>
10 #include <linux/bitops.h>
11 #include <linux/io.h>
12 #include <linux/coresight.h>
13 #include <linux/pm_runtime.h>
14
15 extern struct mutex coresight_mutex;
16 extern const struct device_type coresight_dev_type[];
17
18 /*
19 * Coresight management registers (0xf00-0xfcc)
20 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
21 * Trace registers in PFTv1.1
22 */
23 #define CORESIGHT_ITCTRL 0xf00
24 #define CORESIGHT_CLAIMSET 0xfa0
25 #define CORESIGHT_CLAIMCLR 0xfa4
26 #define CORESIGHT_LAR 0xfb0
27 #define CORESIGHT_LSR 0xfb4
28 #define CORESIGHT_DEVARCH 0xfbc
29 #define CORESIGHT_AUTHSTATUS 0xfb8
30 #define CORESIGHT_DEVID 0xfc8
31 #define CORESIGHT_DEVTYPE 0xfcc
32
33
34 /*
35 * Coresight device CLAIM protocol.
36 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
37 */
38 #define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
39
40 #define TIMEOUT_US 100
41 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
42
43 #define ETM_MODE_EXCL_KERN BIT(30)
44 #define ETM_MODE_EXCL_USER BIT(31)
45 #define ETM_MODE_EXCL_HOST BIT(32)
46 #define ETM_MODE_EXCL_GUEST BIT(33)
47
48 struct cs_pair_attribute {
49 struct device_attribute attr;
50 u32 lo_off;
51 u32 hi_off;
52 };
53
54 struct cs_off_attribute {
55 struct device_attribute attr;
56 u32 off;
57 };
58
59 extern ssize_t coresight_simple_show32(struct device *_dev,
60 struct device_attribute *attr, char *buf);
61 extern ssize_t coresight_simple_show_pair(struct device *_dev,
62 struct device_attribute *attr, char *buf);
63
64 #define coresight_simple_reg32(name, offset) \
65 (&((struct cs_off_attribute[]) { \
66 { \
67 __ATTR(name, 0444, coresight_simple_show32, NULL), \
68 offset \
69 } \
70 })[0].attr.attr)
71
72 #define coresight_simple_reg64(name, lo_off, hi_off) \
73 (&((struct cs_pair_attribute[]) { \
74 { \
75 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
76 lo_off, hi_off \
77 } \
78 })[0].attr.attr)
79
80 extern const u32 coresight_barrier_pkt[4];
81 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
82
83 enum etm_addr_type {
84 ETM_ADDR_TYPE_NONE,
85 ETM_ADDR_TYPE_SINGLE,
86 ETM_ADDR_TYPE_RANGE,
87 ETM_ADDR_TYPE_START,
88 ETM_ADDR_TYPE_STOP,
89 };
90
91 /**
92 * struct cs_buffer - keep track of a recording session' specifics
93 * @cur: index of the current buffer
94 * @nr_pages: max number of pages granted to us
95 * @pid: PID this cs_buffer belongs to
96 * @offset: offset within the current buffer
97 * @data_size: how much we collected in this run
98 * @snapshot: is this run in snapshot mode
99 * @data_pages: a handle the ring buffer
100 */
101 struct cs_buffers {
102 unsigned int cur;
103 unsigned int nr_pages;
104 pid_t pid;
105 unsigned long offset;
106 local_t data_size;
107 bool snapshot;
108 void **data_pages;
109 };
110
coresight_insert_barrier_packet(void * buf)111 static inline void coresight_insert_barrier_packet(void *buf)
112 {
113 if (buf)
114 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
115 }
116
CS_LOCK(void __iomem * addr)117 static inline void CS_LOCK(void __iomem *addr)
118 {
119 do {
120 /* Wait for things to settle */
121 mb();
122 writel_relaxed(0x0, addr + CORESIGHT_LAR);
123 } while (0);
124 }
125
CS_UNLOCK(void __iomem * addr)126 static inline void CS_UNLOCK(void __iomem *addr)
127 {
128 do {
129 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
130 /* Make sure everyone has seen this */
131 mb();
132 } while (0);
133 }
134
135 void coresight_disable_path(struct list_head *path);
136 int coresight_enable_path(struct list_head *path, enum cs_mode mode,
137 void *sink_data);
138 struct coresight_device *coresight_get_sink(struct list_head *path);
139 struct coresight_device *coresight_get_sink_by_id(u32 id);
140 struct coresight_device *
141 coresight_find_default_sink(struct coresight_device *csdev);
142 struct list_head *coresight_build_path(struct coresight_device *csdev,
143 struct coresight_device *sink);
144 void coresight_release_path(struct list_head *path);
145 int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
146 void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
147 int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
148 void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
149 int coresight_make_links(struct coresight_device *orig,
150 struct coresight_connection *conn,
151 struct coresight_device *target);
152 void coresight_remove_links(struct coresight_device *orig,
153 struct coresight_connection *conn);
154 u32 coresight_get_sink_id(struct coresight_device *csdev);
155
156 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
157 extern int etm_readl_cp14(u32 off, unsigned int *val);
158 extern int etm_writel_cp14(u32 off, u32 val);
159 #else
etm_readl_cp14(u32 off,unsigned int * val)160 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
etm_writel_cp14(u32 off,u32 val)161 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
162 #endif
163
164 struct cti_assoc_op {
165 void (*add)(struct coresight_device *csdev);
166 void (*remove)(struct coresight_device *csdev);
167 };
168
169 extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
170 extern void coresight_remove_cti_ops(void);
171
172 /*
173 * Macros and inline functions to handle CoreSight UCI data and driver
174 * private data in AMBA ID table entries, and extract data values.
175 */
176
177 /* coresight AMBA ID, no UCI, no driver data: id table entry */
178 #define CS_AMBA_ID(pid) \
179 { \
180 .id = pid, \
181 .mask = 0x000fffff, \
182 }
183
184 /* coresight AMBA ID, UCI with driver data only: id table entry. */
185 #define CS_AMBA_ID_DATA(pid, dval) \
186 { \
187 .id = pid, \
188 .mask = 0x000fffff, \
189 .data = (void *)&(struct amba_cs_uci_id) \
190 { \
191 .data = (void *)dval, \
192 } \
193 }
194
195 /* coresight AMBA ID, full UCI structure: id table entry. */
196 #define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
197 { \
198 .id = pid, \
199 .mask = m, \
200 .data = (void *)uci_ptr \
201 }
202 #define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
203 /*
204 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
205 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
206 * as a match value for blanket matching all devices in the given CoreSight
207 * device type and architecture.
208 */
209 #define PIDR2_JEDEC BIT(3)
210 #define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
211 /*
212 * Match all PIDs in a given CoreSight device type and architecture, defined
213 * by the uci.
214 */
215 #define CS_AMBA_MATCH_ALL_UCI(uci) \
216 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
217
218 /* extract the data value from a UCI structure given amba_id pointer. */
coresight_get_uci_data(const struct amba_id * id)219 static inline void *coresight_get_uci_data(const struct amba_id *id)
220 {
221 struct amba_cs_uci_id *uci_id = id->data;
222
223 if (!uci_id)
224 return NULL;
225
226 return uci_id->data;
227 }
228
coresight_get_uci_data_from_amba(const struct amba_id * table,u32 pid)229 static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
230 {
231 while (table->mask) {
232 if ((pid & table->mask) == table->id)
233 return coresight_get_uci_data(table);
234 table++;
235 };
236 return NULL;
237 }
238
239 void coresight_release_platform_data(struct coresight_device *csdev,
240 struct device *dev,
241 struct coresight_platform_data *pdata);
242 struct coresight_device *
243 coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
244 void coresight_add_helper(struct coresight_device *csdev,
245 struct coresight_device *helper);
246
247 void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
248 struct coresight_device *coresight_get_percpu_sink(int cpu);
249 void coresight_disable_source(struct coresight_device *csdev, void *data);
250
251 #endif
252