1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/kvm_host.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/err.h>
16 #include <linux/fs.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/smp.h>
20 #include <linux/sysfs.h>
21 #include <linux/stat.h>
22 #include <linux/clk.h>
23 #include <linux/cpu.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/coresight.h>
26 #include <linux/coresight-pmu.h>
27 #include <linux/pm_wakeup.h>
28 #include <linux/amba/bus.h>
29 #include <linux/seq_file.h>
30 #include <linux/uaccess.h>
31 #include <linux/perf_event.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/property.h>
35 #include <linux/clk/clk-conf.h>
36
37 #include <asm/barrier.h>
38 #include <asm/sections.h>
39 #include <asm/sysreg.h>
40 #include <asm/local.h>
41 #include <asm/virt.h>
42
43 #include "coresight-etm4x.h"
44 #include "coresight-etm-perf.h"
45 #include "coresight-etm4x-cfg.h"
46 #include "coresight-self-hosted-trace.h"
47 #include "coresight-syscfg.h"
48 #include "coresight-trace-id.h"
49
50 static int boot_enable;
51 module_param(boot_enable, int, 0444);
52 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
53
54 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
55 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
56 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
57
58 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
59 module_param(pm_save_enable, int, 0444);
60 MODULE_PARM_DESC(pm_save_enable,
61 "Save/restore state on power down: 1 = never, 2 = self-hosted");
62
63 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
64 static void etm4_set_default_config(struct etmv4_config *config);
65 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
66 struct perf_event *event);
67 static u64 etm4_get_access_type(struct etmv4_config *config);
68
69 static enum cpuhp_state hp_online;
70
71 struct etm4_init_arg {
72 struct device *dev;
73 struct csdev_access *csa;
74 };
75
76 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
77 static int etm4_probe_cpu(unsigned int cpu);
78
79 /*
80 * Check if TRCSSPCICRn(i) is implemented for a given instance.
81 *
82 * TRCSSPCICRn is implemented only if :
83 * TRCSSPCICR<n> is present only if all of the following are true:
84 * TRCIDR4.NUMSSCC > n.
85 * TRCIDR4.NUMPC > 0b0000 .
86 * TRCSSCSR<n>.PC == 0b1
87 */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)88 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
89 {
90 return (n < drvdata->nr_ss_cmp) &&
91 drvdata->nr_pe &&
92 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
93 }
94
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)95 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
96 {
97 u64 res = 0;
98
99 switch (offset) {
100 ETM4x_READ_SYSREG_CASES(res)
101 default :
102 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
103 offset);
104 }
105
106 if (!_relaxed)
107 __io_ar(res); /* Imitate the !relaxed I/O helpers */
108
109 return res;
110 }
111
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)112 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
113 {
114 if (!_relaxed)
115 __io_bw(); /* Imitate the !relaxed I/O helpers */
116 if (!_64bit)
117 val &= GENMASK(31, 0);
118
119 switch (offset) {
120 ETM4x_WRITE_SYSREG_CASES(val)
121 default :
122 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
123 offset);
124 }
125 }
126
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)127 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
128 {
129 u64 res = 0;
130
131 switch (offset) {
132 ETE_READ_CASES(res)
133 default :
134 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
135 offset);
136 }
137
138 if (!_relaxed)
139 __io_ar(res); /* Imitate the !relaxed I/O helpers */
140
141 return res;
142 }
143
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)144 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
145 {
146 if (!_relaxed)
147 __io_bw(); /* Imitate the !relaxed I/O helpers */
148 if (!_64bit)
149 val &= GENMASK(31, 0);
150
151 switch (offset) {
152 ETE_WRITE_CASES(val)
153 default :
154 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
155 offset);
156 }
157 }
158
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)159 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
160 struct csdev_access *csa)
161 {
162 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
163
164 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
165 }
166
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)167 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
168 struct csdev_access *csa, u32 val)
169 {
170 val = !!val;
171
172 switch (drvdata->os_lock_model) {
173 case ETM_OSLOCK_PRESENT:
174 etm4x_relaxed_write32(csa, val, TRCOSLAR);
175 break;
176 case ETM_OSLOCK_PE:
177 write_sysreg_s(val, SYS_OSLAR_EL1);
178 break;
179 default:
180 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
181 smp_processor_id(), drvdata->os_lock_model);
182 fallthrough;
183 case ETM_OSLOCK_NI:
184 return;
185 }
186 isb();
187 }
188
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)189 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
190 struct csdev_access *csa)
191 {
192 WARN_ON(drvdata->cpu != smp_processor_id());
193
194 /* Writing 0 to OS Lock unlocks the trace unit registers */
195 etm_write_os_lock(drvdata, csa, 0x0);
196 drvdata->os_unlock = true;
197 }
198
etm4_os_unlock(struct etmv4_drvdata * drvdata)199 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
200 {
201 if (!WARN_ON(!drvdata->csdev))
202 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
203 }
204
etm4_os_lock(struct etmv4_drvdata * drvdata)205 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
206 {
207 if (WARN_ON(!drvdata->csdev))
208 return;
209 /* Writing 0x1 to OS Lock locks the trace registers */
210 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
211 drvdata->os_unlock = false;
212 }
213
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)214 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
215 struct csdev_access *csa)
216 {
217 /* Software Lock is only accessible via memory mapped interface */
218 if (csa->io_mem)
219 CS_LOCK(csa->base);
220 }
221
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)222 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
223 struct csdev_access *csa)
224 {
225 if (csa->io_mem)
226 CS_UNLOCK(csa->base);
227 }
228
etm4_cpu_id(struct coresight_device * csdev)229 static int etm4_cpu_id(struct coresight_device *csdev)
230 {
231 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
232
233 return drvdata->cpu;
234 }
235
etm4_read_alloc_trace_id(struct etmv4_drvdata * drvdata)236 int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
237 {
238 int trace_id;
239
240 /*
241 * This will allocate a trace ID to the cpu,
242 * or return the one currently allocated.
243 * The trace id function has its own lock
244 */
245 trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
246 if (IS_VALID_CS_TRACE_ID(trace_id))
247 drvdata->trcid = (u8)trace_id;
248 else
249 dev_err(&drvdata->csdev->dev,
250 "Failed to allocate trace ID for %s on CPU%d\n",
251 dev_name(&drvdata->csdev->dev), drvdata->cpu);
252 return trace_id;
253 }
254
etm4_release_trace_id(struct etmv4_drvdata * drvdata)255 void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
256 {
257 coresight_trace_id_put_cpu_id(drvdata->cpu);
258 }
259
260 struct etm4_enable_arg {
261 struct etmv4_drvdata *drvdata;
262 int rc;
263 };
264
265 /*
266 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
267 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
268 * prohibited state by filtering the Exception levels via TRFCR_EL1.
269 */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)270 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
271 {
272 u64 trfcr;
273
274 /* If the CPU doesn't support FEAT_TRF, nothing to do */
275 if (!drvdata->trfcr)
276 return;
277
278 trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
279
280 write_trfcr(trfcr);
281 kvm_tracing_set_el1_configuration(trfcr);
282 }
283
etm4x_get_kern_user_filter(struct etmv4_drvdata * drvdata)284 static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
285 {
286 u64 trfcr = drvdata->trfcr;
287
288 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
289 trfcr &= ~TRFCR_EL1_ExTRE;
290 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
291 trfcr &= ~TRFCR_EL1_E0TRE;
292
293 return trfcr;
294 }
295
296 /*
297 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
298 * as configured by the drvdata->config.mode for the current
299 * session. Even though we have TRCVICTLR bits to filter the
300 * trace in the ELs, it doesn't prevent the ETM from generating
301 * a packet (e.g, TraceInfo) that might contain the addresses from
302 * the excluded levels. Thus we use the additional controls provided
303 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
304 * is generated for the excluded ELs.
305 */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)306 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
307 {
308 u64 trfcr, guest_trfcr;
309
310 /* If the CPU doesn't support FEAT_TRF, nothing to do */
311 if (!drvdata->trfcr)
312 return;
313
314 if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
315 trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
316 else
317 trfcr = etm4x_get_kern_user_filter(drvdata);
318
319 write_trfcr(trfcr);
320
321 /* Set filters for guests and pass to KVM */
322 if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
323 guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
324 else
325 guest_trfcr = etm4x_get_kern_user_filter(drvdata);
326
327 /* TRFCR_EL1 doesn't have CX so mask it out. */
328 guest_trfcr &= ~TRFCR_EL2_CX;
329 kvm_tracing_set_el1_configuration(guest_trfcr);
330 }
331
332 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
333
334 #define HISI_HIP08_AMBA_ID 0x000b6d01
335 #define ETM4_AMBA_MASK 0xfffff
336 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
337 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
338 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
339 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
340 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
341
342 struct etm4_arch_features {
343 void (*arch_callback)(bool enable);
344 };
345
etm4_hisi_match_pid(unsigned int id)346 static bool etm4_hisi_match_pid(unsigned int id)
347 {
348 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
349 }
350
etm4_hisi_config_core_commit(bool enable)351 static void etm4_hisi_config_core_commit(bool enable)
352 {
353 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
354 HISI_HIP08_CORE_COMMIT_FULL;
355 u64 val;
356
357 /*
358 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
359 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
360 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
361 * speed(minimun value). So bit 12 and 13 should be cleared together.
362 */
363 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
364 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
365 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
366 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
367 }
368
369 static struct etm4_arch_features etm4_features[] = {
370 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
371 .arch_callback = etm4_hisi_config_core_commit,
372 },
373 {},
374 };
375
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)376 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
377 {
378 struct etm4_arch_features *ftr;
379 int bit;
380
381 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
382 ftr = &etm4_features[bit];
383
384 if (ftr->arch_callback)
385 ftr->arch_callback(true);
386 }
387 }
388
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)389 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
390 {
391 struct etm4_arch_features *ftr;
392 int bit;
393
394 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
395 ftr = &etm4_features[bit];
396
397 if (ftr->arch_callback)
398 ftr->arch_callback(false);
399 }
400 }
401
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)402 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
403 struct csdev_access *csa)
404 {
405 /*
406 * TRCPIDR* registers are not required for ETMs with system
407 * instructions. They must be identified by the MIDR+REVIDRs.
408 * Skip the TRCPID checks for now.
409 */
410 if (!csa->io_mem)
411 return;
412
413 if (etm4_hisi_match_pid(coresight_get_pid(csa)))
414 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
415 }
416 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)417 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
418 {
419 }
420
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)421 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
422 {
423 }
424
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)425 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
426 struct csdev_access *csa)
427 {
428 }
429 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
430
etm4x_sys_ins_barrier(struct csdev_access * csa,u32 offset,int pos,int val)431 static void etm4x_sys_ins_barrier(struct csdev_access *csa, u32 offset, int pos, int val)
432 {
433 if (!csa->io_mem)
434 isb();
435 }
436
437 /*
438 * etm4x_wait_status: Poll for TRCSTATR.<pos> == <val>. While using system
439 * instruction to access the trace unit, each access must be separated by a
440 * synchronization barrier. See ARM IHI0064H.b section "4.3.7 Synchronization of
441 * register updates", for system instructions section, in "Notes":
442 *
443 * "In particular, whenever disabling or enabling the trace unit, a poll of
444 * TRCSTATR needs explicit synchronization between each read of TRCSTATR"
445 */
etm4x_wait_status(struct csdev_access * csa,int pos,int val)446 static int etm4x_wait_status(struct csdev_access *csa, int pos, int val)
447 {
448 if (!csa->io_mem)
449 return coresight_timeout_action(csa, TRCSTATR, pos, val,
450 etm4x_sys_ins_barrier);
451 return coresight_timeout(csa, TRCSTATR, pos, val);
452 }
453
etm4_enable_hw(struct etmv4_drvdata * drvdata)454 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
455 {
456 int i, rc;
457 struct etmv4_config *config = &drvdata->config;
458 struct coresight_device *csdev = drvdata->csdev;
459 struct device *etm_dev = &csdev->dev;
460 struct csdev_access *csa = &csdev->access;
461
462
463 etm4_cs_unlock(drvdata, csa);
464 etm4_enable_arch_specific(drvdata);
465
466 etm4_os_unlock(drvdata);
467
468 rc = coresight_claim_device_unlocked(csdev);
469 if (rc)
470 goto done;
471
472 /* Disable the trace unit before programming trace registers */
473 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
474
475 /*
476 * If we use system instructions, we need to synchronize the
477 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
478 * See ARM IHI0064F, section
479 * "4.3.7 Synchronization of register updates"
480 */
481 if (!csa->io_mem)
482 isb();
483
484 /* wait for TRCSTATR.IDLE to go up */
485 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
486 dev_err(etm_dev,
487 "timeout while waiting for Idle Trace Status\n");
488 if (drvdata->nr_pe)
489 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
490 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
491 /* nothing specific implemented */
492 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
493 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
494 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
495 if (drvdata->stallctl)
496 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
497 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
498 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
499 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
500 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
501 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
502 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
503 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
504 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
505 if (drvdata->nr_pe_cmp)
506 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
507 for (i = 0; i < drvdata->nrseqstate - 1; i++)
508 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
509 if (drvdata->nrseqstate) {
510 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
511 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
512 }
513 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
514 for (i = 0; i < drvdata->nr_cntr; i++) {
515 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
516 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
517 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
518 }
519
520 /*
521 * Resource selector pair 0 is always implemented and reserved. As
522 * such start at 2.
523 */
524 for (i = 2; i < drvdata->nr_resource * 2; i++)
525 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
526
527 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
528 /* always clear status bit on restart if using single-shot */
529 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
530 config->ss_status[i] &= ~TRCSSCSRn_STATUS;
531 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
532 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
533 if (etm4x_sspcicrn_present(drvdata, i))
534 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
535 }
536 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
537 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
538 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
539 }
540 for (i = 0; i < drvdata->numcidc; i++)
541 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
542 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
543 if (drvdata->numcidc > 4)
544 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
545
546 for (i = 0; i < drvdata->numvmidc; i++)
547 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
548 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
549 if (drvdata->numvmidc > 4)
550 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
551
552 if (!drvdata->skip_power_up) {
553 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
554
555 /*
556 * Request to keep the trace unit powered and also
557 * emulation of powerdown
558 */
559 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
560 }
561
562 /*
563 * ETE mandates that the TRCRSR is written to before
564 * enabling it.
565 */
566 if (etm4x_is_ete(drvdata))
567 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
568
569 etm4x_allow_trace(drvdata);
570 /* Enable the trace unit */
571 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
572
573 /* Synchronize the register updates for sysreg access */
574 if (!csa->io_mem)
575 isb();
576
577 /* wait for TRCSTATR.IDLE to go back down to '0' */
578 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0))
579 dev_err(etm_dev,
580 "timeout while waiting for Idle Trace Status\n");
581
582 /*
583 * As recommended by section 4.3.7 ("Synchronization when using the
584 * memory-mapped interface") of ARM IHI 0064D
585 */
586 dsb(sy);
587 isb();
588
589 done:
590 etm4_cs_lock(drvdata, csa);
591
592 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
593 drvdata->cpu, rc);
594 return rc;
595 }
596
etm4_enable_hw_smp_call(void * info)597 static void etm4_enable_hw_smp_call(void *info)
598 {
599 struct etm4_enable_arg *arg = info;
600
601 if (WARN_ON(!arg))
602 return;
603 arg->rc = etm4_enable_hw(arg->drvdata);
604 }
605
606 /*
607 * The goal of function etm4_config_timestamp_event() is to configure a
608 * counter that will tell the tracer to emit a timestamp packet when it
609 * reaches zero. This is done in order to get a more fine grained idea
610 * of when instructions are executed so that they can be correlated
611 * with execution on other CPUs.
612 *
613 * To do this the counter itself is configured to self reload and
614 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
615 * there a resource selector is configured with the counter and the
616 * timestamp control register to use the resource selector to trigger the
617 * event that will insert a timestamp packet in the stream.
618 */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)619 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
620 {
621 int ctridx, ret = -EINVAL;
622 int counter, rselector;
623 u32 val = 0;
624 struct etmv4_config *config = &drvdata->config;
625
626 /* No point in trying if we don't have at least one counter */
627 if (!drvdata->nr_cntr)
628 goto out;
629
630 /* Find a counter that hasn't been initialised */
631 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
632 if (config->cntr_val[ctridx] == 0)
633 break;
634
635 /* All the counters have been configured already, bail out */
636 if (ctridx == drvdata->nr_cntr) {
637 pr_debug("%s: no available counter found\n", __func__);
638 ret = -ENOSPC;
639 goto out;
640 }
641
642 /*
643 * Searching for an available resource selector to use, starting at
644 * '2' since every implementation has at least 2 resource selector.
645 * ETMIDR4 gives the number of resource selector _pairs_,
646 * hence multiply by 2.
647 */
648 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
649 if (!config->res_ctrl[rselector])
650 break;
651
652 if (rselector == drvdata->nr_resource * 2) {
653 pr_debug("%s: no available resource selector found\n",
654 __func__);
655 ret = -ENOSPC;
656 goto out;
657 }
658
659 /* Remember what counter we used */
660 counter = 1 << ctridx;
661
662 /*
663 * Initialise original and reload counter value to the smallest
664 * possible value in order to get as much precision as we can.
665 */
666 config->cntr_val[ctridx] = 1;
667 config->cntrldvr[ctridx] = 1;
668
669 /* Set the trace counter control register */
670 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
671 0x0 << 7 | /* Select single resource selector */
672 0x1; /* Resource selector 1, i.e always true */
673
674 config->cntr_ctrl[ctridx] = val;
675
676 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
677 counter << 0; /* Counter to use */
678
679 config->res_ctrl[rselector] = val;
680
681 val = 0x0 << 7 | /* Select single resource selector */
682 rselector; /* Resource selector */
683
684 config->ts_ctrl = val;
685
686 ret = 0;
687 out:
688 return ret;
689 }
690
etm4_parse_event_config(struct coresight_device * csdev,struct perf_event * event)691 static int etm4_parse_event_config(struct coresight_device *csdev,
692 struct perf_event *event)
693 {
694 int ret = 0;
695 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
696 struct etmv4_config *config = &drvdata->config;
697 struct perf_event_attr *attr = &event->attr;
698 unsigned long cfg_hash;
699 int preset, cc_threshold;
700
701 /* Clear configuration from previous run */
702 memset(config, 0, sizeof(struct etmv4_config));
703
704 if (attr->exclude_kernel)
705 config->mode = ETM_MODE_EXCL_KERN;
706
707 if (attr->exclude_user)
708 config->mode = ETM_MODE_EXCL_USER;
709
710 if (attr->exclude_host)
711 config->mode |= ETM_MODE_EXCL_HOST;
712
713 if (attr->exclude_guest)
714 config->mode |= ETM_MODE_EXCL_GUEST;
715
716 /* Always start from the default config */
717 etm4_set_default_config(config);
718
719 /* Configure filters specified on the perf cmd line, if any. */
720 ret = etm4_set_event_filters(drvdata, event);
721 if (ret)
722 goto out;
723
724 /* Go from generic option to ETMv4 specifics */
725 if (attr->config & BIT(ETM_OPT_CYCACC)) {
726 config->cfg |= TRCCONFIGR_CCI;
727 /* TRM: Must program this for cycacc to work */
728 cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
729 if (!cc_threshold)
730 cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
731 if (cc_threshold < drvdata->ccitmin)
732 cc_threshold = drvdata->ccitmin;
733 config->ccctlr = cc_threshold;
734 }
735 if (attr->config & BIT(ETM_OPT_TS)) {
736 /*
737 * Configure timestamps to be emitted at regular intervals in
738 * order to correlate instructions executed on different CPUs
739 * (CPU-wide trace scenarios).
740 */
741 ret = etm4_config_timestamp_event(drvdata);
742
743 /*
744 * No need to go further if timestamp intervals can't
745 * be configured.
746 */
747 if (ret)
748 goto out;
749
750 /* bit[11], Global timestamp tracing bit */
751 config->cfg |= TRCCONFIGR_TS;
752 }
753
754 /* Only trace contextID when runs in root PID namespace */
755 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
756 task_is_in_init_pid_ns(current))
757 /* bit[6], Context ID tracing bit */
758 config->cfg |= TRCCONFIGR_CID;
759
760 /*
761 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
762 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
763 * kernel is not running in EL2.
764 */
765 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
766 if (!is_kernel_in_hyp_mode()) {
767 ret = -EINVAL;
768 goto out;
769 }
770 /* Only trace virtual contextID when runs in root PID namespace */
771 if (task_is_in_init_pid_ns(current))
772 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
773 }
774
775 /* return stack - enable if selected and supported */
776 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
777 /* bit[12], Return stack enable bit */
778 config->cfg |= TRCCONFIGR_RS;
779
780 /*
781 * Set any selected configuration and preset.
782 *
783 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
784 * in the perf attributes defined in coresight-etm-perf.c.
785 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
786 * A zero configid means no configuration active, preset = 0 means no preset selected.
787 */
788 if (attr->config2 & GENMASK_ULL(63, 32)) {
789 cfg_hash = (u32)(attr->config2 >> 32);
790 preset = attr->config & 0xF;
791 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
792 }
793
794 /* branch broadcast - enable if selected and supported */
795 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
796 if (!drvdata->trcbb) {
797 /*
798 * Missing BB support could cause silent decode errors
799 * so fail to open if it's not supported.
800 */
801 ret = -EINVAL;
802 goto out;
803 } else {
804 config->cfg |= BIT(ETM4_CFG_BIT_BB);
805 }
806 }
807
808 out:
809 return ret;
810 }
811
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event,struct coresight_trace_id_map * id_map)812 static int etm4_enable_perf(struct coresight_device *csdev,
813 struct perf_event *event,
814 struct coresight_trace_id_map *id_map)
815 {
816 int ret = 0, trace_id;
817 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
818
819 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
820 ret = -EINVAL;
821 goto out;
822 }
823
824 /* Configure the tracer based on the session's specifics */
825 ret = etm4_parse_event_config(csdev, event);
826 if (ret)
827 goto out;
828
829 /*
830 * perf allocates cpu ids as part of _setup_aux() - device needs to use
831 * the allocated ID. This reads the current version without allocation.
832 *
833 * This does not use the trace id lock to prevent lock_dep issues
834 * with perf locks - we know the ID cannot change until perf shuts down
835 * the session
836 */
837 trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map);
838 if (!IS_VALID_CS_TRACE_ID(trace_id)) {
839 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
840 dev_name(&drvdata->csdev->dev), drvdata->cpu);
841 ret = -EINVAL;
842 goto out;
843 }
844 drvdata->trcid = (u8)trace_id;
845
846 /* And enable it */
847 ret = etm4_enable_hw(drvdata);
848
849 out:
850 return ret;
851 }
852
etm4_enable_sysfs(struct coresight_device * csdev)853 static int etm4_enable_sysfs(struct coresight_device *csdev)
854 {
855 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
856 struct etm4_enable_arg arg = { };
857 unsigned long cfg_hash;
858 int ret, preset;
859
860 /* enable any config activated by configfs */
861 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
862 if (cfg_hash) {
863 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
864 if (ret)
865 return ret;
866 }
867
868 spin_lock(&drvdata->spinlock);
869
870 /* sysfs needs to read and allocate a trace ID */
871 ret = etm4_read_alloc_trace_id(drvdata);
872 if (ret < 0)
873 goto unlock_sysfs_enable;
874
875 /*
876 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
877 * ensures that register writes occur when cpu is powered.
878 */
879 arg.drvdata = drvdata;
880 ret = smp_call_function_single(drvdata->cpu,
881 etm4_enable_hw_smp_call, &arg, 1);
882 if (!ret)
883 ret = arg.rc;
884 if (!ret)
885 drvdata->sticky_enable = true;
886
887 if (ret)
888 etm4_release_trace_id(drvdata);
889
890 unlock_sysfs_enable:
891 spin_unlock(&drvdata->spinlock);
892
893 if (!ret)
894 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
895 return ret;
896 }
897
etm4_enable(struct coresight_device * csdev,struct perf_event * event,enum cs_mode mode,struct coresight_trace_id_map * id_map)898 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
899 enum cs_mode mode, struct coresight_trace_id_map *id_map)
900 {
901 int ret;
902
903 if (!coresight_take_mode(csdev, mode)) {
904 /* Someone is already using the tracer */
905 return -EBUSY;
906 }
907
908 switch (mode) {
909 case CS_MODE_SYSFS:
910 ret = etm4_enable_sysfs(csdev);
911 break;
912 case CS_MODE_PERF:
913 ret = etm4_enable_perf(csdev, event, id_map);
914 break;
915 default:
916 ret = -EINVAL;
917 }
918
919 /* The tracer didn't start */
920 if (ret)
921 coresight_set_mode(csdev, CS_MODE_DISABLED);
922
923 return ret;
924 }
925
etm4_disable_hw(void * info)926 static void etm4_disable_hw(void *info)
927 {
928 u32 control;
929 struct etmv4_drvdata *drvdata = info;
930 struct etmv4_config *config = &drvdata->config;
931 struct coresight_device *csdev = drvdata->csdev;
932 struct device *etm_dev = &csdev->dev;
933 struct csdev_access *csa = &csdev->access;
934 int i;
935
936 etm4_cs_unlock(drvdata, csa);
937 etm4_disable_arch_specific(drvdata);
938
939 if (!drvdata->skip_power_up) {
940 /* power can be removed from the trace unit now */
941 control = etm4x_relaxed_read32(csa, TRCPDCR);
942 control &= ~TRCPDCR_PU;
943 etm4x_relaxed_write32(csa, control, TRCPDCR);
944 }
945
946 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
947
948 /* EN, bit[0] Trace unit enable bit */
949 control &= ~0x1;
950
951 /*
952 * If the CPU supports v8.4 Trace filter Control,
953 * set the ETM to trace prohibited region.
954 */
955 etm4x_prohibit_trace(drvdata);
956 /*
957 * Make sure everything completes before disabling, as recommended
958 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
959 * SSTATUS") of ARM IHI 0064D
960 */
961 dsb(sy);
962 isb();
963 /* Trace synchronization barrier, is a nop if not supported */
964 tsb_csync();
965 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
966
967 /*
968 * As recommended by section 4.3.7 ("Synchronization when using system
969 * instructions to progrom the trace unit") of ARM IHI 0064H.b, the
970 * self-hosted trace analyzer must perform a Context synchronization
971 * event between writing to the TRCPRGCTLR and reading the TRCSTATR.
972 */
973 if (!csa->io_mem)
974 isb();
975
976 /* wait for TRCSTATR.PMSTABLE to go to '1' */
977 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1))
978 dev_err(etm_dev,
979 "timeout while waiting for PM stable Trace Status\n");
980 /*
981 * As recommended by section 4.3.7 (Synchronization of register updates)
982 * of ARM IHI 0064H.b.
983 */
984 isb();
985
986 /* read the status of the single shot comparators */
987 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
988 config->ss_status[i] =
989 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
990 }
991
992 /* read back the current counter values */
993 for (i = 0; i < drvdata->nr_cntr; i++) {
994 config->cntr_val[i] =
995 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
996 }
997
998 coresight_disclaim_device_unlocked(csdev);
999 etm4_cs_lock(drvdata, csa);
1000
1001 dev_dbg(&drvdata->csdev->dev,
1002 "cpu: %d disable smp call done\n", drvdata->cpu);
1003 }
1004
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)1005 static int etm4_disable_perf(struct coresight_device *csdev,
1006 struct perf_event *event)
1007 {
1008 u32 control;
1009 struct etm_filters *filters = event->hw.addr_filters;
1010 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1011 struct perf_event_attr *attr = &event->attr;
1012
1013 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
1014 return -EINVAL;
1015
1016 etm4_disable_hw(drvdata);
1017 /*
1018 * The config_id occupies bits 63:32 of the config2 perf event attr
1019 * field. If this is non-zero then we will have enabled a config.
1020 */
1021 if (attr->config2 & GENMASK_ULL(63, 32))
1022 cscfg_csdev_disable_active_config(csdev);
1023
1024 /*
1025 * Check if the start/stop logic was active when the unit was stopped.
1026 * That way we can re-enable the start/stop logic when the process is
1027 * scheduled again. Configuration of the start/stop logic happens in
1028 * function etm4_set_event_filters().
1029 */
1030 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
1031 /* TRCVICTLR::SSSTATUS, bit[9] */
1032 filters->ssstatus = (control & BIT(9));
1033
1034 /*
1035 * perf will release trace ids when _free_aux() is
1036 * called at the end of the session.
1037 */
1038
1039 return 0;
1040 }
1041
etm4_disable_sysfs(struct coresight_device * csdev)1042 static void etm4_disable_sysfs(struct coresight_device *csdev)
1043 {
1044 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1045
1046 /*
1047 * Taking hotplug lock here protects from clocks getting disabled
1048 * with tracing being left on (crash scenario) if user disable occurs
1049 * after cpu online mask indicates the cpu is offline but before the
1050 * DYING hotplug callback is serviced by the ETM driver.
1051 */
1052 cpus_read_lock();
1053 spin_lock(&drvdata->spinlock);
1054
1055 /*
1056 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
1057 * ensures that register writes occur when cpu is powered.
1058 */
1059 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
1060
1061 spin_unlock(&drvdata->spinlock);
1062 cpus_read_unlock();
1063
1064 /*
1065 * we only release trace IDs when resetting sysfs.
1066 * This permits sysfs users to read the trace ID after the trace
1067 * session has completed. This maintains operational behaviour with
1068 * prior trace id allocation method
1069 */
1070
1071 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
1072 }
1073
etm4_disable(struct coresight_device * csdev,struct perf_event * event)1074 static void etm4_disable(struct coresight_device *csdev,
1075 struct perf_event *event)
1076 {
1077 enum cs_mode mode;
1078
1079 /*
1080 * For as long as the tracer isn't disabled another entity can't
1081 * change its status. As such we can read the status here without
1082 * fearing it will change under us.
1083 */
1084 mode = coresight_get_mode(csdev);
1085
1086 switch (mode) {
1087 case CS_MODE_DISABLED:
1088 break;
1089 case CS_MODE_SYSFS:
1090 etm4_disable_sysfs(csdev);
1091 break;
1092 case CS_MODE_PERF:
1093 etm4_disable_perf(csdev, event);
1094 break;
1095 }
1096
1097 if (mode)
1098 coresight_set_mode(csdev, CS_MODE_DISABLED);
1099 }
1100
1101 static const struct coresight_ops_source etm4_source_ops = {
1102 .cpu_id = etm4_cpu_id,
1103 .enable = etm4_enable,
1104 .disable = etm4_disable,
1105 };
1106
1107 static const struct coresight_ops etm4_cs_ops = {
1108 .source_ops = &etm4_source_ops,
1109 };
1110
cpu_supports_sysreg_trace(void)1111 static inline bool cpu_supports_sysreg_trace(void)
1112 {
1113 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1114
1115 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1116 }
1117
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1118 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1119 struct csdev_access *csa)
1120 {
1121 u32 devarch;
1122
1123 if (!cpu_supports_sysreg_trace())
1124 return false;
1125
1126 /*
1127 * ETMs implementing sysreg access must implement TRCDEVARCH.
1128 */
1129 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1130 switch (devarch & ETM_DEVARCH_ID_MASK) {
1131 case ETM_DEVARCH_ETMv4x_ARCH:
1132 *csa = (struct csdev_access) {
1133 .io_mem = false,
1134 .read = etm4x_sysreg_read,
1135 .write = etm4x_sysreg_write,
1136 };
1137 break;
1138 case ETM_DEVARCH_ETE_ARCH:
1139 *csa = (struct csdev_access) {
1140 .io_mem = false,
1141 .read = ete_sysreg_read,
1142 .write = ete_sysreg_write,
1143 };
1144 break;
1145 default:
1146 return false;
1147 }
1148
1149 drvdata->arch = etm_devarch_to_arch(devarch);
1150 return true;
1151 }
1152
is_devtype_cpu_trace(void __iomem * base)1153 static bool is_devtype_cpu_trace(void __iomem *base)
1154 {
1155 u32 devtype = readl(base + TRCDEVTYPE);
1156
1157 return (devtype == CS_DEVTYPE_PE_TRACE);
1158 }
1159
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1160 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1161 struct csdev_access *csa)
1162 {
1163 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1164
1165 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1166 return false;
1167
1168 /*
1169 * All ETMs must implement TRCDEVARCH to indicate that
1170 * the component is an ETMv4. Even though TRCIDR1 also
1171 * contains the information, it is part of the "Trace"
1172 * register and must be accessed with the OSLK cleared,
1173 * with MMIO. But we cannot touch the OSLK until we are
1174 * sure this is an ETM. So rely only on the TRCDEVARCH.
1175 */
1176 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1177 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1178 return false;
1179 }
1180
1181 drvdata->arch = etm_devarch_to_arch(devarch);
1182 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1183 return true;
1184 }
1185
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1186 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1187 struct csdev_access *csa)
1188 {
1189 /*
1190 * Always choose the memory mapped io, if there is
1191 * a memory map to prevent sysreg access on broken
1192 * systems.
1193 */
1194 if (drvdata->base)
1195 return etm4_init_iomem_access(drvdata, csa);
1196
1197 if (etm4_init_sysreg_access(drvdata, csa))
1198 return true;
1199
1200 return false;
1201 }
1202
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1203 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1204 {
1205 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1206 u64 trfcr;
1207
1208 drvdata->trfcr = 0;
1209 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1210 return;
1211
1212 /*
1213 * If the CPU supports v8.4 SelfHosted Tracing, enable
1214 * tracing at the kernel EL and EL0, forcing to use the
1215 * virtual time as the timestamp.
1216 */
1217 trfcr = (TRFCR_EL1_TS_VIRTUAL |
1218 TRFCR_EL1_ExTRE |
1219 TRFCR_EL1_E0TRE);
1220
1221 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1222 if (is_kernel_in_hyp_mode())
1223 trfcr |= TRFCR_EL2_CX;
1224
1225 drvdata->trfcr = trfcr;
1226 }
1227
1228 /*
1229 * The following errata on applicable cpu ranges, affect the CCITMIN filed
1230 * in TCRIDR3 register. Software read for the field returns 0x100 limiting
1231 * the cycle threshold granularity, whereas the right value should have
1232 * been 0x4, which is well supported in the hardware.
1233 */
1234 static struct midr_range etm_wrong_ccitmin_cpus[] = {
1235 /* Erratum #1490853 - Cortex-A76 */
1236 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
1237 /* Erratum #1490853 - Neoverse-N1 */
1238 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
1239 /* Erratum #1491015 - Cortex-A77 */
1240 MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
1241 /* Erratum #1502854 - Cortex-X1 */
1242 MIDR_REV(MIDR_CORTEX_X1, 0, 0),
1243 /* Erratum #1619801 - Neoverse-V1 */
1244 MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
1245 {},
1246 };
1247
etm4_fixup_wrong_ccitmin(struct etmv4_drvdata * drvdata)1248 static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
1249 {
1250 /*
1251 * Erratum affected cpus will read 256 as the minimum
1252 * instruction trace cycle counting threshold whereas
1253 * the correct value should be 4 instead. Override the
1254 * recorded value for 'drvdata->ccitmin' to workaround
1255 * this problem.
1256 */
1257 if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) {
1258 if (drvdata->ccitmin == 256)
1259 drvdata->ccitmin = 4;
1260 }
1261 }
1262
etm4_init_arch_data(void * info)1263 static void etm4_init_arch_data(void *info)
1264 {
1265 u32 etmidr0;
1266 u32 etmidr2;
1267 u32 etmidr3;
1268 u32 etmidr4;
1269 u32 etmidr5;
1270 struct etm4_init_arg *init_arg = info;
1271 struct etmv4_drvdata *drvdata;
1272 struct csdev_access *csa;
1273 struct device *dev = init_arg->dev;
1274 int i;
1275
1276 drvdata = dev_get_drvdata(init_arg->dev);
1277 csa = init_arg->csa;
1278
1279 /*
1280 * If we are unable to detect the access mechanism,
1281 * or unable to detect the trace unit type, fail
1282 * early.
1283 */
1284 if (!etm4_init_csdev_access(drvdata, csa))
1285 return;
1286
1287 if (!csa->io_mem ||
1288 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1289 drvdata->skip_power_up = true;
1290
1291 /* Detect the support for OS Lock before we actually use it */
1292 etm_detect_os_lock(drvdata, csa);
1293
1294 /* Make sure all registers are accessible */
1295 etm4_os_unlock_csa(drvdata, csa);
1296 etm4_cs_unlock(drvdata, csa);
1297
1298 etm4_check_arch_features(drvdata, csa);
1299
1300 /* find all capabilities of the tracing unit */
1301 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1302
1303 /* INSTP0, bits[2:1] P0 tracing support field */
1304 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1305 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1306 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1307 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1308 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1309 /* TRCCCI, bit[7] Cycle counting instruction bit */
1310 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1311 /* RETSTACK, bit[9] Return stack bit */
1312 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1313 /* NUMEVENT, bits[11:10] Number of events field */
1314 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1315 /* QSUPP, bits[16:15] Q element support field */
1316 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1317 if (drvdata->q_support)
1318 drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
1319 /* TSSIZE, bits[28:24] Global timestamp size field */
1320 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1321
1322 /* maximum size of resources */
1323 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1324 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1325 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1326 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1327 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1328 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1329 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1330
1331 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1332 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1333 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1334 etm4_fixup_wrong_ccitmin(drvdata);
1335
1336 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1337 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1338 drvdata->config.s_ex_level = drvdata->s_ex_level;
1339 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1340 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1341 /*
1342 * TRCERR, bit[24] whether a trace unit can trace a
1343 * system error exception.
1344 */
1345 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1346 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1347 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1348 /* STALLCTL, bit[26] is stall control implemented? */
1349 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1350 /* SYSSTALL, bit[27] implementation can support stall control? */
1351 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1352 /*
1353 * NUMPROC - the number of PEs available for tracing, 5bits
1354 * = TRCIDR3.bits[13:12]bits[30:28]
1355 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1356 * bits[3:0] = TRCIDR3.bits[30:28]
1357 */
1358 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1359 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1360 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1361 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1362
1363 /* number of resources trace unit supports */
1364 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1365 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1366 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1367 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1368 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1369 /*
1370 * NUMRSPAIR, bits[19:16]
1371 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1372 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1373 * As such add 1 to the value of NUMRSPAIR for a better representation.
1374 *
1375 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1376 * the default TRUE and FALSE resource selectors are omitted.
1377 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1378 */
1379 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1380 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1381 drvdata->nr_resource += 1;
1382 /*
1383 * NUMSSCC, bits[23:20] the number of single-shot
1384 * comparator control for tracing. Read any status regs as these
1385 * also contain RO capability data.
1386 */
1387 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1388 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1389 drvdata->config.ss_status[i] =
1390 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1391 }
1392 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1393 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1394 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1395 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1396
1397 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1398 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1399 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1400 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1401 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1402 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1403 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1404 /*
1405 * LPOVERRIDE, bit[23] implementation supports
1406 * low-power state override
1407 */
1408 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1409 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1410 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1411 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1412 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1413 etm4_cs_lock(drvdata, csa);
1414 cpu_detect_trace_filtering(drvdata);
1415 }
1416
etm4_get_victlr_access_type(struct etmv4_config * config)1417 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1418 {
1419 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1420 }
1421
1422 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1423 static void etm4_set_victlr_access(struct etmv4_config *config)
1424 {
1425 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1426 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1427 }
1428
etm4_set_default_config(struct etmv4_config * config)1429 static void etm4_set_default_config(struct etmv4_config *config)
1430 {
1431 /* disable all events tracing */
1432 config->eventctrl0 = 0x0;
1433 config->eventctrl1 = 0x0;
1434
1435 /* disable stalling */
1436 config->stall_ctrl = 0x0;
1437
1438 /* enable trace synchronization every 4096 bytes, if available */
1439 config->syncfreq = 0xC;
1440
1441 /* disable timestamp event */
1442 config->ts_ctrl = 0x0;
1443
1444 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1445 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1446
1447 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1448 etm4_set_victlr_access(config);
1449 }
1450
etm4_get_ns_access_type(struct etmv4_config * config)1451 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1452 {
1453 u64 access_type = 0;
1454
1455 /*
1456 * EXLEVEL_NS, for NonSecure Exception levels.
1457 * The mask here is a generic value and must be
1458 * shifted to the corresponding field for the registers
1459 */
1460 if (!is_kernel_in_hyp_mode()) {
1461 /* Stay away from hypervisor mode for non-VHE */
1462 access_type = ETM_EXLEVEL_NS_HYP;
1463 if (config->mode & ETM_MODE_EXCL_KERN)
1464 access_type |= ETM_EXLEVEL_NS_OS;
1465 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1466 access_type = ETM_EXLEVEL_NS_HYP;
1467 }
1468
1469 if (config->mode & ETM_MODE_EXCL_USER)
1470 access_type |= ETM_EXLEVEL_NS_APP;
1471
1472 return access_type;
1473 }
1474
1475 /*
1476 * Construct the exception level masks for a given config.
1477 * This must be shifted to the corresponding register field
1478 * for usage.
1479 */
etm4_get_access_type(struct etmv4_config * config)1480 static u64 etm4_get_access_type(struct etmv4_config *config)
1481 {
1482 /* All Secure exception levels are excluded from the trace */
1483 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1484 }
1485
etm4_get_comparator_access_type(struct etmv4_config * config)1486 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1487 {
1488 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1489 }
1490
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1491 static void etm4_set_comparator_filter(struct etmv4_config *config,
1492 u64 start, u64 stop, int comparator)
1493 {
1494 u64 access_type = etm4_get_comparator_access_type(config);
1495
1496 /* First half of default address comparator */
1497 config->addr_val[comparator] = start;
1498 config->addr_acc[comparator] = access_type;
1499 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1500
1501 /* Second half of default address comparator */
1502 config->addr_val[comparator + 1] = stop;
1503 config->addr_acc[comparator + 1] = access_type;
1504 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1505
1506 /*
1507 * Configure the ViewInst function to include this address range
1508 * comparator.
1509 *
1510 * @comparator is divided by two since it is the index in the
1511 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1512 * address range comparator _pairs_.
1513 *
1514 * Therefore:
1515 * index 0 -> compatator pair 0
1516 * index 2 -> comparator pair 1
1517 * index 4 -> comparator pair 2
1518 * ...
1519 * index 14 -> comparator pair 7
1520 */
1521 config->viiectlr |= BIT(comparator / 2);
1522 }
1523
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1524 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1525 u64 address, int comparator,
1526 enum etm_addr_type type)
1527 {
1528 int shift;
1529 u64 access_type = etm4_get_comparator_access_type(config);
1530
1531 /* Configure the comparator */
1532 config->addr_val[comparator] = address;
1533 config->addr_acc[comparator] = access_type;
1534 config->addr_type[comparator] = type;
1535
1536 /*
1537 * Configure ViewInst Start-Stop control register.
1538 * Addresses configured to start tracing go from bit 0 to n-1,
1539 * while those configured to stop tracing from 16 to 16 + n-1.
1540 */
1541 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1542 config->vissctlr |= BIT(shift + comparator);
1543 }
1544
etm4_set_default_filter(struct etmv4_config * config)1545 static void etm4_set_default_filter(struct etmv4_config *config)
1546 {
1547 /* Trace everything 'default' filter achieved by no filtering */
1548 config->viiectlr = 0x0;
1549
1550 /*
1551 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1552 * in the started state
1553 */
1554 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1555 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1556
1557 /* No start-stop filtering for ViewInst */
1558 config->vissctlr = 0x0;
1559 }
1560
etm4_set_default(struct etmv4_config * config)1561 static void etm4_set_default(struct etmv4_config *config)
1562 {
1563 if (WARN_ON_ONCE(!config))
1564 return;
1565
1566 /*
1567 * Make default initialisation trace everything
1568 *
1569 * This is done by a minimum default config sufficient to enable
1570 * full instruction trace - with a default filter for trace all
1571 * achieved by having no filtering.
1572 */
1573 etm4_set_default_config(config);
1574 etm4_set_default_filter(config);
1575 }
1576
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1577 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1578 {
1579 int nr_comparator, index = 0;
1580 struct etmv4_config *config = &drvdata->config;
1581
1582 /*
1583 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1584 * for the total number of comparators.
1585 */
1586 nr_comparator = drvdata->nr_addr_cmp * 2;
1587
1588 /* Go through the tally of comparators looking for a free one. */
1589 while (index < nr_comparator) {
1590 switch (type) {
1591 case ETM_ADDR_TYPE_RANGE:
1592 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1593 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1594 return index;
1595
1596 /* Address range comparators go in pairs */
1597 index += 2;
1598 break;
1599 case ETM_ADDR_TYPE_START:
1600 case ETM_ADDR_TYPE_STOP:
1601 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1602 return index;
1603
1604 /* Start/stop address can have odd indexes */
1605 index += 1;
1606 break;
1607 default:
1608 return -EINVAL;
1609 }
1610 }
1611
1612 /* If we are here all the comparators have been used. */
1613 return -ENOSPC;
1614 }
1615
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1616 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1617 struct perf_event *event)
1618 {
1619 int i, comparator, ret = 0;
1620 u64 address;
1621 struct etmv4_config *config = &drvdata->config;
1622 struct etm_filters *filters = event->hw.addr_filters;
1623
1624 if (!filters)
1625 goto default_filter;
1626
1627 /* Sync events with what Perf got */
1628 perf_event_addr_filters_sync(event);
1629
1630 /*
1631 * If there are no filters to deal with simply go ahead with
1632 * the default filter, i.e the entire address range.
1633 */
1634 if (!filters->nr_filters)
1635 goto default_filter;
1636
1637 for (i = 0; i < filters->nr_filters; i++) {
1638 struct etm_filter *filter = &filters->etm_filter[i];
1639 enum etm_addr_type type = filter->type;
1640
1641 /* See if a comparator is free. */
1642 comparator = etm4_get_next_comparator(drvdata, type);
1643 if (comparator < 0) {
1644 ret = comparator;
1645 goto out;
1646 }
1647
1648 switch (type) {
1649 case ETM_ADDR_TYPE_RANGE:
1650 etm4_set_comparator_filter(config,
1651 filter->start_addr,
1652 filter->stop_addr,
1653 comparator);
1654 /*
1655 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1656 * in the started state
1657 */
1658 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1659
1660 /* No start-stop filtering for ViewInst */
1661 config->vissctlr = 0x0;
1662 break;
1663 case ETM_ADDR_TYPE_START:
1664 case ETM_ADDR_TYPE_STOP:
1665 /* Get the right start or stop address */
1666 address = (type == ETM_ADDR_TYPE_START ?
1667 filter->start_addr :
1668 filter->stop_addr);
1669
1670 /* Configure comparator */
1671 etm4_set_start_stop_filter(config, address,
1672 comparator, type);
1673
1674 /*
1675 * If filters::ssstatus == 1, trace acquisition was
1676 * started but the process was yanked away before the
1677 * stop address was hit. As such the start/stop
1678 * logic needs to be re-started so that tracing can
1679 * resume where it left.
1680 *
1681 * The start/stop logic status when a process is
1682 * scheduled out is checked in function
1683 * etm4_disable_perf().
1684 */
1685 if (filters->ssstatus)
1686 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1687
1688 /* No include/exclude filtering for ViewInst */
1689 config->viiectlr = 0x0;
1690 break;
1691 default:
1692 ret = -EINVAL;
1693 goto out;
1694 }
1695 }
1696
1697 goto out;
1698
1699
1700 default_filter:
1701 etm4_set_default_filter(config);
1702
1703 out:
1704 return ret;
1705 }
1706
etm4_config_trace_mode(struct etmv4_config * config)1707 void etm4_config_trace_mode(struct etmv4_config *config)
1708 {
1709 u32 mode;
1710
1711 mode = config->mode;
1712 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1713
1714 /* excluding kernel AND user space doesn't make sense */
1715 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1716
1717 /* nothing to do if neither flags are set */
1718 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1719 return;
1720
1721 etm4_set_victlr_access(config);
1722 }
1723
etm4_online_cpu(unsigned int cpu)1724 static int etm4_online_cpu(unsigned int cpu)
1725 {
1726 if (!etmdrvdata[cpu])
1727 return etm4_probe_cpu(cpu);
1728
1729 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1730 coresight_enable_sysfs(etmdrvdata[cpu]->csdev);
1731 return 0;
1732 }
1733
etm4_starting_cpu(unsigned int cpu)1734 static int etm4_starting_cpu(unsigned int cpu)
1735 {
1736 if (!etmdrvdata[cpu])
1737 return 0;
1738
1739 spin_lock(&etmdrvdata[cpu]->spinlock);
1740 if (!etmdrvdata[cpu]->os_unlock)
1741 etm4_os_unlock(etmdrvdata[cpu]);
1742
1743 if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1744 etm4_enable_hw(etmdrvdata[cpu]);
1745 spin_unlock(&etmdrvdata[cpu]->spinlock);
1746 return 0;
1747 }
1748
etm4_dying_cpu(unsigned int cpu)1749 static int etm4_dying_cpu(unsigned int cpu)
1750 {
1751 if (!etmdrvdata[cpu])
1752 return 0;
1753
1754 spin_lock(&etmdrvdata[cpu]->spinlock);
1755 if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1756 etm4_disable_hw(etmdrvdata[cpu]);
1757 spin_unlock(&etmdrvdata[cpu]->spinlock);
1758 return 0;
1759 }
1760
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1761 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1762 {
1763 int i, ret = 0;
1764 struct etmv4_save_state *state;
1765 struct coresight_device *csdev = drvdata->csdev;
1766 struct csdev_access *csa;
1767 struct device *etm_dev;
1768
1769 if (WARN_ON(!csdev))
1770 return -ENODEV;
1771
1772 etm_dev = &csdev->dev;
1773 csa = &csdev->access;
1774
1775 /*
1776 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1777 * of ARM IHI 0064D
1778 */
1779 dsb(sy);
1780 isb();
1781
1782 etm4_cs_unlock(drvdata, csa);
1783 /* Lock the OS lock to disable trace and external debugger access */
1784 etm4_os_lock(drvdata);
1785
1786 /* wait for TRCSTATR.PMSTABLE to go up */
1787 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1788 dev_err(etm_dev,
1789 "timeout while waiting for PM Stable Status\n");
1790 etm4_os_unlock(drvdata);
1791 ret = -EBUSY;
1792 goto out;
1793 }
1794
1795 state = drvdata->save_state;
1796
1797 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1798 if (drvdata->nr_pe)
1799 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1800 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1801 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1802 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1803 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1804 if (drvdata->stallctl)
1805 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1806 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1807 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1808 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1809 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1810 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1811 if (drvdata->q_filt)
1812 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1813
1814 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1815 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1816 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1817 if (drvdata->nr_pe_cmp)
1818 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1819
1820 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1821 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1822
1823 if (drvdata->nrseqstate) {
1824 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1825 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1826 }
1827 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1828
1829 for (i = 0; i < drvdata->nr_cntr; i++) {
1830 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1831 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1832 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1833 }
1834
1835 /* Resource selector pair 0 is reserved */
1836 for (i = 2; i < drvdata->nr_resource * 2; i++)
1837 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1838
1839 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1840 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1841 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1842 if (etm4x_sspcicrn_present(drvdata, i))
1843 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1844 }
1845
1846 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1847 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1848 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1849 }
1850
1851 /*
1852 * Data trace stream is architecturally prohibited for A profile cores
1853 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1854 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1855 * unit") of ARM IHI 0064D.
1856 */
1857
1858 for (i = 0; i < drvdata->numcidc; i++)
1859 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1860
1861 for (i = 0; i < drvdata->numvmidc; i++)
1862 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1863
1864 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1865 if (drvdata->numcidc > 4)
1866 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1867
1868 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1869 if (drvdata->numvmidc > 4)
1870 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1871
1872 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1873
1874 if (!drvdata->skip_power_up)
1875 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1876
1877 /* wait for TRCSTATR.IDLE to go up */
1878 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1879 dev_err(etm_dev,
1880 "timeout while waiting for Idle Trace Status\n");
1881 etm4_os_unlock(drvdata);
1882 ret = -EBUSY;
1883 goto out;
1884 }
1885
1886 drvdata->state_needs_restore = true;
1887
1888 /*
1889 * Power can be removed from the trace unit now. We do this to
1890 * potentially save power on systems that respect the TRCPDCR_PU
1891 * despite requesting software to save/restore state.
1892 */
1893 if (!drvdata->skip_power_up)
1894 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1895 TRCPDCR);
1896 out:
1897 etm4_cs_lock(drvdata, csa);
1898 return ret;
1899 }
1900
etm4_cpu_save(struct etmv4_drvdata * drvdata)1901 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1902 {
1903 int ret = 0;
1904
1905 /* Save the TRFCR irrespective of whether the ETM is ON */
1906 if (drvdata->trfcr)
1907 drvdata->save_trfcr = read_trfcr();
1908 /*
1909 * Save and restore the ETM Trace registers only if
1910 * the ETM is active.
1911 */
1912 if (coresight_get_mode(drvdata->csdev) && drvdata->save_state)
1913 ret = __etm4_cpu_save(drvdata);
1914 return ret;
1915 }
1916
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1917 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1918 {
1919 int i;
1920 struct etmv4_save_state *state = drvdata->save_state;
1921 struct csdev_access *csa = &drvdata->csdev->access;
1922
1923 if (WARN_ON(!drvdata->csdev))
1924 return;
1925
1926 etm4_cs_unlock(drvdata, csa);
1927 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1928
1929 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1930 if (drvdata->nr_pe)
1931 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1932 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1933 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1934 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1935 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1936 if (drvdata->stallctl)
1937 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1938 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1939 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1940 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1941 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1942 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1943 if (drvdata->q_filt)
1944 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1945
1946 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1947 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1948 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1949 if (drvdata->nr_pe_cmp)
1950 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1951
1952 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1953 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1954
1955 if (drvdata->nrseqstate) {
1956 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1957 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1958 }
1959 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1960
1961 for (i = 0; i < drvdata->nr_cntr; i++) {
1962 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1963 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1964 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1965 }
1966
1967 /* Resource selector pair 0 is reserved */
1968 for (i = 2; i < drvdata->nr_resource * 2; i++)
1969 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1970
1971 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1972 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1973 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1974 if (etm4x_sspcicrn_present(drvdata, i))
1975 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1976 }
1977
1978 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1979 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1980 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1981 }
1982
1983 for (i = 0; i < drvdata->numcidc; i++)
1984 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1985
1986 for (i = 0; i < drvdata->numvmidc; i++)
1987 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1988
1989 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1990 if (drvdata->numcidc > 4)
1991 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1992
1993 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1994 if (drvdata->numvmidc > 4)
1995 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1996
1997 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1998
1999 if (!drvdata->skip_power_up)
2000 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
2001
2002 drvdata->state_needs_restore = false;
2003
2004 /*
2005 * As recommended by section 4.3.7 ("Synchronization when using the
2006 * memory-mapped interface") of ARM IHI 0064D
2007 */
2008 dsb(sy);
2009 isb();
2010
2011 /* Unlock the OS lock to re-enable trace and external debug access */
2012 etm4_os_unlock(drvdata);
2013 etm4_cs_lock(drvdata, csa);
2014 }
2015
etm4_cpu_restore(struct etmv4_drvdata * drvdata)2016 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
2017 {
2018 if (drvdata->trfcr)
2019 write_trfcr(drvdata->save_trfcr);
2020 if (drvdata->state_needs_restore)
2021 __etm4_cpu_restore(drvdata);
2022 }
2023
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)2024 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
2025 void *v)
2026 {
2027 struct etmv4_drvdata *drvdata;
2028 unsigned int cpu = smp_processor_id();
2029
2030 if (!etmdrvdata[cpu])
2031 return NOTIFY_OK;
2032
2033 drvdata = etmdrvdata[cpu];
2034
2035 if (WARN_ON_ONCE(drvdata->cpu != cpu))
2036 return NOTIFY_BAD;
2037
2038 switch (cmd) {
2039 case CPU_PM_ENTER:
2040 if (etm4_cpu_save(drvdata))
2041 return NOTIFY_BAD;
2042 break;
2043 case CPU_PM_EXIT:
2044 case CPU_PM_ENTER_FAILED:
2045 etm4_cpu_restore(drvdata);
2046 break;
2047 default:
2048 return NOTIFY_DONE;
2049 }
2050
2051 return NOTIFY_OK;
2052 }
2053
2054 static struct notifier_block etm4_cpu_pm_nb = {
2055 .notifier_call = etm4_cpu_pm_notify,
2056 };
2057
2058 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)2059 static int __init etm4_pm_setup(void)
2060 {
2061 int ret;
2062
2063 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
2064 if (ret)
2065 return ret;
2066
2067 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
2068 "arm/coresight4:starting",
2069 etm4_starting_cpu, etm4_dying_cpu);
2070
2071 if (ret)
2072 goto unregister_notifier;
2073
2074 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
2075 "arm/coresight4:online",
2076 etm4_online_cpu, NULL);
2077
2078 /* HP dyn state ID returned in ret on success */
2079 if (ret > 0) {
2080 hp_online = ret;
2081 return 0;
2082 }
2083
2084 /* failed dyn state - remove others */
2085 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2086
2087 unregister_notifier:
2088 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2089 return ret;
2090 }
2091
etm4_pm_clear(void)2092 static void etm4_pm_clear(void)
2093 {
2094 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2095 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2096 if (hp_online) {
2097 cpuhp_remove_state_nocalls(hp_online);
2098 hp_online = 0;
2099 }
2100 }
2101
etm4_add_coresight_dev(struct etm4_init_arg * init_arg)2102 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
2103 {
2104 int ret;
2105 struct coresight_platform_data *pdata = NULL;
2106 struct device *dev = init_arg->dev;
2107 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2108 struct coresight_desc desc = { 0 };
2109 u8 major, minor;
2110 char *type_name;
2111
2112 if (!drvdata)
2113 return -EINVAL;
2114
2115 desc.access = *init_arg->csa;
2116
2117 if (!drvdata->arch)
2118 return -EINVAL;
2119
2120 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2121 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2122
2123 if (etm4x_is_ete(drvdata)) {
2124 type_name = "ete";
2125 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
2126 major -= 4;
2127 } else {
2128 type_name = "etm";
2129 }
2130
2131 desc.name = devm_kasprintf(dev, GFP_KERNEL,
2132 "%s%d", type_name, drvdata->cpu);
2133 if (!desc.name)
2134 return -ENOMEM;
2135
2136 etm4_set_default(&drvdata->config);
2137
2138 pdata = coresight_get_platform_data(dev);
2139 if (IS_ERR(pdata))
2140 return PTR_ERR(pdata);
2141
2142 dev->platform_data = pdata;
2143
2144 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2145 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2146 desc.ops = &etm4_cs_ops;
2147 desc.pdata = pdata;
2148 desc.dev = dev;
2149 desc.groups = coresight_etmv4_groups;
2150 drvdata->csdev = coresight_register(&desc);
2151 if (IS_ERR(drvdata->csdev))
2152 return PTR_ERR(drvdata->csdev);
2153
2154 ret = etm_perf_symlink(drvdata->csdev, true);
2155 if (ret) {
2156 coresight_unregister(drvdata->csdev);
2157 return ret;
2158 }
2159
2160 /* register with config infrastructure & load any current features */
2161 ret = etm4_cscfg_register(drvdata->csdev);
2162 if (ret) {
2163 coresight_unregister(drvdata->csdev);
2164 return ret;
2165 }
2166
2167 etmdrvdata[drvdata->cpu] = drvdata;
2168
2169 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2170 drvdata->cpu, type_name, major, minor);
2171
2172 if (boot_enable) {
2173 coresight_enable_sysfs(drvdata->csdev);
2174 drvdata->boot_enable = true;
2175 }
2176
2177 return 0;
2178 }
2179
etm4_probe(struct device * dev)2180 static int etm4_probe(struct device *dev)
2181 {
2182 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2183 struct csdev_access access = { 0 };
2184 struct etm4_init_arg init_arg = { 0 };
2185 struct etm4_init_arg *delayed;
2186
2187 if (WARN_ON(!drvdata))
2188 return -ENOMEM;
2189
2190 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2191 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2192 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2193
2194 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2195 drvdata->save_state = devm_kmalloc(dev,
2196 sizeof(struct etmv4_save_state), GFP_KERNEL);
2197 if (!drvdata->save_state)
2198 return -ENOMEM;
2199 }
2200
2201 spin_lock_init(&drvdata->spinlock);
2202
2203 drvdata->cpu = coresight_get_cpu(dev);
2204 if (drvdata->cpu < 0)
2205 return drvdata->cpu;
2206
2207 init_arg.dev = dev;
2208 init_arg.csa = &access;
2209
2210 /*
2211 * Serialize against CPUHP callbacks to avoid race condition
2212 * between the smp call and saving the delayed probe.
2213 */
2214 cpus_read_lock();
2215 if (smp_call_function_single(drvdata->cpu,
2216 etm4_init_arch_data, &init_arg, 1)) {
2217 /* The CPU was offline, try again once it comes online. */
2218 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2219 if (!delayed) {
2220 cpus_read_unlock();
2221 return -ENOMEM;
2222 }
2223
2224 *delayed = init_arg;
2225
2226 per_cpu(delayed_probe, drvdata->cpu) = delayed;
2227
2228 cpus_read_unlock();
2229 return 0;
2230 }
2231 cpus_read_unlock();
2232
2233 return etm4_add_coresight_dev(&init_arg);
2234 }
2235
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2236 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2237 {
2238 struct etmv4_drvdata *drvdata;
2239 void __iomem *base;
2240 struct device *dev = &adev->dev;
2241 struct resource *res = &adev->res;
2242 int ret;
2243
2244 /* Validity for the resource is already checked by the AMBA core */
2245 base = devm_ioremap_resource(dev, res);
2246 if (IS_ERR(base))
2247 return PTR_ERR(base);
2248
2249 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2250 if (!drvdata)
2251 return -ENOMEM;
2252
2253 drvdata->base = base;
2254 dev_set_drvdata(dev, drvdata);
2255 ret = etm4_probe(dev);
2256 if (!ret)
2257 pm_runtime_put(&adev->dev);
2258
2259 return ret;
2260 }
2261
etm4_probe_platform_dev(struct platform_device * pdev)2262 static int etm4_probe_platform_dev(struct platform_device *pdev)
2263 {
2264 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2265 struct etmv4_drvdata *drvdata;
2266 int ret;
2267
2268 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2269 if (!drvdata)
2270 return -ENOMEM;
2271
2272 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2273 if (IS_ERR(drvdata->pclk))
2274 return -ENODEV;
2275
2276 if (res) {
2277 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2278 if (IS_ERR(drvdata->base)) {
2279 clk_put(drvdata->pclk);
2280 return PTR_ERR(drvdata->base);
2281 }
2282 }
2283
2284 dev_set_drvdata(&pdev->dev, drvdata);
2285 pm_runtime_get_noresume(&pdev->dev);
2286 pm_runtime_set_active(&pdev->dev);
2287 pm_runtime_enable(&pdev->dev);
2288
2289 ret = etm4_probe(&pdev->dev);
2290
2291 pm_runtime_put(&pdev->dev);
2292 if (ret)
2293 pm_runtime_disable(&pdev->dev);
2294
2295 return ret;
2296 }
2297
etm4_probe_cpu(unsigned int cpu)2298 static int etm4_probe_cpu(unsigned int cpu)
2299 {
2300 int ret;
2301 struct etm4_init_arg init_arg;
2302 struct csdev_access access = { 0 };
2303 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2304
2305 if (!iap)
2306 return 0;
2307
2308 init_arg = *iap;
2309 devm_kfree(init_arg.dev, iap);
2310 *this_cpu_ptr(&delayed_probe) = NULL;
2311
2312 ret = pm_runtime_resume_and_get(init_arg.dev);
2313 if (ret < 0) {
2314 dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2315 return 0;
2316 }
2317
2318 init_arg.csa = &access;
2319 etm4_init_arch_data(&init_arg);
2320
2321 etm4_add_coresight_dev(&init_arg);
2322
2323 pm_runtime_put(init_arg.dev);
2324 return 0;
2325 }
2326
2327 static struct amba_cs_uci_id uci_id_etm4[] = {
2328 {
2329 /* ETMv4 UCI data */
2330 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2331 .devarch_mask = ETM_DEVARCH_ID_MASK,
2332 .devtype = CS_DEVTYPE_PE_TRACE,
2333 }
2334 };
2335
clear_etmdrvdata(void * info)2336 static void clear_etmdrvdata(void *info)
2337 {
2338 int cpu = *(int *)info;
2339
2340 etmdrvdata[cpu] = NULL;
2341 per_cpu(delayed_probe, cpu) = NULL;
2342 }
2343
etm4_remove_dev(struct etmv4_drvdata * drvdata)2344 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2345 {
2346 bool had_delayed_probe;
2347 /*
2348 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2349 * and CPU hotplug call backs.
2350 */
2351 cpus_read_lock();
2352
2353 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2354
2355 /*
2356 * The readers for etmdrvdata[] are CPU hotplug call backs
2357 * and PM notification call backs. Change etmdrvdata[i] on
2358 * CPU i ensures these call backs has consistent view
2359 * inside one call back function.
2360 */
2361 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2362 clear_etmdrvdata(&drvdata->cpu);
2363
2364 cpus_read_unlock();
2365
2366 if (!had_delayed_probe) {
2367 etm_perf_symlink(drvdata->csdev, false);
2368 cscfg_unregister_csdev(drvdata->csdev);
2369 coresight_unregister(drvdata->csdev);
2370 }
2371 }
2372
etm4_remove_amba(struct amba_device * adev)2373 static void etm4_remove_amba(struct amba_device *adev)
2374 {
2375 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2376
2377 if (drvdata)
2378 etm4_remove_dev(drvdata);
2379 }
2380
etm4_remove_platform_dev(struct platform_device * pdev)2381 static void etm4_remove_platform_dev(struct platform_device *pdev)
2382 {
2383 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2384
2385 if (drvdata)
2386 etm4_remove_dev(drvdata);
2387 pm_runtime_disable(&pdev->dev);
2388
2389 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2390 clk_put(drvdata->pclk);
2391 }
2392
2393 static const struct amba_id etm4_ids[] = {
2394 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2395 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2396 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2397 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2398 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2399 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2400 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2401 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2402 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2403 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2404 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2405 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2406 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2407 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2408 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2409 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2410 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2411 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2412 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2413 /*
2414 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2415 * CPUs to the list here.
2416 */
2417 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2418 {},
2419 };
2420
2421 MODULE_DEVICE_TABLE(amba, etm4_ids);
2422
2423 static struct amba_driver etm4x_amba_driver = {
2424 .drv = {
2425 .name = "coresight-etm4x",
2426 .suppress_bind_attrs = true,
2427 },
2428 .probe = etm4_probe_amba,
2429 .remove = etm4_remove_amba,
2430 .id_table = etm4_ids,
2431 };
2432
2433 #ifdef CONFIG_PM
etm4_runtime_suspend(struct device * dev)2434 static int etm4_runtime_suspend(struct device *dev)
2435 {
2436 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2437
2438 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2439 clk_disable_unprepare(drvdata->pclk);
2440
2441 return 0;
2442 }
2443
etm4_runtime_resume(struct device * dev)2444 static int etm4_runtime_resume(struct device *dev)
2445 {
2446 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2447
2448 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2449 clk_prepare_enable(drvdata->pclk);
2450
2451 return 0;
2452 }
2453 #endif
2454
2455 static const struct dev_pm_ops etm4_dev_pm_ops = {
2456 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2457 };
2458
2459 static const struct of_device_id etm4_sysreg_match[] = {
2460 { .compatible = "arm,coresight-etm4x-sysreg" },
2461 { .compatible = "arm,embedded-trace-extension" },
2462 {}
2463 };
2464
2465 #ifdef CONFIG_ACPI
2466 static const struct acpi_device_id etm4x_acpi_ids[] = {
2467 {"ARMHC500", 0, 0, 0}, /* ARM CoreSight ETM4x */
2468 {}
2469 };
2470 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2471 #endif
2472
2473 static struct platform_driver etm4_platform_driver = {
2474 .probe = etm4_probe_platform_dev,
2475 .remove = etm4_remove_platform_dev,
2476 .driver = {
2477 .name = "coresight-etm4x",
2478 .of_match_table = etm4_sysreg_match,
2479 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids),
2480 .suppress_bind_attrs = true,
2481 .pm = &etm4_dev_pm_ops,
2482 },
2483 };
2484
etm4x_init(void)2485 static int __init etm4x_init(void)
2486 {
2487 int ret;
2488
2489 ret = etm4_pm_setup();
2490
2491 /* etm4_pm_setup() does its own cleanup - exit on error */
2492 if (ret)
2493 return ret;
2494
2495 ret = amba_driver_register(&etm4x_amba_driver);
2496 if (ret) {
2497 pr_err("Error registering etm4x AMBA driver\n");
2498 goto clear_pm;
2499 }
2500
2501 ret = platform_driver_register(&etm4_platform_driver);
2502 if (!ret)
2503 return 0;
2504
2505 pr_err("Error registering etm4x platform driver\n");
2506 amba_driver_unregister(&etm4x_amba_driver);
2507
2508 clear_pm:
2509 etm4_pm_clear();
2510 return ret;
2511 }
2512
etm4x_exit(void)2513 static void __exit etm4x_exit(void)
2514 {
2515 amba_driver_unregister(&etm4x_amba_driver);
2516 platform_driver_unregister(&etm4_platform_driver);
2517 etm4_pm_clear();
2518 }
2519
2520 module_init(etm4x_init);
2521 module_exit(etm4x_exit);
2522
2523 MODULE_AUTHOR("Pratik Patel <[email protected]>");
2524 MODULE_AUTHOR("Mathieu Poirier <[email protected]>");
2525 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2526 MODULE_LICENSE("GPL v2");
2527