1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <[email protected]>
7 * Copyright (c) 2020 Guenter Roeck <[email protected]>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/hwmon.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 #include <asm/amd_node.h>
24 #include <asm/processor.h>
25
26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27 MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
28 MODULE_LICENSE("GPL");
29
30 static bool force;
31 module_param(force, bool, 0444);
32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34 /* Provide lock for writing to NB_SMU_IND_ADDR */
35 static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39 #endif
40
41 /* CPUID function 0x80000001, ebx */
42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46 /* DRAM controller (PCI function 2) */
47 #define REG_DCT0_CONFIG_HIGH 0x094
48 #define DDR3_MODE BIT(8)
49
50 /* miscellaneous (PCI function 3) */
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
53
54 #define REG_REPORTED_TEMPERATURE 0xa4
55
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57 #define NB_CAP_HTC BIT(10)
58
59 /*
60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
61 * and REG_REPORTED_TEMPERATURE have been moved to
62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
64 */
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68 /* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */
69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
70
71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
72 (offset) + ((x) * 4))
73 #define ZEN_CCD_TEMP_VALID BIT(11)
74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
75
76 #define ZEN_CUR_TEMP_SHIFT 21
77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
78 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
79
80 /*
81 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
82 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
83 * Do not round off to zero for negative Tctl or Tdie values if the flag is set
84 */
85 #define AMD_I3255_STR "3255"
86
87 struct k10temp_data {
88 struct pci_dev *pdev;
89 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
90 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
91 int temp_offset;
92 u32 temp_adjust_mask;
93 u32 show_temp;
94 bool is_zen;
95 u32 ccd_offset;
96 bool disp_negative;
97 };
98
99 #define TCTL_BIT 0
100 #define TDIE_BIT 1
101 #define TCCD_BIT(x) ((x) + 2)
102
103 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
104
105 struct tctl_offset {
106 u8 model;
107 char const *id;
108 int offset;
109 };
110
111 static const struct tctl_offset tctl_offset_table[] = {
112 { 0x17, "AMD Ryzen 5 1600X", 20000 },
113 { 0x17, "AMD Ryzen 7 1700X", 20000 },
114 { 0x17, "AMD Ryzen 7 1800X", 20000 },
115 { 0x17, "AMD Ryzen 7 2700X", 10000 },
116 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
117 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
118 };
119
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)120 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
121 {
122 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
123 }
124
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)125 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
126 {
127 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
128 }
129
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)130 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
131 unsigned int base, int offset, u32 *val)
132 {
133 mutex_lock(&nb_smu_ind_mutex);
134 pci_bus_write_config_dword(pdev->bus, devfn,
135 base, offset);
136 pci_bus_read_config_dword(pdev->bus, devfn,
137 base + 4, val);
138 mutex_unlock(&nb_smu_ind_mutex);
139 }
140
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)141 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
142 {
143 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
144 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
145 }
146
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)147 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
148 {
149 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
150 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
151 }
152
amd_pci_dev_to_node_id(struct pci_dev * pdev)153 static u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
154 {
155 return PCI_SLOT(pdev->devfn) - AMD_NODE0_PCI_SLOT;
156 }
157
read_tempreg_nb_zen(struct pci_dev * pdev,u32 * regval)158 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
159 {
160 if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
161 ZEN_REPORTED_TEMP_CTRL_BASE, regval))
162 *regval = 0;
163 }
164
read_ccd_temp_reg(struct k10temp_data * data,int ccd,u32 * regval)165 static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval)
166 {
167 u16 node_id = amd_pci_dev_to_node_id(data->pdev);
168
169 return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);
170 }
171
get_raw_temp(struct k10temp_data * data)172 static long get_raw_temp(struct k10temp_data *data)
173 {
174 u32 regval;
175 long temp;
176
177 data->read_tempreg(data->pdev, ®val);
178 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
179 if ((regval & data->temp_adjust_mask) ||
180 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
181 temp -= 49000;
182 return temp;
183 }
184
185 static const char *k10temp_temp_label[] = {
186 "Tctl",
187 "Tdie",
188 "Tccd1",
189 "Tccd2",
190 "Tccd3",
191 "Tccd4",
192 "Tccd5",
193 "Tccd6",
194 "Tccd7",
195 "Tccd8",
196 "Tccd9",
197 "Tccd10",
198 "Tccd11",
199 "Tccd12",
200 };
201
k10temp_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)202 static int k10temp_read_labels(struct device *dev,
203 enum hwmon_sensor_types type,
204 u32 attr, int channel, const char **str)
205 {
206 switch (type) {
207 case hwmon_temp:
208 *str = k10temp_temp_label[channel];
209 break;
210 default:
211 return -EOPNOTSUPP;
212 }
213 return 0;
214 }
215
k10temp_read_temp(struct device * dev,u32 attr,int channel,long * val)216 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
217 long *val)
218 {
219 struct k10temp_data *data = dev_get_drvdata(dev);
220 int ret = -EOPNOTSUPP;
221 u32 regval;
222
223 switch (attr) {
224 case hwmon_temp_input:
225 switch (channel) {
226 case 0: /* Tctl */
227 *val = get_raw_temp(data);
228 if (*val < 0 && !data->disp_negative)
229 *val = 0;
230 break;
231 case 1: /* Tdie */
232 *val = get_raw_temp(data) - data->temp_offset;
233 if (*val < 0 && !data->disp_negative)
234 *val = 0;
235 break;
236 case 2 ... 13: /* Tccd{1-12} */
237 ret = read_ccd_temp_reg(data, channel - 2, ®val);
238
239 if (ret)
240 return ret;
241
242 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
243 break;
244 default:
245 return ret;
246 }
247 break;
248 case hwmon_temp_max:
249 *val = 70 * 1000;
250 break;
251 case hwmon_temp_crit:
252 data->read_htcreg(data->pdev, ®val);
253 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
254 break;
255 case hwmon_temp_crit_hyst:
256 data->read_htcreg(data->pdev, ®val);
257 *val = (((regval >> 16) & 0x7f)
258 - ((regval >> 24) & 0xf)) * 500 + 52000;
259 break;
260 default:
261 return ret;
262 }
263 return 0;
264 }
265
k10temp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)266 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
267 u32 attr, int channel, long *val)
268 {
269 switch (type) {
270 case hwmon_temp:
271 return k10temp_read_temp(dev, attr, channel, val);
272 default:
273 return -EOPNOTSUPP;
274 }
275 }
276
k10temp_is_visible(const void * drvdata,enum hwmon_sensor_types type,u32 attr,int channel)277 static umode_t k10temp_is_visible(const void *drvdata,
278 enum hwmon_sensor_types type,
279 u32 attr, int channel)
280 {
281 const struct k10temp_data *data = drvdata;
282 struct pci_dev *pdev = data->pdev;
283 u32 reg;
284
285 switch (type) {
286 case hwmon_temp:
287 switch (attr) {
288 case hwmon_temp_input:
289 if (!HAVE_TEMP(data, channel))
290 return 0;
291 break;
292 case hwmon_temp_max:
293 if (channel || data->is_zen)
294 return 0;
295 break;
296 case hwmon_temp_crit:
297 case hwmon_temp_crit_hyst:
298 if (channel || !data->read_htcreg)
299 return 0;
300
301 pci_read_config_dword(pdev,
302 REG_NORTHBRIDGE_CAPABILITIES,
303 ®);
304 if (!(reg & NB_CAP_HTC))
305 return 0;
306
307 data->read_htcreg(data->pdev, ®);
308 if (!(reg & HTC_ENABLE))
309 return 0;
310 break;
311 case hwmon_temp_label:
312 /* Show temperature labels only on Zen CPUs */
313 if (!data->is_zen || !HAVE_TEMP(data, channel))
314 return 0;
315 break;
316 default:
317 return 0;
318 }
319 break;
320 default:
321 return 0;
322 }
323 return 0444;
324 }
325
has_erratum_319(struct pci_dev * pdev)326 static bool has_erratum_319(struct pci_dev *pdev)
327 {
328 u32 pkg_type, reg_dram_cfg;
329
330 if (boot_cpu_data.x86 != 0x10)
331 return false;
332
333 /*
334 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
335 * may be unreliable.
336 */
337 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
338 if (pkg_type == CPUID_PKGTYPE_F)
339 return true;
340 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
341 return false;
342
343 /* DDR3 memory implies socket AM3, which is good */
344 pci_bus_read_config_dword(pdev->bus,
345 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
346 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
347 if (reg_dram_cfg & DDR3_MODE)
348 return false;
349
350 /*
351 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
352 * memory. We blacklist all the cores which do exist in socket AM2+
353 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
354 * and AM3 formats, but that's the best we can do.
355 */
356 return boot_cpu_data.x86_model < 4 ||
357 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
358 }
359
360 static const struct hwmon_channel_info * const k10temp_info[] = {
361 HWMON_CHANNEL_INFO(temp,
362 HWMON_T_INPUT | HWMON_T_MAX |
363 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
364 HWMON_T_LABEL,
365 HWMON_T_INPUT | HWMON_T_LABEL,
366 HWMON_T_INPUT | HWMON_T_LABEL,
367 HWMON_T_INPUT | HWMON_T_LABEL,
368 HWMON_T_INPUT | HWMON_T_LABEL,
369 HWMON_T_INPUT | HWMON_T_LABEL,
370 HWMON_T_INPUT | HWMON_T_LABEL,
371 HWMON_T_INPUT | HWMON_T_LABEL,
372 HWMON_T_INPUT | HWMON_T_LABEL,
373 HWMON_T_INPUT | HWMON_T_LABEL,
374 HWMON_T_INPUT | HWMON_T_LABEL,
375 HWMON_T_INPUT | HWMON_T_LABEL,
376 HWMON_T_INPUT | HWMON_T_LABEL,
377 HWMON_T_INPUT | HWMON_T_LABEL),
378 NULL
379 };
380
381 static const struct hwmon_ops k10temp_hwmon_ops = {
382 .is_visible = k10temp_is_visible,
383 .read = k10temp_read,
384 .read_string = k10temp_read_labels,
385 };
386
387 static const struct hwmon_chip_info k10temp_chip_info = {
388 .ops = &k10temp_hwmon_ops,
389 .info = k10temp_info,
390 };
391
k10temp_get_ccd_support(struct k10temp_data * data,int limit)392 static void k10temp_get_ccd_support(struct k10temp_data *data, int limit)
393 {
394 u32 regval;
395 int i;
396
397 for (i = 0; i < limit; i++) {
398 /*
399 * Ignore inaccessible CCDs.
400 *
401 * Some systems will return a register value of 0, and the TEMP_VALID
402 * bit check below will naturally fail.
403 *
404 * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for
405 * the register value. And this will incorrectly pass the TEMP_VALID
406 * bit check.
407 */
408 if (read_ccd_temp_reg(data, i, ®val))
409 continue;
410
411 if (regval & ZEN_CCD_TEMP_VALID)
412 data->show_temp |= BIT(TCCD_BIT(i));
413 }
414 }
415
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)416 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
417 {
418 int unreliable = has_erratum_319(pdev);
419 struct device *dev = &pdev->dev;
420 struct k10temp_data *data;
421 struct device *hwmon_dev;
422 int i;
423
424 if (unreliable) {
425 if (!force) {
426 dev_err(dev,
427 "unreliable CPU thermal sensor; monitoring disabled\n");
428 return -ENODEV;
429 }
430 dev_warn(dev,
431 "unreliable CPU thermal sensor; check erratum 319\n");
432 }
433
434 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
435 if (!data)
436 return -ENOMEM;
437
438 data->pdev = pdev;
439 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
440
441 if (boot_cpu_data.x86 == 0x17 &&
442 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
443 data->disp_negative = true;
444 }
445
446 data->is_zen = cpu_feature_enabled(X86_FEATURE_ZEN);
447 if (data->is_zen) {
448 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
449 data->read_tempreg = read_tempreg_nb_zen;
450 } else if (boot_cpu_data.x86 == 0x15 &&
451 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
452 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
453 data->read_htcreg = read_htcreg_nb_f15;
454 data->read_tempreg = read_tempreg_nb_f15;
455 } else {
456 data->read_htcreg = read_htcreg_pci;
457 data->read_tempreg = read_tempreg_pci;
458 }
459
460 if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
461 switch (boot_cpu_data.x86_model) {
462 case 0x1: /* Zen */
463 case 0x8: /* Zen+ */
464 case 0x11: /* Zen APU */
465 case 0x18: /* Zen+ APU */
466 data->ccd_offset = 0x154;
467 k10temp_get_ccd_support(data, 4);
468 break;
469 case 0x31: /* Zen2 Threadripper */
470 case 0x60: /* Renoir */
471 case 0x68: /* Lucienne */
472 case 0x71: /* Zen2 */
473 data->ccd_offset = 0x154;
474 k10temp_get_ccd_support(data, 8);
475 break;
476 case 0xa0 ... 0xaf:
477 data->ccd_offset = 0x300;
478 k10temp_get_ccd_support(data, 8);
479 break;
480 }
481 } else if (boot_cpu_data.x86 == 0x19) {
482 switch (boot_cpu_data.x86_model) {
483 case 0x0 ... 0x1: /* Zen3 SP3/TR */
484 case 0x8: /* Zen3 TR Chagall */
485 case 0x21: /* Zen3 Ryzen Desktop */
486 case 0x50 ... 0x5f: /* Green Sardine */
487 data->ccd_offset = 0x154;
488 k10temp_get_ccd_support(data, 8);
489 break;
490 case 0x40 ... 0x4f: /* Yellow Carp */
491 data->ccd_offset = 0x300;
492 k10temp_get_ccd_support(data, 8);
493 break;
494 case 0x60 ... 0x6f:
495 case 0x70 ... 0x7f:
496 data->ccd_offset = 0x308;
497 k10temp_get_ccd_support(data, 8);
498 break;
499 case 0x10 ... 0x1f:
500 case 0xa0 ... 0xaf:
501 data->ccd_offset = 0x300;
502 k10temp_get_ccd_support(data, 12);
503 break;
504 }
505 }
506
507 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
508 const struct tctl_offset *entry = &tctl_offset_table[i];
509
510 if (boot_cpu_data.x86 == entry->model &&
511 strstr(boot_cpu_data.x86_model_id, entry->id)) {
512 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
513 data->temp_offset = entry->offset;
514 break;
515 }
516 }
517
518 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
519 &k10temp_chip_info,
520 NULL);
521 return PTR_ERR_OR_ZERO(hwmon_dev);
522 }
523
524 static const struct pci_device_id k10temp_id_table[] = {
525 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
526 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
527 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
528 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
529 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
530 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
531 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
532 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
533 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
534 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
535 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
536 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
537 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
538 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
539 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
540 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
541 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
542 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
543 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
544 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
545 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
546 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
547 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
548 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
549 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
550 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) },
551 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
552 {}
553 };
554 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
555
556 static struct pci_driver k10temp_driver = {
557 .name = "k10temp",
558 .id_table = k10temp_id_table,
559 .probe = k10temp_probe,
560 };
561
562 module_pci_driver(k10temp_driver);
563