1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _QUICKSPI_DEV_H_ 5 #define _QUICKSPI_DEV_H_ 6 7 #include <linux/bits.h> 8 #include <linux/hid-over-spi.h> 9 #include <linux/sizes.h> 10 #include <linux/wait.h> 11 12 #include "quickspi-protocol.h" 13 14 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT1 0x7E49 15 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT2 0x7E4B 16 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT1 0xA849 17 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT2 0xA84B 18 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT1 0xE349 19 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT2 0xE34B 20 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT1 0xE449 21 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT2 0xE44B 22 23 /* HIDSPI special ACPI parameters DSM methods */ 24 #define ACPI_QUICKSPI_REVISION_NUM 2 25 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_HDR_ADDR 1 26 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_BDY_ADDR 2 27 #define ACPI_QUICKSPI_FUNC_NUM_OUTPUT_REP_ADDR 3 28 #define ACPI_QUICKSPI_FUNC_NUM_READ_OPCODE 4 29 #define ACPI_QUICKSPI_FUNC_NUM_WRITE_OPCODE 5 30 #define ACPI_QUICKSPI_FUNC_NUM_IO_MODE 6 31 32 /* QickSPI device special ACPI parameters DSM methods */ 33 #define ACPI_QUICKSPI_FUNC_NUM_CONNECTION_SPEED 1 34 #define ACPI_QUICKSPI_FUNC_NUM_LIMIT_PACKET_SIZE 2 35 #define ACPI_QUICKSPI_FUNC_NUM_PERFORMANCE_LIMIT 3 36 37 /* Platform special ACPI parameters DSM methods */ 38 #define ACPI_QUICKSPI_FUNC_NUM_ACTIVE_LTR 1 39 #define ACPI_QUICKSPI_FUNC_NUM_LP_LTR 2 40 41 #define SPI_WRITE_IO_MODE BIT(13) 42 #define SPI_IO_MODE_OPCODE GENMASK(15, 14) 43 #define PERFORMANCE_LIMITATION GENMASK(15, 0) 44 45 /* Packet size value, the unit is 16 bytes */ 46 #define DEFAULT_MIN_PACKET_SIZE_VALUE 4 47 #define MAX_PACKET_SIZE_VALUE_MTL 128 48 #define MAX_PACKET_SIZE_VALUE_LNL 256 49 50 /* 51 * THC uses runtime auto suspend to dynamically switch between THC active LTR 52 * and low power LTR to save CPU power. 53 * Default value is 5000ms, that means if no touch event in this time, THC will 54 * change to low power LTR mode. 55 */ 56 #define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000 57 58 enum quickspi_dev_state { 59 QUICKSPI_NONE, 60 QUICKSPI_RESETING, 61 QUICKSPI_RESETED, 62 QUICKSPI_INITED, 63 QUICKSPI_ENABLED, 64 QUICKSPI_DISABLED, 65 }; 66 67 /** 68 * struct quickspi_driver_data - Driver specific data for quickspi device 69 * @max_packet_size_value: identify max packet size, unit is 16 bytes 70 */ 71 struct quickspi_driver_data { 72 u32 max_packet_size_value; 73 }; 74 75 struct device; 76 struct pci_dev; 77 struct thc_device; 78 struct hid_device; 79 struct acpi_device; 80 81 /** 82 * struct quickspi_device - THC QuickSpi device struct 83 * @dev: point to kernel device 84 * @pdev: point to PCI device 85 * @thc_hw: point to THC device 86 * @hid_dev: point to hid device 87 * @acpi_dev: point to ACPI device 88 * @driver_data: point to quickspi specific driver data 89 * @state: THC SPI device state 90 * @mem_addr: MMIO memory address 91 * @dev_desc: device descriptor for HIDSPI protocol 92 * @input_report_hdr_addr: device input report header address 93 * @input_report_bdy_addr: device input report body address 94 * @output_report_bdy_addr: device output report address 95 * @spi_freq_val: device supported max SPI frequnecy, in Hz 96 * @spi_read_io_mode: device supported SPI read io mode 97 * @spi_write_io_mode: device supported SPI write io mode 98 * @spi_read_opcode: device read opcode 99 * @spi_write_opcode: device write opcode 100 * @limit_packet_size: 1 - limit read/write packet to 64Bytes 101 * 0 - device no packet size limiation for read/write 102 * @performance_limit: delay time, in ms. 103 * if device has performance limitation, must give a delay 104 * before write operation after a read operation. 105 * @active_ltr_val: THC active LTR value 106 * @low_power_ltr_val: THC low power LTR value 107 * @report_descriptor: store a copy of device report descriptor 108 * @input_buf: store a copy of latest input report data 109 * @report_buf: store a copy of latest input/output report packet from set/get feature 110 * @report_len: the length of input/output report packet 111 * @reset_ack_wq: workqueue for waiting reset response from device 112 * @reset_ack: indicate reset response received or not 113 * @nondma_int_received_wq: workqueue for waiting THC non-DMA interrupt 114 * @nondma_int_received: indicate THC non-DMA interrupt received or not 115 * @report_desc_got_wq: workqueue for waiting device report descriptor 116 * @report_desc_got: indicate device report descritor received or not 117 * @set_power_on_wq: workqueue for waiting set power on response from device 118 * @set_power_on: indicate set power on response received or not 119 * @get_feature_cmpl_wq: workqueue for waiting get feature response from device 120 * @get_feature_cmpl: indicate get feature received or not 121 * @set_feature_cmpl_wq: workqueue for waiting set feature to device 122 * @set_feature_cmpl: indicate set feature send complete or not 123 */ 124 struct quickspi_device { 125 struct device *dev; 126 struct pci_dev *pdev; 127 struct thc_device *thc_hw; 128 struct hid_device *hid_dev; 129 struct acpi_device *acpi_dev; 130 struct quickspi_driver_data *driver_data; 131 enum quickspi_dev_state state; 132 133 void __iomem *mem_addr; 134 135 struct hidspi_dev_descriptor dev_desc; 136 u32 input_report_hdr_addr; 137 u32 input_report_bdy_addr; 138 u32 output_report_addr; 139 u32 spi_freq_val; 140 u32 spi_read_io_mode; 141 u32 spi_write_io_mode; 142 u32 spi_read_opcode; 143 u32 spi_write_opcode; 144 u32 limit_packet_size; 145 u32 spi_packet_size; 146 u32 performance_limit; 147 148 u32 active_ltr_val; 149 u32 low_power_ltr_val; 150 151 u8 *report_descriptor; 152 u8 *input_buf; 153 u8 *report_buf; 154 u32 report_len; 155 156 wait_queue_head_t reset_ack_wq; 157 bool reset_ack; 158 159 wait_queue_head_t nondma_int_received_wq; 160 bool nondma_int_received; 161 162 wait_queue_head_t report_desc_got_wq; 163 bool report_desc_got; 164 165 wait_queue_head_t get_report_cmpl_wq; 166 bool get_report_cmpl; 167 168 wait_queue_head_t set_report_cmpl_wq; 169 bool set_report_cmpl; 170 }; 171 172 #endif /* _QUICKSPI_DEV_H_ */ 173