1 /*
2  * Copyright (C) 2015 Red Hat, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_gem_atomic_helper.h>
30 #include <linux/virtio_dma_buf.h>
31 
32 #include "virtgpu_drv.h"
33 
34 static const uint32_t virtio_gpu_formats[] = {
35 	DRM_FORMAT_HOST_XRGB8888,
36 };
37 
38 static const uint32_t virtio_gpu_cursor_formats[] = {
39 	DRM_FORMAT_HOST_ARGB8888,
40 };
41 
virtio_gpu_translate_format(uint32_t drm_fourcc)42 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
43 {
44 	uint32_t format;
45 
46 	switch (drm_fourcc) {
47 	case DRM_FORMAT_XRGB8888:
48 		format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
49 		break;
50 	case DRM_FORMAT_ARGB8888:
51 		format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
52 		break;
53 	case DRM_FORMAT_BGRX8888:
54 		format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
55 		break;
56 	case DRM_FORMAT_BGRA8888:
57 		format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
58 		break;
59 	default:
60 		/*
61 		 * This should not happen, we handle everything listed
62 		 * in virtio_gpu_formats[].
63 		 */
64 		format = 0;
65 		break;
66 	}
67 	WARN_ON(format == 0);
68 	return format;
69 }
70 
71 static struct
virtio_gpu_plane_duplicate_state(struct drm_plane * plane)72 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane)
73 {
74 	struct virtio_gpu_plane_state *new;
75 
76 	if (WARN_ON(!plane->state))
77 		return NULL;
78 
79 	new = kzalloc(sizeof(*new), GFP_KERNEL);
80 	if (!new)
81 		return NULL;
82 
83 	__drm_atomic_helper_plane_duplicate_state(plane, &new->base);
84 
85 	return &new->base;
86 }
87 
88 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
89 	.update_plane		= drm_atomic_helper_update_plane,
90 	.disable_plane		= drm_atomic_helper_disable_plane,
91 	.reset			= drm_atomic_helper_plane_reset,
92 	.atomic_duplicate_state = virtio_gpu_plane_duplicate_state,
93 	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
94 };
95 
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)96 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
97 					 struct drm_atomic_state *state)
98 {
99 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
100 										 plane);
101 	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
102 										 plane);
103 	bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
104 	struct drm_crtc_state *crtc_state;
105 	int ret;
106 
107 	if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
108 		return 0;
109 
110 	/*
111 	 * Ignore damage clips if the framebuffer attached to the plane's state
112 	 * has changed since the last plane update (page-flip). In this case, a
113 	 * full plane update should happen because uploads are done per-buffer.
114 	 */
115 	if (old_plane_state->fb != new_plane_state->fb)
116 		new_plane_state->ignore_damage_clips = true;
117 
118 	crtc_state = drm_atomic_get_crtc_state(state,
119 					       new_plane_state->crtc);
120 	if (IS_ERR(crtc_state))
121                 return PTR_ERR(crtc_state);
122 
123 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
124 						  DRM_PLANE_NO_SCALING,
125 						  DRM_PLANE_NO_SCALING,
126 						  is_cursor, true);
127 	return ret;
128 }
129 
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)130 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
131 				      struct drm_plane_state *state,
132 				      struct drm_rect *rect)
133 {
134 	struct virtio_gpu_object *bo =
135 		gem_to_virtio_gpu_obj(state->fb->obj[0]);
136 	struct virtio_gpu_object_array *objs;
137 	uint32_t w = rect->x2 - rect->x1;
138 	uint32_t h = rect->y2 - rect->y1;
139 	uint32_t x = rect->x1;
140 	uint32_t y = rect->y1;
141 	uint32_t off = x * state->fb->format->cpp[0] +
142 		y * state->fb->pitches[0];
143 
144 	objs = virtio_gpu_array_alloc(1);
145 	if (!objs)
146 		return;
147 	virtio_gpu_array_add_obj(objs, &bo->base.base);
148 
149 	virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
150 					   objs, NULL);
151 }
152 
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)153 static void virtio_gpu_resource_flush(struct drm_plane *plane,
154 				      uint32_t x, uint32_t y,
155 				      uint32_t width, uint32_t height)
156 {
157 	struct drm_device *dev = plane->dev;
158 	struct virtio_gpu_device *vgdev = dev->dev_private;
159 	struct virtio_gpu_framebuffer *vgfb;
160 	struct virtio_gpu_plane_state *vgplane_st;
161 	struct virtio_gpu_object *bo;
162 
163 	vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
164 	vgplane_st = to_virtio_gpu_plane_state(plane->state);
165 	bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
166 	if (vgplane_st->fence) {
167 		struct virtio_gpu_object_array *objs;
168 
169 		objs = virtio_gpu_array_alloc(1);
170 		if (!objs)
171 			return;
172 		virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
173 		virtio_gpu_array_lock_resv(objs);
174 		virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
175 					      width, height, objs,
176 					      vgplane_st->fence);
177 		virtio_gpu_notify(vgdev);
178 		dma_fence_wait_timeout(&vgplane_st->fence->f, true,
179 				       msecs_to_jiffies(50));
180 	} else {
181 		virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
182 					      width, height, NULL, NULL);
183 		virtio_gpu_notify(vgdev);
184 	}
185 }
186 
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)187 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
188 					    struct drm_atomic_state *state)
189 {
190 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
191 									   plane);
192 	struct drm_device *dev = plane->dev;
193 	struct virtio_gpu_device *vgdev = dev->dev_private;
194 	struct virtio_gpu_output *output = NULL;
195 	struct virtio_gpu_object *bo;
196 	struct drm_rect rect;
197 
198 	if (plane->state->crtc)
199 		output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
200 	if (old_state->crtc)
201 		output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
202 	if (WARN_ON(!output))
203 		return;
204 
205 	if (!plane->state->fb || !output->crtc.state->active) {
206 		DRM_DEBUG("nofb\n");
207 		virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
208 					   plane->state->src_w >> 16,
209 					   plane->state->src_h >> 16,
210 					   0, 0);
211 		virtio_gpu_notify(vgdev);
212 		return;
213 	}
214 
215 	if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
216 		return;
217 
218 	bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
219 	if (bo->dumb)
220 		virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
221 
222 	if (plane->state->fb != old_state->fb ||
223 	    plane->state->src_w != old_state->src_w ||
224 	    plane->state->src_h != old_state->src_h ||
225 	    plane->state->src_x != old_state->src_x ||
226 	    plane->state->src_y != old_state->src_y ||
227 	    output->needs_modeset) {
228 		output->needs_modeset = false;
229 		DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
230 			  bo->hw_res_handle,
231 			  plane->state->crtc_w, plane->state->crtc_h,
232 			  plane->state->crtc_x, plane->state->crtc_y,
233 			  plane->state->src_w >> 16,
234 			  plane->state->src_h >> 16,
235 			  plane->state->src_x >> 16,
236 			  plane->state->src_y >> 16);
237 
238 		if (bo->host3d_blob || bo->guest_blob) {
239 			virtio_gpu_cmd_set_scanout_blob
240 						(vgdev, output->index, bo,
241 						 plane->state->fb,
242 						 plane->state->src_w >> 16,
243 						 plane->state->src_h >> 16,
244 						 plane->state->src_x >> 16,
245 						 plane->state->src_y >> 16);
246 		} else {
247 			virtio_gpu_cmd_set_scanout(vgdev, output->index,
248 						   bo->hw_res_handle,
249 						   plane->state->src_w >> 16,
250 						   plane->state->src_h >> 16,
251 						   plane->state->src_x >> 16,
252 						   plane->state->src_y >> 16);
253 		}
254 	}
255 
256 	virtio_gpu_resource_flush(plane,
257 				  rect.x1,
258 				  rect.y1,
259 				  rect.x2 - rect.x1,
260 				  rect.y2 - rect.y1);
261 }
262 
virtio_gpu_prepare_imported_obj(struct drm_plane * plane,struct drm_plane_state * new_state,struct drm_gem_object * obj)263 static int virtio_gpu_prepare_imported_obj(struct drm_plane *plane,
264 					   struct drm_plane_state *new_state,
265 					   struct drm_gem_object *obj)
266 {
267 	struct virtio_gpu_device *vgdev = plane->dev->dev_private;
268 	struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
269 	struct dma_buf_attachment *attach = obj->import_attach;
270 	struct dma_resv *resv = attach->dmabuf->resv;
271 	struct virtio_gpu_mem_entry *ents = NULL;
272 	unsigned int nents;
273 	int ret;
274 
275 	dma_resv_lock(resv, NULL);
276 
277 	ret = dma_buf_pin(attach);
278 	if (ret) {
279 		dma_resv_unlock(resv);
280 		return ret;
281 	}
282 
283 	if (!bo->sgt) {
284 		ret = virtgpu_dma_buf_import_sgt(&ents, &nents,
285 						 bo, attach);
286 		if (ret)
287 			goto err;
288 
289 		virtio_gpu_object_attach(vgdev, bo, ents, nents);
290 	}
291 
292 	dma_resv_unlock(resv);
293 	return 0;
294 
295 err:
296 	dma_buf_unpin(attach);
297 	dma_resv_unlock(resv);
298 	return ret;
299 }
300 
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)301 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
302 				       struct drm_plane_state *new_state)
303 {
304 	struct drm_device *dev = plane->dev;
305 	struct virtio_gpu_device *vgdev = dev->dev_private;
306 	struct virtio_gpu_framebuffer *vgfb;
307 	struct virtio_gpu_plane_state *vgplane_st;
308 	struct virtio_gpu_object *bo;
309 	struct drm_gem_object *obj;
310 	int ret;
311 
312 	if (!new_state->fb)
313 		return 0;
314 
315 	vgfb = to_virtio_gpu_framebuffer(new_state->fb);
316 	vgplane_st = to_virtio_gpu_plane_state(new_state);
317 	bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
318 
319 	drm_gem_plane_helper_prepare_fb(plane, new_state);
320 
321 	if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
322 		return 0;
323 
324 	obj = new_state->fb->obj[0];
325 	if (bo->dumb || obj->import_attach) {
326 		vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,
327 						     vgdev->fence_drv.context,
328 						     0);
329 		if (!vgplane_st->fence)
330 			return -ENOMEM;
331 	}
332 
333 	if (obj->import_attach) {
334 		ret = virtio_gpu_prepare_imported_obj(plane, new_state, obj);
335 		if (ret)
336 			goto err_fence;
337 	}
338 
339 	return 0;
340 
341 err_fence:
342 	if (vgplane_st->fence) {
343 		dma_fence_put(&vgplane_st->fence->f);
344 		vgplane_st->fence = NULL;
345 	}
346 
347 	return ret;
348 }
349 
virtio_gpu_cleanup_imported_obj(struct drm_gem_object * obj)350 static void virtio_gpu_cleanup_imported_obj(struct drm_gem_object *obj)
351 {
352 	struct dma_buf_attachment *attach = obj->import_attach;
353 	struct dma_resv *resv = attach->dmabuf->resv;
354 
355 	dma_resv_lock(resv, NULL);
356 	dma_buf_unpin(attach);
357 	dma_resv_unlock(resv);
358 }
359 
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)360 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
361 					struct drm_plane_state *state)
362 {
363 	struct virtio_gpu_plane_state *vgplane_st;
364 	struct drm_gem_object *obj;
365 
366 	if (!state->fb)
367 		return;
368 
369 	vgplane_st = to_virtio_gpu_plane_state(state);
370 	if (vgplane_st->fence) {
371 		dma_fence_put(&vgplane_st->fence->f);
372 		vgplane_st->fence = NULL;
373 	}
374 
375 	obj = state->fb->obj[0];
376 	if (obj->import_attach)
377 		virtio_gpu_cleanup_imported_obj(obj);
378 }
379 
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)380 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
381 					   struct drm_atomic_state *state)
382 {
383 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
384 									   plane);
385 	struct drm_device *dev = plane->dev;
386 	struct virtio_gpu_device *vgdev = dev->dev_private;
387 	struct virtio_gpu_output *output = NULL;
388 	struct virtio_gpu_framebuffer *vgfb;
389 	struct virtio_gpu_plane_state *vgplane_st;
390 	struct virtio_gpu_object *bo = NULL;
391 	uint32_t handle;
392 
393 	if (plane->state->crtc)
394 		output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
395 	if (old_state->crtc)
396 		output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
397 	if (WARN_ON(!output))
398 		return;
399 
400 	if (plane->state->fb) {
401 		vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
402 		vgplane_st = to_virtio_gpu_plane_state(plane->state);
403 		bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
404 		handle = bo->hw_res_handle;
405 	} else {
406 		handle = 0;
407 	}
408 
409 	if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
410 		/* new cursor -- update & wait */
411 		struct virtio_gpu_object_array *objs;
412 
413 		objs = virtio_gpu_array_alloc(1);
414 		if (!objs)
415 			return;
416 		virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
417 		virtio_gpu_array_lock_resv(objs);
418 		virtio_gpu_cmd_transfer_to_host_2d
419 			(vgdev, 0,
420 			 plane->state->crtc_w,
421 			 plane->state->crtc_h,
422 			 0, 0, objs, vgplane_st->fence);
423 		virtio_gpu_notify(vgdev);
424 		dma_fence_wait(&vgplane_st->fence->f, true);
425 	}
426 
427 	if (plane->state->fb != old_state->fb) {
428 		DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
429 			  plane->state->crtc_x,
430 			  plane->state->crtc_y,
431 			  plane->state->hotspot_x,
432 			  plane->state->hotspot_y);
433 		output->cursor.hdr.type =
434 			cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
435 		output->cursor.resource_id = cpu_to_le32(handle);
436 		if (plane->state->fb) {
437 			output->cursor.hot_x =
438 				cpu_to_le32(plane->state->hotspot_x);
439 			output->cursor.hot_y =
440 				cpu_to_le32(plane->state->hotspot_y);
441 		} else {
442 			output->cursor.hot_x = cpu_to_le32(0);
443 			output->cursor.hot_y = cpu_to_le32(0);
444 		}
445 	} else {
446 		DRM_DEBUG("move +%d+%d\n",
447 			  plane->state->crtc_x,
448 			  plane->state->crtc_y);
449 		output->cursor.hdr.type =
450 			cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
451 	}
452 	output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
453 	output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
454 	virtio_gpu_cursor_ping(vgdev, output);
455 }
456 
457 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
458 	.prepare_fb		= virtio_gpu_plane_prepare_fb,
459 	.cleanup_fb		= virtio_gpu_plane_cleanup_fb,
460 	.atomic_check		= virtio_gpu_plane_atomic_check,
461 	.atomic_update		= virtio_gpu_primary_plane_update,
462 };
463 
464 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
465 	.prepare_fb		= virtio_gpu_plane_prepare_fb,
466 	.cleanup_fb		= virtio_gpu_plane_cleanup_fb,
467 	.atomic_check		= virtio_gpu_plane_atomic_check,
468 	.atomic_update		= virtio_gpu_cursor_plane_update,
469 };
470 
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)471 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
472 					enum drm_plane_type type,
473 					int index)
474 {
475 	struct drm_device *dev = vgdev->ddev;
476 	const struct drm_plane_helper_funcs *funcs;
477 	struct drm_plane *plane;
478 	const uint32_t *formats;
479 	int nformats;
480 
481 	if (type == DRM_PLANE_TYPE_CURSOR) {
482 		formats = virtio_gpu_cursor_formats;
483 		nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
484 		funcs = &virtio_gpu_cursor_helper_funcs;
485 	} else {
486 		formats = virtio_gpu_formats;
487 		nformats = ARRAY_SIZE(virtio_gpu_formats);
488 		funcs = &virtio_gpu_primary_helper_funcs;
489 	}
490 
491 	plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
492 					   1 << index, &virtio_gpu_plane_funcs,
493 					   formats, nformats, NULL, type, NULL);
494 	if (IS_ERR(plane))
495 		return plane;
496 
497 	drm_plane_helper_add(plane, funcs);
498 
499 	if (type == DRM_PLANE_TYPE_PRIMARY)
500 		drm_plane_enable_fb_damage_clips(plane);
501 
502 	return plane;
503 }
504