1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="display/mdp_common.xml"/> 7 8<domain name="MDP4" width="32"> 9 <enum name="mdp4_pipe"> 10 <brief>pipe names, index into PIPE[]</brief> 11 <value name="VG1" value="0"/> 12 <value name="VG2" value="1"/> 13 <value name="RGB1" value="2"/> 14 <value name="RGB2" value="3"/> 15 <value name="RGB3" value="4"/> 16 <value name="VG3" value="5"/> 17 <value name="VG4" value="6"/> 18 </enum> 19 20 <enum name="mdp4_mixer"> 21 <value name="MIXER0" value="0"/> 22 <value name="MIXER1" value="1"/> 23 <value name="MIXER2" value="2"/> 24 </enum> 25 26 <enum name="mdp4_intf"> 27 <!-- 28 A bit confusing the enums for interface selection: 29 enum { 30 LCDC_RGB_INTF, /* 0 */ 31 DTV_INTF = LCDC_RGB_INTF, /* 0 */ 32 MDDI_LCDC_INTF, /* 1 */ 33 MDDI_INTF, /* 2 */ 34 EBI2_INTF, /* 3 */ 35 TV_INTF = EBI2_INTF, /* 3 */ 36 DSI_VIDEO_INTF, 37 DSI_CMD_INTF 38 }; 39 there is some overlap, and not all the values end up getting 40 written to hw (mdp4_display_intf_sel() remaps the last two 41 values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so 42 taking some liberties in guessing the actual meanings/names: 43 --> 44 <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) --> 45 <value name="INTF_DSI_VIDEO" value="1"/> 46 <value name="INTF_DSI_CMD" value="2"/> 47 <value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) --> 48 </enum> 49 <enum name="mdp4_cursor_format"> 50 <value name="CURSOR_ARGB" value="1"/> 51 <value name="CURSOR_XRGB" value="2"/> 52 </enum> 53 <enum name="mdp4_frame_format"> 54 <value name="FRAME_LINEAR" value="0"/> 55 <value name="FRAME_TILE_ARGB_4X4" value="1"/> 56 <value name="FRAME_TILE_YCBCR_420" value="2"/> 57 </enum> 58 <enum name="mdp4_scale_unit"> 59 <value name="SCALE_FIR" value="0"/> 60 <value name="SCALE_MN_PHASE" value="1"/> 61 <value name="SCALE_PIXEL_RPT" value="2"/> 62 </enum> 63 64 <bitset name="mdp4_layermixer_in_cfg" inline="yes"> 65 <brief>appears to map pipe to mixer stage</brief> 66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/> 67 <bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/> 68 <bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/> 69 <bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/> 70 <bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/> 71 <bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/> 72 <bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/> 73 <bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/> 74 <bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/> 75 <bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/> 76 <bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/> 77 <bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/> 78 <bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/> 79 <bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/> 80 <bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/> 81 <bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/> 82 </bitset> 83 84 <bitset name="MDP4_IRQ"> 85 <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/> 86 <bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/> 87 <bitfield name="DMA_S_DONE" pos="2" type="boolean"/> 88 <bitfield name="DMA_E_DONE" pos="3" type="boolean"/> 89 <bitfield name="DMA_P_DONE" pos="4" type="boolean"/> 90 <bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/> 91 <bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/> 92 <bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/> 93 <bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/> 94 <bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/> 95 <bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/> 96 <bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer --> 97 <bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/> 98 <bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/> 99 <bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/> 100 </bitset> 101 102 <reg32 offset="0x00000" name="VERSION"> 103 <!-- 104 from mdp_probe() we can see minor rev starts at 16.. assume 105 major is above that.. not sure the rest of bits but doesn't 106 really seem to matter 107 --> 108 <bitfield name="MINOR" low="16" high="23" type="uint"/> 109 <bitfield name="MAJOR" low="24" high="31" type="uint"/> 110 </reg32> 111 <reg32 offset="0x00004" name="OVLP0_KICK"/> 112 <reg32 offset="0x00008" name="OVLP1_KICK"/> 113 <reg32 offset="0x000d0" name="OVLP2_KICK"/> 114 <reg32 offset="0x0000c" name="DMA_P_KICK"/> 115 <reg32 offset="0x00010" name="DMA_S_KICK"/> 116 <reg32 offset="0x00014" name="DMA_E_KICK"/> 117 <reg32 offset="0x00018" name="DISP_STATUS"/> 118 119 <reg32 offset="0x00038" name="DISP_INTF_SEL"> 120 <bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/> 121 <bitfield name="SEC" low="2" high="3" type="mdp4_intf"/> 122 <bitfield name="EXT" low="4" high="5" type="mdp4_intf"/> 123 <bitfield name="DSI_VIDEO" pos="6" type="boolean"/> 124 <bitfield name="DSI_CMD" pos="7" type="boolean"/> 125 </reg32> 126 <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 --> 127 <reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. --> 128 <reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/> 129 <reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/> 130 <reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/> 131 <reg32 offset="0x00060" name="EBI2_LCD0"/> 132 <reg32 offset="0x00064" name="EBI2_LCD1"/> 133 <reg32 offset="0x00070" name="PORTMAP_MODE"/> 134 135 <!-- mdp chip-select controller: --> 136 <reg32 offset="0x000c0" name="CS_CONTROLLER0"/> 137 <reg32 offset="0x000c4" name="CS_CONTROLLER1"/> 138 139 <reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/> 140 <reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/> 141 <reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/> 142 143 <reg32 offset="0x30050" name="VG2_SRC_FORMAT"/> 144 <reg32 offset="0x31008" name="VG2_CONST_COLOR"/> 145 146 <reg32 offset="0x18000" name="OVERLAY_FLUSH"> 147 <bitfield name="OVLP0" pos="0" type="boolean"/> 148 <bitfield name="OVLP1" pos="1" type="boolean"/> 149 <bitfield name="VG1" pos="2" type="boolean"/> 150 <bitfield name="VG2" pos="3" type="boolean"/> 151 <bitfield name="RGB1" pos="4" type="boolean"/> 152 <bitfield name="RGB2" pos="5" type="boolean"/> 153 </reg32> 154 155 <array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000"> 156 <reg32 offset="0x0004" name="CFG"/> 157 <reg32 offset="0x0008" name="SIZE" type="reg_wh"/> 158 <reg32 offset="0x000c" name="BASE"/> 159 <reg32 offset="0x0010" name="STRIDE" type="uint"/> 160 <reg32 offset="0x0014" name="OPMODE"/> 161 162 <array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c"> 163 <reg32 offset="0x00" name="OP"> 164 <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/> 165 <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/> 166 <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/> 167 <bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/> 168 <bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/> 169 <bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/> 170 <bitfield name="FG_TRANSP" pos="8" type="boolean"/> 171 <bitfield name="BG_TRANSP" pos="9" type="boolean"/> 172 </reg32> 173 <reg32 offset="0x04" name="FG_ALPHA"/> 174 <reg32 offset="0x08" name="BG_ALPHA"/> 175 <reg32 offset="0x0c" name="TRANSP_LOW0"/> 176 <reg32 offset="0x10" name="TRANSP_LOW1"/> 177 <reg32 offset="0x14" name="TRANSP_HIGH0"/> 178 <reg32 offset="0x18" name="TRANSP_HIGH1"/> 179 </array> 180 181 <array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4"> 182 <reg32 offset="0" name="SEL"> 183 <bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha --> 184 </reg32> 185 </array> 186 187 <reg32 offset="0x0180" name="TRANSP_LOW0"/> 188 <reg32 offset="0x0184" name="TRANSP_LOW1"/> 189 <reg32 offset="0x0188" name="TRANSP_HIGH0"/> 190 <reg32 offset="0x018c" name="TRANSP_HIGH1"/> 191 192 <reg32 offset="0x0200" name="CSC_CONFIG"/> 193 194 <array offset="0x2000" name="CSC" length="1" stride="0x700"> 195 <array offset="0x400" name="MV" length="9" stride="4"> 196 <reg32 offset="0" name="VAL"/> 197 </array> 198 <array offset="0x500" name="PRE_BV" length="3" stride="4"> 199 <reg32 offset="0" name="VAL"/> 200 </array> 201 <array offset="0x580" name="POST_BV" length="3" stride="4"> 202 <reg32 offset="0" name="VAL"/> 203 </array> 204 <array offset="0x600" name="PRE_LV" length="6" stride="4"> 205 <reg32 offset="0" name="VAL"/> 206 </array> 207 <array offset="0x680" name="POST_LV" length="6" stride="4"> 208 <reg32 offset="0" name="VAL"/> 209 </array> 210 </array> 211 </array> 212 213 <enum name="mdp4_dma"> 214 <value name="DMA_P" value="0"/> 215 <value name="DMA_S" value="1"/> 216 <value name="DMA_E" value="2"/> 217 </enum> 218 <reg32 offset="0x90070" name="DMA_P_OP_MODE"/> 219 <array offset="0x94800" name="LUTN" length="2" stride="0x400"> 220 <array offset="0" name="LUT" length="0x100" stride="4"> 221 <reg32 offset="0" name="VAL"/> 222 </array> 223 </array> 224 <reg32 offset="0xa0028" name="DMA_S_OP_MODE"/> 225 <!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. --> 226 <reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/> 227 <array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma"> 228 <reg32 offset="0x0000" name="CONFIG"> 229 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/> 230 <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/> 231 <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/> 232 <bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/> 233 <bitfield name="PACK" low="8" high="15"/> 234 <!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E --> 235 <bitfield name="DEFLKR_EN" pos="24" type="boolean"/> 236 <bitfield name="DITHER_EN" pos="24" type="boolean"/> 237 </reg32> 238 <reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/> 239 <reg32 offset="0x0008" name="SRC_BASE"/> 240 <reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/> 241 <reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/> 242 243 <reg32 offset="0x0044" name="CURSOR_SIZE"> 244 <!-- seems the limit is 64x64: --> 245 <bitfield name="WIDTH" low="0" high="6" type="uint"/> 246 <bitfield name="HEIGHT" low="16" high="22" type="uint"/> 247 </reg32> 248 <reg32 offset="0x0048" name="CURSOR_BASE"/> 249 <reg32 offset="0x004c" name="CURSOR_POS"> 250 <bitfield name="X" low="0" high="15" type="uint"/> 251 <bitfield name="Y" low="16" high="31" type="uint"/> 252 </reg32> 253 <reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG"> 254 <bitfield name="CURSOR_EN" pos="0" type="boolean"/> 255 <bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/> 256 <bitfield name="TRANSP_EN" pos="3" type="boolean"/> 257 </reg32> 258 <reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/> 259 <reg32 offset="0x0068" name="BLEND_TRANS_LOW"/> 260 <reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/> 261 262 <reg32 offset="0x1004" name="FETCH_CONFIG"/> 263 <array offset="0x3000" name="CSC" length="1" stride="0x700"> 264 <array offset="0x400" name="MV" length="9" stride="4"> 265 <reg32 offset="0" name="VAL"/> 266 </array> 267 <array offset="0x500" name="PRE_BV" length="3" stride="4"> 268 <reg32 offset="0" name="VAL"/> 269 </array> 270 <array offset="0x580" name="POST_BV" length="3" stride="4"> 271 <reg32 offset="0" name="VAL"/> 272 </array> 273 <array offset="0x600" name="PRE_LV" length="6" stride="4"> 274 <reg32 offset="0" name="VAL"/> 275 </array> 276 <array offset="0x680" name="POST_LV" length="6" stride="4"> 277 <reg32 offset="0" name="VAL"/> 278 </array> 279 </array> 280 </array> 281 282 <!-- 283 TODO length should be 7, but that would collide w/ OVLP2..!?! 284 this register map is a bit strange.. 285 --> 286 <array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe"> 287 <reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/> 288 <reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/> 289 <reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/> 290 <reg32 offset="0x000c" name="DST_XY" type="reg_xy"/> 291 <reg32 offset="0x0010" name="SRCP0_BASE"/> 292 <reg32 offset="0x0014" name="SRCP1_BASE"/> 293 <reg32 offset="0x0018" name="SRCP2_BASE"/> 294 <reg32 offset="0x001c" name="SRCP3_BASE"/> 295 <reg32 offset="0x0040" name="SRC_STRIDE_A"> 296 <bitfield name="P0" low="0" high="15" type="uint"/> 297 <bitfield name="P1" low="16" high="31" type="uint"/> 298 </reg32> 299 <reg32 offset="0x0044" name="SRC_STRIDE_B"> 300 <bitfield name="P2" low="0" high="15" type="uint"/> 301 <bitfield name="P3" low="16" high="31" type="uint"/> 302 </reg32> 303 <reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/> 304 <reg32 offset="0x0050" name="SRC_FORMAT"> 305 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/> 306 <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/> 307 <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/> 308 <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/> 309 <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/> 310 <bitfield name="CPP" low="9" high="10" type="uint"> 311 <brief>8bit characters per pixel minus 1</brief> 312 </bitfield> 313 <bitfield name="ROTATED_90" pos="12" type="boolean"/> 314 <bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/> 315 <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/> 316 <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/> 317 <bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/> 318 <bitfield name="SOLID_FILL" pos="22" type="boolean"/> 319 <bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/> 320 <bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/> 321 </reg32> 322 <reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/> 323 <reg32 offset="0x0058" name="OP_MODE"> 324 <bitfield name="SCALEX_EN" pos="0" type="boolean"/> 325 <bitfield name="SCALEY_EN" pos="1" type="boolean"/> 326 <bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/> 327 <bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/> 328 <bitfield name="SRC_YCBCR" pos="9" type="boolean"/> 329 <bitfield name="DST_YCBCR" pos="10" type="boolean"/> 330 <bitfield name="CSC_EN" pos="11" type="boolean"/> 331 <bitfield name="FLIP_LR" pos="13" type="boolean"/> 332 <bitfield name="FLIP_UD" pos="14" type="boolean"/> 333 <bitfield name="DITHER_EN" pos="15" type="boolean"/> 334 <bitfield name="IGC_LUT_EN" pos="16" type="boolean"/> 335 <bitfield name="DEINT_EN" pos="18" type="boolean"/> 336 <bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/> 337 </reg32> 338 <reg32 offset="0x005c" name="PHASEX_STEP"/> 339 <reg32 offset="0x0060" name="PHASEY_STEP"/> 340 <reg32 offset="0x1004" name="FETCH_CONFIG"/> 341 <reg32 offset="0x1008" name="SOLID_COLOR"/> 342 343 <array offset="0x4000" name="CSC" length="1" stride="0x700"> 344 <array offset="0x400" name="MV" length="9" stride="4"> 345 <reg32 offset="0" name="VAL"/> 346 </array> 347 <array offset="0x500" name="PRE_BV" length="3" stride="4"> 348 <reg32 offset="0" name="VAL"/> 349 </array> 350 <array offset="0x580" name="POST_BV" length="3" stride="4"> 351 <reg32 offset="0" name="VAL"/> 352 </array> 353 <array offset="0x600" name="PRE_LV" length="6" stride="4"> 354 <reg32 offset="0" name="VAL"/> 355 </array> 356 <array offset="0x680" name="POST_LV" length="6" stride="4"> 357 <reg32 offset="0" name="VAL"/> 358 </array> 359 </array> 360 </array> 361 362 <!-- 363 ENCODERS 364 LCDC and DSI seem the same, DTV is just slightly different.. 365 --> 366 367 <bitset name="mdp4_ctrl_polarity" inline="yes"> 368 <!-- not entirely sure if these bits mean hi or low.. --> 369 <bitfield name="HSYNC_LOW" pos="0" type="boolean"/> 370 <bitfield name="VSYNC_LOW" pos="1" type="boolean"/> 371 <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/> 372 </bitset> 373 374 <bitset name="mdp4_active_hctl" inline="yes"> 375 <bitfield name="START" low="0" high="14" type="uint"/> 376 <bitfield name="END" low="16" high="30" type="uint"/> 377 <bitfield name="ACTIVE_START_X" pos="31" type="boolean"/> 378 </bitset> 379 380 <bitset name="mdp4_display_hctl" inline="yes"> 381 <bitfield name="START" low="0" high="15" type="uint"/> 382 <bitfield name="END" low="16" high="31" type="uint"/> 383 </bitset> 384 385 <bitset name="mdp4_hsync_ctrl" inline="yes"> 386 <bitfield name="PULSEW" low="0" high="15" type="uint"/> 387 <bitfield name="PERIOD" low="16" high="31" type="uint"/> 388 </bitset> 389 390 <bitset name="mdp4_underflow_clr" inline="yes"> 391 <bitfield name="COLOR" low="0" high="23"/> 392 <bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/> 393 </bitset> 394 395 <!-- offset is 0xe0000 on !mdp4.. --> 396 <array offset="0xc0000" name="LCDC" length="1" stride="0x1000"> 397 <reg32 offset="0x0000" name="ENABLE"/> 398 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 399 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 400 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 401 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 402 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/> 403 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/> 404 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 405 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/> 406 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/> 407 <reg32 offset="0x0028" name="BORDER_CLR"/> 408 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 409 <reg32 offset="0x0030" name="HSYNC_SKEW"/> 410 <reg32 offset="0x0034" name="TEST_CNTL"/> 411 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 412 </array> 413 414 <reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL"> 415 <bitfield name="MODE_SEL" pos="2" type="boolean"/> 416 <bitfield name="RGB_OUT" pos="3" type="boolean"/> 417 <bitfield name="CH_SWAP" pos="4" type="boolean"/> 418 <bitfield name="CH1_RES_BIT" pos="5" type="boolean"/> 419 <bitfield name="CH2_RES_BIT" pos="6" type="boolean"/> 420 <bitfield name="ENABLE" pos="7" type="boolean"/> 421 <bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/> 422 <bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/> 423 <bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/> 424 <bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/> 425 <bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/> 426 <bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/> 427 <bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/> 428 <bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/> 429 <bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/> 430 <bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/> 431 </reg32> 432 433 <array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8"> 434 <reg32 offset="0x0" name="3_TO_0"> 435 <bitfield name="BIT0" low="0" high="7"/> 436 <bitfield name="BIT1" low="8" high="15"/> 437 <bitfield name="BIT2" low="16" high="23"/> 438 <bitfield name="BIT3" low="24" high="31"/> 439 </reg32> 440 <reg32 offset="0x4" name="6_TO_4"> 441 <bitfield name="BIT4" low="0" high="7"/> 442 <bitfield name="BIT5" low="8" high="15"/> 443 <bitfield name="BIT6" low="16" high="23"/> 444 </reg32> 445 </array> 446 447 <reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/> 448 449 <reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/> 450 <reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/> 451 <reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/> 452 <reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/> 453 <reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/> 454 <reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/> 455 <reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/> 456 <reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/> 457 <reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/> 458 <reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/> 459 <reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/> 460 461 <reg32 offset="0xc3100" name="LVDS_PHY_CFG0"> 462 <bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/> 463 <bitfield name="CHANNEL0" pos="6" type="boolean"/> 464 <bitfield name="CHANNEL1" pos="7" type="boolean"/> 465 </reg32> 466 467 <array offset="0xd0000" name="DTV" length="1" stride="0x1000"> 468 <reg32 offset="0x0000" name="ENABLE"/> 469 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 470 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 471 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 472 <reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 473 <reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/> 474 <reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/> 475 <reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 476 <reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/> 477 <reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/> 478 <reg32 offset="0x0040" name="BORDER_CLR"/> 479 <reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 480 <reg32 offset="0x0048" name="HSYNC_SKEW"/> 481 <reg32 offset="0x004c" name="TEST_CNTL"/> 482 <reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 483 </array> 484 485 <array offset="0xe0000" name="DSI" length="1" stride="0x1000"> 486 <reg32 offset="0x0000" name="ENABLE"/> 487 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/> 488 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/> 489 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/> 490 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/> 491 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/> 492 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/> 493 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/> 494 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/> 495 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/> 496 <reg32 offset="0x0028" name="BORDER_CLR"/> 497 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/> 498 <reg32 offset="0x0030" name="HSYNC_SKEW"/> 499 <reg32 offset="0x0034" name="TEST_CNTL"/> 500 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/> 501 </array> 502</domain> 503 504</database> 505