1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7 8<enum name="vgt_event_type" varset="chip"> 9 <value name="VS_DEALLOC" value="0"/> 10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/> 11 <value name="VS_DONE_TS" value="2"/> 12 <value name="PS_DONE_TS" value="3"/> 13 <doc> 14 Flushes dirty data from UCHE, and also writes a GPU timestamp to 15 the address if one is provided. 16 </doc> 17 <value name="CACHE_FLUSH_TS" value="4"/> 18 <value name="CONTEXT_DONE" value="5"/> 19 <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/> 20 <value name="VIZQUERY_START" value="7" variants="A2XX"/> 21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> 22 <value name="VIZQUERY_END" value="8" variants="A2XX"/> 23 <value name="SC_WAIT_WC" value="9" variants="A2XX"/> 24 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/> 25 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/> 26 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/> 27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 28 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> 29 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> 30 <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/> 31 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> 32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> 33 <doc> 34 If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed 35 sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main 36 memory, skipping UCHE. 37 </doc> 38 <value name="ZPASS_DONE" value="21"/> 39 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/> 40 41 <doc> 42 Writes the GPU timestamp to the address that follows, once RB 43 access and flushes are complete. 44 </doc> 45 <value name="RB_DONE_TS" value="22" variants="A3XX-"/> 46 47 <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/> 48 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/> 49 <value name="VS_FETCH_DONE" value="27"/> 50 <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/> 51 52 <!-- a5xx events --> 53 <value name="WT_DONE_TS" value="8" variants="A5XX-"/> 54 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/> 55 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/> 56 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/> 57 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/> 58 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/> 59 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/> 60 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/> 61 <value name="FLUSH_SO_3" value="20" variants="A5XX-"/> 62 63 <doc> 64 Invalidates depth attachment data from the CCU. We assume this 65 happens in the last stage. 66 </doc> 67 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/> 68 69 <doc> 70 Invalidates color attachment data from the CCU. We assume this 71 happens in the last stage. 72 </doc> 73 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/> 74 75 <doc> 76 Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, 77 along with its registers, would be better named RESOLVE). 78 </doc> 79 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/> 80 81 <doc> 82 Flushes depth attachment data from the CCU. We assume this 83 happens in the last stage. 84 </doc> 85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/> 86 87 <doc> 88 Flushes color attachment data from the CCU. We assume this 89 happens in the last stage. 90 </doc> 91 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/> 92 93 <doc> 94 2D blit to resolve GMEM to system memory (skipping CCU) at the 95 end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for 96 more general blitting. 97 </doc> 98 <value name="BLIT" value="30" variants="A5XX-"/> 99 100 <doc> 101 Clears based on GRAS_LRZ_CNTL configuration, could clear 102 fast-clear buffer or LRZ direction. 103 LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which 104 could be expressed by enum: 105 CUR_DIR_DISABLED = 0x0 106 CUR_DIR_GE = 0x1 107 CUR_DIR_LE = 0x2 108 CUR_DIR_UNSET = 0x3 109 Clear of direction means setting the direction to CUR_DIR_UNSET. 110 </doc> 111 <value name="LRZ_CLEAR" value="37" variants="A5XX-"/> 112 113 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 114 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 115 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 116 <value name="UNK_40" value="40" variants="A7XX"/> 117 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 118 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 119 <value name="UNK_2C" value="44" variants="A5XX-"/> 120 <value name="UNK_2D" value="45" variants="A5XX-"/> 121 122 <!-- a6xx events --> 123 <doc> 124 Invalidates UCHE. 125 </doc> 126 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/> 127 128 <value name="LABEL" value="63" variants="A6XX-"/> 129 130 <!-- note, some of these are the same as a6xx, just named differently --> 131 132 <doc> Doesn't seem to do anything </doc> 133 <value name="DUMMY_EVENT" value="1" variants="A7XX"/> 134 <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/> 135 <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/> 136 <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/> 137 <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/> 138 <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/> 139 <value name="CCU_RESOLVE" value="30" variants="A7XX"/> 140 <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/> 141 <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/> 142 <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/> 143 <value name="CACHE_RESET" value="48" variants="A7XX"/> 144 <value name="CACHE_CLEAN" value="49" variants="A7XX"/> 145 <!-- TODO: deal with name conflicts with other gens --> 146 <value name="CACHE_FLUSH7" value="50" variants="A7XX"/> 147 <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/> 148</enum> 149 150<enum name="pc_di_primtype"> 151 <value name="DI_PT_NONE" value="0"/> 152 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> 153 <value name="DI_PT_POINTLIST_PSIZE" value="1"/> 154 <value name="DI_PT_LINELIST" value="2"/> 155 <value name="DI_PT_LINESTRIP" value="3"/> 156 <value name="DI_PT_TRILIST" value="4"/> 157 <value name="DI_PT_TRIFAN" value="5"/> 158 <value name="DI_PT_TRISTRIP" value="6"/> 159 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> 160 <value name="DI_PT_RECTLIST" value="8"/> 161 <value name="DI_PT_POINTLIST" value="9"/> 162 <value name="DI_PT_LINE_ADJ" value="0xa"/> 163 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> 164 <value name="DI_PT_TRI_ADJ" value="0xc"/> 165 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> 166 167 <value name="DI_PT_PATCHES0" value="0x1f"/> 168 <value name="DI_PT_PATCHES1" value="0x20"/> 169 <value name="DI_PT_PATCHES2" value="0x21"/> 170 <value name="DI_PT_PATCHES3" value="0x22"/> 171 <value name="DI_PT_PATCHES4" value="0x23"/> 172 <value name="DI_PT_PATCHES5" value="0x24"/> 173 <value name="DI_PT_PATCHES6" value="0x25"/> 174 <value name="DI_PT_PATCHES7" value="0x26"/> 175 <value name="DI_PT_PATCHES8" value="0x27"/> 176 <value name="DI_PT_PATCHES9" value="0x28"/> 177 <value name="DI_PT_PATCHES10" value="0x29"/> 178 <value name="DI_PT_PATCHES11" value="0x2a"/> 179 <value name="DI_PT_PATCHES12" value="0x2b"/> 180 <value name="DI_PT_PATCHES13" value="0x2c"/> 181 <value name="DI_PT_PATCHES14" value="0x2d"/> 182 <value name="DI_PT_PATCHES15" value="0x2e"/> 183 <value name="DI_PT_PATCHES16" value="0x2f"/> 184 <value name="DI_PT_PATCHES17" value="0x30"/> 185 <value name="DI_PT_PATCHES18" value="0x31"/> 186 <value name="DI_PT_PATCHES19" value="0x32"/> 187 <value name="DI_PT_PATCHES20" value="0x33"/> 188 <value name="DI_PT_PATCHES21" value="0x34"/> 189 <value name="DI_PT_PATCHES22" value="0x35"/> 190 <value name="DI_PT_PATCHES23" value="0x36"/> 191 <value name="DI_PT_PATCHES24" value="0x37"/> 192 <value name="DI_PT_PATCHES25" value="0x38"/> 193 <value name="DI_PT_PATCHES26" value="0x39"/> 194 <value name="DI_PT_PATCHES27" value="0x3a"/> 195 <value name="DI_PT_PATCHES28" value="0x3b"/> 196 <value name="DI_PT_PATCHES29" value="0x3c"/> 197 <value name="DI_PT_PATCHES30" value="0x3d"/> 198 <value name="DI_PT_PATCHES31" value="0x3e"/> 199</enum> 200 201<enum name="pc_di_src_sel"> 202 <value name="DI_SRC_SEL_DMA" value="0"/> 203 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> 204 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> 205 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/> 206</enum> 207 208<enum name="pc_di_face_cull_sel"> 209 <value name="DI_FACE_CULL_NONE" value="0"/> 210 <value name="DI_FACE_CULL_FETCH" value="1"/> 211 <value name="DI_FACE_BACKFACE_CULL" value="2"/> 212 <value name="DI_FACE_FRONTFACE_CULL" value="3"/> 213</enum> 214 215<enum name="pc_di_index_size"> 216 <value name="INDEX_SIZE_IGN" value="0"/> 217 <value name="INDEX_SIZE_16_BIT" value="0"/> 218 <value name="INDEX_SIZE_32_BIT" value="1"/> 219 <value name="INDEX_SIZE_8_BIT" value="2"/> 220 <value name="INDEX_SIZE_INVALID"/> 221</enum> 222 223<enum name="pc_di_vis_cull_mode"> 224 <value name="IGNORE_VISIBILITY" value="0"/> 225 <value name="USE_VISIBILITY" value="1"/> 226</enum> 227 228<enum name="adreno_pm4_packet_type"> 229 <value name="CP_TYPE0_PKT" value="0x00000000"/> 230 <value name="CP_TYPE1_PKT" value="0x40000000"/> 231 <value name="CP_TYPE2_PKT" value="0x80000000"/> 232 <value name="CP_TYPE3_PKT" value="0xc0000000"/> 233 <value name="CP_TYPE4_PKT" value="0x40000000"/> 234 <value name="CP_TYPE7_PKT" value="0x70000000"/> 235</enum> 236 237<!-- 238 Note that in some cases, the same packet id is recycled on a later 239 generation, so variants attribute is used to distinguish. They 240 may not be completely accurate, we would probably have to analyze 241 the pfp and me/pm4 firmware to verify the packet is actually 242 handled on a particular generation. But it is at least enough to 243 disambiguate the packet-id's that were re-used for different 244 packets starting with a5xx. 245 --> 246<enum name="adreno_pm4_type3_packets" varset="chip"> 247 <doc>initialize CP's micro-engine</doc> 248 <value name="CP_ME_INIT" value="0x48"/> 249 <doc>skip N 32-bit words to get to the next packet</doc> 250 <value name="CP_NOP" value="0x10"/> 251 <doc> 252 indirect buffer dispatch. prefetch parser uses this packet 253 type to determine whether to pre-fetch the IB 254 </doc> 255 <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/> 256 <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/> 257 <value name="CP_INDIRECT_BUFFER" value="0x3f"/> 258 <doc> 259 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to 260 another buffer at the same level. Must be at the end of IB, and 261 doesn't work with draw state IB's. 262 </doc> 263 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/> 264 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> 265 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> 266 <doc> 267 Waits for the IDLE state of the engine before further drawing. 268 This is pipelined, so the CP may continue. 269 </doc> 270 <value name="CP_WAIT_FOR_IDLE" value="0x26"/> 271 <doc>wait until a register or memory location is a specific value</doc> 272 <value name="CP_WAIT_REG_MEM" value="0x3c"/> 273 <doc>wait until a register location is equal to a specific value</doc> 274 <value name="CP_WAIT_REG_EQ" value="0x52"/> 275 <doc>wait until a register location is >= a specific value</doc> 276 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/> 277 <doc>wait until a read completes</doc> 278 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/> 279 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> 280 <!-- 281 NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and 282 recycled for something new on a7xx 283 --> 284 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/> 285 <doc>register read/modify/write</doc> 286 <value name="CP_REG_RMW" value="0x21"/> 287 <doc>Set binning configuration registers</doc> 288 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/> 289 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/> 290 <doc>reads register in chip and writes to memory</doc> 291 <value name="CP_REG_TO_MEM" value="0x3e"/> 292 <doc>write N 32-bit words to memory</doc> 293 <value name="CP_MEM_WRITE" value="0x3d"/> 294 <doc>write CP_PROG_COUNTER value to memory</doc> 295 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> 296 <doc>conditional execution of a sequence of packets</doc> 297 <value name="CP_COND_EXEC" value="0x44"/> 298 <doc>conditional write to memory or register</doc> 299 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/> 300 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/> 301 <doc>generate an event that creates a write to memory when completed</doc> 302 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/> 303 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/> 304 <doc>generate a VS|PS_done event</doc> 305 <value name="CP_EVENT_WRITE_SHD" value="0x58"/> 306 <doc>generate a cache flush done event</doc> 307 <value name="CP_EVENT_WRITE_CFL" value="0x59"/> 308 <doc>generate a z_pass done event</doc> 309 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> 310 <doc> 311 not sure the real name, but this seems to be what is used for 312 opencl, instead of CP_DRAW_INDX.. 313 </doc> 314 <value name="CP_RUN_OPENCL" value="0x31"/> 315 <doc>initiate fetch of index buffer and draw</doc> 316 <value name="CP_DRAW_INDX" value="0x22"/> 317 <doc>draw using supplied indices in packet</doc> 318 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> 319 <doc>initiate fetch of index buffer and binIDs and draw</doc> 320 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/> 321 <doc>initiate fetch of bin IDs and draw using supplied indices</doc> 322 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/> 323 <doc>begin/end initiator for viz query extent processing</doc> 324 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/> 325 <doc>fetch state sub-blocks and initiate shader code DMAs</doc> 326 <value name="CP_SET_STATE" value="0x25"/> 327 <doc>load constant into chip and to memory</doc> 328 <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/> 329 <doc>load sequencer instruction memory (pointer-based)</doc> 330 <value name="CP_IM_LOAD" value="0x27"/> 331 <doc>load sequencer instruction memory (code embedded in packet)</doc> 332 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> 333 <doc>load constants from a location in memory</doc> 334 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> 335 <doc>selective invalidation of state pointers</doc> 336 <value name="CP_INVALIDATE_STATE" value="0x3b"/> 337 <doc>dynamically changes shader instruction memory partition</doc> 338 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/> 339 <doc>sets the 64-bit BIN_MASK register in the PFP</doc> 340 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/> 341 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> 342 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/> 343 <doc>updates the current context, if needed</doc> 344 <value name="CP_CONTEXT_UPDATE" value="0x5e"/> 345 <doc>generate interrupt from the command stream</doc> 346 <value name="CP_INTERRUPT" value="0x40"/> 347 <doc>copy sequencer instruction memory to system memory</doc> 348 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/> 349 350 <!-- For a20x --> 351<!-- TODO handle variants.. 352 <doc> 353 Program an offset that will added to the BIN_BASE value of 354 the 3D_DRAW_INDX_BIN packet 355 </doc> 356 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> 357 --> 358 359 <!-- for a22x --> 360 <doc> 361 sets draw initiator flags register in PFP, gets bitwise-ORed into 362 every draw initiator 363 </doc> 364 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> 365 <doc>sets the register protection mode</doc> 366 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> 367 368 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> 369 370 <!-- for a3xx --> 371 <doc>load high level sequencer command</doc> 372 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> 373 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> 374 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 375 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> 376 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 377 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> 378 <doc>Load a buffer with pre-fetch enabled</doc> 379 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> 380 <doc>Set bin (?)</doc> 381 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/> 382 383 <doc>test 2 memory locations to dword values specified</doc> 384 <value name="CP_TEST_TWO_MEMS" value="0x71"/> 385 386 <doc>Write register, ignoring context state for context sensitive registers</doc> 387 <value name="CP_REG_WR_NO_CTXT" value="0x78"/> 388 389 <doc>Record the real-time when this packet is processed by PFP</doc> 390 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> 391 392 <!-- Used to switch GPU between secure and non-secure modes --> 393 <value name="CP_SET_SECURE_MODE" value="0x66"/> 394 395 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> 396 <value name="CP_WAIT_FOR_ME" value="0x13"/> 397 398 <!-- for a4xx --> 399 <doc> 400 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple 401 groups of registers. Looks like it can be used to create state 402 objects in GPU memory, and on state change only emit pointer 403 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU 404 overhead: 405 406 (A4x) save PM4 stream pointers to execute upon a visible draw 407 </doc> 408 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/> 409 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> 410 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/> 411 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/> 412 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/> 413 <value name="CP_DRAW_AUTO" value="0x24"/> 414 415 <doc> 416 Enable or disable predication globally. Also resets the 417 predicate to "passing" and the local bit to enabled when 418 enabling global predication. 419 </doc> 420 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/> 421 422 <doc> 423 Enable or disable predication locally. Unlike globally enabling 424 predication, this packet doesn't touch any other state. 425 Predication only happens when enabled globally and locally and a 426 predicate has been set. This should be used for internal draws 427 which aren't supposed to use the predication state: 428 429 CP_DRAW_PRED_ENABLE_LOCAL(0) 430 ... do draw... 431 CP_DRAW_PRED_ENABLE_LOCAL(1) 432 </doc> 433 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/> 434 435 <doc> 436 Latch a draw predicate into the internal register. 437 </doc> 438 <value name="CP_DRAW_PRED_SET" value="0x4e"/> 439 440 <doc> 441 for A4xx 442 Write to register with address that does not fit into type-0 pkt 443 </doc> 444 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/> 445 446 <doc>copy from ME scratch RAM to a register</doc> 447 <value name="CP_SCRATCH_TO_REG" value="0x4d"/> 448 449 <doc>Copy from REG to ME scratch RAM</doc> 450 <value name="CP_REG_TO_SCRATCH" value="0x4a"/> 451 452 <doc>Wait for memory writes to complete</doc> 453 <value name="CP_WAIT_MEM_WRITES" value="0x12"/> 454 455 <doc>Conditional execution based on register comparison</doc> 456 <value name="CP_COND_REG_EXEC" value="0x47"/> 457 458 <doc>Memory to REG copy</doc> 459 <value name="CP_MEM_TO_REG" value="0x42"/> 460 461 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/> 462 <value name="CP_EXEC_CS" value="0x33"/> 463 464 <doc> 465 for a5xx 466 </doc> 467 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> 468 <!-- switches SMMU pagetable, used on a5xx+ only --> 469 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/> 470 <!-- for a6xx --> 471 <doc>Tells CP the current mode of GPU operation</doc> 472 <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/> 473 <doc>Instruct CP to set a few internal CP registers</doc> 474 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/> 475 <!-- 476 pairs of regid and value.. seems to be used to program some TF 477 related regs: 478 --> 479 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/> 480 <!-- A5XX Enable yield in RB only --> 481 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/> 482 <doc> 483 Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and 484 nothing is left in the visibility stream, then 485 CP_INDIRECT_BUFFER will be skipped, and draws will early return 486 from their IB. 487 </doc> 488 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/> 489 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/> 490 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/> 491 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/> 492 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/> 493 <!-- Enable/Disable/Defer A5x global preemption model --> 494 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> 495 <!-- Enable/Disable A5x local preemption model --> 496 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> 497 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> 498 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/> 499 <!-- Inform CP about current render mode (needed for a5xx preemption) --> 500 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/> 501 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> 502 <!-- check if this works on earlier.. --> 503 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/> 504 505 <doc> 506 General purpose 2D blit engine for image transfers and mipmap 507 generation. Reads through UCHE, writes through the CCU cache in 508 the PS stage. 509 </doc> 510 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/> 511 512 <!-- Test specified bit in specified register and set predicate --> 513 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/> 514 515 <!-- 516 Seems to set the mode flags which control which CP_SET_DRAW_STATE 517 packets are executed, based on their ENABLE_MASK values 518 519 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 520 packets w/ ENABLE_MASK & 0x6 to execute immediately 521 --> 522 <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/> 523 524 <!-- 525 Seems like there are now separate blocks of state for VS vs FS/CS 526 (probably these amounts to geometry vs fragments so that geometry 527 stage of the pipeline for next draw can start while fragment stage 528 of current draw is still running. The format of the payload of the 529 packets is the same, the only difference is the offsets of the regs 530 the firmware code that handles the packet writes. 531 532 Note that for CL, starting with a6xx, the preferred # of local 533 threads is no longer the same as the max, implying that the shader 534 core can now run warps from unrelated shaders (ie. 535 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs 536 CL_KERNEL_WORK_GROUP_SIZE) 537 --> 538 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/> 539 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> 540 <!-- 541 Note: For IBO state (Image/SSBOs) which have shared state across 542 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 543 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 544 interchangable. 545 --> 546 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/> 547 548 <!-- internal packets: --> 549 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/> 550 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/> 551 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/> 552 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/> 553 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/> 554 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/> 555 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/> 556 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/> 557 558 <!-- internal jumptable entries on a6xx+, possibly a5xx: --> 559 560 <!-- jmptable entry used to handle type4 packet on a5xx+: --> 561 <value name="PKT4" value="0x04" variants="A5XX-"/> 562 <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs --> 563 <value name="IN_IB_END" value="0x0a" variants="A6XX-"/> 564 <!-- handles IFPC save/restore --> 565 <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/> 566 <!-- preemption/context-swtich routine --> 567 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/> 568 569 <!-- TODO do these exist on A5xx? --> 570 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/> 571 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/> 572 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/> 573 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> 574 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/> 575 <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/> 576 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/> 577 <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values --> 578 <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/> 579 <doc> 580 Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords, 581 and forcibly switch to the indicated context. 582 </doc> 583 <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/> 584 <value name="CP_SET_AMBLE" value="0x55" variants="A6XX-"/> 585 586 <!-- 587 Seems to always have the payload: 588 00000002 00008801 00004010 589 or: 590 00000002 00008801 00004090 591 or: 592 00000002 00008801 00000010 593 00000002 00008801 00010010 594 00000002 00008801 00d64010 595 ... 596 Note set for compute shaders.. 597 Is 0x8801 a register offset? 598 This appears to be a special sort of register write packet 599 more or less, but the firmware has some special handling.. 600 Seems like it intercepts/modifies certain register offsets, 601 but others are treated like a normal PKT4 reg write. I 602 guess there are some registers that the fw controls certain 603 bits. 604 --> 605 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/> 606 607 <doc> 608 These first appear in a650_sqe.bin. They can in theory be used 609 to loop any sequence of IB1 commands, but in practice they are 610 used to loop over bins. There is a fixed-size per-iteration 611 prefix, used to set per-bin state, and then the following IB1 612 commands are executed until CP_END_BIN which are always the same 613 for each iteration and usually contain a list of 614 CP_INDIRECT_BUFFER calls to IB2 commands which setup state and 615 execute restore/draw/save commands. This replaces the previous 616 technique of just repeating the CP_INDIRECT_BUFFER calls and 617 "unrolling" the loop. 618 </doc> 619 <value name="CP_START_BIN" value="0x50" variants="A6XX-"/> 620 <value name="CP_END_BIN" value="0x51" variants="A6XX-"/> 621 622 <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc> 623 <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/> 624 625 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/> 626 <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword --> 627 <value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 --> 628 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/> 629 <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?--> 630 <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/> 631 <doc> Can clear BV/BR counters, or wait until one catches up to another </doc> 632 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/> 633 <doc> Clears, adds to local, or adds to global timestamp </doc> 634 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> 635 <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? --> 636 <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/> 637 <doc> 638 Write to a scratch memory that is read by CP_REG_TEST with 639 SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. 640 However it uses the same memory space. 641 </doc> 642 <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/> 643 644 <doc> 645 Executes an array of fixed-size command buffers where each 646 buffer is assumed to have one draw call, skipping buffers with 647 non-visible draw calls. 648 </doc> 649 <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/> 650 651 <doc>Reset various on-chip state used for synchronization</doc> 652 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/> 653</enum> 654 655 656<domain name="CP_LOAD_STATE" width="32"> 657 <doc>Load state, a3xx (and later?)</doc> 658 <enum name="adreno_state_block"> 659 <value name="SB_VERT_TEX" value="0"/> 660 <value name="SB_VERT_MIPADDR" value="1"/> 661 <value name="SB_FRAG_TEX" value="2"/> 662 <value name="SB_FRAG_MIPADDR" value="3"/> 663 <value name="SB_VERT_SHADER" value="4"/> 664 <value name="SB_GEOM_SHADER" value="5"/> 665 <value name="SB_FRAG_SHADER" value="6"/> 666 <value name="SB_COMPUTE_SHADER" value="7"/> 667 </enum> 668 <enum name="adreno_state_type"> 669 <value name="ST_SHADER" value="0"/> 670 <value name="ST_CONSTANTS" value="1"/> 671 </enum> 672 <enum name="adreno_state_src"> 673 <value name="SS_DIRECT" value="0"> 674 <doc>inline with the CP_LOAD_STATE packet</doc> 675 </value> 676 <value name="SS_INVALID_ALL_IC" value="2"/> 677 <value name="SS_INVALID_PART_IC" value="3"/> 678 <value name="SS_INDIRECT" value="4"> 679 <doc>in buffer pointed to by EXT_SRC_ADDR</doc> 680 </value> 681 <value name="SS_INDIRECT_TCM" value="5"/> 682 <value name="SS_INDIRECT_STM" value="6"/> 683 </enum> 684 <reg32 offset="0" name="0"> 685 <bitfield name="DST_OFF" low="0" high="15" type="uint"/> 686 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> 687 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> 688 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 689 </reg32> 690 <reg32 offset="1" name="1"> 691 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> 692 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 693 </reg32> 694</domain> 695 696<domain name="CP_LOAD_STATE4" width="32" varset="chip"> 697 <doc>Load state, a4xx+</doc> 698 <enum name="a4xx_state_block"> 699 <!-- 700 unknown: 0x7 and 0xf <- seen in compute shader 701 702 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? 703 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains 704 the gpuaddr of the following shader constants block. DST_OFF seems 705 to specify which shader stage: 706 707 16 -> vert 708 36 -> tcs 709 56 -> tes 710 76 -> geom 711 96 -> frag 712 713 Example: 714 715opcode: CP_LOAD_STATE4 (30) (12 dwords) 716 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } 717 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } 718 { EXT_SRC_ADDR_HI = 0 } 719 0000: c0264100 00000000 00000000 00000000 720 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 721 722opcode: CP_LOAD_STATE4 (30) (4 dwords) 723 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 724 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } 725 { EXT_SRC_ADDR_HI = 0 } 726 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 727 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 728 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 729 730 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. 731 732 --> 733 <value name="SB4_VS_TEX" value="0x0"/> 734 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> 735 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> 736 <value name="SB4_GS_TEX" value="0x3"/> 737 <value name="SB4_FS_TEX" value="0x4"/> 738 <value name="SB4_CS_TEX" value="0x5"/> 739 <value name="SB4_VS_SHADER" value="0x8"/> 740 <value name="SB4_HS_SHADER" value="0x9"/> 741 <value name="SB4_DS_SHADER" value="0xa"/> 742 <value name="SB4_GS_SHADER" value="0xb"/> 743 <value name="SB4_FS_SHADER" value="0xc"/> 744 <value name="SB4_CS_SHADER" value="0xd"/> 745 <!-- 746 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), 747 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) 748 749 Compute has it's own dedicated SSBO state, it seems, but the rest 750 of the stages share state 751 --> 752 <value name="SB4_SSBO" value="0xe"/> 753 <value name="SB4_CS_SSBO" value="0xf"/> 754 </enum> 755 <enum name="a4xx_state_type"> 756 <value name="ST4_SHADER" value="0"/> 757 <value name="ST4_CONSTANTS" value="1"/> 758 <value name="ST4_UBO" value="2"/> 759 </enum> 760 <enum name="a4xx_state_src"> 761 <value name="SS4_DIRECT" value="0"/> 762 <value name="SS4_INDIRECT" value="2"/> 763 </enum> 764 <reg32 offset="0" name="0"> 765 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 766 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> 767 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> 768 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 769 </reg32> 770 <reg32 offset="1" name="1"> 771 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> 772 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 773 </reg32> 774 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 775 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 776 </reg32> 777</domain> 778 779<!-- looks basically same CP_LOAD_STATE4 --> 780<domain name="CP_LOAD_STATE6" width="32" varset="chip"> 781 <doc>Load state, a6xx+</doc> 782 <enum name="a6xx_state_block"> 783 <value name="SB6_VS_TEX" value="0x0"/> 784 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> 785 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> 786 <value name="SB6_GS_TEX" value="0x3"/> 787 <value name="SB6_FS_TEX" value="0x4"/> 788 <value name="SB6_CS_TEX" value="0x5"/> 789 <value name="SB6_VS_SHADER" value="0x8"/> 790 <value name="SB6_HS_SHADER" value="0x9"/> 791 <value name="SB6_DS_SHADER" value="0xa"/> 792 <value name="SB6_GS_SHADER" value="0xb"/> 793 <value name="SB6_FS_SHADER" value="0xc"/> 794 <value name="SB6_CS_SHADER" value="0xd"/> 795 <value name="SB6_IBO" value="0xe"/> 796 <value name="SB6_CS_IBO" value="0xf"/> 797 </enum> 798 <enum name="a6xx_state_type"> 799 <value name="ST6_SHADER" value="0"/> 800 <value name="ST6_CONSTANTS" value="1"/> 801 <value name="ST6_UBO" value="2"/> 802 <value name="ST6_IBO" value="3"/> 803 </enum> 804 <enum name="a6xx_state_src"> 805 <value name="SS6_DIRECT" value="0"/> 806 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? --> 807 <value name="SS6_INDIRECT" value="2"/> 808 <doc> 809 SS6_UBO used by the a6xx vulkan blob with tesselation constants 810 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) 811 to load constants from a UBO loaded with DST_OFF = 14 and offset 0, 812 EXT_SRC_ADDR = 0xe0000 813 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) 814 </doc> 815 <value name="SS6_UBO" value="3"/> 816 </enum> 817 <reg32 offset="0" name="0"> 818 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 819 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> 820 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> 821 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> 822 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 823 </reg32> 824 <reg32 offset="1" name="1"> 825 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 826 </reg32> 827 <reg32 offset="2" name="2"> 828 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 829 </reg32> 830 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/> 831</domain> 832 833<bitset name="vgt_draw_initiator" inline="yes"> 834 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 835 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 836 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> 837 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> 838 <bitfield name="NOT_EOP" pos="12" type="boolean"/> 839 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> 840 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> 841 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> 842</bitset> 843 844<!-- changed on a4xx: --> 845<enum name="a4xx_index_size"> 846 <value name="INDEX4_SIZE_8_BIT" value="0"/> 847 <value name="INDEX4_SIZE_16_BIT" value="1"/> 848 <value name="INDEX4_SIZE_32_BIT" value="2"/> 849</enum> 850 851<enum name="a6xx_patch_type"> 852 <value name="TESS_QUADS" value="0"/> 853 <value name="TESS_TRIANGLES" value="1"/> 854 <value name="TESS_ISOLINES" value="2"/> 855</enum> 856 857<bitset name="vgt_draw_initiator_a4xx" inline="yes"> 858 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> 859 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 860 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 861 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> 862 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> 863 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> 864 <bitfield name="GS_ENABLE" pos="16" type="boolean"/> 865 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> 866</bitset> 867 868<domain name="CP_DRAW_INDX" width="32"> 869 <reg32 offset="0" name="0"> 870 <bitfield name="VIZ_QUERY" low="0" high="31"/> 871 </reg32> 872 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 873 <reg32 offset="2" name="2"> 874 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 875 </reg32> 876 <reg32 offset="3" name="3"> 877 <bitfield name="INDX_BASE" low="0" high="31"/> 878 </reg32> 879 <reg32 offset="4" name="4"> 880 <bitfield name="INDX_SIZE" low="0" high="31"/> 881 </reg32> 882</domain> 883 884<domain name="CP_DRAW_INDX_2" width="32"> 885 <reg32 offset="0" name="0"> 886 <bitfield name="VIZ_QUERY" low="0" high="31"/> 887 </reg32> 888 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 889 <reg32 offset="2" name="2"> 890 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 891 </reg32> 892 <!-- followed by NUM_INDICES indices.. --> 893</domain> 894 895<domain name="CP_DRAW_INDX_OFFSET" width="32"> 896 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 897 <reg32 offset="1" name="1"> 898 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 899 </reg32> 900 <reg32 offset="2" name="2"> 901 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 902 </reg32> 903 <reg32 offset="3" name="3"> 904 <bitfield name="FIRST_INDX" low="0" high="31"/> 905 </reg32> 906 907 <stripe varset="chip" variants="A5XX-"> 908 <reg32 offset="4" name="4"> 909 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 910 </reg32> 911 <reg32 offset="5" name="5"> 912 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 913 </reg32> 914 <reg64 offset="4" name="INDX_BASE" type="address"/> 915 <reg32 offset="6" name="6"> 916 <!-- max # of elements in index buffer --> 917 <bitfield name="MAX_INDICES" low="0" high="31"/> 918 </reg32> 919 </stripe> 920 921 <reg32 offset="4" name="4"> 922 <bitfield name="INDX_BASE" low="0" high="31" type="address"/> 923 </reg32> 924 925 <reg32 offset="5" name="5"> 926 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 927 </reg32> 928</domain> 929 930<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 931 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 932 <stripe varset="chip" variants="A4XX"> 933 <reg32 offset="1" name="1"> 934 <bitfield name="INDIRECT" low="0" high="31"/> 935 </reg32> 936 </stripe> 937 <stripe varset="chip" variants="A5XX-"> 938 <reg32 offset="1" name="1"> 939 <bitfield name="INDIRECT_LO" low="0" high="31"/> 940 </reg32> 941 <reg32 offset="2" name="2"> 942 <bitfield name="INDIRECT_HI" low="0" high="31"/> 943 </reg32> 944 <reg64 offset="1" name="INDIRECT" type="address"/> 945 </stripe> 946</domain> 947 948<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 949 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 950 <stripe varset="chip" variants="A4XX"> 951 <reg32 offset="1" name="1"> 952 <bitfield name="INDX_BASE" low="0" high="31"/> 953 </reg32> 954 <reg32 offset="2" name="2"> 955 <!-- max # of bytes in index buffer --> 956 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 957 </reg32> 958 <reg32 offset="3" name="3"> 959 <bitfield name="INDIRECT" low="0" high="31"/> 960 </reg32> 961 </stripe> 962 <stripe varset="chip" variants="A5XX-"> 963 <reg32 offset="1" name="1"> 964 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 965 </reg32> 966 <reg32 offset="2" name="2"> 967 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 968 </reg32> 969 <reg64 offset="1" name="INDX_BASE" type="address"/> 970 <reg32 offset="3" name="3"> 971 <!-- max # of elements in index buffer --> 972 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> 973 </reg32> 974 <reg32 offset="4" name="4"> 975 <bitfield name="INDIRECT_LO" low="0" high="31"/> 976 </reg32> 977 <reg32 offset="5" name="5"> 978 <bitfield name="INDIRECT_HI" low="0" high="31"/> 979 </reg32> 980 <reg64 offset="4" name="INDIRECT" type="address"/> 981 </stripe> 982</domain> 983 984<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-"> 985 <enum name="a6xx_draw_indirect_opcode"> 986 <value name="INDIRECT_OP_NORMAL" value="0x2"/> 987 <value name="INDIRECT_OP_INDEXED" value="0x4"/> 988 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/> 989 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/> 990 </enum> 991 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 992 <reg32 offset="1" name="1"> 993 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/> 994 <doc> 995 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will 996 be updated for each draw to {draw_id, first_vertex, first_instance, 0} 997 value of 0 disables it 998 </doc> 999 <bitfield name="DST_OFF" low="8" high="21" type="hex"/> 1000 </reg32> 1001 <reg32 offset="2" name="DRAW_COUNT" type="uint"/> 1002 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL"> 1003 <reg64 offset="3" name="INDIRECT" type="address"/> 1004 <reg32 offset="5" name="STRIDE" type="uint"/> 1005 </stripe> 1006 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED"> 1007 <reg64 offset="3" name="INDEX" type="address"/> 1008 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1009 <reg64 offset="6" name="INDIRECT" type="address"/> 1010 <reg32 offset="8" name="STRIDE" type="uint"/> 1011 </stripe> 1012 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT"> 1013 <reg64 offset="3" name="INDIRECT" type="address"/> 1014 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/> 1015 <reg32 offset="7" name="STRIDE" type="uint"/> 1016 </stripe> 1017 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED"> 1018 <reg64 offset="3" name="INDEX" type="address"/> 1019 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1020 <reg64 offset="6" name="INDIRECT" type="address"/> 1021 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/> 1022 <reg32 offset="10" name="STRIDE" type="uint"/> 1023 </stripe> 1024</domain> 1025 1026<domain name="CP_DRAW_AUTO" width="32"> 1027 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 1028 <reg32 offset="1" name="1"> 1029 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 1030 </reg32> 1031 <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/> 1032 <reg32 offset="4" name="4"> 1033 <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/> 1034 </reg32> 1035 <reg32 offset="5" name="5"> 1036 <bitfield name="STRIDE" low="0" high="31" type="uint"/> 1037 </reg32> 1038</domain> 1039 1040<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip"> 1041 <reg32 offset="0" name="0"> 1042 <bitfield name="ENABLE" pos="0" type="boolean"/> 1043 </reg32> 1044</domain> 1045 1046<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip"> 1047 <reg32 offset="0" name="0"> 1048 <bitfield name="ENABLE" pos="0" type="boolean"/> 1049 </reg32> 1050</domain> 1051 1052<domain name="CP_DRAW_PRED_SET" width="32" varset="chip"> 1053 <enum name="cp_draw_pred_src"> 1054 <!-- 1055 Sources 1-4 seem to be about combining reading 1056 SO/primitive queries and setting the predicate, which is 1057 a DX11-specific optimization (since in DX11 you can only 1058 predicate on the result of queries). 1059 --> 1060 <value name="PRED_SRC_MEM" value="5"> 1061 <doc> 1062 Read a 64-bit value at the given address and 1063 test if it equals/doesn't equal 0. 1064 </doc> 1065 </value> 1066 </enum> 1067 <enum name="cp_draw_pred_test"> 1068 <value name="NE_0_PASS" value="0"/> 1069 <value name="EQ_0_PASS" value="1"/> 1070 </enum> 1071 <reg32 offset="0" name="0"> 1072 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/> 1073 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/> 1074 </reg32> 1075 <reg64 offset="1" name="MEM_ADDR" type="address"/> 1076</domain> 1077 1078<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> 1079 <array offset="0" stride="3" length="100"> 1080 <reg32 offset="0" name="0"> 1081 <bitfield name="COUNT" low="0" high="15" type="uint"/> 1082 <bitfield name="DIRTY" pos="16" type="boolean"/> 1083 <bitfield name="DISABLE" pos="17" type="boolean"/> 1084 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> 1085 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> 1086 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1087 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 1088 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 1089 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 1090 </reg32> 1091 <reg32 offset="1" name="1"> 1092 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 1093 </reg32> 1094 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1095 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> 1096 </reg32> 1097 </array> 1098</domain> 1099 1100<domain name="CP_SET_BIN" width="32"> 1101 <doc>value at offset 0 always seems to be 0x00000000..</doc> 1102 <reg32 offset="0" name="0"/> 1103 <reg32 offset="1" name="1"> 1104 <bitfield name="X1" low="0" high="15" type="uint"/> 1105 <bitfield name="Y1" low="16" high="31" type="uint"/> 1106 </reg32> 1107 <reg32 offset="2" name="2"> 1108 <bitfield name="X2" low="0" high="15" type="uint"/> 1109 <bitfield name="Y2" low="16" high="31" type="uint"/> 1110 </reg32> 1111</domain> 1112 1113<domain name="CP_SET_BIN_DATA" width="32"> 1114 <reg32 offset="0" name="0"> 1115 <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> 1116 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> 1117 </reg32> 1118 <reg32 offset="1" name="1"> 1119 <!-- seesm to correspond to VSC_SIZE_ADDRESS --> 1120 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> 1121 </reg32> 1122</domain> 1123 1124<domain name="CP_SET_BIN_DATA5" width="32"> 1125 <reg32 offset="0" name="0"> 1126 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1127 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1128 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1129 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1130 </reg32> 1131 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1132 <reg32 offset="1" name="1"> 1133 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1134 </reg32> 1135 <reg32 offset="2" name="2"> 1136 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1137 </reg32> 1138 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1139 <reg32 offset="3" name="3"> 1140 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1141 </reg32> 1142 <reg32 offset="4" name="4"> 1143 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1144 </reg32> 1145 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1146 <reg32 offset="5" name="5"> 1147 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1148 </reg32> 1149 <reg32 offset="6" name="6"> 1150 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1151 </reg32> 1152 <!-- 1153 a7xx adds a few more addresses to the end of the pkt 1154 --> 1155 <reg64 offset="7" name="7"/> 1156 <reg64 offset="9" name="9"/> 1157</domain> 1158 1159<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> 1160 <doc> 1161 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the 1162 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful 1163 for Vulkan where these values aren't known when the command 1164 stream is recorded. 1165 </doc> 1166 <reg32 offset="0" name="0"> 1167 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1168 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1169 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1170 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1171 </reg32> 1172 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1173 <reg32 offset="1" name="1"> 1174 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1175 </reg32> 1176 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1177 <reg32 offset="2" name="2"> 1178 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1179 </reg32> 1180 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1181 <reg32 offset="3" name="3"> 1182 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1183 </reg32> 1184</domain> 1185 1186<domain name="CP_REG_RMW" width="32"> 1187 <doc> 1188 Modifies DST_REG using two sources that can either be registers 1189 or immediates. If SRC1_ADD is set, then do the following: 1190 1191 $dst = (($dst & $src0) rot $rotate) + $src1 1192 1193 Otherwise: 1194 1195 $dst = (($dst & $src0) rot $rotate) | $src1 1196 1197 Here "rot" means rotate left. 1198 </doc> 1199 <reg32 offset="0" name="0"> 1200 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1201 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1202 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1203 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> 1204 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> 1205 </reg32> 1206 <reg32 offset="1" name="1"> 1207 <bitfield name="SRC0" low="0" high="31" type="uint"/> 1208 </reg32> 1209 <reg32 offset="2" name="2"> 1210 <bitfield name="SRC1" low="0" high="31" type="uint"/> 1211 </reg32> 1212</domain> 1213 1214<domain name="CP_REG_TO_MEM" width="32"> 1215 <reg32 offset="0" name="0"> 1216 <bitfield name="REG" low="0" high="17" type="hex"/> 1217 <!-- number of registers/dwords copied is max(CNT, 1). --> 1218 <bitfield name="CNT" low="18" high="29" type="uint"/> 1219 <bitfield name="64B" pos="30" type="boolean"/> 1220 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1221 </reg32> 1222 <reg32 offset="1" name="1"> 1223 <bitfield name="DEST" low="0" high="31"/> 1224 </reg32> 1225 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1226 <bitfield name="DEST_HI" low="0" high="31"/> 1227 </reg32> 1228</domain> 1229 1230<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> 1231 <doc> 1232 Like CP_REG_TO_MEM, but the memory address to write to can be 1233 offsetted using either one or two registers or scratch 1234 registers. 1235 </doc> 1236 <reg32 offset="0" name="0"> 1237 <bitfield name="REG" low="0" high="17" type="hex"/> 1238 <!-- number of registers/dwords copied is max(CNT, 1). --> 1239 <bitfield name="CNT" low="18" high="29" type="uint"/> 1240 <bitfield name="64B" pos="30" type="boolean"/> 1241 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1242 </reg32> 1243 <reg32 offset="1" name="1"> 1244 <bitfield name="DEST" low="0" high="31"/> 1245 </reg32> 1246 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1247 <bitfield name="DEST_HI" low="0" high="31"/> 1248 </reg32> 1249 <reg32 offset="3" name="3"> 1250 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1251 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> 1252 </reg32> 1253 <!-- followed by an optional identical OFFSET1 dword --> 1254</domain> 1255 1256<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> 1257 <doc> 1258 Like CP_REG_TO_MEM, but the memory address to write to can be 1259 offsetted using a DWORD in memory. 1260 </doc> 1261 <reg32 offset="0" name="0"> 1262 <bitfield name="REG" low="0" high="17" type="hex"/> 1263 <!-- number of registers/dwords copied is max(CNT, 1). --> 1264 <bitfield name="CNT" low="18" high="29" type="uint"/> 1265 <bitfield name="64B" pos="30" type="boolean"/> 1266 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1267 </reg32> 1268 <reg32 offset="1" name="1"> 1269 <bitfield name="DEST" low="0" high="31"/> 1270 </reg32> 1271 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1272 <bitfield name="DEST_HI" low="0" high="31"/> 1273 </reg32> 1274 <reg32 offset="3" name="3"> 1275 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1276 </reg32> 1277 <reg32 offset="4" name="4"> 1278 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1279 </reg32> 1280</domain> 1281 1282<domain name="CP_MEM_TO_REG" width="32"> 1283 <reg32 offset="0" name="0"> 1284 <bitfield name="REG" low="0" high="17" type="hex"/> 1285 <!-- number of registers/dwords copied is max(CNT, 1). --> 1286 <bitfield name="CNT" low="19" high="29" type="uint"/> 1287 <!-- shift each DWORD left by 2 while copying --> 1288 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> 1289 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1290 <bitfield name="UNK31" pos="31" type="boolean"/> 1291 </reg32> 1292 <reg32 offset="1" name="1"> 1293 <bitfield name="SRC" low="0" high="31"/> 1294 </reg32> 1295 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1296 <bitfield name="SRC_HI" low="0" high="31"/> 1297 </reg32> 1298</domain> 1299 1300<domain name="CP_MEM_TO_MEM" width="32"> 1301 <reg32 offset="0" name="0"> 1302 <!-- 1303 not sure how many src operands we have, but the low 1304 bits negate the n'th src argument. 1305 --> 1306 <bitfield name="NEG_A" pos="0" type="boolean"/> 1307 <bitfield name="NEG_B" pos="1" type="boolean"/> 1308 <bitfield name="NEG_C" pos="2" type="boolean"/> 1309 1310 <!-- if set treat src/dst as 64bit values --> 1311 <bitfield name="DOUBLE" pos="29" type="boolean"/> 1312 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> 1313 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> 1314 <!-- some other kind of wait --> 1315 <bitfield name="UNK31" pos="31" type="boolean"/> 1316 </reg32> 1317 <!-- 1318 followed by sequence of addresses.. the first is the 1319 destination and the rest are N src addresses which are 1320 summed (after being negated if NEG_x bit set) allowing 1321 to do things like 'result += end - start' (which turns 1322 out to be useful for queries and accumulating results 1323 across multiple tiles) 1324 --> 1325</domain> 1326 1327<domain name="CP_MEMCPY" width="32"> 1328 <reg32 offset="0" name="0"> 1329 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1330 </reg32> 1331 <reg32 offset="1" name="1"> 1332 <bitfield name="SRC_LO" low="0" high="31" type="hex"/> 1333 </reg32> 1334 <reg32 offset="2" name="2"> 1335 <bitfield name="SRC_HI" low="0" high="31" type="hex"/> 1336 </reg32> 1337 <reg32 offset="3" name="3"> 1338 <bitfield name="DST_LO" low="0" high="31" type="hex"/> 1339 </reg32> 1340 <reg32 offset="4" name="4"> 1341 <bitfield name="DST_HI" low="0" high="31" type="hex"/> 1342 </reg32> 1343</domain> 1344 1345<domain name="CP_REG_TO_SCRATCH" width="32"> 1346 <reg32 offset="0" name="0"> 1347 <bitfield name="REG" low="0" high="17" type="hex"/> 1348 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1349 <!-- number of registers/dwords copied is CNT + 1. --> 1350 <bitfield name="CNT" low="24" high="26" type="uint"/> 1351 </reg32> 1352</domain> 1353 1354<domain name="CP_SCRATCH_TO_REG" width="32"> 1355 <reg32 offset="0" name="0"> 1356 <bitfield name="REG" low="0" high="17" type="hex"/> 1357 <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> 1358 <bitfield name="UNK18" pos="18" type="boolean"/> 1359 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1360 <!-- number of registers/dwords copied is CNT + 1. --> 1361 <bitfield name="CNT" low="24" high="26" type="uint"/> 1362 </reg32> 1363</domain> 1364 1365<domain name="CP_SCRATCH_WRITE" width="32"> 1366 <reg32 offset="0" name="0"> 1367 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1368 </reg32> 1369 <!-- followed by one or more DWORDs to write to scratch registers --> 1370</domain> 1371 1372<domain name="CP_MEM_WRITE" width="32"> 1373 <reg32 offset="0" name="0"> 1374 <bitfield name="ADDR_LO" low="0" high="31"/> 1375 </reg32> 1376 <reg32 offset="1" name="1"> 1377 <bitfield name="ADDR_HI" low="0" high="31"/> 1378 </reg32> 1379 <!-- followed by the DWORDs to write --> 1380</domain> 1381 1382<enum name="cp_cond_function"> 1383 <value value="0" name="WRITE_ALWAYS"/> 1384 <value value="1" name="WRITE_LT"/> 1385 <value value="2" name="WRITE_LE"/> 1386 <value value="3" name="WRITE_EQ"/> 1387 <value value="4" name="WRITE_NE"/> 1388 <value value="5" name="WRITE_GE"/> 1389 <value value="6" name="WRITE_GT"/> 1390</enum> 1391 1392<domain name="CP_COND_WRITE" width="32"> 1393 <reg32 offset="0" name="0"> 1394 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1395 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1396 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1397 </reg32> 1398 <reg32 offset="1" name="1"> 1399 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> 1400 </reg32> 1401 <reg32 offset="2" name="2"> 1402 <bitfield name="REF" low="0" high="31"/> 1403 </reg32> 1404 <reg32 offset="3" name="3"> 1405 <bitfield name="MASK" low="0" high="31"/> 1406 </reg32> 1407 <reg32 offset="4" name="4"> 1408 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> 1409 </reg32> 1410 <reg32 offset="5" name="5"> 1411 <bitfield name="WRITE_DATA" low="0" high="31"/> 1412 </reg32> 1413</domain> 1414 1415<enum name="poll_memory_type"> 1416 <value value="0" name="POLL_REGISTER"/> 1417 <value value="1" name="POLL_MEMORY"/> 1418 <value value="2" name="POLL_SCRATCH"/> 1419 <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/> 1420</enum> 1421 1422<domain name="CP_COND_WRITE5" width="32"> 1423 <reg32 offset="0" name="0"> 1424 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1425 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1426 <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. --> 1427 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1428 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1429 </reg32> 1430 <reg32 offset="1" name="1"> 1431 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1432 </reg32> 1433 <reg32 offset="2" name="2"> 1434 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1435 </reg32> 1436 <reg32 offset="3" name="3"> 1437 <bitfield name="REF" low="0" high="31"/> 1438 </reg32> 1439 <reg32 offset="4" name="4"> 1440 <bitfield name="MASK" low="0" high="31"/> 1441 </reg32> 1442 <reg32 offset="5" name="5"> 1443 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1444 </reg32> 1445 <reg32 offset="6" name="6"> 1446 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1447 </reg32> 1448 <reg32 offset="7" name="7"> 1449 <bitfield name="WRITE_DATA" low="0" high="31"/> 1450 </reg32> 1451</domain> 1452 1453<domain name="CP_WAIT_MEM_GTE" width="32"> 1454 <doc> 1455 Wait until a memory value is greater than or equal to the 1456 reference, using signed comparison. 1457 </doc> 1458 <reg32 offset="0" name="0"> 1459 <!-- Reserved for flags, presumably? Unused in FW --> 1460 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1461 </reg32> 1462 <reg32 offset="1" name="1"> 1463 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1464 </reg32> 1465 <reg32 offset="2" name="2"> 1466 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1467 </reg32> 1468 <reg32 offset="3" name="3"> 1469 <bitfield name="REF" low="0" high="31"/> 1470 </reg32> 1471</domain> 1472 1473<domain name="CP_WAIT_REG_MEM" width="32"> 1474 <doc> 1475 This uses the same internal comparison as CP_COND_WRITE, 1476 but waits until the comparison is true instead. It busy-loops in 1477 the CP for the given number of cycles before trying again. 1478 </doc> 1479 <reg32 offset="0" name="0"> 1480 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1481 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1482 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1483 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1484 </reg32> 1485 <reg32 offset="1" name="1"> 1486 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1487 </reg32> 1488 <reg32 offset="2" name="2"> 1489 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1490 </reg32> 1491 <reg32 offset="3" name="3"> 1492 <bitfield name="REF" low="0" high="31"/> 1493 </reg32> 1494 <reg32 offset="4" name="4"> 1495 <bitfield name="MASK" low="0" high="31"/> 1496 </reg32> 1497 <reg32 offset="5" name="5"> 1498 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> 1499 </reg32> 1500</domain> 1501 1502<domain name="CP_WAIT_TWO_REGS" width="32"> 1503 <doc> 1504 Waits for REG0 to not be 0 or REG1 to not equal REF 1505 </doc> 1506 <reg32 offset="0" name="0"> 1507 <bitfield name="REG0" low="0" high="17" type="hex"/> 1508 </reg32> 1509 <reg32 offset="1" name="1"> 1510 <bitfield name="REG1" low="0" high="17" type="hex"/> 1511 </reg32> 1512 <reg32 offset="2" name="2"> 1513 <bitfield name="REF" low="0" high="31" type="uint"/> 1514 </reg32> 1515</domain> 1516 1517<domain name="CP_DISPATCH_COMPUTE" width="32"> 1518 <reg32 offset="0" name="0"/> 1519 <reg32 offset="1" name="1"> 1520 <bitfield name="X" low="0" high="31"/> 1521 </reg32> 1522 <reg32 offset="2" name="2"> 1523 <bitfield name="Y" low="0" high="31"/> 1524 </reg32> 1525 <reg32 offset="3" name="3"> 1526 <bitfield name="Z" low="0" high="31"/> 1527 </reg32> 1528</domain> 1529 1530<domain name="CP_SET_RENDER_MODE" width="32"> 1531 <enum name="render_mode_cmd"> 1532 <value value="1" name="BYPASS"/> 1533 <value value="2" name="BINNING"/> 1534 <value value="3" name="GMEM"/> 1535 <value value="5" name="BLIT2D"/> 1536 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> 1537 <value value="7" name="BLIT2DSCALE"/> 1538 <!-- 8 set before going back to BYPASS exiting 2D --> 1539 <value value="8" name="END2D"/> 1540 </enum> 1541 <reg32 offset="0" name="0"> 1542 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> 1543 <!-- 1544 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in 1545 0x21xx range.. possibly (at least some) a5xx variants have a 1546 2d core? 1547 --> 1548 </reg32> 1549 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1550 <reg32 offset="1" name="1"> 1551 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1552 </reg32> 1553 <reg32 offset="2" name="2"> 1554 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1555 </reg32> 1556 <reg32 offset="3" name="3"> 1557 <!-- 1558 set when in GMEM.. maybe indicates GMEM contents need to be 1559 preserved on ctx switch? 1560 --> 1561 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> 1562 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> 1563 </reg32> 1564 <reg32 offset="4" name="4"/> 1565 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1566 <reg32 offset="5" name="5"> 1567 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1568 </reg32> 1569 <reg32 offset="6" name="6"> 1570 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1571 </reg32> 1572 <reg32 offset="7" name="7"> 1573 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1574 </reg32> 1575</domain> 1576 1577<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> 1578<domain name="CP_COMPUTE_CHECKPOINT" width="32"> 1579 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1580 <reg32 offset="0" name="0"> 1581 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1582 </reg32> 1583 <reg32 offset="1" name="1"> 1584 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1585 </reg32> 1586 <reg32 offset="2" name="2"> 1587 </reg32> 1588 <reg32 offset="3" name="3"/> 1589 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1590 <reg32 offset="4" name="4"> 1591 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1592 </reg32> 1593 <reg32 offset="5" name="5"> 1594 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1595 </reg32> 1596 <reg32 offset="6" name="6"> 1597 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1598 </reg32> 1599 <reg32 offset="7" name="7"/> 1600</domain> 1601 1602<domain name="CP_PERFCOUNTER_ACTION" width="32"> 1603 <reg32 offset="0" name="0"> 1604 </reg32> 1605 <reg32 offset="1" name="1"> 1606 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1607 </reg32> 1608 <reg32 offset="2" name="2"> 1609 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1610 </reg32> 1611</domain> 1612 1613<domain varset="chip" name="CP_EVENT_WRITE" width="32"> 1614 <reg32 offset="0" name="0"> 1615 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1616 <!-- when set, write back timestamp instead of value from packet: --> 1617 <bitfield name="TIMESTAMP" pos="30" type="boolean"/> 1618 <bitfield name="IRQ" pos="31" type="boolean"/> 1619 </reg32> 1620 <!-- 1621 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1622 context switch? 1623 --> 1624 <reg32 offset="1" name="1"> 1625 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1626 </reg32> 1627 <reg32 offset="2" name="2"> 1628 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1629 </reg32> 1630 <reg32 offset="3" name="3"> 1631 <!-- ??? --> 1632 </reg32> 1633</domain> 1634 1635<domain varset="chip" name="CP_EVENT_WRITE7" width="32"> 1636 <enum name="event_write_src"> 1637 <!-- Write payload[0] --> 1638 <value value="0" name="EV_WRITE_USER_32B"/> 1639 <!-- Write payload[0] payload[1] --> 1640 <value value="1" name="EV_WRITE_USER_64B"/> 1641 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 1642 <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/> 1643 <value value="3" name="EV_WRITE_ALWAYSON"/> 1644 <!-- Write payload[1] regs starting at payload[0] offset --> 1645 <value value="4" name="EV_WRITE_REGS_CONTENT"/> 1646 </enum> 1647 1648 <enum name="event_write_dst"> 1649 <value value="0" name="EV_DST_RAM"/> 1650 <value value="1" name="EV_DST_ONCHIP"/> 1651 </enum> 1652 1653 <reg32 offset="0" name="0"> 1654 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1655 <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/> 1656 <!-- Write sample count at (iova + 16) --> 1657 <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/> 1658 <!-- *(iova + 8) = *(iova + 16) - *iova --> 1659 <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> 1660 1661 <!-- Next 4 flags are valid to set only when concurrent binning is enabled --> 1662 <!-- Increment 16b BV counter. Valid only in BV pipe --> 1663 <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/> 1664 <!-- Increment 16b BR counter. Valid only in BR pipe --> 1665 <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/> 1666 <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/> 1667 <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/> 1668 1669 <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/> 1670 <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/> 1671 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. --> 1672 <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/> 1673 </reg32> 1674 1675 <stripe varset="event_write_dst" variants="EV_DST_RAM"> 1676 <reg32 offset="1" name="1"> 1677 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1678 </reg32> 1679 <reg32 offset="2" name="2"> 1680 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1681 </reg32> 1682 <reg32 offset="3" name="3"> 1683 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1684 </reg32> 1685 <reg32 offset="4" name="4"> 1686 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1687 </reg32> 1688 </stripe> 1689 1690 <stripe varset="event_write_dst" variants="EV_DST_ONCHIP"> 1691 <reg32 offset="1" name="1"> 1692 <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/> 1693 </reg32> 1694 <reg32 offset="3" name="3"> 1695 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1696 </reg32> 1697 <reg32 offset="4" name="4"> 1698 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1699 </reg32> 1700 </stripe> 1701</domain> 1702 1703<domain name="CP_BLIT" width="32"> 1704 <enum name="cp_blit_cmd"> 1705 <value value="0" name="BLIT_OP_FILL"/> 1706 <value value="1" name="BLIT_OP_COPY"/> 1707 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> 1708 </enum> 1709 <reg32 offset="0" name="0"> 1710 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> 1711 </reg32> 1712 <reg32 offset="1" name="1"> 1713 <bitfield name="SRC_X1" low="0" high="13" type="uint"/> 1714 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> 1715 </reg32> 1716 <reg32 offset="2" name="2"> 1717 <bitfield name="SRC_X2" low="0" high="13" type="uint"/> 1718 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> 1719 </reg32> 1720 <reg32 offset="3" name="3"> 1721 <bitfield name="DST_X1" low="0" high="13" type="uint"/> 1722 <bitfield name="DST_Y1" low="16" high="29" type="uint"/> 1723 </reg32> 1724 <reg32 offset="4" name="4"> 1725 <bitfield name="DST_X2" low="0" high="13" type="uint"/> 1726 <bitfield name="DST_Y2" low="16" high="29" type="uint"/> 1727 </reg32> 1728</domain> 1729 1730<domain name="CP_EXEC_CS" width="32"> 1731 <reg32 offset="0" name="0"> 1732 </reg32> 1733 <reg32 offset="1" name="1"> 1734 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> 1735 </reg32> 1736 <reg32 offset="2" name="2"> 1737 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> 1738 </reg32> 1739 <reg32 offset="3" name="3"> 1740 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> 1741 </reg32> 1742</domain> 1743 1744<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 1745 <reg32 offset="0" name="0"> 1746 </reg32> 1747 <stripe varset="chip" variants="A4XX"> 1748 <reg32 offset="1" name="1"> 1749 <bitfield name="ADDR" low="0" high="31"/> 1750 </reg32> 1751 <reg32 offset="2" name="2"> 1752 <!-- localsize is value minus one: --> 1753 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1754 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1755 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1756 </reg32> 1757 </stripe> 1758 <stripe varset="chip" variants="A5XX-"> 1759 <reg32 offset="1" name="1"> 1760 <bitfield name="ADDR_LO" low="0" high="31"/> 1761 </reg32> 1762 <reg32 offset="2" name="2"> 1763 <bitfield name="ADDR_HI" low="0" high="31"/> 1764 </reg32> 1765 <reg32 offset="3" name="3"> 1766 <!-- localsize is value minus one: --> 1767 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1768 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1769 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1770 </reg32> 1771 </stripe> 1772</domain> 1773 1774<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1775 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1776 <enum name="a6xx_marker"> 1777 <value value="1" name="RM6_BYPASS"/> 1778 <value value="2" name="RM6_BINNING"/> 1779 <value value="4" name="RM6_GMEM"/> 1780 <value value="5" name="RM6_ENDVIS"/> 1781 <value value="6" name="RM6_RESOLVE"/> 1782 <value value="7" name="RM6_YIELD"/> 1783 <value value="8" name="RM6_COMPUTE"/> 1784 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1785 1786 <!-- 1787 These values come from a6xx_set_marker() in the 1788 downstream kernel, and they can only be set by the kernel 1789 --> 1790 <value value="0xd" name="RM6_IB1LIST_START"/> 1791 <value value="0xe" name="RM6_IB1LIST_END"/> 1792 <!-- IFPC - inter-frame power collapse --> 1793 <value value="0x100" name="RM6_IFPC_ENABLE"/> 1794 <value value="0x101" name="RM6_IFPC_DISABLE"/> 1795 </enum> 1796 <reg32 offset="0" name="0"> 1797 <!-- 1798 NOTE: blob driver and some versions of freedreno/turnip set 1799 b4, which is unused (at least by current sqe fw), but interferes 1800 with parsing if we extend the size of the bitfield to include 1801 b8 (only sent by kernel mode driver). Really, the way the 1802 parsing works in the firmware, only b0-b3 are considered, but 1803 if b8 is set, the low bits are interpreted differently. To 1804 model this, without getting confused by spurious b4, this is 1805 described as two overlapping bitfields: 1806 --> 1807 <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/> 1808 <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/> 1809 </reg32> 1810</domain> 1811 1812<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1813 <doc>Set internal CP registers, used to indicate context save data addresses</doc> 1814 <enum name="pseudo_reg"> 1815 <value value="0" name="SMMU_INFO"/> 1816 <value value="1" name="NON_SECURE_SAVE_ADDR"/> 1817 <value value="2" name="SECURE_SAVE_ADDR"/> 1818 <value value="3" name="NON_PRIV_SAVE_ADDR"/> 1819 <value value="4" name="COUNTER"/> 1820 1821 <!-- 1822 On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them, 1823 but that doesn't work with concurrent binning because BR will be reading from 1824 a different set of streams than BV is writing, so on a7xx we have these 1825 pseudo-regs instead, which do the right thing. 1826 1827 The corresponding VSC registers exist, and they're written by BV when it 1828 encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG 1829 it will only write some private scratch registers which are read by 1830 CP_SET_BIN_DATA5_OFFSET. 1831 1832 If concurrent binning is disabled then BR also does binning so it will also 1833 write the "real" registers in BR. 1834 --> 1835 <value value="8" name="DRAW_STRM_ADDRESS"/> 1836 <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/> 1837 <value value="10" name="PRIM_STRM_ADDRESS"/> 1838 <value value="11" name="UNK_STRM_ADDRESS"/> 1839 <value value="12" name="UNK_STRM_SIZE_ADDRESS"/> 1840 1841 <value value="16" name="BINDLESS_BASE_0_ADDR"/> 1842 <value value="17" name="BINDLESS_BASE_1_ADDR"/> 1843 <value value="18" name="BINDLESS_BASE_2_ADDR"/> 1844 <value value="19" name="BINDLESS_BASE_3_ADDR"/> 1845 <value value="20" name="BINDLESS_BASE_4_ADDR"/> 1846 <value value="21" name="BINDLESS_BASE_5_ADDR"/> 1847 <value value="22" name="BINDLESS_BASE_6_ADDR"/> 1848 </enum> 1849 <array offset="0" stride="3" length="100"> 1850 <reg32 offset="0" name="0"> 1851 <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/> 1852 </reg32> 1853 <reg32 offset="1" name="1"> 1854 <bitfield name="LO" low="0" high="31"/> 1855 </reg32> 1856 <reg32 offset="2" name="2"> 1857 <bitfield name="HI" low="0" high="31"/> 1858 </reg32> 1859 </array> 1860</domain> 1861 1862<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1863 <doc> 1864 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. 1865 So: 1866 1867 opcode: CP_REG_TEST (39) (2 dwords) 1868 { REG = 0xc10 | BIT = 0 } 1869 0000: 70b90001 00000c10 1870 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1871 0000: 70c70002 10000000 00000004 1872 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) 1873 1874 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at 1875 offset 0x0c10 is 1 1876 </doc> 1877 <enum name="source_type"> 1878 <value value="0" name="SOURCE_REG"/> 1879 <!-- Don't confuse with scratch registers, this is a separate memory 1880 written into by CP_MEM_TO_SCRATCH_MEM. --> 1881 <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/> 1882 </enum> 1883 <reg32 offset="0" name="0"> 1884 <!-- the register to test --> 1885 <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/> 1886 <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/> 1887 <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/> 1888 <!-- the bit to test --> 1889 <bitfield name="BIT" low="20" high="24" type="uint"/> 1890 <!-- skip implied CP_WAIT_FOR_ME --> 1891 <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/> 1892 <!-- the predicate bit to set (new in gen3+) --> 1893 <bitfield name="PRED_BIT" low="26" high="30" type="uint"/> 1894 <!-- update the predicate reg directly (new in gen3+) --> 1895 <bitfield name="PRED_UPDATE" pos="31" type="boolean"/> 1896 </reg32> 1897 1898 <!-- 1899 In PRED_UPDATE mode, the predicate reg is updated directly using two 1900 more dwords, ignoring other bits: 1901 1902 PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK); 1903 --> 1904 <reg32 offset="1" name="PRED_MASK" type="hex"/> 1905 <reg32 offset="2" name="PRED_VAL" type="hex"/> 1906</domain> 1907 1908<!-- I *think* this existed at least as far back as a4xx --> 1909<domain name="CP_COND_REG_EXEC" width="32"> 1910 <enum name="compare_mode"> 1911 <!-- use the predicate bit set by CP_REG_TEST --> 1912 <value value="1" name="PRED_TEST"/> 1913 <!-- compare two registers directly for equality --> 1914 <value value="2" name="REG_COMPARE"/> 1915 <!-- test if certain render modes are set via CP_SET_MARKER --> 1916 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> 1917 <!-- compare REG0 for equality with immediate --> 1918 <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/> 1919 <!-- test which of BR/BV are enabled --> 1920 <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/> 1921 </enum> 1922 <reg32 offset="0" name="0" varset="compare_mode"> 1923 <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/> 1924 1925 <!-- the predicate bit to test (new in gen3+) --> 1926 <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/> 1927 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/> 1928 <!-- With REG_COMPARE instead of register read from ONCHIP memory --> 1929 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 1930 1931 <!-- 1932 Note: these bits have the same meaning, and use the same 1933 internal mechanism as the bits in CP_SET_DRAW_STATE. 1934 When RENDER_MODE is selected, they're used as 1935 a bitmask of which modes pass the test. 1936 --> 1937 1938 <!-- RM6_BINNING --> 1939 <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/> 1940 <!-- all others --> 1941 <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/> 1942 <!-- RM6_BYPASS --> 1943 <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/> 1944 1945 <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/> 1946 <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/> 1947 <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/> 1948 1949 <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/> 1950 </reg32> 1951 1952 <stripe varset="compare_mode" variants="PRED_TEST"> 1953 <reg32 offset="1" name="1"> 1954 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 1955 </reg32> 1956 </stripe> 1957 1958 <stripe varset="compare_mode" variants="REG_COMPARE"> 1959 <reg32 offset="1" name="1"> 1960 <bitfield name="REG1" low="0" high="17" type="hex"/> 1961 <!-- Instead of register read from ONCHIP memory --> 1962 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 1963 </reg32> 1964 </stripe> 1965 1966 <stripe varset="compare_mode" variants="RENDER_MODE"> 1967 <reg32 offset="1" name="1"> 1968 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 1969 </reg32> 1970 </stripe> 1971 1972 <stripe varset="compare_mode" variants="REG_COMPARE_IMM"> 1973 <reg32 offset="1" name="1"> 1974 <bitfield name="IMM" low="0" high="31"/> 1975 </reg32> 1976 </stripe> 1977 1978 <stripe varset="compare_mode" variants="THREAD_MODE"> 1979 <reg32 offset="1" name="1"> 1980 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 1981 </reg32> 1982 </stripe> 1983 1984 <reg32 offset="2" name="2"> 1985 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 1986 </reg32> 1987</domain> 1988 1989<domain name="CP_COND_EXEC" width="32"> 1990 <doc> 1991 Executes the following DWORDs of commands if the dword at ADDR0 1992 is not equal to 0 and the dword at ADDR1 is less than REF 1993 (signed comparison). 1994 </doc> 1995 <reg32 offset="0" name="0"> 1996 <bitfield name="ADDR0_LO" low="0" high="31"/> 1997 </reg32> 1998 <reg32 offset="1" name="1"> 1999 <bitfield name="ADDR0_HI" low="0" high="31"/> 2000 </reg32> 2001 <reg32 offset="2" name="2"> 2002 <bitfield name="ADDR1_LO" low="0" high="31"/> 2003 </reg32> 2004 <reg32 offset="3" name="3"> 2005 <bitfield name="ADDR1_HI" low="0" high="31"/> 2006 </reg32> 2007 <reg32 offset="4" name="4"> 2008 <bitfield name="REF" low="0" high="31"/> 2009 </reg32> 2010 <reg32 offset="5" name="5"> 2011 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 2012 </reg32> 2013</domain> 2014 2015<domain name="CP_SET_AMBLE" width="32"> 2016 <doc> 2017 Used by the userspace and kernel drivers to set various IB's 2018 which are executed during context save/restore for handling 2019 state that isn't restored by the context switch routine itself. 2020 </doc> 2021 <enum name="amble_type"> 2022 <value name="PREAMBLE_AMBLE_TYPE" value="0"> 2023 <doc>Executed unconditionally when switching back to the context.</doc> 2024 </value> 2025 <value name="BIN_PREAMBLE_AMBLE_TYPE" value="1"> 2026 <doc> 2027 Executed when switching back after switching 2028 away during execution of 2029 a CP_SET_MARKER packet with RM6_BIN_RENDER_END as the 2030 payload *and* skipsaverestore is set. This is 2031 expected to restore static register values not 2032 saved when skipsaverestore is set. 2033 </doc> 2034 </value> 2035 <value name="POSTAMBLE_AMBLE_TYPE" value="2"> 2036 <doc> 2037 Executed when switching away from the context, 2038 except for context switches initiated via 2039 CP_YIELD. 2040 </doc> 2041 </value> 2042 <value name="KMD_AMBLE_TYPE" value="3"> 2043 <doc> 2044 This can only be set by the RB (i.e. the kernel) 2045 and executes with protected mode off, but 2046 is otherwise similar to POSTAMBLE_AMBLE_TYPE. 2047 </doc> 2048 </value> 2049 </enum> 2050 <reg32 offset="0" name="0"> 2051 <bitfield name="ADDR_LO" low="0" high="31"/> 2052 </reg32> 2053 <reg32 offset="1" name="1"> 2054 <bitfield name="ADDR_HI" low="0" high="31"/> 2055 </reg32> 2056 <reg32 offset="2" name="2"> 2057 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 2058 <bitfield name="TYPE" low="20" high="21" type="amble_type"/> 2059 </reg32> 2060</domain> 2061 2062<domain name="CP_REG_WRITE" width="32"> 2063 <enum name="reg_tracker"> 2064 <doc> 2065 Keep shadow copies of these registers and only set them 2066 when drawing, avoiding redundant writes: 2067 - VPC_CNTL_0 2068 - HLSQ_CONTROL_1_REG 2069 - HLSQ_UNKNOWN_B980 2070 </doc> 2071 <value name="TRACK_CNTL_REG" value="0x1"/> 2072 <doc> 2073 Track RB_RENDER_CNTL, and insert a WFI in the following 2074 situation: 2075 - There is a write that disables binning 2076 - There was a draw with binning left enabled, but in 2077 BYPASS mode 2078 Presumably this is a hang workaround? 2079 </doc> 2080 <value name="TRACK_RENDER_CNTL" value="0x2"/> 2081 <doc> 2082 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of 2083 the data to write is 0. Used by the Vulkan blob with 2084 PC_MULTIVIEW_CNTL, but this isn't predicated on particular 2085 register(s) like the others. 2086 </doc> 2087 <value name="UNK_EVENT_WRITE" value="0x4"/> 2088 <doc> 2089 Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and 2090 GRAS_LRZ_DEPTH_VIEW with previous values, and if one of 2091 the following is true: 2092 - GRAS_LRZ_CNTL::GREATER has changed 2093 - GRAS_LRZ_CNTL::DIR has changed, the old value is not 2094 CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED 2095 - GRAS_LRZ_DEPTH_VIEW has changed 2096 then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE 2097 forced to 1. 2098 Only exists in a650_sqe.fw. 2099 </doc> 2100 <value name="TRACK_LRZ" value="0x8"/> 2101 </enum> 2102 <reg32 offset="0" name="0"> 2103 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/> 2104 </reg32> 2105 <reg32 offset="1" name="1"/> 2106 <reg32 offset="2" name="2"/> 2107</domain> 2108 2109<domain name="CP_SMMU_TABLE_UPDATE" width="32"> 2110 <doc> 2111 Note that the SMMU's definition of TTBRn can take different forms 2112 depending on the pgtable format. But a5xx+ only uses aarch64 2113 format. 2114 </doc> 2115 <reg32 offset="0" name="0"> 2116 <bitfield name="TTBR0_LO" low="0" high="31"/> 2117 </reg32> 2118 <reg32 offset="1" name="1"> 2119 <bitfield name="TTBR0_HI" low="0" high="15"/> 2120 <bitfield name="ASID" low="16" high="31"/> 2121 </reg32> 2122 <reg32 offset="2" name="2"> 2123 <doc>Unused, does not apply to aarch64 pgtable format</doc> 2124 <bitfield name="CONTEXTIDR" low="0" high="31"/> 2125 </reg32> 2126 <reg32 offset="3" name="3"> 2127 <bitfield name="CONTEXTBANK" low="0" high="31"/> 2128 </reg32> 2129</domain> 2130 2131<domain name="CP_START_BIN" width="32"> 2132 <reg32 offset="0" name="BIN_COUNT" type="uint"/> 2133 <reg64 offset="1" name="PREFIX_ADDR" type="address"/> 2134 <reg32 offset="3" name="PREFIX_DWORDS"> 2135 <doc> 2136 Size of prefix for each bin. For each bin index i, the 2137 prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are 2138 executed in an IB2 before the IB1 commands following 2139 this packet. 2140 </doc> 2141 </reg32> 2142 <reg32 offset="4" name="BODY_DWORDS"> 2143 <doc>Number of dwords after this packet until CP_END_BIN</doc> 2144 </reg32> 2145</domain> 2146 2147<domain name="CP_WAIT_TIMESTAMP" width="32"> 2148 <enum name="ts_wait_value_src"> 2149 <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) --> 2150 <value value="0" name="TS_WAIT_GE_32B"/> 2151 <!-- Wait for value at memory address to be >= SRC_0 (unsigned) --> 2152 <value value="1" name="TS_WAIT_GE_64B"/> 2153 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 2154 <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/> 2155 </enum> 2156 2157 <enum name="ts_wait_type"> 2158 <value value="0" name="TS_WAIT_RAM"/> 2159 <value value="1" name="TS_WAIT_ONCHIP"/> 2160 </enum> 2161 2162 <reg32 offset="0" name="0"> 2163 <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/> 2164 <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/> 2165 </reg32> 2166 2167 <stripe varset="ts_wait_type" variants="TS_WAIT_RAM"> 2168 <reg64 offset="1" name="ADDR" type="address"/> 2169 </stripe> 2170 2171 <stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP"> 2172 <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/> 2173 </stripe> 2174 2175 <reg32 offset="3" name="SRC_0"/> 2176 <reg32 offset="4" name="SRC_1"/> 2177</domain> 2178 2179<domain name="CP_BV_BR_COUNT_OPS" width="32"> 2180 <enum name="pipe_count_op"> 2181 <value name="PIPE_CLEAR_BV_BR" value="0x1"/> 2182 <value name="PIPE_SET_BR_OFFSET" value="0x2"/> 2183 <!-- Wait until for BV_counter > BR_counter --> 2184 <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/> 2185 <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter --> 2186 <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/> 2187 </enum> 2188 <reg32 offset="0" name="0"> 2189 <bitfield name="OP" low="0" high="3" type="pipe_count_op"/> 2190 </reg32> 2191 <reg32 offset="1" name="1"> 2192 <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/> 2193 </reg32> 2194</domain> 2195 2196<domain name="CP_MODIFY_TIMESTAMP" width="32"> 2197 <enum name="timestamp_op"> 2198 <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/> 2199 <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/> 2200 <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/> 2201 </enum> 2202 <reg32 offset="0" name="0"> 2203 <bitfield name="ADD" low="0" high="7" type="uint"/> 2204 <bitfield name="OP" low="28" high="31" type="timestamp_op"/> 2205 </reg32> 2206</domain> 2207 2208<domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> 2209 <doc> 2210 Best guess is that it is a faster way to fetch all the VSC_STATE registers 2211 and keep them in a local scratch memory instead of fetching every time 2212 when skipping IBs. 2213 </doc> 2214 <reg32 offset="0" name="0"> 2215 <bitfield name="CNT" low="0" high="5" type="uint"/> 2216 </reg32> 2217 <reg32 offset="1" name="1"> 2218 <doc>Scratch memory size is 48 dwords`</doc> 2219 <bitfield name="OFFSET" low="0" high="5" type="uint"/> 2220 </reg32> 2221 <reg32 offset="2" name="2"> 2222 <bitfield name="SRC" low="0" high="31"/> 2223 </reg32> 2224 <reg32 offset="3" name="3"> 2225 <bitfield name="SRC_HI" low="0" high="31"/> 2226 </reg32> 2227</domain> 2228 2229<domain name="CP_THREAD_CONTROL" width="32"> 2230 <enum name="cp_thread"> 2231 <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render --> 2232 <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility --> 2233 <value name="CP_SET_THREAD_BOTH" value="3"/> 2234 </enum> 2235 <reg32 offset="0" name="0"> 2236 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/> 2237 <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/> 2238 <bitfield pos="31" name="SYNC_THREADS" type="boolean"/> 2239 </reg32> 2240</domain> 2241 2242<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32"> 2243 <reg64 offset="0" name="IB_BASE"/> 2244 <reg32 offset="2" name="2"> 2245 <!-- STRIDE * COUNT --> 2246 <bitfield name="IB_SIZE" low="0" high="11"/> 2247 <bitfield name="STRIDE" low="20" high="31"/> 2248 </reg32> 2249 <reg32 offset="3" name="3"> 2250 <bitfield name="COUNT" low="0" high="31"/> 2251 </reg32> 2252</domain> 2253 2254<domain name="CP_RESET_CONTEXT_STATE" width="32"> 2255 <reg32 offset="0" name="0"> 2256 <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/> 2257 <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/> 2258 <bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/> 2259 </reg32> 2260</domain> 2261 2262<domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-"> 2263 <reg64 offset="0" name="IB_BASE" type="address"/> 2264 <reg32 offset="2" name="2"> 2265 <bitfield name="IB_SIZE" low="0" high="19"/> 2266 </reg32> 2267</domain> 2268 2269</database> 2270 2271