1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_dpm.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_sienna_cichlid.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "sienna_cichlid_ppt.h"
40 #include "smu_v11_0_7_pptable.h"
41 #include "smu_v11_0_7_ppsmc.h"
42 #include "nbio/nbio_2_3_offset.h"
43 #include "nbio/nbio_2_3_sh_mask.h"
44 #include "thm/thm_11_0_2_offset.h"
45 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "mp/mp_11_0_offset.h"
47 #include "mp/mp_11_0_sh_mask.h"
48
49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
50 #include "amdgpu_ras.h"
51 #include "smu_cmn.h"
52
53 /*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58 #undef pr_err
59 #undef pr_warn
60 #undef pr_info
61 #undef pr_debug
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 #define GET_PPTABLE_MEMBER(field, member) \
77 do { \
78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
79 IP_VERSION(11, 0, 13)) \
80 (*member) = (smu->smu_table.driver_pptable + \
81 offsetof(PPTable_beige_goby_t, field)); \
82 else \
83 (*member) = (smu->smu_table.driver_pptable + \
84 offsetof(PPTable_t, field)); \
85 } while (0)
86
87 /* STB FIFO depth is in 64bit units */
88 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
89
90 /*
91 * SMU support ECCTABLE since version 58.70.0,
92 * use this to check whether ECCTABLE feature is supported.
93 */
94 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
95
get_table_size(struct smu_context * smu)96 static int get_table_size(struct smu_context *smu)
97 {
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
99 return sizeof(PPTable_beige_goby_t);
100 else
101 return sizeof(PPTable_t);
102 }
103
104 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
162 };
163
164 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
165 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
166 CLK_MAP(SCLK, PPCLK_GFXCLK),
167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
168 CLK_MAP(FCLK, PPCLK_FCLK),
169 CLK_MAP(UCLK, PPCLK_UCLK),
170 CLK_MAP(MCLK, PPCLK_UCLK),
171 CLK_MAP(DCLK, PPCLK_DCLK_0),
172 CLK_MAP(DCLK1, PPCLK_DCLK_1),
173 CLK_MAP(VCLK, PPCLK_VCLK_0),
174 CLK_MAP(VCLK1, PPCLK_VCLK_1),
175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
177 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
178 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
179 };
180
181 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
182 FEA_MAP(DPM_PREFETCHER),
183 FEA_MAP(DPM_GFXCLK),
184 FEA_MAP(DPM_GFX_GPO),
185 FEA_MAP(DPM_UCLK),
186 FEA_MAP(DPM_FCLK),
187 FEA_MAP(DPM_SOCCLK),
188 FEA_MAP(DPM_MP0CLK),
189 FEA_MAP(DPM_LINK),
190 FEA_MAP(DPM_DCEFCLK),
191 FEA_MAP(DPM_XGMI),
192 FEA_MAP(MEM_VDDCI_SCALING),
193 FEA_MAP(MEM_MVDD_SCALING),
194 FEA_MAP(DS_GFXCLK),
195 FEA_MAP(DS_SOCCLK),
196 FEA_MAP(DS_FCLK),
197 FEA_MAP(DS_LCLK),
198 FEA_MAP(DS_DCEFCLK),
199 FEA_MAP(DS_UCLK),
200 FEA_MAP(GFX_ULV),
201 FEA_MAP(FW_DSTATE),
202 FEA_MAP(GFXOFF),
203 FEA_MAP(BACO),
204 FEA_MAP(MM_DPM_PG),
205 FEA_MAP(RSMU_SMN_CG),
206 FEA_MAP(PPT),
207 FEA_MAP(TDC),
208 FEA_MAP(APCC_PLUS),
209 FEA_MAP(GTHR),
210 FEA_MAP(ACDC),
211 FEA_MAP(VR0HOT),
212 FEA_MAP(VR1HOT),
213 FEA_MAP(FW_CTF),
214 FEA_MAP(FAN_CONTROL),
215 FEA_MAP(THERMAL),
216 FEA_MAP(GFX_DCS),
217 FEA_MAP(RM),
218 FEA_MAP(LED_DISPLAY),
219 FEA_MAP(GFX_SS),
220 FEA_MAP(OUT_OF_BAND_MONITOR),
221 FEA_MAP(TEMP_DEPENDENT_VMIN),
222 FEA_MAP(MMHUB_PG),
223 FEA_MAP(ATHUB_PG),
224 FEA_MAP(APCC_DFLL),
225 };
226
227 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
228 TAB_MAP(PPTABLE),
229 TAB_MAP(WATERMARKS),
230 TAB_MAP(AVFS_PSM_DEBUG),
231 TAB_MAP(AVFS_FUSE_OVERRIDE),
232 TAB_MAP(PMSTATUSLOG),
233 TAB_MAP(SMU_METRICS),
234 TAB_MAP(DRIVER_SMU_CONFIG),
235 TAB_MAP(ACTIVITY_MONITOR_COEFF),
236 TAB_MAP(OVERDRIVE),
237 TAB_MAP(I2C_COMMANDS),
238 TAB_MAP(PACE),
239 TAB_MAP(ECCINFO),
240 };
241
242 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
243 PWR_MAP(AC),
244 PWR_MAP(DC),
245 };
246
247 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
255 };
256
257 static const uint8_t sienna_cichlid_throttler_map[] = {
258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
276 };
277
278 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
281 {
282 struct amdgpu_device *adev = smu->adev;
283
284 if (num > 2)
285 return -EINVAL;
286
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
288
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
300 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
301 | FEATURE_MASK(FEATURE_PPT_BIT)
302 | FEATURE_MASK(FEATURE_TDC_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307 | FEATURE_MASK(FEATURE_THERMAL_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
313 }
314
315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317 !(adev->flags & AMD_IS_APU))
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
319
320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
324
325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
327
328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
330
331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
333
334 if (adev->pm.pp_feature & PP_ULV_MASK)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
336
337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
339
340 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
342
343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
345
346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
348
349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
352
353 if (smu->dc_controlled_by_gpio)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
355
356 if (amdgpu_device_should_use_aspm(adev))
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
358
359 return 0;
360 }
361
sienna_cichlid_check_bxco_support(struct smu_context * smu)362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
363 {
364 struct smu_table_context *table_context = &smu->smu_table;
365 struct smu_11_0_7_powerplay_table *powerplay_table =
366 table_context->power_play_table;
367 struct smu_baco_context *smu_baco = &smu->smu_baco;
368 struct amdgpu_device *adev = smu->adev;
369 uint32_t val;
370
371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
373 smu_baco->platform_support =
374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
375 false;
376
377 /*
378 * Disable BACO entry/exit completely on below SKUs to
379 * avoid hardware intermittent failures.
380 */
381 if (((adev->pdev->device == 0x73A1) &&
382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73BF) &&
384 (adev->pdev->revision == 0xCF)) ||
385 ((adev->pdev->device == 0x7422) &&
386 (adev->pdev->revision == 0x00)) ||
387 ((adev->pdev->device == 0x73A3) &&
388 (adev->pdev->revision == 0x00)) ||
389 ((adev->pdev->device == 0x73E3) &&
390 (adev->pdev->revision == 0x00)))
391 smu_baco->platform_support = false;
392
393 }
394 }
395
sienna_cichlid_check_fan_support(struct smu_context * smu)396 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
397 {
398 struct smu_table_context *table_context = &smu->smu_table;
399 PPTable_t *pptable = table_context->driver_pptable;
400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
401
402 /* Fan control is not possible if PPTable has it disabled */
403 smu->adev->pm.no_fan =
404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
405 if (smu->adev->pm.no_fan)
406 dev_info_once(smu->adev->dev,
407 "PMFW based fan control disabled");
408 }
409
sienna_cichlid_check_powerplay_table(struct smu_context * smu)410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
411 {
412 struct smu_table_context *table_context = &smu->smu_table;
413 struct smu_11_0_7_powerplay_table *powerplay_table =
414 table_context->power_play_table;
415
416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
417 smu->dc_controlled_by_gpio = true;
418
419 sienna_cichlid_check_bxco_support(smu);
420 sienna_cichlid_check_fan_support(smu);
421
422 table_context->thermal_controller_type =
423 powerplay_table->thermal_controller_type;
424
425 /*
426 * Instead of having its own buffer space and get overdrive_table copied,
427 * smu->od_settings just points to the actual overdrive_table
428 */
429 smu->od_settings = &powerplay_table->overdrive_table;
430
431 return 0;
432 }
433
sienna_cichlid_append_powerplay_table(struct smu_context * smu)434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
435 {
436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
437 int index, ret;
438 PPTable_beige_goby_t *ppt_beige_goby;
439 PPTable_t *ppt;
440
441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
442 ppt_beige_goby = smu->smu_table.driver_pptable;
443 else
444 ppt = smu->smu_table.driver_pptable;
445
446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
447 smc_dpm_info);
448
449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
450 (uint8_t **)&smc_dpm_table);
451 if (ret)
452 return ret;
453
454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
456 smc_dpm_table, I2cControllers);
457 else
458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
459 smc_dpm_table, I2cControllers);
460
461 return 0;
462 }
463
sienna_cichlid_store_powerplay_table(struct smu_context * smu)464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
465 {
466 struct smu_table_context *table_context = &smu->smu_table;
467 struct smu_11_0_7_powerplay_table *powerplay_table =
468 table_context->power_play_table;
469 int table_size;
470
471 table_size = get_table_size(smu);
472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
473 table_size);
474
475 return 0;
476 }
477
sienna_cichlid_patch_pptable_quirk(struct smu_context * smu)478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
479 {
480 struct amdgpu_device *adev = smu->adev;
481 uint32_t *board_reserved;
482 uint16_t *freq_table_gfx;
483 uint32_t i;
484
485 /* Fix some OEM SKU specific stability issues */
486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
487 if ((adev->pdev->device == 0x73DF) &&
488 (adev->pdev->revision == 0XC3) &&
489 (adev->pdev->subsystem_device == 0x16C2) &&
490 (adev->pdev->subsystem_vendor == 0x1043))
491 board_reserved[0] = 1387;
492
493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
494 if ((adev->pdev->device == 0x73DF) &&
495 (adev->pdev->revision == 0XC3) &&
496 ((adev->pdev->subsystem_device == 0x16C2) ||
497 (adev->pdev->subsystem_device == 0x133C)) &&
498 (adev->pdev->subsystem_vendor == 0x1043)) {
499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
500 if (freq_table_gfx[i] > 2500)
501 freq_table_gfx[i] = 2500;
502 }
503 }
504
505 return 0;
506 }
507
sienna_cichlid_setup_pptable(struct smu_context * smu)508 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
509 {
510 int ret = 0;
511
512 ret = smu_v11_0_setup_pptable(smu);
513 if (ret)
514 return ret;
515
516 ret = sienna_cichlid_store_powerplay_table(smu);
517 if (ret)
518 return ret;
519
520 ret = sienna_cichlid_append_powerplay_table(smu);
521 if (ret)
522 return ret;
523
524 ret = sienna_cichlid_check_powerplay_table(smu);
525 if (ret)
526 return ret;
527
528 return sienna_cichlid_patch_pptable_quirk(smu);
529 }
530
sienna_cichlid_tables_init(struct smu_context * smu)531 static int sienna_cichlid_tables_init(struct smu_context *smu)
532 {
533 struct smu_table_context *smu_table = &smu->smu_table;
534 struct smu_table *tables = smu_table->tables;
535 int table_size;
536
537 table_size = get_table_size(smu);
538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
552 AMDGPU_GEM_DOMAIN_VRAM);
553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
557
558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
559 if (!smu_table->metrics_table)
560 goto err0_out;
561 smu_table->metrics_time = 0;
562
563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
565 if (!smu_table->gpu_metrics_table)
566 goto err1_out;
567
568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
569 if (!smu_table->watermarks_table)
570 goto err2_out;
571
572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
573 if (!smu_table->ecc_table)
574 goto err3_out;
575
576 smu_table->driver_smu_config_table =
577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
578 if (!smu_table->driver_smu_config_table)
579 goto err4_out;
580
581 return 0;
582
583 err4_out:
584 kfree(smu_table->ecc_table);
585 err3_out:
586 kfree(smu_table->watermarks_table);
587 err2_out:
588 kfree(smu_table->gpu_metrics_table);
589 err1_out:
590 kfree(smu_table->metrics_table);
591 err0_out:
592 return -ENOMEM;
593 }
594
sienna_cichlid_get_throttler_status_locked(struct smu_context * smu,bool use_metrics_v3,bool use_metrics_v2)595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
596 bool use_metrics_v3,
597 bool use_metrics_v2)
598 {
599 struct smu_table_context *smu_table= &smu->smu_table;
600 SmuMetricsExternal_t *metrics_ext =
601 (SmuMetricsExternal_t *)(smu_table->metrics_table);
602 uint32_t throttler_status = 0;
603 int i;
604
605 if (use_metrics_v3) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else if (use_metrics_v2) {
610 for (i = 0; i < THROTTLER_COUNT; i++)
611 throttler_status |=
612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
613 } else {
614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
615 }
616
617 return throttler_status;
618 }
619
sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODFEATURE_CAP cap)620 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
621 enum SMU_11_0_7_ODFEATURE_CAP cap)
622 {
623 return od_table->cap[cap];
624 }
625
sienna_cichlid_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)626 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
627 uint32_t *current_power_limit,
628 uint32_t *default_power_limit,
629 uint32_t *max_power_limit,
630 uint32_t *min_power_limit)
631 {
632 struct smu_11_0_7_powerplay_table *powerplay_table =
633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
635 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
636 uint16_t *table_member;
637
638 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
639
640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
641 power_limit =
642 table_member[PPT_THROTTLER_PPT0];
643 }
644
645 if (current_power_limit)
646 *current_power_limit = power_limit;
647 if (default_power_limit)
648 *default_power_limit = power_limit;
649
650 if (powerplay_table) {
651 if (smu->od_enabled &&
652 sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) {
653 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
654 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
655 } else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) {
656 od_percent_upper = 0;
657 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
658 }
659 }
660
661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
662 od_percent_upper, od_percent_lower, power_limit);
663
664 if (max_power_limit) {
665 *max_power_limit = power_limit * (100 + od_percent_upper);
666 *max_power_limit /= 100;
667 }
668
669 if (min_power_limit) {
670 *min_power_limit = power_limit * (100 - od_percent_lower);
671 *min_power_limit /= 100;
672 }
673 return 0;
674 }
675
sienna_cichlid_get_smartshift_power_percentage(struct smu_context * smu,uint32_t * apu_percent,uint32_t * dgpu_percent)676 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
677 uint32_t *apu_percent,
678 uint32_t *dgpu_percent)
679 {
680 struct smu_table_context *smu_table = &smu->smu_table;
681 SmuMetrics_V4_t *metrics_v4 =
682 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
683 uint16_t powerRatio = 0;
684 uint16_t apu_power_limit = 0;
685 uint16_t dgpu_power_limit = 0;
686 uint32_t apu_boost = 0;
687 uint32_t dgpu_boost = 0;
688 uint32_t cur_power_limit;
689
690 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL);
692 apu_power_limit = metrics_v4->ApuSTAPMLimit;
693 dgpu_power_limit = cur_power_limit;
694 powerRatio = (((apu_power_limit +
695 dgpu_power_limit) * 100) /
696 metrics_v4->ApuSTAPMSmartShiftLimit);
697 if (powerRatio > 100) {
698 apu_power_limit = (apu_power_limit * 100) /
699 powerRatio;
700 dgpu_power_limit = (dgpu_power_limit * 100) /
701 powerRatio;
702 }
703 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
704 apu_power_limit != 0) {
705 apu_boost = ((metrics_v4->AverageApuSocketPower -
706 apu_power_limit) * 100) /
707 apu_power_limit;
708 if (apu_boost > 100)
709 apu_boost = 100;
710 }
711
712 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
713 dgpu_power_limit != 0) {
714 dgpu_boost = ((metrics_v4->AverageSocketPower -
715 dgpu_power_limit) * 100) /
716 dgpu_power_limit;
717 if (dgpu_boost > 100)
718 dgpu_boost = 100;
719 }
720
721 if (dgpu_boost >= apu_boost)
722 apu_boost = 0;
723 else
724 dgpu_boost = 0;
725 }
726 *apu_percent = apu_boost;
727 *dgpu_percent = dgpu_boost;
728 }
729
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)730 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
731 MetricsMember_t member,
732 uint32_t *value)
733 {
734 struct smu_table_context *smu_table= &smu->smu_table;
735 SmuMetrics_t *metrics =
736 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
737 SmuMetrics_V2_t *metrics_v2 =
738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
739 SmuMetrics_V3_t *metrics_v3 =
740 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
741 bool use_metrics_v2 = false;
742 bool use_metrics_v3 = false;
743 uint16_t average_gfx_activity;
744 int ret = 0;
745 uint32_t apu_percent = 0;
746 uint32_t dgpu_percent = 0;
747
748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
749 case IP_VERSION(11, 0, 7):
750 if (smu->smc_fw_version >= 0x3A4900)
751 use_metrics_v3 = true;
752 else if (smu->smc_fw_version >= 0x3A4300)
753 use_metrics_v2 = true;
754 break;
755 case IP_VERSION(11, 0, 11):
756 if (smu->smc_fw_version >= 0x412D00)
757 use_metrics_v2 = true;
758 break;
759 case IP_VERSION(11, 0, 12):
760 if (smu->smc_fw_version >= 0x3B2300)
761 use_metrics_v2 = true;
762 break;
763 case IP_VERSION(11, 0, 13):
764 if (smu->smc_fw_version >= 0x491100)
765 use_metrics_v2 = true;
766 break;
767 default:
768 break;
769 }
770
771 ret = smu_cmn_get_metrics_table(smu,
772 NULL,
773 false);
774 if (ret)
775 return ret;
776
777 switch (member) {
778 case METRICS_CURR_GFXCLK:
779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
781 metrics->CurrClock[PPCLK_GFXCLK];
782 break;
783 case METRICS_CURR_SOCCLK:
784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
786 metrics->CurrClock[PPCLK_SOCCLK];
787 break;
788 case METRICS_CURR_UCLK:
789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
791 metrics->CurrClock[PPCLK_UCLK];
792 break;
793 case METRICS_CURR_VCLK:
794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
796 metrics->CurrClock[PPCLK_VCLK_0];
797 break;
798 case METRICS_CURR_VCLK1:
799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
801 metrics->CurrClock[PPCLK_VCLK_1];
802 break;
803 case METRICS_CURR_DCLK:
804 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
806 metrics->CurrClock[PPCLK_DCLK_0];
807 break;
808 case METRICS_CURR_DCLK1:
809 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
810 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
811 metrics->CurrClock[PPCLK_DCLK_1];
812 break;
813 case METRICS_CURR_DCEFCLK:
814 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
815 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
816 metrics->CurrClock[PPCLK_DCEFCLK];
817 break;
818 case METRICS_CURR_FCLK:
819 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
820 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
821 metrics->CurrClock[PPCLK_FCLK];
822 break;
823 case METRICS_AVERAGE_GFXCLK:
824 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
825 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
826 metrics->AverageGfxActivity;
827 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
828 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
829 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
830 metrics->AverageGfxclkFrequencyPostDs;
831 else
832 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
833 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
834 metrics->AverageGfxclkFrequencyPreDs;
835 break;
836 case METRICS_AVERAGE_FCLK:
837 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
838 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
839 metrics->AverageFclkFrequencyPostDs;
840 break;
841 case METRICS_AVERAGE_UCLK:
842 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
843 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
844 metrics->AverageUclkFrequencyPostDs;
845 break;
846 case METRICS_AVERAGE_GFXACTIVITY:
847 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
848 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
849 metrics->AverageGfxActivity;
850 break;
851 case METRICS_AVERAGE_MEMACTIVITY:
852 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
853 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
854 metrics->AverageUclkActivity;
855 break;
856 case METRICS_AVERAGE_SOCKETPOWER:
857 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
858 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
859 metrics->AverageSocketPower << 8;
860 break;
861 case METRICS_TEMPERATURE_EDGE:
862 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
863 use_metrics_v2 ? metrics_v2->TemperatureEdge :
864 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
865 break;
866 case METRICS_TEMPERATURE_HOTSPOT:
867 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
868 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
869 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
870 break;
871 case METRICS_TEMPERATURE_MEM:
872 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
873 use_metrics_v2 ? metrics_v2->TemperatureMem :
874 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
875 break;
876 case METRICS_TEMPERATURE_VRGFX:
877 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
878 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
879 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
880 break;
881 case METRICS_TEMPERATURE_VRSOC:
882 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
883 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
884 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
885 break;
886 case METRICS_THROTTLER_STATUS:
887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
888 break;
889 case METRICS_CURR_FANSPEED:
890 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
891 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
892 break;
893 case METRICS_UNIQUE_ID_UPPER32:
894 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
895 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
896 break;
897 case METRICS_UNIQUE_ID_LOWER32:
898 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
899 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
900 break;
901 case METRICS_SS_APU_SHARE:
902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
903 *value = apu_percent;
904 break;
905 case METRICS_SS_DGPU_SHARE:
906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
907 *value = dgpu_percent;
908 break;
909
910 default:
911 *value = UINT_MAX;
912 break;
913 }
914
915 return ret;
916
917 }
918
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)919 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
920 {
921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
922
923 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
924 GFP_KERNEL);
925 if (!smu_dpm->dpm_context)
926 return -ENOMEM;
927
928 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
929
930 return 0;
931 }
932
933 static void sienna_cichlid_stb_init(struct smu_context *smu);
934
sienna_cichlid_init_smc_tables(struct smu_context * smu)935 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
936 {
937 struct amdgpu_device *adev = smu->adev;
938 int ret = 0;
939
940 ret = sienna_cichlid_tables_init(smu);
941 if (ret)
942 return ret;
943
944 ret = sienna_cichlid_allocate_dpm_context(smu);
945 if (ret)
946 return ret;
947
948 if (!amdgpu_sriov_vf(adev))
949 sienna_cichlid_stb_init(smu);
950
951 return smu_v11_0_init_smc_tables(smu);
952 }
953
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)954 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
955 {
956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
957 struct smu_11_0_dpm_table *dpm_table;
958 struct amdgpu_device *adev = smu->adev;
959 int i, ret = 0;
960 DpmDescriptor_t *table_member;
961
962 /* socclk dpm table setup */
963 dpm_table = &dpm_context->dpm_tables.soc_table;
964 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
966 ret = smu_v11_0_set_single_dpm_table(smu,
967 SMU_SOCCLK,
968 dpm_table);
969 if (ret)
970 return ret;
971 dpm_table->is_fine_grained =
972 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
973 } else {
974 dpm_table->count = 1;
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
976 dpm_table->dpm_levels[0].enabled = true;
977 dpm_table->min = dpm_table->dpm_levels[0].value;
978 dpm_table->max = dpm_table->dpm_levels[0].value;
979 }
980
981 /* gfxclk dpm table setup */
982 dpm_table = &dpm_context->dpm_tables.gfx_table;
983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
984 ret = smu_v11_0_set_single_dpm_table(smu,
985 SMU_GFXCLK,
986 dpm_table);
987 if (ret)
988 return ret;
989 dpm_table->is_fine_grained =
990 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
991 } else {
992 dpm_table->count = 1;
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
994 dpm_table->dpm_levels[0].enabled = true;
995 dpm_table->min = dpm_table->dpm_levels[0].value;
996 dpm_table->max = dpm_table->dpm_levels[0].value;
997 }
998
999 /* uclk dpm table setup */
1000 dpm_table = &dpm_context->dpm_tables.uclk_table;
1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1002 ret = smu_v11_0_set_single_dpm_table(smu,
1003 SMU_UCLK,
1004 dpm_table);
1005 if (ret)
1006 return ret;
1007 dpm_table->is_fine_grained =
1008 !table_member[PPCLK_UCLK].SnapToDiscrete;
1009 } else {
1010 dpm_table->count = 1;
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1012 dpm_table->dpm_levels[0].enabled = true;
1013 dpm_table->min = dpm_table->dpm_levels[0].value;
1014 dpm_table->max = dpm_table->dpm_levels[0].value;
1015 }
1016
1017 /* fclk dpm table setup */
1018 dpm_table = &dpm_context->dpm_tables.fclk_table;
1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1020 ret = smu_v11_0_set_single_dpm_table(smu,
1021 SMU_FCLK,
1022 dpm_table);
1023 if (ret)
1024 return ret;
1025 dpm_table->is_fine_grained =
1026 !table_member[PPCLK_FCLK].SnapToDiscrete;
1027 } else {
1028 dpm_table->count = 1;
1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1030 dpm_table->dpm_levels[0].enabled = true;
1031 dpm_table->min = dpm_table->dpm_levels[0].value;
1032 dpm_table->max = dpm_table->dpm_levels[0].value;
1033 }
1034
1035 /* vclk0/1 dpm table setup */
1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1037 if (adev->vcn.harvest_config & (1 << i))
1038 continue;
1039
1040 dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1043 i ? SMU_VCLK1 : SMU_VCLK,
1044 dpm_table);
1045 if (ret)
1046 return ret;
1047 dpm_table->is_fine_grained =
1048 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1049 } else {
1050 dpm_table->count = 1;
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 dpm_table->dpm_levels[0].enabled = true;
1053 dpm_table->min = dpm_table->dpm_levels[0].value;
1054 dpm_table->max = dpm_table->dpm_levels[0].value;
1055 }
1056 }
1057
1058 /* dclk0/1 dpm table setup */
1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1060 if (adev->vcn.harvest_config & (1 << i))
1061 continue;
1062 dpm_table = &dpm_context->dpm_tables.dclk_table;
1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1064 ret = smu_v11_0_set_single_dpm_table(smu,
1065 i ? SMU_DCLK1 : SMU_DCLK,
1066 dpm_table);
1067 if (ret)
1068 return ret;
1069 dpm_table->is_fine_grained =
1070 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1071 } else {
1072 dpm_table->count = 1;
1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1074 dpm_table->dpm_levels[0].enabled = true;
1075 dpm_table->min = dpm_table->dpm_levels[0].value;
1076 dpm_table->max = dpm_table->dpm_levels[0].value;
1077 }
1078 }
1079
1080 /* dcefclk dpm table setup */
1081 dpm_table = &dpm_context->dpm_tables.dcef_table;
1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1083 ret = smu_v11_0_set_single_dpm_table(smu,
1084 SMU_DCEFCLK,
1085 dpm_table);
1086 if (ret)
1087 return ret;
1088 dpm_table->is_fine_grained =
1089 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1090 } else {
1091 dpm_table->count = 1;
1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1093 dpm_table->dpm_levels[0].enabled = true;
1094 dpm_table->min = dpm_table->dpm_levels[0].value;
1095 dpm_table->max = dpm_table->dpm_levels[0].value;
1096 }
1097
1098 /* pixelclk dpm table setup */
1099 dpm_table = &dpm_context->dpm_tables.pixel_table;
1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1101 ret = smu_v11_0_set_single_dpm_table(smu,
1102 SMU_PIXCLK,
1103 dpm_table);
1104 if (ret)
1105 return ret;
1106 dpm_table->is_fine_grained =
1107 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1108 } else {
1109 dpm_table->count = 1;
1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1111 dpm_table->dpm_levels[0].enabled = true;
1112 dpm_table->min = dpm_table->dpm_levels[0].value;
1113 dpm_table->max = dpm_table->dpm_levels[0].value;
1114 }
1115
1116 /* displayclk dpm table setup */
1117 dpm_table = &dpm_context->dpm_tables.display_table;
1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1119 ret = smu_v11_0_set_single_dpm_table(smu,
1120 SMU_DISPCLK,
1121 dpm_table);
1122 if (ret)
1123 return ret;
1124 dpm_table->is_fine_grained =
1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1126 } else {
1127 dpm_table->count = 1;
1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1129 dpm_table->dpm_levels[0].enabled = true;
1130 dpm_table->min = dpm_table->dpm_levels[0].value;
1131 dpm_table->max = dpm_table->dpm_levels[0].value;
1132 }
1133
1134 /* phyclk dpm table setup */
1135 dpm_table = &dpm_context->dpm_tables.phy_table;
1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1137 ret = smu_v11_0_set_single_dpm_table(smu,
1138 SMU_PHYCLK,
1139 dpm_table);
1140 if (ret)
1141 return ret;
1142 dpm_table->is_fine_grained =
1143 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1144 } else {
1145 dpm_table->count = 1;
1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1147 dpm_table->dpm_levels[0].enabled = true;
1148 dpm_table->min = dpm_table->dpm_levels[0].value;
1149 dpm_table->max = dpm_table->dpm_levels[0].value;
1150 }
1151
1152 return 0;
1153 }
1154
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1155 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu,
1156 bool enable,
1157 int inst)
1158 {
1159 struct amdgpu_device *adev = smu->adev;
1160 int ret = 0;
1161
1162 if (adev->vcn.harvest_config & (1 << inst))
1163 return ret;
1164 /* vcn dpm on is a prerequisite for vcn power gate messages */
1165 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1166 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1167 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1168 0x10000 * inst, NULL);
1169 }
1170
1171 return ret;
1172 }
1173
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)1174 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1175 {
1176 int ret = 0;
1177
1178 if (enable) {
1179 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1180 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1181 if (ret)
1182 return ret;
1183 }
1184 } else {
1185 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1186 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1187 if (ret)
1188 return ret;
1189 }
1190 }
1191
1192 return ret;
1193 }
1194
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1195 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1196 enum smu_clk_type clk_type,
1197 uint32_t *value)
1198 {
1199 MetricsMember_t member_type;
1200 int clk_id = 0;
1201
1202 clk_id = smu_cmn_to_asic_specific_index(smu,
1203 CMN2ASIC_MAPPING_CLK,
1204 clk_type);
1205 if (clk_id < 0)
1206 return clk_id;
1207
1208 switch (clk_id) {
1209 case PPCLK_GFXCLK:
1210 member_type = METRICS_CURR_GFXCLK;
1211 break;
1212 case PPCLK_UCLK:
1213 member_type = METRICS_CURR_UCLK;
1214 break;
1215 case PPCLK_SOCCLK:
1216 member_type = METRICS_CURR_SOCCLK;
1217 break;
1218 case PPCLK_FCLK:
1219 member_type = METRICS_CURR_FCLK;
1220 break;
1221 case PPCLK_VCLK_0:
1222 member_type = METRICS_CURR_VCLK;
1223 break;
1224 case PPCLK_VCLK_1:
1225 member_type = METRICS_CURR_VCLK1;
1226 break;
1227 case PPCLK_DCLK_0:
1228 member_type = METRICS_CURR_DCLK;
1229 break;
1230 case PPCLK_DCLK_1:
1231 member_type = METRICS_CURR_DCLK1;
1232 break;
1233 case PPCLK_DCEFCLK:
1234 member_type = METRICS_CURR_DCEFCLK;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 return sienna_cichlid_get_smu_metrics_data(smu,
1241 member_type,
1242 value);
1243
1244 }
1245
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1246 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1247 {
1248 DpmDescriptor_t *dpm_desc = NULL;
1249 DpmDescriptor_t *table_member;
1250 uint32_t clk_index = 0;
1251
1252 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1253 clk_index = smu_cmn_to_asic_specific_index(smu,
1254 CMN2ASIC_MAPPING_CLK,
1255 clk_type);
1256 dpm_desc = &table_member[clk_index];
1257
1258 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1259 return dpm_desc->SnapToDiscrete == 0;
1260 }
1261
sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1262 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1263 enum SMU_11_0_7_ODSETTING_ID setting,
1264 uint32_t *min, uint32_t *max)
1265 {
1266 if (min)
1267 *min = od_table->min[setting];
1268 if (max)
1269 *max = od_table->max[setting];
1270 }
1271
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1272 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1273 enum smu_clk_type clk_type, char *buf)
1274 {
1275 struct amdgpu_device *adev = smu->adev;
1276 struct smu_table_context *table_context = &smu->smu_table;
1277 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1278 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1279 uint16_t *table_member;
1280
1281 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1282 OverDriveTable_t *od_table =
1283 (OverDriveTable_t *)table_context->overdrive_table;
1284 int i, size = 0, ret = 0;
1285 uint32_t cur_value = 0, value = 0, count = 0;
1286 uint32_t freq_values[3] = {0};
1287 uint32_t mark_index = 0;
1288 uint32_t gen_speed, lane_width;
1289 uint32_t min_value, max_value;
1290
1291 smu_cmn_get_sysfs_buf(&buf, &size);
1292
1293 switch (clk_type) {
1294 case SMU_GFXCLK:
1295 case SMU_SCLK:
1296 case SMU_SOCCLK:
1297 case SMU_MCLK:
1298 case SMU_UCLK:
1299 case SMU_FCLK:
1300 case SMU_VCLK:
1301 case SMU_VCLK1:
1302 case SMU_DCLK:
1303 case SMU_DCLK1:
1304 case SMU_DCEFCLK:
1305 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1306 if (ret)
1307 goto print_clk_out;
1308
1309 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1310 if (ret)
1311 goto print_clk_out;
1312
1313 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1314 for (i = 0; i < count; i++) {
1315 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1316 if (ret)
1317 goto print_clk_out;
1318
1319 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1320 cur_value == value ? "*" : "");
1321 }
1322 } else {
1323 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1324 if (ret)
1325 goto print_clk_out;
1326 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1327 if (ret)
1328 goto print_clk_out;
1329
1330 freq_values[1] = cur_value;
1331 mark_index = cur_value == freq_values[0] ? 0 :
1332 cur_value == freq_values[2] ? 2 : 1;
1333
1334 count = 3;
1335 if (mark_index != 1) {
1336 count = 2;
1337 freq_values[1] = freq_values[2];
1338 }
1339
1340 for (i = 0; i < count; i++) {
1341 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1342 cur_value == freq_values[i] ? "*" : "");
1343 }
1344
1345 }
1346 break;
1347 case SMU_PCIE:
1348 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1349 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1350 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1351 for (i = 0; i < NUM_LINK_LEVELS; i++)
1352 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1353 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1354 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1355 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1356 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1357 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1358 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1360 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1361 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1362 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1363 table_member[i],
1364 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1365 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1366 "*" : "");
1367 break;
1368 case SMU_OD_SCLK:
1369 if (!smu->od_enabled || !od_table || !od_settings)
1370 break;
1371
1372 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1373 break;
1374
1375 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1376 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1377 break;
1378
1379 case SMU_OD_MCLK:
1380 if (!smu->od_enabled || !od_table || !od_settings)
1381 break;
1382
1383 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1384 break;
1385
1386 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1387 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1388 break;
1389
1390 case SMU_OD_VDDGFX_OFFSET:
1391 if (!smu->od_enabled || !od_table || !od_settings)
1392 break;
1393
1394 /*
1395 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1396 * and onwards SMU firmwares.
1397 */
1398 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1399 IP_VERSION(11, 0, 7)) &&
1400 (smu->smc_fw_version < 0x003a2900))
1401 break;
1402
1403 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1404 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1405 break;
1406
1407 case SMU_OD_RANGE:
1408 if (!smu->od_enabled || !od_table || !od_settings)
1409 break;
1410
1411 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1412
1413 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1414 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1415 &min_value, NULL);
1416 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1417 NULL, &max_value);
1418 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1419 min_value, max_value);
1420 }
1421
1422 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1423 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1424 &min_value, NULL);
1425 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1426 NULL, &max_value);
1427 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1428 min_value, max_value);
1429 }
1430 break;
1431
1432 default:
1433 break;
1434 }
1435
1436 print_clk_out:
1437 return size;
1438 }
1439
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1440 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1441 enum smu_clk_type clk_type, uint32_t mask)
1442 {
1443 int ret = 0;
1444 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1445
1446 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1447 soft_max_level = mask ? (fls(mask) - 1) : 0;
1448
1449 switch (clk_type) {
1450 case SMU_GFXCLK:
1451 case SMU_SCLK:
1452 case SMU_SOCCLK:
1453 case SMU_MCLK:
1454 case SMU_UCLK:
1455 case SMU_FCLK:
1456 /* There is only 2 levels for fine grained DPM */
1457 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1458 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1459 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1460 }
1461
1462 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1463 if (ret)
1464 goto forec_level_out;
1465
1466 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1467 if (ret)
1468 goto forec_level_out;
1469
1470 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
1471 if (ret)
1472 goto forec_level_out;
1473 break;
1474 case SMU_DCEFCLK:
1475 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1476 break;
1477 default:
1478 break;
1479 }
1480
1481 forec_level_out:
1482 return 0;
1483 }
1484
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1485 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1486 {
1487 struct smu_11_0_dpm_context *dpm_context =
1488 smu->smu_dpm.dpm_context;
1489 struct smu_11_0_dpm_table *gfx_table =
1490 &dpm_context->dpm_tables.gfx_table;
1491 struct smu_11_0_dpm_table *mem_table =
1492 &dpm_context->dpm_tables.uclk_table;
1493 struct smu_11_0_dpm_table *soc_table =
1494 &dpm_context->dpm_tables.soc_table;
1495 struct smu_umd_pstate_table *pstate_table =
1496 &smu->pstate_table;
1497 struct amdgpu_device *adev = smu->adev;
1498
1499 pstate_table->gfxclk_pstate.min = gfx_table->min;
1500 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1501
1502 pstate_table->uclk_pstate.min = mem_table->min;
1503 pstate_table->uclk_pstate.peak = mem_table->max;
1504
1505 pstate_table->socclk_pstate.min = soc_table->min;
1506 pstate_table->socclk_pstate.peak = soc_table->max;
1507
1508 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1509 case IP_VERSION(11, 0, 7):
1510 case IP_VERSION(11, 0, 11):
1511 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1512 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1513 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1514 break;
1515 case IP_VERSION(11, 0, 12):
1516 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1517 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1518 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1519 break;
1520 case IP_VERSION(11, 0, 13):
1521 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1522 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1523 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1524 break;
1525 default:
1526 break;
1527 }
1528
1529 return 0;
1530 }
1531
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1532 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1533 {
1534 int ret = 0;
1535 uint32_t max_freq = 0;
1536
1537 /* Sienna_Cichlid do not support to change display num currently */
1538 return 0;
1539 #if 0
1540 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1541 if (ret)
1542 return ret;
1543 #endif
1544
1545 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1546 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1547 if (ret)
1548 return ret;
1549 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1550 if (ret)
1551 return ret;
1552 }
1553
1554 return ret;
1555 }
1556
sienna_cichlid_display_config_changed(struct smu_context * smu)1557 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1558 {
1559 int ret = 0;
1560
1561 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1562 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1563 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1564 #if 0
1565 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1566 smu->display_config->num_display,
1567 NULL);
1568 #endif
1569 if (ret)
1570 return ret;
1571 }
1572
1573 return ret;
1574 }
1575
sienna_cichlid_is_dpm_running(struct smu_context * smu)1576 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1577 {
1578 int ret = 0;
1579 uint64_t feature_enabled;
1580
1581 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1582 if (ret)
1583 return false;
1584
1585 return !!(feature_enabled & SMC_DPM_FEATURE);
1586 }
1587
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1588 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1589 uint32_t *speed)
1590 {
1591 if (!speed)
1592 return -EINVAL;
1593
1594 /*
1595 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1596 * by pmfw is always trustable(even when the fan control feature
1597 * disabled or 0 RPM kicked in).
1598 */
1599 return sienna_cichlid_get_smu_metrics_data(smu,
1600 METRICS_CURR_FANSPEED,
1601 speed);
1602 }
1603
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1604 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1605 {
1606 uint16_t *table_member;
1607
1608 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1609 smu->fan_max_rpm = *table_member;
1610
1611 return 0;
1612 }
1613
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1614 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1615 {
1616 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1617 DpmActivityMonitorCoeffInt_t *activity_monitor =
1618 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1619 uint32_t i, size = 0;
1620 int16_t workload_type = 0;
1621 static const char *title[] = {
1622 "PROFILE_INDEX(NAME)",
1623 "CLOCK_TYPE(NAME)",
1624 "FPS",
1625 "MinFreqType",
1626 "MinActiveFreqType",
1627 "MinActiveFreq",
1628 "BoosterFreqType",
1629 "BoosterFreq",
1630 "PD_Data_limit_c",
1631 "PD_Data_error_coeff",
1632 "PD_Data_error_rate_coeff"};
1633 int result = 0;
1634
1635 if (!buf)
1636 return -EINVAL;
1637
1638 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1639 title[0], title[1], title[2], title[3], title[4], title[5],
1640 title[6], title[7], title[8], title[9], title[10]);
1641
1642 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1643 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1644 workload_type = smu_cmn_to_asic_specific_index(smu,
1645 CMN2ASIC_MAPPING_WORKLOAD,
1646 i);
1647 if (workload_type < 0)
1648 return -EINVAL;
1649
1650 result = smu_cmn_update_table(smu,
1651 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1652 (void *)(&activity_monitor_external), false);
1653 if (result) {
1654 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1655 return result;
1656 }
1657
1658 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1659 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1660
1661 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1662 " ",
1663 0,
1664 "GFXCLK",
1665 activity_monitor->Gfx_FPS,
1666 activity_monitor->Gfx_MinFreqStep,
1667 activity_monitor->Gfx_MinActiveFreqType,
1668 activity_monitor->Gfx_MinActiveFreq,
1669 activity_monitor->Gfx_BoosterFreqType,
1670 activity_monitor->Gfx_BoosterFreq,
1671 activity_monitor->Gfx_PD_Data_limit_c,
1672 activity_monitor->Gfx_PD_Data_error_coeff,
1673 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1674
1675 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1676 " ",
1677 1,
1678 "SOCCLK",
1679 activity_monitor->Fclk_FPS,
1680 activity_monitor->Fclk_MinFreqStep,
1681 activity_monitor->Fclk_MinActiveFreqType,
1682 activity_monitor->Fclk_MinActiveFreq,
1683 activity_monitor->Fclk_BoosterFreqType,
1684 activity_monitor->Fclk_BoosterFreq,
1685 activity_monitor->Fclk_PD_Data_limit_c,
1686 activity_monitor->Fclk_PD_Data_error_coeff,
1687 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1688
1689 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1690 " ",
1691 2,
1692 "MEMCLK",
1693 activity_monitor->Mem_FPS,
1694 activity_monitor->Mem_MinFreqStep,
1695 activity_monitor->Mem_MinActiveFreqType,
1696 activity_monitor->Mem_MinActiveFreq,
1697 activity_monitor->Mem_BoosterFreqType,
1698 activity_monitor->Mem_BoosterFreq,
1699 activity_monitor->Mem_PD_Data_limit_c,
1700 activity_monitor->Mem_PD_Data_error_coeff,
1701 activity_monitor->Mem_PD_Data_error_rate_coeff);
1702 }
1703
1704 return size;
1705 }
1706
1707 #define SIENNA_CICHLID_CUSTOM_PARAMS_COUNT 10
1708 #define SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT 3
1709 #define SIENNA_CICHLID_CUSTOM_PARAMS_SIZE (SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT * sizeof(long))
1710
sienna_cichlid_set_power_profile_mode_coeff(struct smu_context * smu,long * input)1711 static int sienna_cichlid_set_power_profile_mode_coeff(struct smu_context *smu,
1712 long *input)
1713 {
1714
1715 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1716 DpmActivityMonitorCoeffInt_t *activity_monitor =
1717 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1718 int ret, idx;
1719
1720 ret = smu_cmn_update_table(smu,
1721 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1722 (void *)(&activity_monitor_external), false);
1723 if (ret) {
1724 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1725 return ret;
1726 }
1727
1728 idx = 0 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1729 if (input[idx]) {
1730 /* Gfxclk */
1731 activity_monitor->Gfx_FPS = input[idx + 1];
1732 activity_monitor->Gfx_MinFreqStep = input[idx + 2];
1733 activity_monitor->Gfx_MinActiveFreqType = input[idx + 3];
1734 activity_monitor->Gfx_MinActiveFreq = input[idx + 4];
1735 activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
1736 activity_monitor->Gfx_BoosterFreq = input[idx + 6];
1737 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 7];
1738 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 8];
1739 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 9];
1740 }
1741 idx = 1 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1742 if (input[idx]) {
1743 /* Socclk */
1744 activity_monitor->Fclk_FPS = input[idx + 1];
1745 activity_monitor->Fclk_MinFreqStep = input[idx + 2];
1746 activity_monitor->Fclk_MinActiveFreqType = input[idx + 3];
1747 activity_monitor->Fclk_MinActiveFreq = input[idx + 4];
1748 activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
1749 activity_monitor->Fclk_BoosterFreq = input[idx + 6];
1750 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 7];
1751 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 8];
1752 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 9];
1753 }
1754 idx = 2 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1755 if (input[idx]) {
1756 /* Memclk */
1757 activity_monitor->Mem_FPS = input[idx + 1];
1758 activity_monitor->Mem_MinFreqStep = input[idx + 2];
1759 activity_monitor->Mem_MinActiveFreqType = input[idx + 3];
1760 activity_monitor->Mem_MinActiveFreq = input[idx + 4];
1761 activity_monitor->Mem_BoosterFreqType = input[idx + 5];
1762 activity_monitor->Mem_BoosterFreq = input[idx + 6];
1763 activity_monitor->Mem_PD_Data_limit_c = input[idx + 7];
1764 activity_monitor->Mem_PD_Data_error_coeff = input[idx + 8];
1765 activity_monitor->Mem_PD_Data_error_rate_coeff = input[idx + 9];
1766 }
1767
1768 ret = smu_cmn_update_table(smu,
1769 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1770 (void *)(&activity_monitor_external), true);
1771 if (ret) {
1772 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1773 return ret;
1774 }
1775
1776 return ret;
1777 }
1778
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1779 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu,
1780 u32 workload_mask,
1781 long *custom_params,
1782 u32 custom_params_max_idx)
1783 {
1784 u32 backend_workload_mask = 0;
1785 int ret, idx = -1, i;
1786
1787 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1788 &backend_workload_mask);
1789
1790 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1791 if (!smu->custom_profile_params) {
1792 smu->custom_profile_params =
1793 kzalloc(SIENNA_CICHLID_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1794 if (!smu->custom_profile_params)
1795 return -ENOMEM;
1796 }
1797 if (custom_params && custom_params_max_idx) {
1798 if (custom_params_max_idx != SIENNA_CICHLID_CUSTOM_PARAMS_COUNT)
1799 return -EINVAL;
1800 if (custom_params[0] >= SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT)
1801 return -EINVAL;
1802 idx = custom_params[0] * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT;
1803 smu->custom_profile_params[idx] = 1;
1804 for (i = 1; i < custom_params_max_idx; i++)
1805 smu->custom_profile_params[idx + i] = custom_params[i];
1806 }
1807 ret = sienna_cichlid_set_power_profile_mode_coeff(smu,
1808 smu->custom_profile_params);
1809 if (ret) {
1810 if (idx != -1)
1811 smu->custom_profile_params[idx] = 0;
1812 return ret;
1813 }
1814 } else if (smu->custom_profile_params) {
1815 memset(smu->custom_profile_params, 0, SIENNA_CICHLID_CUSTOM_PARAMS_SIZE);
1816 }
1817
1818 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1819 backend_workload_mask, NULL);
1820 if (ret) {
1821 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1822 workload_mask);
1823 if (idx != -1)
1824 smu->custom_profile_params[idx] = 0;
1825 return ret;
1826 }
1827
1828 return ret;
1829 }
1830
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1831 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1832 {
1833 struct smu_clocks min_clocks = {0};
1834 struct pp_display_clock_request clock_req;
1835 int ret = 0;
1836
1837 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1838 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1839 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1840
1841 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1842 clock_req.clock_type = amd_pp_dcef_clock;
1843 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1844
1845 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1846 if (!ret) {
1847 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1848 ret = smu_cmn_send_smc_msg_with_param(smu,
1849 SMU_MSG_SetMinDeepSleepDcefclk,
1850 min_clocks.dcef_clock_in_sr/100,
1851 NULL);
1852 if (ret) {
1853 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1854 return ret;
1855 }
1856 }
1857 } else {
1858 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1859 }
1860 }
1861
1862 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1863 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1864 if (ret) {
1865 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1866 return ret;
1867 }
1868 }
1869
1870 return 0;
1871 }
1872
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1873 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1874 struct pp_smu_wm_range_sets *clock_ranges)
1875 {
1876 Watermarks_t *table = smu->smu_table.watermarks_table;
1877 int ret = 0;
1878 int i;
1879
1880 if (clock_ranges) {
1881 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1882 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1883 return -EINVAL;
1884
1885 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1886 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1887 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1888 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1889 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1890 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1891 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1892 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1893 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1894
1895 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1896 clock_ranges->reader_wm_sets[i].wm_inst;
1897 }
1898
1899 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1900 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1901 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1902 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1903 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1904 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1905 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1906 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1907 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1908
1909 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1910 clock_ranges->writer_wm_sets[i].wm_inst;
1911 }
1912
1913 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1914 }
1915
1916 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1917 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1918 ret = smu_cmn_write_watermarks_table(smu);
1919 if (ret) {
1920 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1921 return ret;
1922 }
1923 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1924 }
1925
1926 return 0;
1927 }
1928
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1929 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1930 enum amd_pp_sensors sensor,
1931 void *data, uint32_t *size)
1932 {
1933 int ret = 0;
1934 uint16_t *temp;
1935 struct amdgpu_device *adev = smu->adev;
1936
1937 if(!data || !size)
1938 return -EINVAL;
1939
1940 switch (sensor) {
1941 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1942 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1943 *(uint16_t *)data = *temp;
1944 *size = 4;
1945 break;
1946 case AMDGPU_PP_SENSOR_MEM_LOAD:
1947 ret = sienna_cichlid_get_smu_metrics_data(smu,
1948 METRICS_AVERAGE_MEMACTIVITY,
1949 (uint32_t *)data);
1950 *size = 4;
1951 break;
1952 case AMDGPU_PP_SENSOR_GPU_LOAD:
1953 ret = sienna_cichlid_get_smu_metrics_data(smu,
1954 METRICS_AVERAGE_GFXACTIVITY,
1955 (uint32_t *)data);
1956 *size = 4;
1957 break;
1958 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1959 ret = sienna_cichlid_get_smu_metrics_data(smu,
1960 METRICS_AVERAGE_SOCKETPOWER,
1961 (uint32_t *)data);
1962 *size = 4;
1963 break;
1964 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1965 ret = sienna_cichlid_get_smu_metrics_data(smu,
1966 METRICS_TEMPERATURE_HOTSPOT,
1967 (uint32_t *)data);
1968 *size = 4;
1969 break;
1970 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1971 ret = sienna_cichlid_get_smu_metrics_data(smu,
1972 METRICS_TEMPERATURE_EDGE,
1973 (uint32_t *)data);
1974 *size = 4;
1975 break;
1976 case AMDGPU_PP_SENSOR_MEM_TEMP:
1977 ret = sienna_cichlid_get_smu_metrics_data(smu,
1978 METRICS_TEMPERATURE_MEM,
1979 (uint32_t *)data);
1980 *size = 4;
1981 break;
1982 case AMDGPU_PP_SENSOR_GFX_MCLK:
1983 ret = sienna_cichlid_get_smu_metrics_data(smu,
1984 METRICS_CURR_UCLK,
1985 (uint32_t *)data);
1986 *(uint32_t *)data *= 100;
1987 *size = 4;
1988 break;
1989 case AMDGPU_PP_SENSOR_GFX_SCLK:
1990 ret = sienna_cichlid_get_smu_metrics_data(smu,
1991 METRICS_AVERAGE_GFXCLK,
1992 (uint32_t *)data);
1993 *(uint32_t *)data *= 100;
1994 *size = 4;
1995 break;
1996 case AMDGPU_PP_SENSOR_VDDGFX:
1997 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1998 *size = 4;
1999 break;
2000 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
2001 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
2002 IP_VERSION(11, 0, 7)) {
2003 ret = sienna_cichlid_get_smu_metrics_data(smu,
2004 METRICS_SS_APU_SHARE, (uint32_t *)data);
2005 *size = 4;
2006 } else {
2007 ret = -EOPNOTSUPP;
2008 }
2009 break;
2010 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
2011 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
2012 IP_VERSION(11, 0, 7)) {
2013 ret = sienna_cichlid_get_smu_metrics_data(smu,
2014 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
2015 *size = 4;
2016 } else {
2017 ret = -EOPNOTSUPP;
2018 }
2019 break;
2020 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2021 default:
2022 ret = -EOPNOTSUPP;
2023 break;
2024 }
2025
2026 return ret;
2027 }
2028
sienna_cichlid_get_unique_id(struct smu_context * smu)2029 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
2030 {
2031 struct amdgpu_device *adev = smu->adev;
2032 uint32_t upper32 = 0, lower32 = 0;
2033
2034 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
2035 if (smu->smc_fw_version < 0x3A5300 ||
2036 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
2037 return;
2038
2039 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
2040 goto out;
2041 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
2042 goto out;
2043
2044 out:
2045
2046 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2047 }
2048
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)2049 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2050 {
2051 uint32_t num_discrete_levels = 0;
2052 uint16_t *dpm_levels = NULL;
2053 uint16_t i = 0;
2054 struct smu_table_context *table_context = &smu->smu_table;
2055 DpmDescriptor_t *table_member1;
2056 uint16_t *table_member2;
2057
2058 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2059 return -EINVAL;
2060
2061 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2062 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2063 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2064 dpm_levels = table_member2;
2065
2066 if (num_discrete_levels == 0 || dpm_levels == NULL)
2067 return -EINVAL;
2068
2069 *num_states = num_discrete_levels;
2070 for (i = 0; i < num_discrete_levels; i++) {
2071 /* convert to khz */
2072 *clocks_in_khz = (*dpm_levels) * 1000;
2073 clocks_in_khz++;
2074 dpm_levels++;
2075 }
2076
2077 return 0;
2078 }
2079
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2080 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2081 struct smu_temperature_range *range)
2082 {
2083 struct smu_table_context *table_context = &smu->smu_table;
2084 struct smu_11_0_7_powerplay_table *powerplay_table =
2085 table_context->power_play_table;
2086 uint16_t *table_member;
2087 uint16_t temp_edge, temp_hotspot, temp_mem;
2088
2089 if (!range)
2090 return -EINVAL;
2091
2092 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2093
2094 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2095 temp_edge = table_member[TEMP_EDGE];
2096 temp_hotspot = table_member[TEMP_HOTSPOT];
2097 temp_mem = table_member[TEMP_MEM];
2098
2099 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2100 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2101 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2102 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2103 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2104 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2105 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2106 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2107 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108
2109 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2110
2111 return 0;
2112 }
2113
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)2114 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2115 bool disable_memory_clock_switch)
2116 {
2117 int ret = 0;
2118 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2119 (struct smu_11_0_max_sustainable_clocks *)
2120 smu->smu_table.max_sustainable_clocks;
2121 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2122 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2123
2124 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2125 return 0;
2126
2127 if(disable_memory_clock_switch)
2128 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2129 else
2130 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2131
2132 if(!ret)
2133 smu->disable_uclk_switch = disable_memory_clock_switch;
2134
2135 return ret;
2136 }
2137
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2138 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2139 uint8_t pcie_gen_cap,
2140 uint8_t pcie_width_cap)
2141 {
2142 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2143 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2144 uint8_t *table_member1, *table_member2;
2145 uint8_t min_gen_speed, max_gen_speed;
2146 uint8_t min_lane_width, max_lane_width;
2147 uint32_t smu_pcie_arg;
2148 int ret, i;
2149
2150 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2151 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2152
2153 min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
2154 max_gen_speed = min(pcie_gen_cap, table_member1[1]);
2155 min_gen_speed = min_gen_speed > max_gen_speed ?
2156 max_gen_speed : min_gen_speed;
2157 min_lane_width = max_t(uint8_t, 1, table_member2[0]);
2158 max_lane_width = min(pcie_width_cap, table_member2[1]);
2159 min_lane_width = min_lane_width > max_lane_width ?
2160 max_lane_width : min_lane_width;
2161
2162 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2163 pcie_table->pcie_gen[0] = max_gen_speed;
2164 pcie_table->pcie_lane[0] = max_lane_width;
2165 } else {
2166 pcie_table->pcie_gen[0] = min_gen_speed;
2167 pcie_table->pcie_lane[0] = min_lane_width;
2168 }
2169 pcie_table->pcie_gen[1] = max_gen_speed;
2170 pcie_table->pcie_lane[1] = max_lane_width;
2171
2172 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2173 smu_pcie_arg = (i << 16 |
2174 pcie_table->pcie_gen[i] << 8 |
2175 pcie_table->pcie_lane[i]);
2176
2177 ret = smu_cmn_send_smc_msg_with_param(smu,
2178 SMU_MSG_OverridePcieParameters,
2179 smu_pcie_arg,
2180 NULL);
2181 if (ret)
2182 return ret;
2183 }
2184
2185 return 0;
2186 }
2187
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)2188 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2189 enum smu_clk_type clk_type,
2190 uint32_t *min, uint32_t *max)
2191 {
2192 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2193 }
2194
sienna_cichlid_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2195 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2196 OverDriveTable_t *od_table)
2197 {
2198 struct amdgpu_device *adev = smu->adev;
2199
2200 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2201 od_table->GfxclkFmax);
2202 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2203 od_table->UclkFmax);
2204
2205 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2206 (smu->smc_fw_version < 0x003a2900)))
2207 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2208 }
2209
sienna_cichlid_set_default_od_settings(struct smu_context * smu)2210 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2211 {
2212 OverDriveTable_t *od_table =
2213 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2214 OverDriveTable_t *boot_od_table =
2215 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2216 OverDriveTable_t *user_od_table =
2217 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2218 OverDriveTable_t user_od_table_bak;
2219 int ret = 0;
2220
2221 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2222 0, (void *)boot_od_table, false);
2223 if (ret) {
2224 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2225 return ret;
2226 }
2227
2228 sienna_cichlid_dump_od_table(smu, boot_od_table);
2229
2230 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2231
2232 /*
2233 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2234 * but we have to preserve user defined values in "user_od_table".
2235 */
2236 if (!smu->adev->in_suspend) {
2237 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2238 smu->user_dpm_profile.user_od = false;
2239 } else if (smu->user_dpm_profile.user_od) {
2240 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2241 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2242 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2243 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2244 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2245 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2246 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2247 }
2248
2249 return 0;
2250 }
2251
sienna_cichlid_od_setting_check_range(struct smu_context * smu,struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t value)2252 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2253 struct smu_11_0_7_overdrive_table *od_table,
2254 enum SMU_11_0_7_ODSETTING_ID setting,
2255 uint32_t value)
2256 {
2257 if (value < od_table->min[setting]) {
2258 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2259 setting, value, od_table->min[setting]);
2260 return -EINVAL;
2261 }
2262 if (value > od_table->max[setting]) {
2263 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2264 setting, value, od_table->max[setting]);
2265 return -EINVAL;
2266 }
2267
2268 return 0;
2269 }
2270
sienna_cichlid_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2271 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2272 enum PP_OD_DPM_TABLE_COMMAND type,
2273 long input[], uint32_t size)
2274 {
2275 struct smu_table_context *table_context = &smu->smu_table;
2276 OverDriveTable_t *od_table =
2277 (OverDriveTable_t *)table_context->overdrive_table;
2278 struct smu_11_0_7_overdrive_table *od_settings =
2279 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2280 struct amdgpu_device *adev = smu->adev;
2281 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2282 uint16_t *freq_ptr;
2283 int i, ret = 0;
2284
2285 if (!smu->od_enabled) {
2286 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2287 return -EINVAL;
2288 }
2289
2290 if (!smu->od_settings) {
2291 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2292 return -ENOENT;
2293 }
2294
2295 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2296 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2297 return -EINVAL;
2298 }
2299
2300 switch (type) {
2301 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2302 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2303 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2304 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2305 return -ENOTSUPP;
2306 }
2307
2308 for (i = 0; i < size; i += 2) {
2309 if (i + 2 > size) {
2310 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2311 return -EINVAL;
2312 }
2313
2314 switch (input[i]) {
2315 case 0:
2316 if (input[i + 1] > od_table->GfxclkFmax) {
2317 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2318 input[i + 1], od_table->GfxclkFmax);
2319 return -EINVAL;
2320 }
2321
2322 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2323 freq_ptr = &od_table->GfxclkFmin;
2324 break;
2325
2326 case 1:
2327 if (input[i + 1] < od_table->GfxclkFmin) {
2328 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2329 input[i + 1], od_table->GfxclkFmin);
2330 return -EINVAL;
2331 }
2332
2333 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2334 freq_ptr = &od_table->GfxclkFmax;
2335 break;
2336
2337 default:
2338 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2339 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2340 return -EINVAL;
2341 }
2342
2343 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2344 freq_setting, input[i + 1]);
2345 if (ret)
2346 return ret;
2347
2348 *freq_ptr = (uint16_t)input[i + 1];
2349 }
2350 break;
2351
2352 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2353 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2354 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2355 return -ENOTSUPP;
2356 }
2357
2358 for (i = 0; i < size; i += 2) {
2359 if (i + 2 > size) {
2360 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2361 return -EINVAL;
2362 }
2363
2364 switch (input[i]) {
2365 case 0:
2366 if (input[i + 1] > od_table->UclkFmax) {
2367 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2368 input[i + 1], od_table->UclkFmax);
2369 return -EINVAL;
2370 }
2371
2372 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2373 freq_ptr = &od_table->UclkFmin;
2374 break;
2375
2376 case 1:
2377 if (input[i + 1] < od_table->UclkFmin) {
2378 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2379 input[i + 1], od_table->UclkFmin);
2380 return -EINVAL;
2381 }
2382
2383 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2384 freq_ptr = &od_table->UclkFmax;
2385 break;
2386
2387 default:
2388 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2389 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2390 return -EINVAL;
2391 }
2392
2393 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2394 freq_setting, input[i + 1]);
2395 if (ret)
2396 return ret;
2397
2398 *freq_ptr = (uint16_t)input[i + 1];
2399 }
2400 break;
2401
2402 case PP_OD_RESTORE_DEFAULT_TABLE:
2403 memcpy(table_context->overdrive_table,
2404 table_context->boot_overdrive_table,
2405 sizeof(OverDriveTable_t));
2406 fallthrough;
2407
2408 case PP_OD_COMMIT_DPM_TABLE:
2409 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2410 sienna_cichlid_dump_od_table(smu, od_table);
2411 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2412 if (ret) {
2413 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2414 return ret;
2415 }
2416 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2417 smu->user_dpm_profile.user_od = true;
2418
2419 if (!memcmp(table_context->user_overdrive_table,
2420 table_context->boot_overdrive_table,
2421 sizeof(OverDriveTable_t)))
2422 smu->user_dpm_profile.user_od = false;
2423 }
2424 break;
2425
2426 case PP_OD_EDIT_VDDGFX_OFFSET:
2427 if (size != 1) {
2428 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2429 return -EINVAL;
2430 }
2431
2432 /*
2433 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2434 * and onwards SMU firmwares.
2435 */
2436 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2437 IP_VERSION(11, 0, 7)) &&
2438 (smu->smc_fw_version < 0x003a2900)) {
2439 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2440 "only by 58.41.0 and onwards SMU firmwares!\n");
2441 return -EOPNOTSUPP;
2442 }
2443
2444 od_table->VddGfxOffset = (int16_t)input[0];
2445
2446 sienna_cichlid_dump_od_table(smu, od_table);
2447 break;
2448
2449 default:
2450 return -ENOSYS;
2451 }
2452
2453 return ret;
2454 }
2455
sienna_cichlid_restore_user_od_settings(struct smu_context * smu)2456 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2457 {
2458 struct smu_table_context *table_context = &smu->smu_table;
2459 OverDriveTable_t *od_table = table_context->overdrive_table;
2460 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2461 int res;
2462
2463 res = smu_v11_0_restore_user_od_settings(smu);
2464 if (res == 0)
2465 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2466
2467 return res;
2468 }
2469
sienna_cichlid_run_btc(struct smu_context * smu)2470 static int sienna_cichlid_run_btc(struct smu_context *smu)
2471 {
2472 int res;
2473
2474 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2475 if (res)
2476 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2477
2478 return res;
2479 }
2480
sienna_cichlid_baco_enter(struct smu_context * smu)2481 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2482 {
2483 struct amdgpu_device *adev = smu->adev;
2484
2485 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2486 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2487 else
2488 return smu_v11_0_baco_enter(smu);
2489 }
2490
sienna_cichlid_baco_exit(struct smu_context * smu)2491 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2492 {
2493 struct amdgpu_device *adev = smu->adev;
2494
2495 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2496 /* Wait for PMFW handling for the Dstate change */
2497 msleep(10);
2498 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2499 } else {
2500 return smu_v11_0_baco_exit(smu);
2501 }
2502 }
2503
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)2504 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2505 {
2506 struct amdgpu_device *adev = smu->adev;
2507 uint32_t val;
2508 uint32_t smu_version;
2509 int ret;
2510
2511 /**
2512 * SRIOV env will not support SMU mode1 reset
2513 * PM FW support mode1 reset from 58.26
2514 */
2515 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2516 if (ret)
2517 return false;
2518
2519 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2520 return false;
2521
2522 /**
2523 * mode1 reset relies on PSP, so we should check if
2524 * PSP is alive.
2525 */
2526 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2527 return val != 0x0;
2528 }
2529
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2530 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2531 struct i2c_msg *msg, int num_msgs)
2532 {
2533 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2534 struct amdgpu_device *adev = smu_i2c->adev;
2535 struct smu_context *smu = adev->powerplay.pp_handle;
2536 struct smu_table_context *smu_table = &smu->smu_table;
2537 struct smu_table *table = &smu_table->driver_table;
2538 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2539 int i, j, r, c;
2540 u16 dir;
2541
2542 if (!adev->pm.dpm_enabled)
2543 return -EBUSY;
2544
2545 req = kzalloc(sizeof(*req), GFP_KERNEL);
2546 if (!req)
2547 return -ENOMEM;
2548
2549 req->I2CcontrollerPort = smu_i2c->port;
2550 req->I2CSpeed = I2C_SPEED_FAST_400K;
2551 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2552 dir = msg[0].flags & I2C_M_RD;
2553
2554 for (c = i = 0; i < num_msgs; i++) {
2555 for (j = 0; j < msg[i].len; j++, c++) {
2556 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2557
2558 if (!(msg[i].flags & I2C_M_RD)) {
2559 /* write */
2560 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2561 cmd->ReadWriteData = msg[i].buf[j];
2562 }
2563
2564 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2565 /* The direction changes.
2566 */
2567 dir = msg[i].flags & I2C_M_RD;
2568 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2569 }
2570
2571 req->NumCmds++;
2572
2573 /*
2574 * Insert STOP if we are at the last byte of either last
2575 * message for the transaction or the client explicitly
2576 * requires a STOP at this particular message.
2577 */
2578 if ((j == msg[i].len - 1) &&
2579 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2580 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2581 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2582 }
2583 }
2584 }
2585 mutex_lock(&adev->pm.mutex);
2586 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2587 if (r)
2588 goto fail;
2589
2590 for (c = i = 0; i < num_msgs; i++) {
2591 if (!(msg[i].flags & I2C_M_RD)) {
2592 c += msg[i].len;
2593 continue;
2594 }
2595 for (j = 0; j < msg[i].len; j++, c++) {
2596 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2597
2598 msg[i].buf[j] = cmd->ReadWriteData;
2599 }
2600 }
2601 r = num_msgs;
2602 fail:
2603 mutex_unlock(&adev->pm.mutex);
2604 kfree(req);
2605 return r;
2606 }
2607
sienna_cichlid_i2c_func(struct i2c_adapter * adap)2608 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2609 {
2610 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2611 }
2612
2613
2614 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2615 .master_xfer = sienna_cichlid_i2c_xfer,
2616 .functionality = sienna_cichlid_i2c_func,
2617 };
2618
2619 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
2620 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2621 .max_read_len = MAX_SW_I2C_COMMANDS,
2622 .max_write_len = MAX_SW_I2C_COMMANDS,
2623 .max_comb_1st_msg_len = 2,
2624 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2625 };
2626
sienna_cichlid_i2c_control_init(struct smu_context * smu)2627 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
2628 {
2629 struct amdgpu_device *adev = smu->adev;
2630 int res, i;
2631
2632 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2633 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2634 struct i2c_adapter *control = &smu_i2c->adapter;
2635
2636 smu_i2c->adev = adev;
2637 smu_i2c->port = i;
2638 mutex_init(&smu_i2c->mutex);
2639 control->owner = THIS_MODULE;
2640 control->class = I2C_CLASS_HWMON;
2641 control->dev.parent = &adev->pdev->dev;
2642 control->algo = &sienna_cichlid_i2c_algo;
2643 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2644 control->quirks = &sienna_cichlid_i2c_control_quirks;
2645 i2c_set_adapdata(control, smu_i2c);
2646
2647 res = i2c_add_adapter(control);
2648 if (res) {
2649 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2650 goto Out_err;
2651 }
2652 }
2653 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2654 /* XXX ideally this would be something in a vbios data table */
2655 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2656 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2657
2658 return 0;
2659 Out_err:
2660 for ( ; i >= 0; i--) {
2661 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2662 struct i2c_adapter *control = &smu_i2c->adapter;
2663
2664 i2c_del_adapter(control);
2665 }
2666 return res;
2667 }
2668
sienna_cichlid_i2c_control_fini(struct smu_context * smu)2669 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
2670 {
2671 struct amdgpu_device *adev = smu->adev;
2672 int i;
2673
2674 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2675 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2676 struct i2c_adapter *control = &smu_i2c->adapter;
2677
2678 i2c_del_adapter(control);
2679 }
2680 adev->pm.ras_eeprom_i2c_bus = NULL;
2681 adev->pm.fru_eeprom_i2c_bus = NULL;
2682 }
2683
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)2684 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2685 void **table)
2686 {
2687 struct smu_table_context *smu_table = &smu->smu_table;
2688 struct gpu_metrics_v1_3 *gpu_metrics =
2689 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2690 SmuMetricsExternal_t metrics_external;
2691 SmuMetrics_t *metrics =
2692 &(metrics_external.SmuMetrics);
2693 SmuMetrics_V2_t *metrics_v2 =
2694 &(metrics_external.SmuMetrics_V2);
2695 SmuMetrics_V3_t *metrics_v3 =
2696 &(metrics_external.SmuMetrics_V3);
2697 struct amdgpu_device *adev = smu->adev;
2698 bool use_metrics_v2 = false;
2699 bool use_metrics_v3 = false;
2700 uint16_t average_gfx_activity;
2701 int ret = 0;
2702
2703 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
2704 case IP_VERSION(11, 0, 7):
2705 if (smu->smc_fw_version >= 0x3A4900)
2706 use_metrics_v3 = true;
2707 else if (smu->smc_fw_version >= 0x3A4300)
2708 use_metrics_v2 = true;
2709 break;
2710 case IP_VERSION(11, 0, 11):
2711 if (smu->smc_fw_version >= 0x412D00)
2712 use_metrics_v2 = true;
2713 break;
2714 case IP_VERSION(11, 0, 12):
2715 if (smu->smc_fw_version >= 0x3B2300)
2716 use_metrics_v2 = true;
2717 break;
2718 case IP_VERSION(11, 0, 13):
2719 if (smu->smc_fw_version >= 0x491100)
2720 use_metrics_v2 = true;
2721 break;
2722 default:
2723 break;
2724 }
2725
2726 ret = smu_cmn_get_metrics_table(smu,
2727 &metrics_external,
2728 true);
2729 if (ret)
2730 return ret;
2731
2732 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2733
2734 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
2735 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
2736 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
2737 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
2738 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
2739 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
2740 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
2741 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
2742 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
2743 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
2744 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
2745 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
2746
2747 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
2748 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
2749 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
2750 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
2751 gpu_metrics->average_mm_activity = use_metrics_v3 ?
2752 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
2753 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
2754
2755 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
2756 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
2757 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
2758 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
2759
2760 if (metrics->CurrGfxVoltageOffset)
2761 gpu_metrics->voltage_gfx =
2762 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
2763 if (metrics->CurrMemVidOffset)
2764 gpu_metrics->voltage_mem =
2765 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
2766 if (metrics->CurrSocVoltageOffset)
2767 gpu_metrics->voltage_soc =
2768 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
2769
2770 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
2771 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
2772 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2773 gpu_metrics->average_gfxclk_frequency =
2774 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
2775 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
2776 metrics->AverageGfxclkFrequencyPostDs;
2777 else
2778 gpu_metrics->average_gfxclk_frequency =
2779 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
2780 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
2781 metrics->AverageGfxclkFrequencyPreDs;
2782
2783 gpu_metrics->average_uclk_frequency =
2784 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
2785 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
2786 metrics->AverageUclkFrequencyPostDs;
2787 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
2788 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
2789 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
2790 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
2791 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
2792 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
2793 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
2794 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
2795
2796 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
2797 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
2798 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
2799 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
2800 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
2801 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
2802 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
2803 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
2804 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
2805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
2806 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
2807 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
2808 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
2809 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
2810
2811 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
2812 gpu_metrics->indep_throttle_status =
2813 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2814 sienna_cichlid_throttler_map);
2815
2816 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
2817 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
2818
2819 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2820 smu->smc_fw_version > 0x003A1E00) ||
2821 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) &&
2822 smu->smc_fw_version > 0x00410400)) {
2823 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
2824 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
2825 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
2826 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
2827 } else {
2828 gpu_metrics->pcie_link_width =
2829 smu_v11_0_get_current_pcie_link_width(smu);
2830 gpu_metrics->pcie_link_speed =
2831 smu_v11_0_get_current_pcie_link_speed(smu);
2832 }
2833
2834 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2835
2836 *table = (void *)gpu_metrics;
2837
2838 return sizeof(struct gpu_metrics_v1_3);
2839 }
2840
sienna_cichlid_check_ecc_table_support(struct smu_context * smu)2841 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
2842 {
2843 int ret = 0;
2844
2845 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
2846 ret = -EOPNOTSUPP;
2847
2848 return ret;
2849 }
2850
sienna_cichlid_get_ecc_info(struct smu_context * smu,void * table)2851 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
2852 void *table)
2853 {
2854 struct smu_table_context *smu_table = &smu->smu_table;
2855 EccInfoTable_t *ecc_table = NULL;
2856 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
2857 int i, ret = 0;
2858 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
2859
2860 ret = sienna_cichlid_check_ecc_table_support(smu);
2861 if (ret)
2862 return ret;
2863
2864 ret = smu_cmn_update_table(smu,
2865 SMU_TABLE_ECCINFO,
2866 0,
2867 smu_table->ecc_table,
2868 false);
2869 if (ret) {
2870 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
2871 return ret;
2872 }
2873
2874 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
2875
2876 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
2877 ecc_info_per_channel = &(eccinfo->ecc[i]);
2878 ecc_info_per_channel->ce_count_lo_chip =
2879 ecc_table->EccInfo[i].ce_count_lo_chip;
2880 ecc_info_per_channel->ce_count_hi_chip =
2881 ecc_table->EccInfo[i].ce_count_hi_chip;
2882 ecc_info_per_channel->mca_umc_status =
2883 ecc_table->EccInfo[i].mca_umc_status;
2884 ecc_info_per_channel->mca_umc_addr =
2885 ecc_table->EccInfo[i].mca_umc_addr;
2886 }
2887
2888 return ret;
2889 }
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)2890 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2891 {
2892 uint16_t *mgpu_fan_boost_limit_rpm;
2893
2894 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
2895 /*
2896 * Skip the MGpuFanBoost setting for those ASICs
2897 * which do not support it
2898 */
2899 if (*mgpu_fan_boost_limit_rpm == 0)
2900 return 0;
2901
2902 return smu_cmn_send_smc_msg_with_param(smu,
2903 SMU_MSG_SetMGpuFanBoostLimitRpm,
2904 0,
2905 NULL);
2906 }
2907
sienna_cichlid_gpo_control(struct smu_context * smu,bool enablement)2908 static int sienna_cichlid_gpo_control(struct smu_context *smu,
2909 bool enablement)
2910 {
2911 int ret = 0;
2912
2913
2914 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2915
2916 if (enablement) {
2917 if (smu->smc_fw_version < 0x003a2500) {
2918 ret = smu_cmn_send_smc_msg_with_param(smu,
2919 SMU_MSG_SetGpoFeaturePMask,
2920 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2921 NULL);
2922 } else {
2923 ret = smu_cmn_send_smc_msg_with_param(smu,
2924 SMU_MSG_DisallowGpo,
2925 0,
2926 NULL);
2927 }
2928 } else {
2929 if (smu->smc_fw_version < 0x003a2500) {
2930 ret = smu_cmn_send_smc_msg_with_param(smu,
2931 SMU_MSG_SetGpoFeaturePMask,
2932 0,
2933 NULL);
2934 } else {
2935 ret = smu_cmn_send_smc_msg_with_param(smu,
2936 SMU_MSG_DisallowGpo,
2937 1,
2938 NULL);
2939 }
2940 }
2941 }
2942
2943 return ret;
2944 }
2945
sienna_cichlid_notify_2nd_usb20_port(struct smu_context * smu)2946 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
2947 {
2948 /*
2949 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
2950 * onwards PMFWs.
2951 */
2952 if (smu->smc_fw_version < 0x003A2D00)
2953 return 0;
2954
2955 return smu_cmn_send_smc_msg_with_param(smu,
2956 SMU_MSG_Enable2ndUSB20Port,
2957 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
2958 1 : 0,
2959 NULL);
2960 }
2961
sienna_cichlid_system_features_control(struct smu_context * smu,bool en)2962 static int sienna_cichlid_system_features_control(struct smu_context *smu,
2963 bool en)
2964 {
2965 int ret = 0;
2966
2967 if (en) {
2968 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
2969 if (ret)
2970 return ret;
2971 }
2972
2973 return smu_v11_0_system_features_control(smu, en);
2974 }
2975
sienna_cichlid_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2976 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
2977 enum pp_mp1_state mp1_state)
2978 {
2979 int ret;
2980
2981 switch (mp1_state) {
2982 case PP_MP1_STATE_UNLOAD:
2983 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2984 break;
2985 default:
2986 /* Ignore others */
2987 ret = 0;
2988 }
2989
2990 return ret;
2991 }
2992
sienna_cichlid_stb_init(struct smu_context * smu)2993 static void sienna_cichlid_stb_init(struct smu_context *smu)
2994 {
2995 struct amdgpu_device *adev = smu->adev;
2996 uint32_t reg;
2997
2998 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
2999 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
3000
3001 /* STB is disabled */
3002 if (!smu->stb_context.enabled)
3003 return;
3004
3005 spin_lock_init(&smu->stb_context.lock);
3006
3007 /* STB buffer size in bytes as function of FIFO depth */
3008 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
3009 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
3010 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
3011
3012 dev_info(smu->adev->dev, "STB initialized to %d entries",
3013 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
3014
3015 }
3016
sienna_cichlid_get_default_config_table_settings(struct smu_context * smu,struct config_table_setting * table)3017 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
3018 struct config_table_setting *table)
3019 {
3020 struct amdgpu_device *adev = smu->adev;
3021
3022 if (!table)
3023 return -EINVAL;
3024
3025 table->gfxclk_average_tau = 10;
3026 table->socclk_average_tau = 10;
3027 table->fclk_average_tau = 10;
3028 table->uclk_average_tau = 10;
3029 table->gfx_activity_average_tau = 10;
3030 table->mem_activity_average_tau = 10;
3031 table->socket_power_average_tau = 100;
3032 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
3033 table->apu_socket_power_average_tau = 100;
3034
3035 return 0;
3036 }
3037
sienna_cichlid_set_config_table(struct smu_context * smu,struct config_table_setting * table)3038 static int sienna_cichlid_set_config_table(struct smu_context *smu,
3039 struct config_table_setting *table)
3040 {
3041 DriverSmuConfigExternal_t driver_smu_config_table;
3042
3043 if (!table)
3044 return -EINVAL;
3045
3046 memset(&driver_smu_config_table,
3047 0,
3048 sizeof(driver_smu_config_table));
3049 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
3050 table->gfxclk_average_tau;
3051 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
3052 table->fclk_average_tau;
3053 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
3054 table->uclk_average_tau;
3055 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
3056 table->gfx_activity_average_tau;
3057 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
3058 table->mem_activity_average_tau;
3059 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
3060 table->socket_power_average_tau;
3061
3062 return smu_cmn_update_table(smu,
3063 SMU_TABLE_DRIVER_SMU_CONFIG,
3064 0,
3065 (void *)&driver_smu_config_table,
3066 true);
3067 }
3068
sienna_cichlid_stb_get_data_direct(struct smu_context * smu,void * buf,uint32_t size)3069 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
3070 void *buf,
3071 uint32_t size)
3072 {
3073 uint32_t *p = buf;
3074 struct amdgpu_device *adev = smu->adev;
3075
3076 /* No need to disable interrupts for now as we don't lock it yet from ISR */
3077 spin_lock(&smu->stb_context.lock);
3078
3079 /*
3080 * Read the STB FIFO in units of 32bit since this is the accessor window
3081 * (register width) we have.
3082 */
3083 buf = ((char *) buf) + size;
3084 while ((void *)p < buf)
3085 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
3086
3087 spin_unlock(&smu->stb_context.lock);
3088
3089 return 0;
3090 }
3091
sienna_cichlid_is_mode2_reset_supported(struct smu_context * smu)3092 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
3093 {
3094 return true;
3095 }
3096
sienna_cichlid_mode2_reset(struct smu_context * smu)3097 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
3098 {
3099 int ret = 0, index;
3100 struct amdgpu_device *adev = smu->adev;
3101 int timeout = 100;
3102
3103 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
3104 SMU_MSG_DriverMode2Reset);
3105
3106 mutex_lock(&smu->message_lock);
3107
3108 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
3109 SMU_RESET_MODE_2);
3110
3111 ret = smu_cmn_wait_for_response(smu);
3112 while (ret != 0 && timeout) {
3113 ret = smu_cmn_wait_for_response(smu);
3114 /* Wait a bit more time for getting ACK */
3115 if (ret != 0) {
3116 --timeout;
3117 usleep_range(500, 1000);
3118 continue;
3119 } else {
3120 break;
3121 }
3122 }
3123
3124 if (!timeout) {
3125 dev_err(adev->dev,
3126 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
3127 SMU_RESET_MODE_2, ret);
3128 goto out;
3129 }
3130
3131 dev_info(smu->adev->dev, "restore config space...\n");
3132 /* Restore the config space saved during init */
3133 amdgpu_device_load_pci_state(adev->pdev);
3134 out:
3135 mutex_unlock(&smu->message_lock);
3136
3137 return ret;
3138 }
3139
3140 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3141 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3142 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3143 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3144 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3145 .i2c_init = sienna_cichlid_i2c_control_init,
3146 .i2c_fini = sienna_cichlid_i2c_control_fini,
3147 .print_clk_levels = sienna_cichlid_print_clk_levels,
3148 .force_clk_levels = sienna_cichlid_force_clk_levels,
3149 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3150 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3151 .display_config_changed = sienna_cichlid_display_config_changed,
3152 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3153 .is_dpm_running = sienna_cichlid_is_dpm_running,
3154 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3155 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
3156 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3157 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
3158 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3159 .read_sensor = sienna_cichlid_read_sensor,
3160 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
3161 .set_performance_level = smu_v11_0_set_performance_level,
3162 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3163 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3164 .get_power_limit = sienna_cichlid_get_power_limit,
3165 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
3166 .init_microcode = smu_v11_0_init_microcode,
3167 .load_microcode = smu_v11_0_load_microcode,
3168 .fini_microcode = smu_v11_0_fini_microcode,
3169 .init_smc_tables = sienna_cichlid_init_smc_tables,
3170 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3171 .init_power = smu_v11_0_init_power,
3172 .fini_power = smu_v11_0_fini_power,
3173 .check_fw_status = smu_v11_0_check_fw_status,
3174 .setup_pptable = sienna_cichlid_setup_pptable,
3175 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3176 .check_fw_version = smu_v11_0_check_fw_version,
3177 .write_pptable = smu_cmn_write_pptable,
3178 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3179 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3180 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3181 .system_features_control = sienna_cichlid_system_features_control,
3182 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3183 .send_smc_msg = smu_cmn_send_smc_msg,
3184 .init_display_count = NULL,
3185 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3186 .get_enabled_mask = smu_cmn_get_enabled_mask,
3187 .feature_is_enabled = smu_cmn_feature_is_enabled,
3188 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3189 .notify_display_change = NULL,
3190 .set_power_limit = smu_v11_0_set_power_limit,
3191 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3192 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3193 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3194 .set_min_dcef_deep_sleep = NULL,
3195 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3196 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3197 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3198 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3199 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3200 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3201 .gfx_off_control = smu_v11_0_gfx_off_control,
3202 .register_irq_handler = smu_v11_0_register_irq_handler,
3203 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3204 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3205 .get_bamaco_support = smu_v11_0_get_bamaco_support,
3206 .baco_enter = sienna_cichlid_baco_enter,
3207 .baco_exit = sienna_cichlid_baco_exit,
3208 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3209 .mode1_reset = smu_v11_0_mode1_reset,
3210 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
3211 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3212 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
3213 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
3214 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
3215 .run_btc = sienna_cichlid_run_btc,
3216 .set_power_source = smu_v11_0_set_power_source,
3217 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3218 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3219 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
3220 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
3221 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3222 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3223 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
3224 .interrupt_work = smu_v11_0_interrupt_work,
3225 .gpo_control = sienna_cichlid_gpo_control,
3226 .set_mp1_state = sienna_cichlid_set_mp1_state,
3227 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3228 .get_ecc_info = sienna_cichlid_get_ecc_info,
3229 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
3230 .set_config_table = sienna_cichlid_set_config_table,
3231 .get_unique_id = sienna_cichlid_get_unique_id,
3232 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
3233 .mode2_reset = sienna_cichlid_mode2_reset,
3234 };
3235
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)3236 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3237 {
3238 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
3239 smu->message_map = sienna_cichlid_message_map;
3240 smu->clock_map = sienna_cichlid_clk_map;
3241 smu->feature_map = sienna_cichlid_feature_mask_map;
3242 smu->table_map = sienna_cichlid_table_map;
3243 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3244 smu->workload_map = sienna_cichlid_workload_map;
3245 smu_v11_0_set_smu_mailbox_registers(smu);
3246 }
3247