1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dce110/dce110_hwseq.h"
6 #include "dcn10/dcn10_hwseq.h"
7 #include "dcn20/dcn20_hwseq.h"
8 #include "dcn21/dcn21_hwseq.h"
9 #include "dcn30/dcn30_hwseq.h"
10 #include "dcn31/dcn31_hwseq.h"
11 #include "dcn32/dcn32_hwseq.h"
12 #include "dcn401/dcn401_hwseq.h"
13 #include "dcn401_init.h"
14
15 static const struct hw_sequencer_funcs dcn401_funcs = {
16 .program_gamut_remap = dcn401_program_gamut_remap,
17 .init_hw = dcn401_init_hw,
18 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
19 .apply_ctx_for_surface = NULL,
20 .program_front_end_for_ctx = dcn401_program_front_end_for_ctx,
21 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
22 .post_unlock_program_front_end = dcn401_post_unlock_program_front_end,
23 .update_plane_addr = dcn20_update_plane_addr,
24 .update_dchub = dcn10_update_dchub,
25 .update_pending_status = dcn10_update_pending_status,
26 .program_output_csc = dcn20_program_output_csc,
27 .trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load,
28 .enable_accelerated_mode = dce110_enable_accelerated_mode,
29 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
30 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
31 .update_info_frame = dcn31_update_info_frame,
32 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
33 .enable_stream = dcn401_enable_stream,
34 .disable_stream = dce110_disable_stream,
35 .unblank_stream = dcn401_unblank_stream,
36 .blank_stream = dce110_blank_stream,
37 .enable_audio_stream = dce110_enable_audio_stream,
38 .disable_audio_stream = dce110_disable_audio_stream,
39 .disable_plane = dcn20_disable_plane,
40 .pipe_control_lock = dcn20_pipe_control_lock,
41 .interdependent_update_lock = dcn401_interdependent_update_lock,
42 .cursor_lock = dcn10_cursor_lock,
43 .prepare_bandwidth = dcn401_prepare_bandwidth,
44 .optimize_bandwidth = dcn401_optimize_bandwidth,
45 .update_bandwidth = dcn401_update_bandwidth,
46 .set_drr = dcn10_set_drr,
47 .get_position = dcn10_get_position,
48 .set_static_screen_control = dcn31_set_static_screen_control,
49 .setup_stereo = dcn10_setup_stereo,
50 .set_avmute = dcn30_set_avmute,
51 .log_hw_state = dcn10_log_hw_state,
52 .get_hw_state = dcn10_get_hw_state,
53 .clear_status_bits = dcn10_clear_status_bits,
54 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
55 .edp_backlight_control = dce110_edp_backlight_control,
56 .edp_power_control = dce110_edp_power_control,
57 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
58 .edp_wait_for_T12 = dce110_edp_wait_for_T12,
59 .set_cursor_position = dcn401_set_cursor_position,
60 .set_cursor_attribute = dcn10_set_cursor_attribute,
61 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
62 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
63 .set_clock = dcn10_set_clock,
64 .get_clock = dcn10_get_clock,
65 .program_triplebuffer = dcn20_program_triple_buffer,
66 .enable_writeback = dcn30_enable_writeback,
67 .disable_writeback = dcn30_disable_writeback,
68 .update_writeback = dcn30_update_writeback,
69 .dmdata_status_done = dcn20_dmdata_status_done,
70 .program_dmdata_engine = dcn30_program_dmdata_engine,
71 .set_dmdata_attributes = dcn20_set_dmdata_attributes,
72 .init_sys_ctx = dcn20_init_sys_ctx,
73 .init_vm_ctx = dcn20_init_vm_ctx,
74 .set_flip_control_gsl = dcn20_set_flip_control_gsl,
75 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
76 .calc_vupdate_position = dcn10_calc_vupdate_position,
77 .apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations,
78 .does_plane_fit_in_mall = NULL,
79 .set_backlight_level = dcn31_set_backlight_level,
80 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
81 .hardware_release = dcn401_hardware_release,
82 .set_pipe = dcn21_set_pipe,
83 .enable_lvds_link_output = dce110_enable_lvds_link_output,
84 .enable_tmds_link_output = dce110_enable_tmds_link_output,
85 .enable_dp_link_output = dce110_enable_dp_link_output,
86 .disable_link_output = dcn401_disable_link_output,
87 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
88 .get_dcc_en_bits = dcn10_get_dcc_en_bits,
89 .enable_phantom_streams = dcn32_enable_phantom_streams,
90 .disable_phantom_streams = dcn32_disable_phantom_streams,
91 .update_visual_confirm_color = dcn10_update_visual_confirm_color,
92 .update_phantom_vp_position = dcn32_update_phantom_vp_position,
93 .update_dsc_pg = dcn32_update_dsc_pg,
94 .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,
95 .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation,
96 .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,
97 .fams2_global_control_lock = dcn401_fams2_global_control_lock,
98 .fams2_update_config = dcn401_fams2_update_config,
99 .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast,
100 .program_outstanding_updates = dcn401_program_outstanding_updates,
101 .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
102 .detect_pipe_changes = dcn401_detect_pipe_changes,
103 .enable_plane = dcn20_enable_plane,
104 .update_dchubp_dpp = dcn20_update_dchubp_dpp,
105 .post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
106 };
107
108 static const struct hwseq_private_funcs dcn401_private_funcs = {
109 .init_pipes = dcn10_init_pipes,
110 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
111 .update_mpcc = dcn20_update_mpcc,
112 .set_input_transfer_func = dcn32_set_input_transfer_func,
113 .set_output_transfer_func = dcn401_set_output_transfer_func,
114 .power_down = dce110_power_down,
115 .enable_display_power_gating = dcn10_dummy_display_power_gating,
116 .blank_pixel_data = dcn20_blank_pixel_data,
117 .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap,
118 .enable_stream_timing = dcn401_enable_stream_timing,
119 .edp_backlight_control = dce110_edp_backlight_control,
120 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
121 .did_underflow_occur = dcn10_did_underflow_occur,
122 .init_blank = dcn32_init_blank,
123 .disable_vga = dcn20_disable_vga,
124 .bios_golden_init = dcn10_bios_golden_init,
125 .plane_atomic_disable = dcn20_plane_atomic_disable,
126 .plane_atomic_power_down = dcn10_plane_atomic_power_down,
127 .enable_power_gating_plane = dcn32_enable_power_gating_plane,
128 .hubp_pg_control = dcn32_hubp_pg_control,
129 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
130 .update_odm = dcn401_update_odm,
131 .dsc_pg_control = dcn32_dsc_pg_control,
132 .dsc_pg_status = dcn32_dsc_pg_status,
133 .set_hdr_multiplier = dcn10_set_hdr_multiplier,
134 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
135 .wait_for_blank_complete = dcn20_wait_for_blank_complete,
136 .dccg_init = dcn20_dccg_init,
137 .set_mcm_luts = dcn401_set_mcm_luts,
138 .program_mall_pipe_config = dcn32_program_mall_pipe_config,
139 .update_mall_sel = dcn32_update_mall_sel,
140 .calculate_dccg_k1_k2_values = NULL,
141 .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
142 .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe,
143 .populate_mcm_luts = NULL,
144 .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock,
145 };
146
dcn401_hw_sequencer_init_functions(struct dc * dc)147 void dcn401_hw_sequencer_init_functions(struct dc *dc)
148 {
149 dc->hwss = dcn401_funcs;
150 dc->hwseq->funcs = dcn401_private_funcs;
151 }
152