1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_HUBBUB_DCN35_H__ 28 #define __DC_HUBBUB_DCN35_H__ 29 30 #include "dcn32/dcn32_hubbub.h" 31 32 #define HUBBUB_REG_LIST_DCN35(id)\ 33 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 34 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 35 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 37 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 38 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 39 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 40 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 41 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 42 SR(DCHUBBUB_SOFT_RESET),\ 43 SR(DCHUBBUB_CRC_CTRL), \ 44 SR(DCN_VM_FB_LOCATION_BASE),\ 45 SR(DCN_VM_FB_LOCATION_TOP),\ 46 SR(DCN_VM_FB_OFFSET),\ 47 SR(DCN_VM_AGP_BOT),\ 48 SR(DCN_VM_AGP_TOP),\ 49 SR(DCN_VM_AGP_BASE),\ 50 HUBBUB_SR_WATERMARK_REG_LIST(), \ 51 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 52 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 53 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 54 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 55 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 56 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 57 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 58 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 59 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 60 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ 61 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ 62 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ 63 SR(DCHUBBUB_DET0_CTRL),\ 64 SR(DCHUBBUB_DET1_CTRL),\ 65 SR(DCHUBBUB_DET2_CTRL),\ 66 SR(DCHUBBUB_DET3_CTRL),\ 67 SR(DCHUBBUB_COMPBUF_CTRL),\ 68 SR(COMPBUF_RESERVED_SPACE),\ 69 SR(DCHUBBUB_DEBUG_CTRL_0),\ 70 SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ 71 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ 72 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ 73 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ 74 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ 75 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ 76 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ 77 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ 78 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ 79 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ 80 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ 81 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ 82 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ 83 SR(DCN_VM_FAULT_ADDR_MSB),\ 84 SR(DCN_VM_FAULT_ADDR_LSB),\ 85 SR(DCN_VM_FAULT_CNTL),\ 86 SR(DCN_VM_FAULT_STATUS),\ 87 SR(SDPIF_REQUEST_RATE_LIMIT),\ 88 SR(DCHUBBUB_CLOCK_CNTL),\ 89 SR(DCHUBBUB_SDPIF_CFG0),\ 90 SR(DCHUBBUB_SDPIF_CFG1),\ 91 SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ 92 SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ 93 SR(DCHVM_CTRL0),\ 94 SR(DCHVM_MEM_CTRL),\ 95 SR(DCHVM_CLK_CTRL),\ 96 SR(DCHVM_RIOMMU_CTRL0),\ 97 SR(DCHVM_RIOMMU_STAT0),\ 98 SR(DCHUBBUB_COMPBUF_CTRL),\ 99 SR(COMPBUF_RESERVED_SPACE),\ 100 SR(DCHUBBUB_DEBUG_CTRL_0),\ 101 SR(DCHUBBUB_CLOCK_CNTL),\ 102 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ 103 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ 104 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ 105 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ 106 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ 107 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ 108 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ 109 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ 110 SR(DCHUBBUB_ARB_QOS_FORCE) 111 112 113 #define HUBBUB_MASK_SH_LIST_DCN35(mask_sh)\ 114 HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ 115 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ 116 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ 117 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ 118 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ 119 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ 120 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ 121 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ 122 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ 123 HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ 124 HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ 125 HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ 126 HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ 127 HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ 128 HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ 129 HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ 130 HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ 131 HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ 132 HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ 133 HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ 134 HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ 135 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ 136 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ 137 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ 138 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ 139 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ 140 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ 141 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ 142 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ 143 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ 144 HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ 145 HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh) 146 147 void hubbub35_construct(struct dcn20_hubbub *hubbub2, 148 struct dc_context *ctx, 149 const struct dcn_hubbub_registers *hubbub_regs, 150 const struct dcn_hubbub_shift *hubbub_shift, 151 const struct dcn_hubbub_mask *hubbub_mask, 152 int det_size_kb, 153 int pixel_chunk_size_kb, 154 int config_return_buffer_size_kb); 155 #endif 156