1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3 #include "resource.h"
4 #include "dcn351_fpu.h"
5 #include "dcn31/dcn31_resource.h"
6 #include "dcn32/dcn32_resource.h"
7 #include "dcn35/dcn35_resource.h"
8 #include "dcn351/dcn351_resource.h"
9 #include "dml/dcn31/dcn31_fpu.h"
10 #include "dml/dcn35/dcn35_fpu.h"
11 #include "dml/dml_inline_defs.h"
12
13 #include "link.h"
14
15 #define DC_LOGGER_INIT(logger)
16
17 struct _vcs_dpi_ip_params_st dcn3_51_ip = {
18 .VBlankNomDefaultUS = 668,
19 .gpuvm_enable = 1,
20 .gpuvm_max_page_table_levels = 1,
21 .hostvm_enable = 1,
22 .hostvm_max_page_table_levels = 2,
23 .rob_buffer_size_kbytes = 64,
24 .det_buffer_size_kbytes = 1536,
25 .config_return_buffer_size_in_kbytes = 1792,
26 .compressed_buffer_segment_size_in_kbytes = 64,
27 .meta_fifo_size_in_kentries = 32,
28 .zero_size_buffer_entries = 512,
29 .compbuf_reserved_space_64b = 256,
30 .compbuf_reserved_space_zs = 64,
31 .dpp_output_buffer_pixels = 2560,/*not used*/
32 .opp_output_buffer_lines = 1,/*not used*/
33 .pixel_chunk_size_kbytes = 8,
34 //.alpha_pixel_chunk_size_kbytes = 4;/*new*/
35 //.min_pixel_chunk_size_bytes = 1024;/*new*/
36 .meta_chunk_size_kbytes = 2,
37 .min_meta_chunk_size_bytes = 256,
38 .writeback_chunk_size_kbytes = 8,
39 .ptoi_supported = false,
40 .num_dsc = 4,
41 .maximum_dsc_bits_per_component = 12,/*delta from 10*/
42 .dsc422_native_support = true,/*delta from false*/
43 .is_line_buffer_bpp_fixed = true,/*new*/
44 .line_buffer_fixed_bpp = 32,/*delta from 48*/
45 .line_buffer_size_bits = 986880,/*delta from 789504*/
46 .max_line_buffer_lines = 32,/*delta from 12*/
47 .writeback_interface_buffer_size_kbytes = 90,
48 .max_num_dpp = 4,
49 .max_num_otg = 4,
50 .max_num_hdmi_frl_outputs = 1,
51 .max_num_wb = 1,
52 /*.max_num_hdmi_frl_outputs = 1; new in dml2*/
53 /*.max_num_dp2p0_outputs = 2; new in dml2*/
54 /*.max_num_dp2p0_streams = 4; new in dml2*/
55 .max_dchub_pscl_bw_pix_per_clk = 4,
56 .max_pscl_lb_bw_pix_per_clk = 2,
57 .max_lb_vscl_bw_pix_per_clk = 4,
58 .max_vscl_hscl_bw_pix_per_clk = 4,
59 .max_hscl_ratio = 6,
60 .max_vscl_ratio = 6,
61 .max_hscl_taps = 8,
62 .max_vscl_taps = 8,
63 .dpte_buffer_size_in_pte_reqs_luma = 68,/*changed from 64,*/
64 .dpte_buffer_size_in_pte_reqs_chroma = 36,/*changed from 34*/
65 /*.dcc_meta_buffer_size_bytes = 6272; new to dml2*/
66 .dispclk_ramp_margin_percent = 1.11,/*delta from 1*/
67 /*.dppclk_delay_subtotal = 47;
68 .dppclk_delay_scl = 50;
69 .dppclk_delay_scl_lb_only = 16;
70 .dppclk_delay_cnvc_formatter = 28;
71 .dppclk_delay_cnvc_cursor = 6;
72 .dispclk_delay_subtotal = 125;*/ /*new to dml2*/
73 .max_inter_dcn_tile_repeaters = 8,
74 .cursor_buffer_size = 16,
75 .cursor_chunk_size = 2,
76 .writeback_line_buffer_buffer_size = 0,
77 .writeback_min_hscl_ratio = 1,
78 .writeback_min_vscl_ratio = 1,
79 .writeback_max_hscl_ratio = 1,
80 .writeback_max_vscl_ratio = 1,
81 .writeback_max_hscl_taps = 1,
82 .writeback_max_vscl_taps = 1,
83 .dppclk_delay_subtotal = 47, /* changed from 46,*/
84 .dppclk_delay_scl = 50,
85 .dppclk_delay_scl_lb_only = 16,
86 .dppclk_delay_cnvc_formatter = 28,/*changed from 27,*/
87 .dppclk_delay_cnvc_cursor = 6,
88 .dispclk_delay_subtotal = 125, /*changed from 119,*/
89 .dynamic_metadata_vm_enabled = false,
90 .odm_combine_4to1_supported = false,
91 .dcc_supported = true,
92 // .config_return_buffer_segment_size_in_kbytes = 64;/*required, hard coded in dml2_translate_ip_params*/
93
94 };
95
96 struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {
97 /*TODO: correct dispclk/dppclk voltage level determination*/
98 .clock_limits = {
99 {
100 .state = 0,
101 .dcfclk_mhz = 400.0,
102 .fabricclk_mhz = 400.0,
103 .socclk_mhz = 600.0,
104 .dram_speed_mts = 3200.0,
105 .dispclk_mhz = 600.0,
106 .dppclk_mhz = 600.0,
107 .phyclk_mhz = 600.0,
108 .phyclk_d18_mhz = 667.0,
109 .dscclk_mhz = 200.0,
110 .dtbclk_mhz = 600.0,
111 },
112 {
113 .state = 1,
114 .dcfclk_mhz = 600.0,
115 .fabricclk_mhz = 1000.0,
116 .socclk_mhz = 733.0,
117 .dram_speed_mts = 6400.0,
118 .dispclk_mhz = 800.0,
119 .dppclk_mhz = 800.0,
120 .phyclk_mhz = 810.0,
121 .phyclk_d18_mhz = 667.0,
122 .dscclk_mhz = 266.7,
123 .dtbclk_mhz = 600.0,
124 },
125 {
126 .state = 2,
127 .dcfclk_mhz = 738.0,
128 .fabricclk_mhz = 1200.0,
129 .socclk_mhz = 880.0,
130 .dram_speed_mts = 7500.0,
131 .dispclk_mhz = 800.0,
132 .dppclk_mhz = 800.0,
133 .phyclk_mhz = 810.0,
134 .phyclk_d18_mhz = 667.0,
135 .dscclk_mhz = 266.7,
136 .dtbclk_mhz = 600.0,
137 },
138 {
139 .state = 3,
140 .dcfclk_mhz = 800.0,
141 .fabricclk_mhz = 1400.0,
142 .socclk_mhz = 978.0,
143 .dram_speed_mts = 7500.0,
144 .dispclk_mhz = 960.0,
145 .dppclk_mhz = 960.0,
146 .phyclk_mhz = 810.0,
147 .phyclk_d18_mhz = 667.0,
148 .dscclk_mhz = 320.0,
149 .dtbclk_mhz = 600.0,
150 },
151 {
152 .state = 4,
153 .dcfclk_mhz = 873.0,
154 .fabricclk_mhz = 1600.0,
155 .socclk_mhz = 1100.0,
156 .dram_speed_mts = 8533.0,
157 .dispclk_mhz = 1066.7,
158 .dppclk_mhz = 1066.7,
159 .phyclk_mhz = 810.0,
160 .phyclk_d18_mhz = 667.0,
161 .dscclk_mhz = 355.6,
162 .dtbclk_mhz = 600.0,
163 },
164 {
165 .state = 5,
166 .dcfclk_mhz = 960.0,
167 .fabricclk_mhz = 1700.0,
168 .socclk_mhz = 1257.0,
169 .dram_speed_mts = 8533.0,
170 .dispclk_mhz = 1200.0,
171 .dppclk_mhz = 1200.0,
172 .phyclk_mhz = 810.0,
173 .phyclk_d18_mhz = 667.0,
174 .dscclk_mhz = 400.0,
175 .dtbclk_mhz = 600.0,
176 },
177 {
178 .state = 6,
179 .dcfclk_mhz = 1067.0,
180 .fabricclk_mhz = 1850.0,
181 .socclk_mhz = 1257.0,
182 .dram_speed_mts = 8533.0,
183 .dispclk_mhz = 1371.4,
184 .dppclk_mhz = 1371.4,
185 .phyclk_mhz = 810.0,
186 .phyclk_d18_mhz = 667.0,
187 .dscclk_mhz = 457.1,
188 .dtbclk_mhz = 600.0,
189 },
190 {
191 .state = 7,
192 .dcfclk_mhz = 1200.0,
193 .fabricclk_mhz = 2000.0,
194 .socclk_mhz = 1467.0,
195 .dram_speed_mts = 8533.0,
196 .dispclk_mhz = 1600.0,
197 .dppclk_mhz = 1600.0,
198 .phyclk_mhz = 810.0,
199 .phyclk_d18_mhz = 667.0,
200 .dscclk_mhz = 533.3,
201 .dtbclk_mhz = 600.0,
202 },
203 },
204 .num_states = 8,
205 .sr_exit_time_us = 28.0,
206 .sr_enter_plus_exit_time_us = 30.0,
207 .sr_exit_z8_time_us = 263.0,
208 .sr_enter_plus_exit_z8_time_us = 363.0,
209 .fclk_change_latency_us = 24.0,
210 .usr_retraining_latency_us = 2,
211 .writeback_latency_us = 12.0,
212
213 .dram_channel_width_bytes = 4,/*not exist in dml2*/
214 .round_trip_ping_latency_dcfclk_cycles = 106,/*not exist in dml2*/
215 .urgent_latency_pixel_data_only_us = 4.0,
216 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
217 .urgent_latency_vm_data_only_us = 4.0,
218 .dram_clock_change_latency_us = 34,
219 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
220 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
221 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
222
223 .pct_ideal_sdp_bw_after_urgent = 80.0,
224 .pct_ideal_fabric_bw_after_urgent = 80.0, /*new to dml2*/
225 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
226 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
227 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
228 .max_avg_sdp_bw_use_normal_percent = 60.0,
229 .max_avg_dram_bw_use_normal_percent = 60.0,
230 .fabric_datapath_to_dcn_data_return_bytes = 32,
231 .return_bus_width_bytes = 64,
232 .downspread_percent = 0.38,
233 .dcn_downspread_percent = 0.5,
234 .gpuvm_min_page_size_bytes = 4096,
235 .hostvm_min_page_size_bytes = 4096,
236 .do_urgent_latency_adjustment = 0,
237 .urgent_latency_adjustment_fabric_clock_component_us = 0,
238 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
239 .num_chans = 4,
240 .dispclk_dppclk_vco_speed_mhz = 2400.0,
241 };
242
243 /*
244 * dcn351_update_bw_bounding_box
245 *
246 * This would override some dcn3_51 ip_or_soc initial parameters hardcoded from
247 * spreadsheet with actual values as per dGPU SKU:
248 * - with passed few options from dc->config
249 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
250 * need to get it from PM FW)
251 * - with passed latency values (passed in ns units) in dc-> bb override for
252 * debugging purposes
253 * - with passed latencies from VBIOS (in 100_ns units) if available for
254 * certain dGPU SKU
255 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
256 * of the same ASIC)
257 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
258 * FW for different clocks (which might differ for certain dGPU SKU of the
259 * same ASIC)
260 */
dcn351_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)261 void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
262 struct clk_bw_params *bw_params)
263 {
264 unsigned int i, closest_clk_lvl;
265 int j;
266 struct clk_limit_table *clk_table = &bw_params->clk_table;
267 struct _vcs_dpi_voltage_scaling_st *clock_limits =
268 dc->scratch.update_bw_bounding_box.clock_limits;
269 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
270
271 dc_assert_fp_enabled();
272
273 dcn3_51_ip.max_num_otg =
274 dc->res_pool->res_cap->num_timing_generator;
275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count;
276 dcn3_51_soc.num_chans = bw_params->num_channels;
277
278 ASSERT(clk_table->num_entries);
279
280 /* Prepass to find max clocks independent of voltage level. */
281 for (i = 0; i < clk_table->num_entries; ++i) {
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
286 }
287
288 for (i = 0; i < clk_table->num_entries; i++) {
289 /* loop backwards*/
290 for (closest_clk_lvl = 0, j = dcn3_51_soc.num_states - 1;
291 j >= 0; j--) {
292 if (dcn3_51_soc.clock_limits[j].dcfclk_mhz <=
293 clk_table->entries[i].dcfclk_mhz) {
294 closest_clk_lvl = j;
295 break;
296 }
297 }
298 if (clk_table->num_entries == 1) {
299 /*smu gives one DPM level, let's take the highest one*/
300 closest_clk_lvl = dcn3_51_soc.num_states - 1;
301 }
302
303 clock_limits[i].state = i;
304
305 /* Clocks dependent on voltage level. */
306 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
307 if (clk_table->num_entries == 1 &&
308 clock_limits[i].dcfclk_mhz <
309 dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
310 /*SMU fix not released yet*/
311 clock_limits[i].dcfclk_mhz =
312 dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
313 }
314
315 clock_limits[i].fabricclk_mhz =
316 clk_table->entries[i].fclk_mhz;
317 clock_limits[i].socclk_mhz =
318 clk_table->entries[i].socclk_mhz;
319
320 if (clk_table->entries[i].memclk_mhz &&
321 clk_table->entries[i].wck_ratio)
322 clock_limits[i].dram_speed_mts =
323 clk_table->entries[i].memclk_mhz * 2 *
324 clk_table->entries[i].wck_ratio;
325
326 /* Clocks independent of voltage level. */
327 clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
328 max_dispclk_mhz :
329 dcn3_51_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
330
331 clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
332 max_dppclk_mhz :
333 dcn3_51_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
334
335 clock_limits[i].dram_bw_per_chan_gbps =
336 dcn3_51_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
337 clock_limits[i].dscclk_mhz =
338 dcn3_51_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
339 clock_limits[i].dtbclk_mhz =
340 dcn3_51_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
341 clock_limits[i].phyclk_d18_mhz =
342 dcn3_51_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
343 clock_limits[i].phyclk_mhz =
344 dcn3_51_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
345 }
346
347 memcpy(dcn3_51_soc.clock_limits, clock_limits,
348 sizeof(dcn3_51_soc.clock_limits));
349
350 if (clk_table->num_entries)
351 dcn3_51_soc.num_states = clk_table->num_entries;
352
353 if (max_dispclk_mhz) {
354 dcn3_51_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
355 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
356 }
357 if ((int)(dcn3_51_soc.dram_clock_change_latency_us * 1000)
358 != dc->debug.dram_clock_change_latency_ns
359 && dc->debug.dram_clock_change_latency_ns) {
360 dcn3_51_soc.dram_clock_change_latency_us =
361 dc->debug.dram_clock_change_latency_ns / 1000.0;
362 }
363
364 if (dc->bb_overrides.dram_clock_change_latency_ns > 0)
365 dcn3_51_soc.dram_clock_change_latency_us =
366 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
367
368 if (dc->bb_overrides.sr_exit_time_ns > 0)
369 dcn3_51_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
370
371 if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)
372 dcn3_51_soc.sr_enter_plus_exit_time_us =
373 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
374
375 if (dc->bb_overrides.sr_exit_z8_time_ns > 0)
376 dcn3_51_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;
377
378 if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)
379 dcn3_51_soc.sr_enter_plus_exit_z8_time_us =
380 dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
381
382 /*temp till dml2 fully work without dml1*/
383 dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip,
384 DML_PROJECT_DCN31);
385
386 /*copy to dml2, before dml2_create*/
387 if (clk_table->num_entries > 2) {
388
389 for (i = 0; i < clk_table->num_entries; i++) {
390 dc->dml2_options.bbox_overrides.clks_table.num_states =
391 clk_table->num_entries;
392 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
393 clock_limits[i].dcfclk_mhz;
394 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
395 clock_limits[i].fabricclk_mhz;
396 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
397 clock_limits[i].dispclk_mhz;
398 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
399 clock_limits[i].dppclk_mhz;
400 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
401 clock_limits[i].socclk_mhz;
402 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
403 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
404 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
405 clock_limits[i].dtbclk_mhz;
406 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
407 clk_table->num_entries;
408 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
409 clk_table->num_entries;
410 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
411 clk_table->num_entries;
412 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
413 clk_table->num_entries;
414 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
415 clk_table->num_entries;
416 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
417 clk_table->num_entries;
418 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
419 clk_table->num_entries;
420 }
421 }
422
423 /* Update latency values */
424 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_latency_us;
425
426 dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_51_soc.sr_exit_time_us;
427 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_51_soc.sr_enter_plus_exit_time_us;
428
429 dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_51_soc.sr_exit_z8_time_us;
430 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_51_soc.sr_enter_plus_exit_z8_time_us;
431 }
432
is_dual_plane(enum surface_pixel_format format)433 static bool is_dual_plane(enum surface_pixel_format format)
434 {
435 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
436 format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
437 }
438
439 /*
440 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing
441 *
442 * @param: num_us: number of microseconds
443 * @return: number of vertical lines. If exact number of vertical lines is not found then
444 * it will round up to next number of lines to guarantee num_us
445 */
micro_sec_to_vert_lines(unsigned int num_us,struct dc_crtc_timing * timing)446 static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
447 {
448 unsigned int num_lines = 0;
449 unsigned int lines_time_in_ns = 1000.0 *
450 (((float)timing->h_total * 1000.0) /
451 ((float)timing->pix_clk_100hz / 10.0));
452
453 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
454
455 return num_lines;
456 }
457
get_vertical_back_porch(struct dc_crtc_timing * timing)458 static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
459 {
460 unsigned int v_active = 0, v_blank = 0, v_back_porch = 0;
461
462 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;
463 v_blank = timing->v_total - v_active;
464 v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;
465
466 return v_back_porch;
467 }
468
dcn351_populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)469 int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,
470 struct dc_state *context,
471 display_e2e_pipe_params_st *pipes,
472 bool fast_validate)
473 {
474 int i, pipe_cnt;
475 struct resource_context *res_ctx = &context->res_ctx;
476 struct pipe_ctx *pipe = 0;
477 bool upscaled = false;
478 const unsigned int max_allowed_vblank_nom = 1023;
479
480 dcn31_populate_dml_pipes_from_context(dc, context, pipes,
481 fast_validate);
482
483 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
484 struct dc_crtc_timing *timing;
485 unsigned int num_lines = 0;
486 unsigned int v_back_porch = 0;
487
488 if (!res_ctx->pipe_ctx[i].stream)
489 continue;
490
491 pipe = &res_ctx->pipe_ctx[i];
492 timing = &pipe->stream->timing;
493
494 num_lines = micro_sec_to_vert_lines(dcn3_51_ip.VBlankNomDefaultUS, timing);
495 v_back_porch = get_vertical_back_porch(timing);
496
497 if (pipe->stream->adjust.v_total_max ==
498 pipe->stream->adjust.v_total_min &&
499 pipe->stream->adjust.v_total_min > timing->v_total) {
500 pipes[pipe_cnt].pipe.dest.vtotal =
501 pipe->stream->adjust.v_total_min;
502 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
503 pipes[pipe_cnt].pipe.dest.vactive;
504 }
505
506 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
507 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);
508 // vblank_nom should not smaller than (VSync (timing->v_sync_width + v_back_porch) + 2)
509 // + 2 is because
510 // 1 -> VStartup_start should be 1 line before VSync
511 // 1 -> always reserve 1 line between start of vblank to vstartup signal
512 pipes[pipe_cnt].pipe.dest.vblank_nom =
513 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);
514 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);
515
516 if (pipe->plane_state &&
517 (pipe->plane_state->src_rect.height <
518 pipe->plane_state->dst_rect.height ||
519 pipe->plane_state->src_rect.width <
520 pipe->plane_state->dst_rect.width))
521 upscaled = true;
522
523 /*
524 * Immediate flip can be set dynamically after enabling the
525 * plane. We need to require support for immediate flip or
526 * underflow can be intermittently experienced depending on peak
527 * b/w requirements.
528 */
529 pipes[pipe_cnt].pipe.src.immediate_flip = true;
530
531 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
532
533 DC_FP_START();
534 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
535 DC_FP_END();
536
537 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
538 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
539 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
540 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256;
541
542 if (pipes[pipe_cnt].dout.dsc_enable) {
543 switch (timing->display_color_depth) {
544 case COLOR_DEPTH_888:
545 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
546 break;
547 case COLOR_DEPTH_101010:
548 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
549 break;
550 case COLOR_DEPTH_121212:
551 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
552 break;
553 default:
554 ASSERT(0);
555 break;
556 }
557 }
558
559 pipe_cnt++;
560 }
561
562 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/
563 dc->config.enable_4to1MPC = false;
564
565 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
566 if (is_dual_plane(pipe->plane_state->format)
567 && pipe->plane_state->src_rect.width <= 1920 &&
568 pipe->plane_state->src_rect.height <= 1080) {
569 dc->config.enable_4to1MPC = true;
570 } else if (!is_dual_plane(pipe->plane_state->format) &&
571 pipe->plane_state->src_rect.width <= 5120) {
572 /*
573 * Limit to 5k max to avoid forced pipe split when there
574 * is not enough detile for swath
575 */
576 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
577 pipes[0].pipe.src.unbounded_req_mode = true;
578 }
579 } else if (context->stream_count >=
580 dc->debug.crb_alloc_policy_min_disp_count &&
581 dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
582 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
583 dc->debug.crb_alloc_policy * 64;
584 } else if (context->stream_count >= 3 && upscaled) {
585 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
586 }
587
588 for (i = 0; i < dc->res_pool->pipe_count; i++) {
589 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
590
591 if (!pipe->stream)
592 continue;
593
594 if (pipe->stream->signal == SIGNAL_TYPE_EDP &&
595 dc->debug.seamless_boot_odm_combine &&
596 pipe->stream->apply_seamless_boot_optimization) {
597
598 if (pipe->stream->apply_boot_odm_mode ==
599 dm_odm_combine_policy_2to1) {
600 context->bw_ctx.dml.vba.ODMCombinePolicy =
601 dm_odm_combine_policy_2to1;
602 break;
603 }
604 }
605 }
606
607 return pipe_cnt;
608 }
609
dcn351_decide_zstate_support(struct dc * dc,struct dc_state * context)610 void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)
611 {
612 enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
613 unsigned int i, plane_count = 0;
614
615 for (i = 0; i < dc->res_pool->pipe_count; i++) {
616 if (context->res_ctx.pipe_ctx[i].plane_state)
617 plane_count++;
618 }
619
620 /*dcn351 does not support z9/z10*/
621 if (context->stream_count == 0 || plane_count == 0) {
622 support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
623 } else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
624 struct dc_link *link = context->streams[0]->sink->link;
625 bool is_pwrseq0 = link && link->link_index == 0;
626 bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
627 link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
628 bool is_replay = link && link->replay_settings.replay_feature_enabled;
629 int minmum_z8_residency =
630 dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
631 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
632
633 /*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/
634 if (is_pwrseq0 && (is_psr || is_replay))
635 support = allow_z8 ? allow_z8 : DCN_ZSTATE_SUPPORT_DISALLOW;
636 }
637 context->bw_ctx.bw.dcn.clk.zstate_support = support;
638 }
639