1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "dcn10_stream_encoder.h"
29 #include "reg_helper.h"
30 #include "hw_shared.h"
31 #include "link.h"
32 #include "dpcd_defs.h"
33 #include "dcn30/dcn30_afmt.h"
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define DP_BLANK_MAX_RETRY 20
47 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
48
49
50 enum {
51 DP_MST_UPDATE_MAX_RETRY = 50
52 };
53
54 #define CTX \
55 enc1->base.ctx
56
enc1_update_generic_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)57 void enc1_update_generic_info_packet(
58 struct dcn10_stream_encoder *enc1,
59 uint32_t packet_index,
60 const struct dc_info_packet *info_packet)
61 {
62 /* TODOFPGA Figure out a proper number for max_retries polling for lock
63 * use 50 for now.
64 */
65 uint32_t max_retries = 50;
66
67 /*we need turn on clock before programming AFMT block*/
68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
69
70 if (packet_index >= 8)
71 ASSERT(0);
72
73 /* poll dig_update_lock is not locked -> asic internal signal
74 * assume otg master lock will unlock it
75 */
76 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
77 0, 10, max_retries);*/
78
79 /* check if HW reading GSP memory */
80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
81 0, 10, max_retries);
82
83 /* HW does is not reading GSP memory not reading too long ->
84 * something wrong. clear GPS memory access and notify?
85 * hw SW is writing to GSP memory
86 */
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
88
89 /* choose which generic packet to use */
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
91 AFMT_GENERIC_INDEX, packet_index);
92
93 /* write generic packet header
94 * (4th byte is for GENERIC0 only)
95 */
96 REG_SET_4(AFMT_GENERIC_HDR, 0,
97 AFMT_GENERIC_HB0, info_packet->hb0,
98 AFMT_GENERIC_HB1, info_packet->hb1,
99 AFMT_GENERIC_HB2, info_packet->hb2,
100 AFMT_GENERIC_HB3, info_packet->hb3);
101
102 /* write generic packet contents
103 * (we never use last 4 bytes)
104 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
105 */
106 {
107 const uint32_t *content =
108 (const uint32_t *) &info_packet->sb[0];
109
110 REG_WRITE(AFMT_GENERIC_0, *content++);
111 REG_WRITE(AFMT_GENERIC_1, *content++);
112 REG_WRITE(AFMT_GENERIC_2, *content++);
113 REG_WRITE(AFMT_GENERIC_3, *content++);
114 REG_WRITE(AFMT_GENERIC_4, *content++);
115 REG_WRITE(AFMT_GENERIC_5, *content++);
116 REG_WRITE(AFMT_GENERIC_6, *content++);
117 REG_WRITE(AFMT_GENERIC_7, *content);
118 }
119
120 switch (packet_index) {
121 case 0:
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
123 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
124 break;
125 case 1:
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
128 break;
129 case 2:
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
132 break;
133 case 3:
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
136 break;
137 case 4:
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
140 break;
141 case 5:
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
144 break;
145 case 6:
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
148 break;
149 case 7:
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
152 break;
153 default:
154 break;
155 }
156 }
157
enc1_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)158 static void enc1_update_hdmi_info_packet(
159 struct dcn10_stream_encoder *enc1,
160 uint32_t packet_index,
161 const struct dc_info_packet *info_packet)
162 {
163 uint32_t cont, send, line;
164
165 if (info_packet->valid) {
166 enc1_update_generic_info_packet(
167 enc1,
168 packet_index,
169 info_packet);
170
171 /* enable transmission of packet(s) -
172 * packet transmission begins on the next frame
173 */
174 cont = 1;
175 /* send packet(s) every frame */
176 send = 1;
177 /* select line number to send packets on */
178 line = 2;
179 } else {
180 cont = 0;
181 send = 0;
182 line = 0;
183 }
184
185 /* choose which generic packet control to use */
186 switch (packet_index) {
187 case 0:
188 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
189 HDMI_GENERIC0_CONT, cont,
190 HDMI_GENERIC0_SEND, send,
191 HDMI_GENERIC0_LINE, line);
192 break;
193 case 1:
194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
195 HDMI_GENERIC1_CONT, cont,
196 HDMI_GENERIC1_SEND, send,
197 HDMI_GENERIC1_LINE, line);
198 break;
199 case 2:
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
201 HDMI_GENERIC0_CONT, cont,
202 HDMI_GENERIC0_SEND, send,
203 HDMI_GENERIC0_LINE, line);
204 break;
205 case 3:
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
207 HDMI_GENERIC1_CONT, cont,
208 HDMI_GENERIC1_SEND, send,
209 HDMI_GENERIC1_LINE, line);
210 break;
211 case 4:
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
213 HDMI_GENERIC0_CONT, cont,
214 HDMI_GENERIC0_SEND, send,
215 HDMI_GENERIC0_LINE, line);
216 break;
217 case 5:
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
219 HDMI_GENERIC1_CONT, cont,
220 HDMI_GENERIC1_SEND, send,
221 HDMI_GENERIC1_LINE, line);
222 break;
223 case 6:
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
225 HDMI_GENERIC0_CONT, cont,
226 HDMI_GENERIC0_SEND, send,
227 HDMI_GENERIC0_LINE, line);
228 break;
229 case 7:
230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
231 HDMI_GENERIC1_CONT, cont,
232 HDMI_GENERIC1_SEND, send,
233 HDMI_GENERIC1_LINE, line);
234 break;
235 default:
236 /* invalid HW packet index */
237 DC_LOG_WARNING(
238 "Invalid HW packet index: %s()\n",
239 __func__);
240 return;
241 }
242 }
243
244 /* setup stream encoder in dp mode */
enc1_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space,bool use_vsc_sdp_for_colorimetry,uint32_t enable_sdp_splitting)245 void enc1_stream_encoder_dp_set_stream_attribute(
246 struct stream_encoder *enc,
247 struct dc_crtc_timing *crtc_timing,
248 enum dc_color_space output_color_space,
249 bool use_vsc_sdp_for_colorimetry,
250 uint32_t enable_sdp_splitting)
251 {
252 uint32_t h_active_start;
253 uint32_t v_active_start;
254 uint32_t misc0 = 0;
255 uint32_t misc1 = 0;
256 uint32_t h_blank;
257 uint32_t h_back_porch;
258 uint8_t colorimetry_bpc;
259 uint8_t dp_pixel_encoding = 0;
260 uint8_t dp_component_depth = 0;
261
262 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
263 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
264
265 if (hw_crtc_timing.flags.INTERLACE) {
266 /*the input timing is in VESA spec format with Interlace flag =1*/
267 hw_crtc_timing.v_total /= 2;
268 hw_crtc_timing.v_border_top /= 2;
269 hw_crtc_timing.v_addressable /= 2;
270 hw_crtc_timing.v_border_bottom /= 2;
271 hw_crtc_timing.v_front_porch /= 2;
272 hw_crtc_timing.v_sync_width /= 2;
273 }
274
275
276 /* set pixel encoding */
277 switch (hw_crtc_timing.pixel_encoding) {
278 case PIXEL_ENCODING_YCBCR422:
279 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
280 break;
281 case PIXEL_ENCODING_YCBCR444:
282 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
283
284 if (hw_crtc_timing.flags.Y_ONLY)
285 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
286 /* HW testing only, no use case yet.
287 * Color depth of Y-only could be
288 * 8, 10, 12, 16 bits
289 */
290 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
291
292 /* Note: DP_MSA_MISC1 bit 7 is the indicator
293 * of Y-only mode.
294 * This bit is set in HW if register
295 * DP_PIXEL_ENCODING is programmed to 0x4
296 */
297 break;
298 case PIXEL_ENCODING_YCBCR420:
299 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
300 break;
301 default:
302 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
303 break;
304 }
305
306 misc1 = REG_READ(DP_MSA_MISC);
307 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
308 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
309 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
310 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
311 */
312 if (use_vsc_sdp_for_colorimetry)
313 misc1 = misc1 | 0x40;
314 else
315 misc1 = misc1 & ~0x40;
316
317 /* set color depth */
318 switch (hw_crtc_timing.display_color_depth) {
319 case COLOR_DEPTH_666:
320 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
321 break;
322 case COLOR_DEPTH_888:
323 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
324 break;
325 case COLOR_DEPTH_101010:
326 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
327 break;
328 case COLOR_DEPTH_121212:
329 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
330 break;
331 case COLOR_DEPTH_161616:
332 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
333 break;
334 default:
335 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
336 break;
337 }
338
339 /* Set DP pixel encoding and component depth */
340 REG_UPDATE_2(DP_PIXEL_FORMAT,
341 DP_PIXEL_ENCODING, dp_pixel_encoding,
342 DP_COMPONENT_DEPTH, dp_component_depth);
343
344 /* set dynamic range and YCbCr range */
345
346 switch (hw_crtc_timing.display_color_depth) {
347 case COLOR_DEPTH_666:
348 colorimetry_bpc = 0;
349 break;
350 case COLOR_DEPTH_888:
351 colorimetry_bpc = 1;
352 break;
353 case COLOR_DEPTH_101010:
354 colorimetry_bpc = 2;
355 break;
356 case COLOR_DEPTH_121212:
357 colorimetry_bpc = 3;
358 break;
359 default:
360 colorimetry_bpc = 0;
361 break;
362 }
363
364 misc0 = colorimetry_bpc << 5;
365
366 switch (output_color_space) {
367 case COLOR_SPACE_SRGB:
368 misc1 = misc1 & ~0x80; /* bit7 = 0*/
369 break;
370 case COLOR_SPACE_SRGB_LIMITED:
371 misc0 = misc0 | 0x8; /* bit3=1 */
372 misc1 = misc1 & ~0x80; /* bit7 = 0*/
373 break;
374 case COLOR_SPACE_YCBCR601:
375 case COLOR_SPACE_YCBCR601_LIMITED:
376 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
377 misc1 = misc1 & ~0x80; /* bit7 = 0*/
378 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
379 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
380 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
381 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
382 break;
383 case COLOR_SPACE_YCBCR709:
384 case COLOR_SPACE_YCBCR709_LIMITED:
385 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
386 misc1 = misc1 & ~0x80; /* bit7 = 0*/
387 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
388 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
389 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
390 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
391 break;
392 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
393 case COLOR_SPACE_2020_RGB_FULLRANGE:
394 case COLOR_SPACE_2020_YCBCR:
395 case COLOR_SPACE_XR_RGB:
396 case COLOR_SPACE_MSREF_SCRGB:
397 case COLOR_SPACE_ADOBERGB:
398 case COLOR_SPACE_DCIP3:
399 case COLOR_SPACE_XV_YCC_709:
400 case COLOR_SPACE_XV_YCC_601:
401 case COLOR_SPACE_DISPLAYNATIVE:
402 case COLOR_SPACE_DOLBYVISION:
403 case COLOR_SPACE_APPCTRL:
404 case COLOR_SPACE_CUSTOMPOINTS:
405 case COLOR_SPACE_UNKNOWN:
406 case COLOR_SPACE_YCBCR709_BLACK:
407 /* do nothing */
408 break;
409 }
410
411 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
412 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
413
414 /* dcn new register
415 * dc_crtc_timing is vesa dmt struct. data from edid
416 */
417 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
418 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
419 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
420
421 /* calculate from vesa timing parameters
422 * h_active_start related to leading edge of sync
423 */
424
425 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
426 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
427
428 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
429 hw_crtc_timing.h_sync_width;
430
431 /* start at beginning of left border */
432 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
433
434
435 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
436 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
437 hw_crtc_timing.v_front_porch;
438
439
440 /* start at beginning of left border */
441 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
442 DP_MSA_HSTART, h_active_start,
443 DP_MSA_VSTART, v_active_start);
444
445 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
446 DP_MSA_HSYNCWIDTH,
447 hw_crtc_timing.h_sync_width,
448 DP_MSA_HSYNCPOLARITY,
449 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
450 DP_MSA_VSYNCWIDTH,
451 hw_crtc_timing.v_sync_width,
452 DP_MSA_VSYNCPOLARITY,
453 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
454
455 /* HWDITH include border or overscan */
456 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
457 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
458 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
459 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
460 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
461 }
462
enc1_stream_encoder_set_stream_attribute_helper(struct dcn10_stream_encoder * enc1,struct dc_crtc_timing * crtc_timing)463 void enc1_stream_encoder_set_stream_attribute_helper(
464 struct dcn10_stream_encoder *enc1,
465 struct dc_crtc_timing *crtc_timing)
466 {
467 switch (crtc_timing->pixel_encoding) {
468 case PIXEL_ENCODING_YCBCR422:
469 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
470 break;
471 default:
472 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
473 break;
474 }
475 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
476 }
477
478 /* setup stream encoder in hdmi mode */
enc1_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)479 void enc1_stream_encoder_hdmi_set_stream_attribute(
480 struct stream_encoder *enc,
481 struct dc_crtc_timing *crtc_timing,
482 int actual_pix_clk_khz,
483 bool enable_audio)
484 {
485 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
486 struct bp_encoder_control cntl = {0};
487
488 cntl.action = ENCODER_CONTROL_SETUP;
489 cntl.engine_id = enc1->base.id;
490 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
491 cntl.enable_dp_audio = enable_audio;
492 cntl.pixel_clock = actual_pix_clk_khz;
493 cntl.lanes_number = LANE_COUNT_FOUR;
494
495 if (enc1->base.bp->funcs->encoder_control(
496 enc1->base.bp, &cntl) != BP_RESULT_OK)
497 return;
498
499 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
500
501 /* setup HDMI engine */
502 REG_UPDATE_6(HDMI_CONTROL,
503 HDMI_PACKET_GEN_VERSION, 1,
504 HDMI_KEEPOUT_MODE, 1,
505 HDMI_DEEP_COLOR_ENABLE, 0,
506 HDMI_DATA_SCRAMBLE_EN, 0,
507 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
508 HDMI_CLOCK_CHANNEL_RATE, 0);
509
510
511 switch (crtc_timing->display_color_depth) {
512 case COLOR_DEPTH_888:
513 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
514 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
515 break;
516 case COLOR_DEPTH_101010:
517 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
518 REG_UPDATE_2(HDMI_CONTROL,
519 HDMI_DEEP_COLOR_DEPTH, 1,
520 HDMI_DEEP_COLOR_ENABLE, 0);
521 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
522 "disabled for YCBCR422 pixel encoding\n");
523 } else {
524 REG_UPDATE_2(HDMI_CONTROL,
525 HDMI_DEEP_COLOR_DEPTH, 1,
526 HDMI_DEEP_COLOR_ENABLE, 1);
527 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
528 "enabled for YCBCR422 non-pixel encoding\n");
529 }
530 break;
531 case COLOR_DEPTH_121212:
532 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
533 REG_UPDATE_2(HDMI_CONTROL,
534 HDMI_DEEP_COLOR_DEPTH, 2,
535 HDMI_DEEP_COLOR_ENABLE, 0);
536 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
537 "disabled for YCBCR422 pixel encoding\n");
538 } else {
539 REG_UPDATE_2(HDMI_CONTROL,
540 HDMI_DEEP_COLOR_DEPTH, 2,
541 HDMI_DEEP_COLOR_ENABLE, 1);
542 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
543 "enabled for non-pixel YCBCR422 encoding\n");
544 }
545 break;
546 case COLOR_DEPTH_161616:
547 REG_UPDATE_2(HDMI_CONTROL,
548 HDMI_DEEP_COLOR_DEPTH, 3,
549 HDMI_DEEP_COLOR_ENABLE, 1);
550 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \
551 "reserved mode\n");
552 break;
553 default:
554 break;
555 }
556
557 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
558 /* enable HDMI data scrambler
559 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
560 * Clock channel frequency is 1/4 of character rate.
561 */
562 REG_UPDATE_2(HDMI_CONTROL,
563 HDMI_DATA_SCRAMBLE_EN, 1,
564 HDMI_CLOCK_CHANNEL_RATE, 1);
565 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
566
567 /* TODO: New feature for DCE11, still need to implement */
568
569 /* enable HDMI data scrambler
570 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
571 * Clock channel frequency is the same
572 * as character rate
573 */
574 REG_UPDATE_2(HDMI_CONTROL,
575 HDMI_DATA_SCRAMBLE_EN, 1,
576 HDMI_CLOCK_CHANNEL_RATE, 0);
577 }
578
579
580 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
581 HDMI_GC_CONT, 1,
582 HDMI_GC_SEND, 1,
583 HDMI_NULL_SEND, 1);
584
585 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
586
587 /* following belongs to audio */
588 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
589
590 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
591
592 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
593 VBI_LINE_0 + 2);
594
595 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
596 }
597
598 /* setup stream encoder in dvi mode */
enc1_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)599 void enc1_stream_encoder_dvi_set_stream_attribute(
600 struct stream_encoder *enc,
601 struct dc_crtc_timing *crtc_timing,
602 bool is_dual_link)
603 {
604 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
605 struct bp_encoder_control cntl = {0};
606
607 cntl.action = ENCODER_CONTROL_SETUP;
608 cntl.engine_id = enc1->base.id;
609 cntl.signal = is_dual_link ?
610 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
611 cntl.enable_dp_audio = false;
612 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
613 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
614
615 if (enc1->base.bp->funcs->encoder_control(
616 enc1->base.bp, &cntl) != BP_RESULT_OK)
617 return;
618
619 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
620 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
621 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
622 }
623
enc1_stream_encoder_set_throttled_vcp_size(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)624 void enc1_stream_encoder_set_throttled_vcp_size(
625 struct stream_encoder *enc,
626 struct fixed31_32 avg_time_slots_per_mtp)
627 {
628 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
629 uint32_t x = dc_fixpt_floor(
630 avg_time_slots_per_mtp);
631 uint32_t y = dc_fixpt_ceil(
632 dc_fixpt_shl(
633 dc_fixpt_sub_int(
634 avg_time_slots_per_mtp,
635 x),
636 26));
637
638 // If y rounds up to integer, carry it over to x.
639 if (y >> 26) {
640 x += 1;
641 y = 0;
642 }
643
644 REG_SET_2(DP_MSE_RATE_CNTL, 0,
645 DP_MSE_RATE_X, x,
646 DP_MSE_RATE_Y, y);
647
648 /* wait for update to be completed on the link */
649 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
650 /* is reset to 0 (not pending) */
651 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
652 0,
653 10, DP_MST_UPDATE_MAX_RETRY);
654 }
655
enc1_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)656 static void enc1_stream_encoder_update_hdmi_info_packets(
657 struct stream_encoder *enc,
658 const struct encoder_info_frame *info_frame)
659 {
660 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
661
662 /* for bring up, disable dp double TODO */
663 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
664
665 /*Always add mandatory packets first followed by optional ones*/
666 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
667 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
668 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
669 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
670 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
671 enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
672 }
673
enc1_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)674 static void enc1_stream_encoder_stop_hdmi_info_packets(
675 struct stream_encoder *enc)
676 {
677 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
678
679 /* stop generic packets 0 & 1 on HDMI */
680 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
681 HDMI_GENERIC1_CONT, 0,
682 HDMI_GENERIC1_LINE, 0,
683 HDMI_GENERIC1_SEND, 0,
684 HDMI_GENERIC0_CONT, 0,
685 HDMI_GENERIC0_LINE, 0,
686 HDMI_GENERIC0_SEND, 0);
687
688 /* stop generic packets 2 & 3 on HDMI */
689 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
690 HDMI_GENERIC0_CONT, 0,
691 HDMI_GENERIC0_LINE, 0,
692 HDMI_GENERIC0_SEND, 0,
693 HDMI_GENERIC1_CONT, 0,
694 HDMI_GENERIC1_LINE, 0,
695 HDMI_GENERIC1_SEND, 0);
696
697 /* stop generic packets 2 & 3 on HDMI */
698 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
699 HDMI_GENERIC0_CONT, 0,
700 HDMI_GENERIC0_LINE, 0,
701 HDMI_GENERIC0_SEND, 0,
702 HDMI_GENERIC1_CONT, 0,
703 HDMI_GENERIC1_LINE, 0,
704 HDMI_GENERIC1_SEND, 0);
705
706 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
707 HDMI_GENERIC0_CONT, 0,
708 HDMI_GENERIC0_LINE, 0,
709 HDMI_GENERIC0_SEND, 0,
710 HDMI_GENERIC1_CONT, 0,
711 HDMI_GENERIC1_LINE, 0,
712 HDMI_GENERIC1_SEND, 0);
713 }
714
enc1_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)715 void enc1_stream_encoder_update_dp_info_packets(
716 struct stream_encoder *enc,
717 const struct encoder_info_frame *info_frame)
718 {
719 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
720 uint32_t value = 0;
721
722 if (info_frame->vsc.valid)
723 enc1_update_generic_info_packet(
724 enc1,
725 0, /* packetIndex */
726 &info_frame->vsc);
727
728 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
729 * Note that the enablement of GSP1 is not done below,
730 * it's done in FW.
731 */
732 if (info_frame->vsc.valid)
733 enc1_update_generic_info_packet(
734 enc1,
735 1, /* packetIndex */
736 &info_frame->vsc);
737
738 if (info_frame->spd.valid)
739 enc1_update_generic_info_packet(
740 enc1,
741 2, /* packetIndex */
742 &info_frame->spd);
743
744 if (info_frame->hdrsmd.valid)
745 enc1_update_generic_info_packet(
746 enc1,
747 3, /* packetIndex */
748 &info_frame->hdrsmd);
749
750 /* packetIndex 4 is used for send immediate sdp message, and please
751 * use other packetIndex (such as 5,6) for other info packet
752 */
753
754 if (info_frame->adaptive_sync.valid)
755 enc1_update_generic_info_packet(
756 enc1,
757 5, /* packetIndex */
758 &info_frame->adaptive_sync);
759
760 /* enable/disable transmission of packet(s).
761 * If enabled, packet transmission begins on the next frame
762 */
763 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
764 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
765 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
766 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);
767
768 /* This bit is the master enable bit.
769 * When enabling secondary stream engine,
770 * this master bit must also be set.
771 * This register shared with audio info frame.
772 * Therefore we need to enable master bit
773 * if at least on of the fields is not 0
774 */
775 value = REG_READ(DP_SEC_CNTL);
776 if (value)
777 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
778 }
779
enc1_stream_encoder_send_immediate_sdp_message(struct stream_encoder * enc,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)780 void enc1_stream_encoder_send_immediate_sdp_message(
781 struct stream_encoder *enc,
782 const uint8_t *custom_sdp_message,
783 unsigned int sdp_message_size)
784 {
785 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
786 uint32_t value = 0;
787
788 /* TODOFPGA Figure out a proper number for max_retries polling for lock
789 * use 50 for now.
790 */
791 uint32_t max_retries = 50;
792
793 /* check if GSP4 is transmitted */
794 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
795 0, 10, max_retries);
796
797 /* disable GSP4 transmitting */
798 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
799
800 /* transmit GSP4 at the earliest time in a frame */
801 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
802
803 /*we need turn on clock before programming AFMT block*/
804 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
805
806 /* check if HW reading GSP memory */
807 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
808 0, 10, max_retries);
809
810 /* HW does is not reading GSP memory not reading too long ->
811 * something wrong. clear GPS memory access and notify?
812 * hw SW is writing to GSP memory
813 */
814 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
815
816 /* use generic packet 4 for immediate sdp message */
817 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
818 AFMT_GENERIC_INDEX, 4);
819
820 /* write generic packet header
821 * (4th byte is for GENERIC0 only)
822 */
823 REG_SET_4(AFMT_GENERIC_HDR, 0,
824 AFMT_GENERIC_HB0, custom_sdp_message[0],
825 AFMT_GENERIC_HB1, custom_sdp_message[1],
826 AFMT_GENERIC_HB2, custom_sdp_message[2],
827 AFMT_GENERIC_HB3, custom_sdp_message[3]);
828
829 /* write generic packet contents
830 * (we never use last 4 bytes)
831 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
832 */
833 {
834 const uint32_t *content =
835 (const uint32_t *) &custom_sdp_message[4];
836
837 REG_WRITE(AFMT_GENERIC_0, *content++);
838 REG_WRITE(AFMT_GENERIC_1, *content++);
839 REG_WRITE(AFMT_GENERIC_2, *content++);
840 REG_WRITE(AFMT_GENERIC_3, *content++);
841 REG_WRITE(AFMT_GENERIC_4, *content++);
842 REG_WRITE(AFMT_GENERIC_5, *content++);
843 REG_WRITE(AFMT_GENERIC_6, *content++);
844 REG_WRITE(AFMT_GENERIC_7, *content);
845 }
846
847 /* check whether GENERIC4 registers double buffer update in immediate mode
848 * is pending
849 */
850 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
851 0, 10, max_retries);
852
853 /* atomically update double-buffered GENERIC4 registers in immediate mode
854 * (update immediately)
855 */
856 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
857 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
858
859 /* enable GSP4 transmitting */
860 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
861
862 /* This bit is the master enable bit.
863 * When enabling secondary stream engine,
864 * this master bit must also be set.
865 * This register shared with audio info frame.
866 * Therefore we need to enable master bit
867 * if at least on of the fields is not 0
868 */
869 value = REG_READ(DP_SEC_CNTL);
870 if (value)
871 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
872 }
873
enc1_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)874 void enc1_stream_encoder_stop_dp_info_packets(
875 struct stream_encoder *enc)
876 {
877 /* stop generic packets on DP */
878 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
879 uint32_t value = 0;
880
881 REG_SET_10(DP_SEC_CNTL, 0,
882 DP_SEC_GSP0_ENABLE, 0,
883 DP_SEC_GSP1_ENABLE, 0,
884 DP_SEC_GSP2_ENABLE, 0,
885 DP_SEC_GSP3_ENABLE, 0,
886 DP_SEC_GSP4_ENABLE, 0,
887 DP_SEC_GSP5_ENABLE, 0,
888 DP_SEC_GSP6_ENABLE, 0,
889 DP_SEC_GSP7_ENABLE, 0,
890 DP_SEC_MPG_ENABLE, 0,
891 DP_SEC_STREAM_ENABLE, 0);
892
893 /* this register shared with audio info frame.
894 * therefore we need to keep master enabled
895 * if at least one of the fields is not 0 */
896 value = REG_READ(DP_SEC_CNTL);
897 if (value)
898 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
899
900 }
901
enc1_stream_encoder_dp_blank(struct dc_link * link,struct stream_encoder * enc)902 void enc1_stream_encoder_dp_blank(
903 struct dc_link *link,
904 struct stream_encoder *enc)
905 {
906 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
907 uint32_t reg1 = 0;
908 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
909
910 /* Note: For CZ, we are changing driver default to disable
911 * stream deferred to next VBLANK. If results are positive, we
912 * will make the same change to all DCE versions. There are a
913 * handful of panels that cannot handle disable stream at
914 * HBLANK and will result in a white line flash across the
915 * screen on stream disable.
916 */
917 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
918 if ((reg1 & 0x1) == 0)
919 /*stream not enabled*/
920 return;
921 /* Specify the video stream disable point
922 * (2 = start of the next vertical blank)
923 */
924 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
925 /* Larger delay to wait until VBLANK - use max retry of
926 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
927 * a little more because we may not trust delay accuracy.
928 */
929 max_retries = DP_BLANK_MAX_RETRY * 501;
930
931 /* disable DP stream */
932 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
933
934 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
935
936 /* the encoder stops sending the video stream
937 * at the start of the vertical blanking.
938 * Poll for DP_VID_STREAM_STATUS == 0
939 */
940
941 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
942 0,
943 10, max_retries);
944
945 /* Tell the DP encoder to ignore timing from CRTC, must be done after
946 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
947 * complete, stream status will be stuck in video stream enabled state,
948 * i.e. DP_VID_STREAM_STATUS stuck at 1.
949 */
950
951 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
952
953 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
954 }
955
956 /* output video stream to link encoder */
enc1_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)957 void enc1_stream_encoder_dp_unblank(
958 struct dc_link *link,
959 struct stream_encoder *enc,
960 const struct encoder_unblank_param *param)
961 {
962 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
963
964 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
965 uint32_t n_vid = 0x8000;
966 uint32_t m_vid;
967 uint32_t n_multiply = 0;
968 uint64_t m_vid_l = n_vid;
969
970 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
971 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
972 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
973 n_multiply = 1;
974 }
975 /* M / N = Fstream / Flink
976 * m_vid / n_vid = pixel rate / link rate
977 */
978
979 m_vid_l *= param->timing.pix_clk_100hz / 10;
980 m_vid_l = div_u64(m_vid_l,
981 param->link_settings.link_rate
982 * LINK_RATE_REF_FREQ_IN_KHZ);
983
984 m_vid = (uint32_t) m_vid_l;
985
986 /* enable auto measurement */
987
988 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
989
990 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
991 * therefore program initial value for Mvid and Nvid
992 */
993
994 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
995
996 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
997
998 REG_UPDATE_2(DP_VID_TIMING,
999 DP_VID_M_N_GEN_EN, 1,
1000 DP_VID_N_MUL, n_multiply);
1001 }
1002
1003 /* set DIG_START to 0x1 to resync FIFO */
1004
1005 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1006
1007 /* switch DP encoder to CRTC data */
1008
1009 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1010
1011 /* wait 100us for DIG/DP logic to prime
1012 * (i.e. a few video lines)
1013 */
1014 udelay(100);
1015
1016 /* the hardware would start sending video at the start of the next DP
1017 * frame (i.e. rising edge of the vblank).
1018 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1019 * register has no effect on enable transition! HW always guarantees
1020 * VID_STREAM enable at start of next frame, and this is not
1021 * programmable
1022 */
1023
1024 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1025
1026 link->dc->link_srv->dp_trace_source_sequence(link,
1027 DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1028 }
1029
enc1_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)1030 void enc1_stream_encoder_set_avmute(
1031 struct stream_encoder *enc,
1032 bool enable)
1033 {
1034 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1035 unsigned int value = enable ? 1 : 0;
1036
1037 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1038 }
1039
enc1_reset_hdmi_stream_attribute(struct stream_encoder * enc)1040 void enc1_reset_hdmi_stream_attribute(
1041 struct stream_encoder *enc)
1042 {
1043 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1044
1045 REG_UPDATE_5(HDMI_CONTROL,
1046 HDMI_PACKET_GEN_VERSION, 1,
1047 HDMI_KEEPOUT_MODE, 1,
1048 HDMI_DEEP_COLOR_ENABLE, 0,
1049 HDMI_DATA_SCRAMBLE_EN, 0,
1050 HDMI_CLOCK_CHANNEL_RATE, 0);
1051 }
1052
1053
1054 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1055 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1056
1057 #include "include/audio_types.h"
1058
1059
1060 /* 25.2MHz/1.001*/
1061 /* 25.2MHz/1.001*/
1062 /* 25.2MHz*/
1063 /* 27MHz */
1064 /* 27MHz*1.001*/
1065 /* 27MHz*1.001*/
1066 /* 54MHz*/
1067 /* 54MHz*1.001*/
1068 /* 74.25MHz/1.001*/
1069 /* 74.25MHz*/
1070 /* 148.5MHz/1.001*/
1071 /* 148.5MHz*/
1072
1073 static const struct audio_clock_info audio_clock_info_table[16] = {
1074 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1075 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1076 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1077 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1078 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1079 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1080 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1081 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1082 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1083 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1084 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1085 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1086 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1087 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1088 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1089 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1090 };
1091
1092 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1093 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1094 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1095 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1096 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1097 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1098 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1099 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1100 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1101 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1102 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1103 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1104 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1105 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1106 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1107 };
1108
1109 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1110 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1111 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1112 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1113 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1114 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1115 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1116 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1117 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1118 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1119 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1120 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1121 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1122 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1123 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1124
1125
1126 };
1127
speakers_to_channels(struct audio_speaker_flags speaker_flags)1128 static union audio_cea_channels speakers_to_channels(
1129 struct audio_speaker_flags speaker_flags)
1130 {
1131 union audio_cea_channels cea_channels = {0};
1132
1133 /* these are one to one */
1134 cea_channels.channels.FL = speaker_flags.FL_FR;
1135 cea_channels.channels.FR = speaker_flags.FL_FR;
1136 cea_channels.channels.LFE = speaker_flags.LFE;
1137 cea_channels.channels.FC = speaker_flags.FC;
1138
1139 /* if Rear Left and Right exist move RC speaker to channel 7
1140 * otherwise to channel 5
1141 */
1142 if (speaker_flags.RL_RR) {
1143 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1144 cea_channels.channels.RR = speaker_flags.RL_RR;
1145 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1146 } else {
1147 cea_channels.channels.RL_RC = speaker_flags.RC;
1148 }
1149
1150 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1151 if (speaker_flags.FLC_FRC) {
1152 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1153 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1154 } else {
1155 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1156 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1157 }
1158
1159 return cea_channels;
1160 }
1161
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_100Hz,uint32_t actual_pixel_clock_100Hz,struct audio_clock_info * audio_clock_info)1162 void get_audio_clock_info(
1163 enum dc_color_depth color_depth,
1164 uint32_t crtc_pixel_clock_100Hz,
1165 uint32_t actual_pixel_clock_100Hz,
1166 struct audio_clock_info *audio_clock_info)
1167 {
1168 const struct audio_clock_info *clock_info;
1169 uint32_t index;
1170 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1171 uint32_t audio_array_size;
1172
1173 switch (color_depth) {
1174 case COLOR_DEPTH_161616:
1175 clock_info = audio_clock_info_table_48bpc;
1176 audio_array_size = ARRAY_SIZE(
1177 audio_clock_info_table_48bpc);
1178 break;
1179 case COLOR_DEPTH_121212:
1180 clock_info = audio_clock_info_table_36bpc;
1181 audio_array_size = ARRAY_SIZE(
1182 audio_clock_info_table_36bpc);
1183 break;
1184 default:
1185 clock_info = audio_clock_info_table;
1186 audio_array_size = ARRAY_SIZE(
1187 audio_clock_info_table);
1188 break;
1189 }
1190
1191 if (clock_info != NULL) {
1192 /* search for exact pixel clock in table */
1193 for (index = 0; index < audio_array_size; index++) {
1194 if (clock_info[index].pixel_clock_in_10khz >
1195 crtc_pixel_clock_in_10khz)
1196 break; /* not match */
1197 else if (clock_info[index].pixel_clock_in_10khz ==
1198 crtc_pixel_clock_in_10khz) {
1199 /* match found */
1200 *audio_clock_info = clock_info[index];
1201 return;
1202 }
1203 }
1204 }
1205
1206 /* not found */
1207 if (actual_pixel_clock_100Hz == 0)
1208 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1209
1210 /* See HDMI spec the table entry under
1211 * pixel clock of "Other". */
1212 audio_clock_info->pixel_clock_in_10khz =
1213 actual_pixel_clock_100Hz / 100;
1214 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1215 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1216 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1217
1218 audio_clock_info->n_32khz = 4096;
1219 audio_clock_info->n_44khz = 6272;
1220 audio_clock_info->n_48khz = 6144;
1221 }
1222
enc1_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1223 static void enc1_se_audio_setup(
1224 struct stream_encoder *enc,
1225 unsigned int az_inst,
1226 struct audio_info *audio_info)
1227 {
1228 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1229
1230 uint32_t channels = 0;
1231
1232 ASSERT(audio_info);
1233 if (audio_info == NULL)
1234 /* This should not happen.it does so we don't get BSOD*/
1235 return;
1236
1237 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1238
1239 /* setup the audio stream source select (audio -> dig mapping) */
1240 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1241
1242 /* Channel allocation */
1243 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1244 }
1245
enc1_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1246 static void enc1_se_setup_hdmi_audio(
1247 struct stream_encoder *enc,
1248 const struct audio_crtc_info *crtc_info)
1249 {
1250 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1251
1252 struct audio_clock_info audio_clock_info = {0};
1253
1254 /* HDMI_AUDIO_PACKET_CONTROL */
1255 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1256 HDMI_AUDIO_DELAY_EN, 1);
1257
1258 /* AFMT_AUDIO_PACKET_CONTROL */
1259 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1260
1261 /* AFMT_AUDIO_PACKET_CONTROL2 */
1262 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1263 AFMT_AUDIO_LAYOUT_OVRD, 0,
1264 AFMT_60958_OSF_OVRD, 0);
1265
1266 /* HDMI_ACR_PACKET_CONTROL */
1267 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1268 HDMI_ACR_AUTO_SEND, 1,
1269 HDMI_ACR_SOURCE, 0,
1270 HDMI_ACR_AUDIO_PRIORITY, 0);
1271
1272 /* Program audio clock sample/regeneration parameters */
1273 get_audio_clock_info(crtc_info->color_depth,
1274 crtc_info->requested_pixel_clock_100Hz,
1275 crtc_info->calculated_pixel_clock_100Hz,
1276 &audio_clock_info);
1277 DC_LOG_HW_AUDIO(
1278 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1279 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1280 crtc_info->requested_pixel_clock_100Hz, \
1281 crtc_info->calculated_pixel_clock_100Hz);
1282
1283 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1284 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1285
1286 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1287 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1288
1289 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1290 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1291
1292 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1293 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1294
1295 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1296 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1297
1298 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1299 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1300
1301 /* Video driver cannot know in advance which sample rate will
1302 * be used by HD Audio driver
1303 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1304 * programmed below in interruppt callback
1305 */
1306
1307 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1308 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1309 */
1310 REG_UPDATE_2(AFMT_60958_0,
1311 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1312 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1313
1314 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1315 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1316
1317 /* AFMT_60958_2 now keep this settings until
1318 * Programming guide comes out
1319 */
1320 REG_UPDATE_6(AFMT_60958_2,
1321 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1322 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1323 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1324 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1325 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1326 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1327 }
1328
enc1_se_setup_dp_audio(struct stream_encoder * enc)1329 static void enc1_se_setup_dp_audio(
1330 struct stream_encoder *enc)
1331 {
1332 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1333
1334 /* --- DP Audio packet configurations --- */
1335
1336 /* ATP Configuration */
1337 REG_SET(DP_SEC_AUD_N, 0,
1338 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1339
1340 /* Async/auto-calc timestamp mode */
1341 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1342 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1343
1344 /* --- The following are the registers
1345 * copied from the SetupHDMI ---
1346 */
1347
1348 /* AFMT_AUDIO_PACKET_CONTROL */
1349 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1350
1351 /* AFMT_AUDIO_PACKET_CONTROL2 */
1352 /* Program the ATP and AIP next */
1353 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1354 AFMT_AUDIO_LAYOUT_OVRD, 0,
1355 AFMT_60958_OSF_OVRD, 0);
1356
1357 /* AFMT_INFOFRAME_CONTROL0 */
1358 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1359
1360 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1361 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1362 }
1363
enc1_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1364 void enc1_se_enable_audio_clock(
1365 struct stream_encoder *enc,
1366 bool enable)
1367 {
1368 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1369
1370 if (REG(AFMT_CNTL) == 0)
1371 return; /* DCE8/10 does not have this register */
1372
1373 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1374
1375 /* wait for AFMT clock to turn on,
1376 * expectation: this should complete in 1-2 reads
1377 *
1378 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1379 *
1380 * TODO: wait for clock_on does not work well. May need HW
1381 * program sequence. But audio seems work normally even without wait
1382 * for clock_on status change
1383 */
1384 }
1385
enc1_se_enable_dp_audio(struct stream_encoder * enc)1386 void enc1_se_enable_dp_audio(
1387 struct stream_encoder *enc)
1388 {
1389 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1390
1391 /* Enable Audio packets */
1392 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1393
1394 /* Program the ATP and AIP next */
1395 REG_UPDATE_2(DP_SEC_CNTL,
1396 DP_SEC_ATP_ENABLE, 1,
1397 DP_SEC_AIP_ENABLE, 1);
1398
1399 /* Program STREAM_ENABLE after all the other enables. */
1400 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1401 }
1402
enc1_se_disable_dp_audio(struct stream_encoder * enc)1403 static void enc1_se_disable_dp_audio(
1404 struct stream_encoder *enc)
1405 {
1406 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1407 uint32_t value = 0;
1408
1409 /* Disable Audio packets */
1410 REG_UPDATE_5(DP_SEC_CNTL,
1411 DP_SEC_ASP_ENABLE, 0,
1412 DP_SEC_ATP_ENABLE, 0,
1413 DP_SEC_AIP_ENABLE, 0,
1414 DP_SEC_ACM_ENABLE, 0,
1415 DP_SEC_STREAM_ENABLE, 0);
1416
1417 /* This register shared with encoder info frame. Therefore we need to
1418 * keep master enabled if at least on of the fields is not 0
1419 */
1420 value = REG_READ(DP_SEC_CNTL);
1421 if (value != 0)
1422 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1423
1424 }
1425
enc1_se_audio_mute_control(struct stream_encoder * enc,bool mute)1426 void enc1_se_audio_mute_control(
1427 struct stream_encoder *enc,
1428 bool mute)
1429 {
1430 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1431
1432 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1433 }
1434
enc1_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1435 void enc1_se_dp_audio_setup(
1436 struct stream_encoder *enc,
1437 unsigned int az_inst,
1438 struct audio_info *info)
1439 {
1440 enc1_se_audio_setup(enc, az_inst, info);
1441 }
1442
enc1_se_dp_audio_enable(struct stream_encoder * enc)1443 void enc1_se_dp_audio_enable(
1444 struct stream_encoder *enc)
1445 {
1446 enc1_se_enable_audio_clock(enc, true);
1447 enc1_se_setup_dp_audio(enc);
1448 enc1_se_enable_dp_audio(enc);
1449 }
1450
enc1_se_dp_audio_disable(struct stream_encoder * enc)1451 void enc1_se_dp_audio_disable(
1452 struct stream_encoder *enc)
1453 {
1454 enc1_se_disable_dp_audio(enc);
1455 enc1_se_enable_audio_clock(enc, false);
1456 }
1457
enc1_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1458 void enc1_se_hdmi_audio_setup(
1459 struct stream_encoder *enc,
1460 unsigned int az_inst,
1461 struct audio_info *info,
1462 struct audio_crtc_info *audio_crtc_info)
1463 {
1464 enc1_se_enable_audio_clock(enc, true);
1465 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1466 enc1_se_audio_setup(enc, az_inst, info);
1467 }
1468
enc1_se_hdmi_audio_disable(struct stream_encoder * enc)1469 void enc1_se_hdmi_audio_disable(
1470 struct stream_encoder *enc)
1471 {
1472 if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1473 enc->afmt->funcs->afmt_powerdown(enc->afmt);
1474
1475 enc1_se_enable_audio_clock(enc, false);
1476 }
1477
1478
enc1_setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1479 void enc1_setup_stereo_sync(
1480 struct stream_encoder *enc,
1481 int tg_inst, bool enable)
1482 {
1483 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1484 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1485 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1486 }
1487
enc1_dig_connect_to_otg(struct stream_encoder * enc,int tg_inst)1488 void enc1_dig_connect_to_otg(
1489 struct stream_encoder *enc,
1490 int tg_inst)
1491 {
1492 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1493
1494 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1495 }
1496
enc1_dig_source_otg(struct stream_encoder * enc)1497 unsigned int enc1_dig_source_otg(
1498 struct stream_encoder *enc)
1499 {
1500 uint32_t tg_inst = 0;
1501 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1502
1503 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1504
1505 return tg_inst;
1506 }
1507
enc1_stream_encoder_dp_get_pixel_format(struct stream_encoder * enc,enum dc_pixel_encoding * encoding,enum dc_color_depth * depth)1508 bool enc1_stream_encoder_dp_get_pixel_format(
1509 struct stream_encoder *enc,
1510 enum dc_pixel_encoding *encoding,
1511 enum dc_color_depth *depth)
1512 {
1513 uint32_t hw_encoding = 0;
1514 uint32_t hw_depth = 0;
1515 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1516
1517 if (enc == NULL ||
1518 encoding == NULL ||
1519 depth == NULL)
1520 return false;
1521
1522 REG_GET_2(DP_PIXEL_FORMAT,
1523 DP_PIXEL_ENCODING, &hw_encoding,
1524 DP_COMPONENT_DEPTH, &hw_depth);
1525
1526 switch (hw_depth) {
1527 case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1528 *depth = COLOR_DEPTH_666;
1529 break;
1530 case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1531 *depth = COLOR_DEPTH_888;
1532 break;
1533 case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1534 *depth = COLOR_DEPTH_101010;
1535 break;
1536 case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1537 *depth = COLOR_DEPTH_121212;
1538 break;
1539 case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1540 *depth = COLOR_DEPTH_161616;
1541 break;
1542 default:
1543 *depth = COLOR_DEPTH_UNDEFINED;
1544 break;
1545 }
1546
1547 switch (hw_encoding) {
1548 case DP_PIXEL_ENCODING_TYPE_RGB444:
1549 *encoding = PIXEL_ENCODING_RGB;
1550 break;
1551 case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1552 *encoding = PIXEL_ENCODING_YCBCR422;
1553 break;
1554 case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1555 case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1556 *encoding = PIXEL_ENCODING_YCBCR444;
1557 break;
1558 case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1559 *encoding = PIXEL_ENCODING_YCBCR420;
1560 break;
1561 default:
1562 *encoding = PIXEL_ENCODING_UNDEFINED;
1563 break;
1564 }
1565 return true;
1566 }
1567
1568 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1569 .dp_set_stream_attribute =
1570 enc1_stream_encoder_dp_set_stream_attribute,
1571 .hdmi_set_stream_attribute =
1572 enc1_stream_encoder_hdmi_set_stream_attribute,
1573 .dvi_set_stream_attribute =
1574 enc1_stream_encoder_dvi_set_stream_attribute,
1575 .set_throttled_vcp_size =
1576 enc1_stream_encoder_set_throttled_vcp_size,
1577 .update_hdmi_info_packets =
1578 enc1_stream_encoder_update_hdmi_info_packets,
1579 .stop_hdmi_info_packets =
1580 enc1_stream_encoder_stop_hdmi_info_packets,
1581 .update_dp_info_packets =
1582 enc1_stream_encoder_update_dp_info_packets,
1583 .send_immediate_sdp_message =
1584 enc1_stream_encoder_send_immediate_sdp_message,
1585 .stop_dp_info_packets =
1586 enc1_stream_encoder_stop_dp_info_packets,
1587 .dp_blank =
1588 enc1_stream_encoder_dp_blank,
1589 .dp_unblank =
1590 enc1_stream_encoder_dp_unblank,
1591 .audio_mute_control = enc1_se_audio_mute_control,
1592
1593 .dp_audio_setup = enc1_se_dp_audio_setup,
1594 .dp_audio_enable = enc1_se_dp_audio_enable,
1595 .dp_audio_disable = enc1_se_dp_audio_disable,
1596
1597 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1598 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1599 .setup_stereo_sync = enc1_setup_stereo_sync,
1600 .set_avmute = enc1_stream_encoder_set_avmute,
1601 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1602 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1603 .dig_source_otg = enc1_dig_source_otg,
1604
1605 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
1606 };
1607
dcn10_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)1608 void dcn10_stream_encoder_construct(
1609 struct dcn10_stream_encoder *enc1,
1610 struct dc_context *ctx,
1611 struct dc_bios *bp,
1612 enum engine_id eng_id,
1613 const struct dcn10_stream_enc_registers *regs,
1614 const struct dcn10_stream_encoder_shift *se_shift,
1615 const struct dcn10_stream_encoder_mask *se_mask)
1616 {
1617 enc1->base.funcs = &dcn10_str_enc_funcs;
1618 enc1->base.ctx = ctx;
1619 enc1->base.id = eng_id;
1620 enc1->base.bp = bp;
1621 enc1->regs = regs;
1622 enc1->se_shift = se_shift;
1623 enc1->se_mask = se_mask;
1624 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1625 }
1626
1627