1 /*
2 * Copyright 2020 Mauro Rossi <[email protected]>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 /* include DCE6 register header files */
29 #include "dce/dce_6_0_d.h"
30 #include "dce/dce_6_0_sh_mask.h"
31
32 #include "dc_types.h"
33
34 #include "include/grph_object_id.h"
35 #include "include/logger_interface.h"
36 #include "../dce110/dce110_timing_generator.h"
37 #include "dce60_timing_generator.h"
38
39 #include "timing_generator.h"
40
41 enum black_color_format {
42 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
43 BLACK_COLOR_FORMAT_RGB_LIMITED,
44 BLACK_COLOR_FORMAT_YUV_TV,
45 BLACK_COLOR_FORMAT_YUV_CV,
46 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
47
48 BLACK_COLOR_FORMAT_COUNT
49 };
50
51 static const struct dce110_timing_generator_offsets reg_offsets[] = {
52 {
53 .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
54 .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
55 },
56 {
57 .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
58 .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
59 },
60 {
61 .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
62 .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
63 },
64 {
65 .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
66 .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
67 },
68 {
69 .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
70 .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
71 },
72 {
73 .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
74 .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
75 }
76 };
77
78 #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
79
80 #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
81 #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
82
83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
84 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
85 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
86
program_pix_dur(struct timing_generator * tg,uint32_t pix_clk_100hz)87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
88 {
89 uint64_t pix_dur;
90 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
91 + DCE110TG_FROM_TG(tg)->offsets.dmif;
92 uint32_t value = dm_read_reg(tg->ctx, addr);
93
94 if (pix_clk_100hz == 0)
95 return;
96
97 pix_dur = div_u64(10000000000ull, pix_clk_100hz);
98
99 set_reg_field_value(
100 value,
101 pix_dur,
102 DPG_PIPE_ARBITRATION_CONTROL1,
103 PIXEL_DURATION);
104
105 dm_write_reg(tg->ctx, addr, value);
106 }
107
program_timing(struct timing_generator * tg,const struct dc_crtc_timing * timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,int pstate_keepout,const enum signal_type signal,bool use_vbios)108 static void program_timing(struct timing_generator *tg,
109 const struct dc_crtc_timing *timing,
110 int vready_offset,
111 int vstartup_start,
112 int vupdate_offset,
113 int vupdate_width,
114 int pstate_keepout,
115 const enum signal_type signal,
116 bool use_vbios)
117 {
118 if (!use_vbios)
119 program_pix_dur(tg, timing->pix_clk_100hz);
120
121 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);
122 }
123
dce60_timing_generator_enable_advanced_request(struct timing_generator * tg,bool enable,const struct dc_crtc_timing * timing)124 static void dce60_timing_generator_enable_advanced_request(
125 struct timing_generator *tg,
126 bool enable,
127 const struct dc_crtc_timing *timing)
128 {
129 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
130 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
131 uint32_t value = dm_read_reg(tg->ctx, addr);
132 /* DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register */
133 uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL);
134 uint32_t value2 = dm_read_reg(tg->ctx, addr2);
135
136 /* DCE6 does not support CRTC_LEGACY_REQUESTOR_EN bit
137 so here is not possible to set bit based on enable argument */
138
139 if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
140 set_reg_field_value(
141 value,
142 3,
143 CRTC_START_LINE_CONTROL,
144 CRTC_ADVANCED_START_LINE_POSITION);
145 set_reg_field_value(
146 value2,
147 0,
148 CRTC_CONTROL,
149 CRTC_PREFETCH_EN);
150 } else {
151 set_reg_field_value(
152 value,
153 4,
154 CRTC_START_LINE_CONTROL,
155 CRTC_ADVANCED_START_LINE_POSITION);
156 set_reg_field_value(
157 value2,
158 1,
159 CRTC_CONTROL,
160 CRTC_PREFETCH_EN);
161 }
162
163 set_reg_field_value(
164 value,
165 1,
166 CRTC_START_LINE_CONTROL,
167 CRTC_PROGRESSIVE_START_LINE_EARLY);
168
169 set_reg_field_value(
170 value,
171 1,
172 CRTC_START_LINE_CONTROL,
173 CRTC_INTERLACE_START_LINE_EARLY);
174
175 dm_write_reg(tg->ctx, addr, value);
176 dm_write_reg(tg->ctx, addr2, value2);
177 }
178
dce60_is_tg_enabled(struct timing_generator * tg)179 static bool dce60_is_tg_enabled(struct timing_generator *tg)
180 {
181 uint32_t addr = 0;
182 uint32_t value = 0;
183 uint32_t field = 0;
184 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
185
186 addr = CRTC_REG(mmCRTC_CONTROL);
187 value = dm_read_reg(tg->ctx, addr);
188 field = get_reg_field_value(value, CRTC_CONTROL,
189 CRTC_CURRENT_MASTER_EN_STATE);
190 return field == 1;
191 }
192
dce60_configure_crc(struct timing_generator * tg,const struct crc_params * params)193 static bool dce60_configure_crc(struct timing_generator *tg,
194 const struct crc_params *params)
195 {
196 /* Cannot configure crc on a CRTC that is disabled */
197 if (!dce60_is_tg_enabled(tg))
198 return false;
199
200 /* DCE6 has no CRTC_CRC_CNTL register, nothing to do */
201
202 return true;
203 }
204
205 static const struct timing_generator_funcs dce60_tg_funcs = {
206 .validate_timing = dce110_tg_validate_timing,
207 .program_timing = program_timing,
208 .enable_crtc = dce110_timing_generator_enable_crtc,
209 .disable_crtc = dce110_timing_generator_disable_crtc,
210 .is_counter_moving = dce110_timing_generator_is_counter_moving,
211 .get_position = dce110_timing_generator_get_position,
212 .get_frame_count = dce110_timing_generator_get_vblank_counter,
213 .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
214 .set_early_control = dce110_timing_generator_set_early_control,
215 .wait_for_state = dce110_tg_wait_for_state,
216 .set_blank = dce110_tg_set_blank,
217 .is_blanked = dce110_tg_is_blanked,
218 .set_colors = dce110_tg_set_colors,
219 .set_overscan_blank_color =
220 dce110_timing_generator_set_overscan_color_black,
221 .set_blank_color = dce110_timing_generator_program_blank_color,
222 .disable_vga = dce110_timing_generator_disable_vga,
223 .did_triggered_reset_occur =
224 dce110_timing_generator_did_triggered_reset_occur,
225 .setup_global_swap_lock =
226 dce110_timing_generator_setup_global_swap_lock,
227 .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
228 .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
229 .tear_down_global_swap_lock =
230 dce110_timing_generator_tear_down_global_swap_lock,
231 .set_drr = dce110_timing_generator_set_drr,
232 .set_static_screen_control =
233 dce110_timing_generator_set_static_screen_control,
234 .set_test_pattern = dce110_timing_generator_set_test_pattern,
235 .arm_vert_intr = dce110_arm_vert_intr,
236
237 /* DCE6.0 overrides */
238 .enable_advanced_request =
239 dce60_timing_generator_enable_advanced_request,
240 .configure_crc = dce60_configure_crc,
241 .get_crc = dce110_get_crc,
242 .is_two_pixels_per_container = dce110_is_two_pixels_per_container,
243 };
244
dce60_timing_generator_construct(struct dce110_timing_generator * tg110,struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)245 void dce60_timing_generator_construct(
246 struct dce110_timing_generator *tg110,
247 struct dc_context *ctx,
248 uint32_t instance,
249 const struct dce110_timing_generator_offsets *offsets)
250 {
251 tg110->controller_id = CONTROLLER_ID_D0 + instance;
252 tg110->base.inst = instance;
253 tg110->offsets = *offsets;
254 tg110->derived_offsets = reg_offsets[instance];
255
256 tg110->base.funcs = &dce60_tg_funcs;
257
258 tg110->base.ctx = ctx;
259 tg110->base.bp = ctx->dc_bios;
260
261 tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
262 tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
263
264 tg110->min_h_blank = 56;
265 tg110->min_h_front_porch = 4;
266 tg110->min_h_back_porch = 4;
267 }
268
269