1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
4 * Originally split out from the skx_edac driver.
5 *
6 * Copyright (c) 2018, Intel Corporation.
7 */
8
9 #ifndef _SKX_COMM_EDAC_H
10 #define _SKX_COMM_EDAC_H
11
12 #include <linux/bits.h>
13 #include <asm/mce.h>
14
15 #define MSG_SIZE 1024
16
17 /*
18 * Debug macros
19 */
20 #define skx_printk(level, fmt, arg...) \
21 edac_printk(level, "skx", fmt, ##arg)
22
23 #define skx_mc_printk(mci, level, fmt, arg...) \
24 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
25
26 /*
27 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
28 */
29 #define GET_BITFIELD(v, lo, hi) \
30 (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
31
32 #define SKX_NUM_IMC 2 /* Memory controllers per socket */
33 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
34 #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
35
36 #define I10NM_NUM_DDR_IMC 12
37 #define I10NM_NUM_DDR_CHANNELS 2
38 #define I10NM_NUM_DDR_DIMMS 2
39
40 #define I10NM_NUM_HBM_IMC 16
41 #define I10NM_NUM_HBM_CHANNELS 2
42 #define I10NM_NUM_HBM_DIMMS 1
43
44 #define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
45 #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
46 #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
47
48 #define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
49 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
50 #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
51
52 #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
53 #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
54
55 #define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)
56 #define MCI_MISC_ECC_DDRT 8 /* read from DDRT */
57
58 /*
59 * According to Intel Architecture spec vol 3B,
60 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
61 * memory errors should fit one of these masks:
62 * 000f 0000 1mmm cccc (binary)
63 * 000f 0010 1mmm cccc (binary) [RAM used as cache]
64 * where:
65 * f = Correction Report Filtering Bit. If 1, subsequent errors
66 * won't be shown
67 * mmm = error type
68 * cccc = channel
69 */
70 #define MCACOD_MEM_ERR_MASK 0xef80
71 /*
72 * Errors from either the memory of the 1-level memory system or the
73 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
74 */
75 #define MCACOD_MEM_CTL_ERR 0x80
76 /*
77 * Errors from the 1st level memory (the fast "near" memory as cache)
78 * of the 2-level memory system.
79 */
80 #define MCACOD_EXT_MEM_ERR 0x280
81
82 /*
83 * Each cpu socket contains some pci devices that provide global
84 * information, and also some that are local to each of the two
85 * memory controllers on the die.
86 */
87 struct skx_dev {
88 struct list_head list;
89 u8 bus[4];
90 int seg;
91 struct pci_dev *sad_all;
92 struct pci_dev *util_all;
93 struct pci_dev *uracu; /* for i10nm CPU */
94 struct pci_dev *pcu_cr3; /* for HBM memory detection */
95 u32 mcroute;
96 /*
97 * Some server BIOS may hide certain memory controllers, and the
98 * EDAC driver skips those hidden memory controllers. However, the
99 * ADXL still decodes memory error address using physical memory
100 * controller indices. The mapping table is used to convert the
101 * physical indices (reported by ADXL) to the logical indices
102 * (used the EDAC driver) of present memory controllers during the
103 * error handling process.
104 */
105 u8 mc_mapping[NUM_IMC];
106 struct skx_imc {
107 struct mem_ctl_info *mci;
108 struct pci_dev *mdev; /* for i10nm CPU */
109 void __iomem *mbase; /* for i10nm CPU */
110 int chan_mmio_sz; /* for i10nm CPU */
111 int num_channels; /* channels per memory controller */
112 int num_dimms; /* dimms per channel */
113 bool hbm_mc;
114 u8 mc; /* system wide mc# */
115 u8 lmc; /* socket relative mc# */
116 u8 src_id;
117 struct skx_channel {
118 struct pci_dev *cdev;
119 struct pci_dev *edev;
120 u32 retry_rd_err_log_s;
121 u32 retry_rd_err_log_d;
122 u32 retry_rd_err_log_d2;
123 struct skx_dimm {
124 u8 close_pg;
125 u8 bank_xor_enable;
126 u8 fine_grain_bank;
127 u8 rowbits;
128 u8 colbits;
129 } dimms[NUM_DIMMS];
130 } chan[NUM_CHANNELS];
131 } imc[NUM_IMC];
132 };
133
134 struct skx_pvt {
135 struct skx_imc *imc;
136 };
137
138 enum type {
139 SKX,
140 I10NM,
141 SPR,
142 GNR
143 };
144
145 enum {
146 INDEX_SOCKET,
147 INDEX_MEMCTRL,
148 INDEX_CHANNEL,
149 INDEX_DIMM,
150 INDEX_CS,
151 INDEX_NM_FIRST,
152 INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
153 INDEX_NM_CHANNEL,
154 INDEX_NM_DIMM,
155 INDEX_NM_CS,
156 INDEX_MAX
157 };
158
159 enum error_source {
160 ERR_SRC_1LM,
161 ERR_SRC_2LM_NM,
162 ERR_SRC_2LM_FM,
163 ERR_SRC_NOT_MEMORY,
164 };
165
166 #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
167 #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
168 #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
169 #define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
170
171 struct decoded_addr {
172 struct mce *mce;
173 struct skx_dev *dev;
174 u64 addr;
175 int socket;
176 int imc;
177 int channel;
178 u64 chan_addr;
179 int sktways;
180 int chanways;
181 int dimm;
182 int cs;
183 int rank;
184 int channel_rank;
185 u64 rank_address;
186 int row;
187 int column;
188 int bank_address;
189 int bank_group;
190 bool decoded_by_adxl;
191 };
192
193 struct pci_bdf {
194 u32 bus : 8;
195 u32 dev : 5;
196 u32 fun : 3;
197 };
198
199 struct res_config {
200 enum type type;
201 /* Configuration agent device ID */
202 unsigned int decs_did;
203 /* Default bus number configuration register offset */
204 int busno_cfg_offset;
205 /* DDR memory controllers per socket */
206 int ddr_imc_num;
207 /* DDR channels per DDR memory controller */
208 int ddr_chan_num;
209 /* DDR DIMMs per DDR memory channel */
210 int ddr_dimm_num;
211 /* Per DDR channel memory-mapped I/O size */
212 int ddr_chan_mmio_sz;
213 /* HBM memory controllers per socket */
214 int hbm_imc_num;
215 /* HBM channels per HBM memory controller */
216 int hbm_chan_num;
217 /* HBM DIMMs per HBM memory channel */
218 int hbm_dimm_num;
219 /* Per HBM channel memory-mapped I/O size */
220 int hbm_chan_mmio_sz;
221 bool support_ddr5;
222 /* SAD device BDF */
223 struct pci_bdf sad_all_bdf;
224 /* PCU device BDF */
225 struct pci_bdf pcu_cr3_bdf;
226 /* UTIL device BDF */
227 struct pci_bdf util_all_bdf;
228 /* URACU device BDF */
229 struct pci_bdf uracu_bdf;
230 /* DDR mdev device BDF */
231 struct pci_bdf ddr_mdev_bdf;
232 /* HBM mdev device BDF */
233 struct pci_bdf hbm_mdev_bdf;
234 int sad_all_offset;
235 /* Offsets of retry_rd_err_log registers */
236 u32 *offsets_scrub;
237 u32 *offsets_scrub_hbm0;
238 u32 *offsets_scrub_hbm1;
239 u32 *offsets_demand;
240 u32 *offsets_demand2;
241 u32 *offsets_demand_hbm0;
242 u32 *offsets_demand_hbm1;
243 };
244
245 typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
246 struct res_config *cfg);
247 typedef bool (*skx_decode_f)(struct decoded_addr *res);
248 typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);
249
250 int skx_adxl_get(void);
251 void skx_adxl_put(void);
252 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
253 void skx_set_mem_cfg(bool mem_cfg_2lm);
254 void skx_set_res_cfg(struct res_config *cfg);
255 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc);
256
257 int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
258
259 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
260
261 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);
262
263 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
264 struct skx_imc *imc, int chan, int dimmno,
265 struct res_config *cfg);
266
267 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
268 int chan, int dimmno, const char *mod_str);
269
270 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
271 const char *ctl_name, const char *mod_str,
272 get_dimm_config_f get_dimm_config,
273 struct res_config *cfg);
274
275 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
276 void *data);
277
278 void skx_remove(void);
279
280 #ifdef CONFIG_EDAC_DEBUG
281 void skx_setup_debug(const char *name);
282 void skx_teardown_debug(void);
283 #else
skx_setup_debug(const char * name)284 static inline void skx_setup_debug(const char *name) {}
skx_teardown_debug(void)285 static inline void skx_teardown_debug(void) {}
286 #endif
287
288 #endif /* _SKX_COMM_EDAC_H */
289