1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *
4 * Shared code by both skx_edac and i10nm_edac. Originally split out
5 * from the skx_edac driver.
6 *
7 * This file is linked into both skx_edac and i10nm_edac drivers. In
8 * order to avoid link errors, this file must be like a pure library
9 * without including symbols and defines which would otherwise conflict,
10 * when linked once into a module and into a built-in object, at the
11 * same time. For example, __this_module symbol references when that
12 * file is being linked into a built-in object.
13 *
14 * Copyright (c) 2018, Intel Corporation.
15 */
16
17 #include <linux/acpi.h>
18 #include <linux/dmi.h>
19 #include <linux/adxl.h>
20 #include <acpi/nfit.h>
21 #include <asm/mce.h>
22 #include <asm/uv/uv.h>
23 #include "edac_module.h"
24 #include "skx_common.h"
25
26 static const char * const component_names[] = {
27 [INDEX_SOCKET] = "ProcessorSocketId",
28 [INDEX_MEMCTRL] = "MemoryControllerId",
29 [INDEX_CHANNEL] = "ChannelId",
30 [INDEX_DIMM] = "DimmSlotId",
31 [INDEX_CS] = "ChipSelect",
32 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId",
33 [INDEX_NM_CHANNEL] = "NmChannelId",
34 [INDEX_NM_DIMM] = "NmDimmSlotId",
35 [INDEX_NM_CS] = "NmChipSelect",
36 };
37
38 static int component_indices[ARRAY_SIZE(component_names)];
39 static int adxl_component_count;
40 static const char * const *adxl_component_names;
41 static u64 *adxl_values;
42 static char *adxl_msg;
43 static unsigned long adxl_nm_bitmap;
44
45 static char skx_msg[MSG_SIZE];
46 static skx_decode_f driver_decode;
47 static skx_show_retry_log_f skx_show_retry_rd_err_log;
48 static u64 skx_tolm, skx_tohm;
49 static LIST_HEAD(dev_edac_list);
50 static bool skx_mem_cfg_2lm;
51 static struct res_config *skx_res_cfg;
52
skx_adxl_get(void)53 int skx_adxl_get(void)
54 {
55 const char * const *names;
56 int i, j;
57
58 names = adxl_get_component_names();
59 if (!names) {
60 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
61 return -ENODEV;
62 }
63
64 for (i = 0; i < INDEX_MAX; i++) {
65 for (j = 0; names[j]; j++) {
66 if (!strcmp(component_names[i], names[j])) {
67 component_indices[i] = j;
68
69 if (i >= INDEX_NM_FIRST)
70 adxl_nm_bitmap |= 1 << i;
71
72 break;
73 }
74 }
75
76 if (!names[j] && i < INDEX_NM_FIRST)
77 goto err;
78 }
79
80 if (skx_mem_cfg_2lm) {
81 if (!adxl_nm_bitmap)
82 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
83 else
84 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
85 }
86
87 adxl_component_names = names;
88 while (*names++)
89 adxl_component_count++;
90
91 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
92 GFP_KERNEL);
93 if (!adxl_values) {
94 adxl_component_count = 0;
95 return -ENOMEM;
96 }
97
98 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
99 if (!adxl_msg) {
100 adxl_component_count = 0;
101 kfree(adxl_values);
102 return -ENOMEM;
103 }
104
105 return 0;
106 err:
107 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
108 component_names[i]);
109 for (j = 0; names[j]; j++)
110 skx_printk(KERN_CONT, "%s ", names[j]);
111 skx_printk(KERN_CONT, "\n");
112
113 return -ENODEV;
114 }
115 EXPORT_SYMBOL_GPL(skx_adxl_get);
116
skx_adxl_put(void)117 void skx_adxl_put(void)
118 {
119 kfree(adxl_values);
120 kfree(adxl_msg);
121 }
122 EXPORT_SYMBOL_GPL(skx_adxl_put);
123
skx_init_mc_mapping(struct skx_dev * d)124 static void skx_init_mc_mapping(struct skx_dev *d)
125 {
126 /*
127 * By default, the BIOS presents all memory controllers within each
128 * socket to the EDAC driver. The physical indices are the same as
129 * the logical indices of the memory controllers enumerated by the
130 * EDAC driver.
131 */
132 for (int i = 0; i < NUM_IMC; i++)
133 d->mc_mapping[i] = i;
134 }
135
skx_set_mc_mapping(struct skx_dev * d,u8 pmc,u8 lmc)136 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc)
137 {
138 edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n",
139 pmc, lmc);
140
141 d->mc_mapping[pmc] = lmc;
142 }
143 EXPORT_SYMBOL_GPL(skx_set_mc_mapping);
144
skx_get_mc_mapping(struct skx_dev * d,u8 pmc)145 static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc)
146 {
147 edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n",
148 pmc, d->mc_mapping[pmc]);
149
150 return d->mc_mapping[pmc];
151 }
152
skx_adxl_decode(struct decoded_addr * res,enum error_source err_src)153 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src)
154 {
155 struct skx_dev *d;
156 int i, len = 0;
157
158 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
159 res->addr < BIT_ULL(32))) {
160 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
161 return false;
162 }
163
164 if (adxl_decode(res->addr, adxl_values)) {
165 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
166 return false;
167 }
168
169 /*
170 * GNR with a Flat2LM memory configuration may mistakenly classify
171 * a near-memory error(DDR5) as a far-memory error(CXL), resulting
172 * in the incorrect selection of decoded ADXL components.
173 * To address this, prefetch the decoded far-memory controller ID
174 * and adjust the error source to near-memory if the far-memory
175 * controller ID is invalid.
176 */
177 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) {
178 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
179 if (res->imc == -1) {
180 err_src = ERR_SRC_2LM_NM;
181 edac_dbg(0, "Adjust the error source to near-memory.\n");
182 }
183 }
184
185 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
186 if (err_src == ERR_SRC_2LM_NM) {
187 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
188 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
189 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
190 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
191 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ?
192 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
193 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ?
194 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1;
195 } else {
196 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
197 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
198 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
199 res->cs = (int)adxl_values[component_indices[INDEX_CS]];
200 }
201
202 if (res->imc > NUM_IMC - 1 || res->imc < 0) {
203 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
204 return false;
205 }
206
207 list_for_each_entry(d, &dev_edac_list, list) {
208 if (d->imc[0].src_id == res->socket) {
209 res->dev = d;
210 break;
211 }
212 }
213
214 if (!res->dev) {
215 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
216 res->socket, res->imc);
217 return false;
218 }
219
220 res->imc = skx_get_mc_mapping(d, res->imc);
221
222 for (i = 0; i < adxl_component_count; i++) {
223 if (adxl_values[i] == ~0x0ull)
224 continue;
225
226 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
227 adxl_component_names[i], adxl_values[i]);
228 if (MSG_SIZE - len <= 0)
229 break;
230 }
231
232 res->decoded_by_adxl = true;
233
234 return true;
235 }
236
skx_set_mem_cfg(bool mem_cfg_2lm)237 void skx_set_mem_cfg(bool mem_cfg_2lm)
238 {
239 skx_mem_cfg_2lm = mem_cfg_2lm;
240 }
241 EXPORT_SYMBOL_GPL(skx_set_mem_cfg);
242
skx_set_res_cfg(struct res_config * cfg)243 void skx_set_res_cfg(struct res_config *cfg)
244 {
245 skx_res_cfg = cfg;
246 }
247 EXPORT_SYMBOL_GPL(skx_set_res_cfg);
248
skx_set_decode(skx_decode_f decode,skx_show_retry_log_f show_retry_log)249 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
250 {
251 driver_decode = decode;
252 skx_show_retry_rd_err_log = show_retry_log;
253 }
254 EXPORT_SYMBOL_GPL(skx_set_decode);
255
skx_get_pkg_id(struct skx_dev * d,u8 * id)256 static int skx_get_pkg_id(struct skx_dev *d, u8 *id)
257 {
258 int node;
259 int cpu;
260
261 node = pcibus_to_node(d->util_all->bus);
262 if (numa_valid_node(node)) {
263 for_each_cpu(cpu, cpumask_of_pcibus(d->util_all->bus)) {
264 struct cpuinfo_x86 *c = &cpu_data(cpu);
265
266 if (c->initialized && cpu_to_node(cpu) == node) {
267 *id = c->topo.pkg_id;
268 return 0;
269 }
270 }
271 }
272
273 skx_printk(KERN_ERR, "Failed to get package ID from NUMA information\n");
274 return -ENODEV;
275 }
276
skx_get_src_id(struct skx_dev * d,int off,u8 * id)277 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
278 {
279 u32 reg;
280
281 /*
282 * The 3-bit source IDs in PCI configuration space registers are limited
283 * to 8 unique IDs, and each ID is local to a UPI/QPI domain.
284 *
285 * Source IDs cannot be used to map devices to sockets on UV systems
286 * because they can exceed 8 sockets and have multiple UPI/QPI domains
287 * with identical, repeating source IDs.
288 */
289 if (is_uv_system())
290 return skx_get_pkg_id(d, id);
291
292 if (pci_read_config_dword(d->util_all, off, ®)) {
293 skx_printk(KERN_ERR, "Failed to read src id\n");
294 return -ENODEV;
295 }
296
297 *id = GET_BITFIELD(reg, 12, 14);
298 return 0;
299 }
300 EXPORT_SYMBOL_GPL(skx_get_src_id);
301
get_width(u32 mtr)302 static int get_width(u32 mtr)
303 {
304 switch (GET_BITFIELD(mtr, 8, 9)) {
305 case 0:
306 return DEV_X4;
307 case 1:
308 return DEV_X8;
309 case 2:
310 return DEV_X16;
311 }
312 return DEV_UNKNOWN;
313 }
314
315 /*
316 * We use the per-socket device @cfg->did to count how many sockets are present,
317 * and to detemine which PCI buses are associated with each socket. Allocate
318 * and build the full list of all the skx_dev structures that we need here.
319 */
skx_get_all_bus_mappings(struct res_config * cfg,struct list_head ** list)320 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
321 {
322 struct pci_dev *pdev, *prev;
323 struct skx_dev *d;
324 u32 reg;
325 int ndev = 0;
326
327 prev = NULL;
328 for (;;) {
329 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
330 if (!pdev)
331 break;
332 ndev++;
333 d = kzalloc(sizeof(*d), GFP_KERNEL);
334 if (!d) {
335 pci_dev_put(pdev);
336 return -ENOMEM;
337 }
338
339 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) {
340 kfree(d);
341 pci_dev_put(pdev);
342 skx_printk(KERN_ERR, "Failed to read bus idx\n");
343 return -ENODEV;
344 }
345
346 d->bus[0] = GET_BITFIELD(reg, 0, 7);
347 d->bus[1] = GET_BITFIELD(reg, 8, 15);
348 if (cfg->type == SKX) {
349 d->seg = pci_domain_nr(pdev->bus);
350 d->bus[2] = GET_BITFIELD(reg, 16, 23);
351 d->bus[3] = GET_BITFIELD(reg, 24, 31);
352 } else {
353 d->seg = GET_BITFIELD(reg, 16, 23);
354 }
355
356 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
357 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
358 list_add_tail(&d->list, &dev_edac_list);
359 prev = pdev;
360
361 skx_init_mc_mapping(d);
362 }
363
364 if (list)
365 *list = &dev_edac_list;
366 return ndev;
367 }
368 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings);
369
skx_get_hi_lo(unsigned int did,int off[],u64 * tolm,u64 * tohm)370 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
371 {
372 struct pci_dev *pdev;
373 u32 reg;
374
375 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
376 if (!pdev) {
377 edac_dbg(2, "Can't get tolm/tohm\n");
378 return -ENODEV;
379 }
380
381 if (pci_read_config_dword(pdev, off[0], ®)) {
382 skx_printk(KERN_ERR, "Failed to read tolm\n");
383 goto fail;
384 }
385 skx_tolm = reg;
386
387 if (pci_read_config_dword(pdev, off[1], ®)) {
388 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
389 goto fail;
390 }
391 skx_tohm = reg;
392
393 if (pci_read_config_dword(pdev, off[2], ®)) {
394 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
395 goto fail;
396 }
397 skx_tohm |= (u64)reg << 32;
398
399 pci_dev_put(pdev);
400 *tolm = skx_tolm;
401 *tohm = skx_tohm;
402 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
403 return 0;
404 fail:
405 pci_dev_put(pdev);
406 return -ENODEV;
407 }
408 EXPORT_SYMBOL_GPL(skx_get_hi_lo);
409
skx_get_dimm_attr(u32 reg,int lobit,int hibit,int add,int minval,int maxval,const char * name)410 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
411 int minval, int maxval, const char *name)
412 {
413 u32 val = GET_BITFIELD(reg, lobit, hibit);
414
415 if (val < minval || val > maxval) {
416 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
417 return -EINVAL;
418 }
419 return val + add;
420 }
421
422 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
423 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
424 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
425
skx_get_dimm_info(u32 mtr,u32 mcmtr,u32 amap,struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,struct res_config * cfg)426 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
427 struct skx_imc *imc, int chan, int dimmno,
428 struct res_config *cfg)
429 {
430 int banks, ranks, rows, cols, npages;
431 enum mem_type mtype;
432 u64 size;
433
434 ranks = numrank(mtr);
435 rows = numrow(mtr);
436 cols = imc->hbm_mc ? 6 : numcol(mtr);
437
438 if (imc->hbm_mc) {
439 banks = 32;
440 mtype = MEM_HBM2;
441 } else if (cfg->support_ddr5) {
442 banks = 32;
443 mtype = MEM_DDR5;
444 } else {
445 banks = 16;
446 mtype = MEM_DDR4;
447 }
448
449 /*
450 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
451 */
452 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
453 npages = MiB_TO_PAGES(size);
454
455 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
456 imc->mc, chan, dimmno, size, npages,
457 banks, 1 << ranks, rows, cols);
458
459 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
460 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
461 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
462 imc->chan[chan].dimms[dimmno].rowbits = rows;
463 imc->chan[chan].dimms[dimmno].colbits = cols;
464
465 dimm->nr_pages = npages;
466 dimm->grain = 32;
467 dimm->dtype = get_width(mtr);
468 dimm->mtype = mtype;
469 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
470
471 if (imc->hbm_mc)
472 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
473 imc->src_id, imc->lmc, chan);
474 else
475 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
476 imc->src_id, imc->lmc, chan, dimmno);
477
478 return 1;
479 }
480 EXPORT_SYMBOL_GPL(skx_get_dimm_info);
481
skx_get_nvdimm_info(struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,const char * mod_str)482 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
483 int chan, int dimmno, const char *mod_str)
484 {
485 int smbios_handle;
486 u32 dev_handle;
487 u16 flags;
488 u64 size = 0;
489
490 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
491 imc->src_id, 0);
492
493 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
494 if (smbios_handle == -EOPNOTSUPP) {
495 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
496 goto unknown_size;
497 }
498
499 if (smbios_handle < 0) {
500 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
501 goto unknown_size;
502 }
503
504 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
505 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
506 goto unknown_size;
507 }
508
509 size = dmi_memdev_size(smbios_handle);
510 if (size == ~0ull)
511 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
512 dev_handle, smbios_handle);
513
514 unknown_size:
515 dimm->nr_pages = size >> PAGE_SHIFT;
516 dimm->grain = 32;
517 dimm->dtype = DEV_UNKNOWN;
518 dimm->mtype = MEM_NVDIMM;
519 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
520
521 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
522 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
523
524 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
525 imc->src_id, imc->lmc, chan, dimmno);
526
527 return (size == 0 || size == ~0ull) ? 0 : 1;
528 }
529 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info);
530
skx_register_mci(struct skx_imc * imc,struct pci_dev * pdev,const char * ctl_name,const char * mod_str,get_dimm_config_f get_dimm_config,struct res_config * cfg)531 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
532 const char *ctl_name, const char *mod_str,
533 get_dimm_config_f get_dimm_config,
534 struct res_config *cfg)
535 {
536 struct mem_ctl_info *mci;
537 struct edac_mc_layer layers[2];
538 struct skx_pvt *pvt;
539 int rc;
540
541 /* Allocate a new MC control structure */
542 layers[0].type = EDAC_MC_LAYER_CHANNEL;
543 layers[0].size = NUM_CHANNELS;
544 layers[0].is_virt_csrow = false;
545 layers[1].type = EDAC_MC_LAYER_SLOT;
546 layers[1].size = NUM_DIMMS;
547 layers[1].is_virt_csrow = true;
548 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
549 sizeof(struct skx_pvt));
550
551 if (unlikely(!mci))
552 return -ENOMEM;
553
554 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
555
556 /* Associate skx_dev and mci for future usage */
557 imc->mci = mci;
558 pvt = mci->pvt_info;
559 pvt->imc = imc;
560
561 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
562 imc->src_id, imc->lmc);
563 if (!mci->ctl_name) {
564 rc = -ENOMEM;
565 goto fail0;
566 }
567
568 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
569 if (cfg->support_ddr5)
570 mci->mtype_cap |= MEM_FLAG_DDR5;
571 mci->edac_ctl_cap = EDAC_FLAG_NONE;
572 mci->edac_cap = EDAC_FLAG_NONE;
573 mci->mod_name = mod_str;
574 mci->dev_name = pci_name(pdev);
575 mci->ctl_page_to_phys = NULL;
576
577 rc = get_dimm_config(mci, cfg);
578 if (rc < 0)
579 goto fail;
580
581 /* Record ptr to the generic device */
582 mci->pdev = &pdev->dev;
583
584 /* Add this new MC control structure to EDAC's list of MCs */
585 if (unlikely(edac_mc_add_mc(mci))) {
586 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
587 rc = -EINVAL;
588 goto fail;
589 }
590
591 return 0;
592
593 fail:
594 kfree(mci->ctl_name);
595 fail0:
596 edac_mc_free(mci);
597 imc->mci = NULL;
598 return rc;
599 }
600 EXPORT_SYMBOL_GPL(skx_register_mci);
601
skx_unregister_mci(struct skx_imc * imc)602 static void skx_unregister_mci(struct skx_imc *imc)
603 {
604 struct mem_ctl_info *mci = imc->mci;
605
606 if (!mci)
607 return;
608
609 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
610
611 /* Remove MC sysfs nodes */
612 edac_mc_del_mc(mci->pdev);
613
614 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
615 kfree(mci->ctl_name);
616 edac_mc_free(mci);
617 }
618
skx_mce_output_error(struct mem_ctl_info * mci,const struct mce * m,struct decoded_addr * res)619 static void skx_mce_output_error(struct mem_ctl_info *mci,
620 const struct mce *m,
621 struct decoded_addr *res)
622 {
623 enum hw_event_mc_err_type tp_event;
624 char *optype;
625 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
626 bool overflow = GET_BITFIELD(m->status, 62, 62);
627 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
628 bool scrub_err = false;
629 bool recoverable;
630 int len;
631 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
632 u32 mscod = GET_BITFIELD(m->status, 16, 31);
633 u32 errcode = GET_BITFIELD(m->status, 0, 15);
634 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
635
636 recoverable = GET_BITFIELD(m->status, 56, 56);
637
638 if (uncorrected_error) {
639 core_err_cnt = 1;
640 if (ripv) {
641 tp_event = HW_EVENT_ERR_UNCORRECTED;
642 } else {
643 tp_event = HW_EVENT_ERR_FATAL;
644 }
645 } else {
646 tp_event = HW_EVENT_ERR_CORRECTED;
647 }
648
649 switch (optypenum) {
650 case 0:
651 optype = "generic undef request error";
652 break;
653 case 1:
654 optype = "memory read error";
655 break;
656 case 2:
657 optype = "memory write error";
658 break;
659 case 3:
660 optype = "addr/cmd error";
661 break;
662 case 4:
663 optype = "memory scrubbing error";
664 scrub_err = true;
665 break;
666 default:
667 optype = "reserved";
668 break;
669 }
670
671 if (res->decoded_by_adxl) {
672 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
673 overflow ? " OVERFLOW" : "",
674 (uncorrected_error && recoverable) ? " recoverable" : "",
675 mscod, errcode, adxl_msg);
676 } else {
677 len = snprintf(skx_msg, MSG_SIZE,
678 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x",
679 overflow ? " OVERFLOW" : "",
680 (uncorrected_error && recoverable) ? " recoverable" : "",
681 mscod, errcode,
682 res->socket, res->imc, res->rank,
683 res->row, res->column, res->bank_address, res->bank_group);
684 }
685
686 if (skx_show_retry_rd_err_log)
687 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err);
688
689 edac_dbg(0, "%s\n", skx_msg);
690
691 /* Call the helper to output message */
692 edac_mc_handle_error(tp_event, mci, core_err_cnt,
693 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
694 res->channel, res->dimm, -1,
695 optype, skx_msg);
696 }
697
skx_error_source(const struct mce * m)698 static enum error_source skx_error_source(const struct mce *m)
699 {
700 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;
701
702 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR)
703 return ERR_SRC_NOT_MEMORY;
704
705 if (!skx_mem_cfg_2lm)
706 return ERR_SRC_1LM;
707
708 if (errcode == MCACOD_EXT_MEM_ERR)
709 return ERR_SRC_2LM_NM;
710
711 return ERR_SRC_2LM_FM;
712 }
713
skx_mce_check_error(struct notifier_block * nb,unsigned long val,void * data)714 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
715 void *data)
716 {
717 struct mce *mce = (struct mce *)data;
718 enum error_source err_src;
719 struct decoded_addr res;
720 struct mem_ctl_info *mci;
721 char *type;
722
723 if (mce->kflags & MCE_HANDLED_CEC)
724 return NOTIFY_DONE;
725
726 err_src = skx_error_source(mce);
727
728 /* Ignore unless this is memory related with an address */
729 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV))
730 return NOTIFY_DONE;
731
732 memset(&res, 0, sizeof(res));
733 res.mce = mce;
734 res.addr = mce->addr & MCI_ADDR_PHYSADDR;
735 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) {
736 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank);
737 return NOTIFY_DONE;
738 }
739
740 /* Try driver decoder first */
741 if (!(driver_decode && driver_decode(&res))) {
742 /* Then try firmware decoder (ACPI DSM methods) */
743 if (!(adxl_component_count && skx_adxl_decode(&res, err_src)))
744 return NOTIFY_DONE;
745 }
746
747 mci = res.dev->imc[res.imc].mci;
748
749 if (!mci)
750 return NOTIFY_DONE;
751
752 if (mce->mcgstatus & MCG_STATUS_MCIP)
753 type = "Exception";
754 else
755 type = "Event";
756
757 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
758
759 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
760 "Bank %d: 0x%llx\n", mce->extcpu, type,
761 mce->mcgstatus, mce->bank, mce->status);
762 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
763 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
764 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
765
766 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
767 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
768 mce->time, mce->socketid, mce->apicid);
769
770 skx_mce_output_error(mci, mce, &res);
771
772 mce->kflags |= MCE_HANDLED_EDAC;
773 return NOTIFY_DONE;
774 }
775 EXPORT_SYMBOL_GPL(skx_mce_check_error);
776
skx_remove(void)777 void skx_remove(void)
778 {
779 int i, j;
780 struct skx_dev *d, *tmp;
781
782 edac_dbg(0, "\n");
783
784 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
785 list_del(&d->list);
786 for (i = 0; i < NUM_IMC; i++) {
787 if (d->imc[i].mci)
788 skx_unregister_mci(&d->imc[i]);
789
790 if (d->imc[i].mdev)
791 pci_dev_put(d->imc[i].mdev);
792
793 if (d->imc[i].mbase)
794 iounmap(d->imc[i].mbase);
795
796 for (j = 0; j < NUM_CHANNELS; j++) {
797 if (d->imc[i].chan[j].cdev)
798 pci_dev_put(d->imc[i].chan[j].cdev);
799 }
800 }
801 if (d->util_all)
802 pci_dev_put(d->util_all);
803 if (d->pcu_cr3)
804 pci_dev_put(d->pcu_cr3);
805 if (d->sad_all)
806 pci_dev_put(d->sad_all);
807 if (d->uracu)
808 pci_dev_put(d->uracu);
809
810 kfree(d);
811 }
812 }
813 EXPORT_SYMBOL_GPL(skx_remove);
814
815 #ifdef CONFIG_EDAC_DEBUG
816 /*
817 * Debug feature.
818 * Exercise the address decode logic by writing an address to
819 * /sys/kernel/debug/edac/{skx,i10nm}_test/addr.
820 */
821 static struct dentry *skx_test;
822
debugfs_u64_set(void * data,u64 val)823 static int debugfs_u64_set(void *data, u64 val)
824 {
825 struct mce m;
826
827 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
828
829 memset(&m, 0, sizeof(m));
830 /* ADDRV + MemRd + Unknown channel */
831 m.status = MCI_STATUS_ADDRV + 0x90;
832 /* One corrected error */
833 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
834 m.addr = val;
835 skx_mce_check_error(NULL, 0, &m);
836
837 return 0;
838 }
839 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
840
skx_setup_debug(const char * name)841 void skx_setup_debug(const char *name)
842 {
843 skx_test = edac_debugfs_create_dir(name);
844 if (!skx_test)
845 return;
846
847 if (!edac_debugfs_create_file("addr", 0200, skx_test,
848 NULL, &fops_u64_wo)) {
849 debugfs_remove(skx_test);
850 skx_test = NULL;
851 }
852 }
853 EXPORT_SYMBOL_GPL(skx_setup_debug);
854
skx_teardown_debug(void)855 void skx_teardown_debug(void)
856 {
857 debugfs_remove_recursive(skx_test);
858 }
859 EXPORT_SYMBOL_GPL(skx_teardown_debug);
860 #endif /*CONFIG_EDAC_DEBUG*/
861
862 MODULE_LICENSE("GPL v2");
863 MODULE_AUTHOR("Tony Luck");
864 MODULE_DESCRIPTION("MC Driver for Intel server processors");
865