1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW ACCELERATOR defines 6 * 7 * Copyright (c) 2015 Texas Instruments Incorporated 8 */ 9 #ifndef __OMAP_AES_H__ 10 #define __OMAP_AES_H__ 11 12 #include <crypto/aes.h> 13 14 #define DST_MAXBURST 4 15 #define DMA_MIN (DST_MAXBURST * sizeof(u32)) 16 17 /* 18 * OMAP TRM gives bitfields as start:end, where start is the higher bit 19 * number. For example 7:0 20 */ 21 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 22 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 23 24 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 25 (((x) ^ 0x01) * 0x04)) 26 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 27 28 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 29 #define AES_REG_CTRL_CONTEXT_READY BIT(31) 30 #define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7) 31 #define AES_REG_CTRL_CTR_WIDTH_32 0 32 #define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) 33 #define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) 34 #define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7) 35 #define AES_REG_CTRL_GCM GENMASK(17, 16) 36 #define AES_REG_CTRL_CTR BIT(6) 37 #define AES_REG_CTRL_CBC BIT(5) 38 #define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3) 39 #define AES_REG_CTRL_DIRECTION BIT(2) 40 #define AES_REG_CTRL_INPUT_READY BIT(1) 41 #define AES_REG_CTRL_OUTPUT_READY BIT(0) 42 #define AES_REG_CTRL_MASK GENMASK(24, 2) 43 44 #define AES_REG_C_LEN_0 0x54 45 #define AES_REG_C_LEN_1 0x58 46 #define AES_REG_A_LEN 0x5C 47 48 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 49 #define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04)) 50 51 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) 52 53 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 54 #define AES_REG_MASK_SIDLE BIT(6) 55 #define AES_REG_MASK_START BIT(5) 56 #define AES_REG_MASK_DMA_OUT_EN BIT(3) 57 #define AES_REG_MASK_DMA_IN_EN BIT(2) 58 #define AES_REG_MASK_SOFTRESET BIT(1) 59 #define AES_REG_AUTOIDLE BIT(0) 60 61 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) 62 63 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 64 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 65 #define AES_REG_IRQ_DATA_IN BIT(1) 66 #define AES_REG_IRQ_DATA_OUT BIT(2) 67 #define DEFAULT_TIMEOUT (5 * HZ) 68 69 #define DEFAULT_AUTOSUSPEND_DELAY 1000 70 71 #define FLAGS_MODE_MASK 0x001f 72 #define FLAGS_ENCRYPT BIT(0) 73 #define FLAGS_CBC BIT(1) 74 #define FLAGS_CTR BIT(2) 75 #define FLAGS_GCM BIT(3) 76 #define FLAGS_RFC4106_GCM BIT(4) 77 78 #define FLAGS_INIT BIT(5) 79 #define FLAGS_FAST BIT(6) 80 81 #define FLAGS_IN_DATA_ST_SHIFT 8 82 #define FLAGS_OUT_DATA_ST_SHIFT 10 83 #define FLAGS_ASSOC_DATA_ST_SHIFT 12 84 85 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) 86 87 struct omap_aes_gcm_result { 88 struct completion completion; 89 int err; 90 }; 91 92 struct omap_aes_ctx { 93 int keylen; 94 u32 key[AES_KEYSIZE_256 / sizeof(u32)]; 95 u8 nonce[4]; 96 struct crypto_skcipher *fallback; 97 }; 98 99 struct omap_aes_gcm_ctx { 100 struct omap_aes_ctx octx; 101 struct crypto_aes_ctx actx; 102 }; 103 104 struct omap_aes_reqctx { 105 struct omap_aes_dev *dd; 106 unsigned long mode; 107 u8 iv[AES_BLOCK_SIZE]; 108 u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)]; 109 struct skcipher_request fallback_req; // keep at the end 110 }; 111 112 #define OMAP_AES_QUEUE_LENGTH 1 113 #define OMAP_AES_CACHE_SIZE 0 114 115 struct omap_aes_algs_info { 116 struct skcipher_engine_alg *algs_list; 117 unsigned int size; 118 unsigned int registered; 119 }; 120 121 struct omap_aes_aead_algs { 122 struct aead_engine_alg *algs_list; 123 unsigned int size; 124 unsigned int registered; 125 }; 126 127 struct omap_aes_pdata { 128 struct omap_aes_algs_info *algs_info; 129 unsigned int algs_info_size; 130 struct omap_aes_aead_algs *aead_algs_info; 131 132 void (*trigger)(struct omap_aes_dev *dd, int length); 133 134 u32 key_ofs; 135 u32 iv_ofs; 136 u32 ctrl_ofs; 137 u32 data_ofs; 138 u32 rev_ofs; 139 u32 mask_ofs; 140 u32 irq_enable_ofs; 141 u32 irq_status_ofs; 142 143 u32 dma_enable_in; 144 u32 dma_enable_out; 145 u32 dma_start; 146 147 u32 major_mask; 148 u32 major_shift; 149 u32 minor_mask; 150 u32 minor_shift; 151 }; 152 153 struct omap_aes_dev { 154 struct list_head list; 155 unsigned long phys_base; 156 void __iomem *io_base; 157 struct omap_aes_ctx *ctx; 158 struct device *dev; 159 unsigned long flags; 160 int err; 161 162 struct tasklet_struct done_task; 163 struct aead_queue aead_queue; 164 spinlock_t lock; 165 166 struct skcipher_request *req; 167 struct aead_request *aead_req; 168 struct crypto_engine *engine; 169 170 /* 171 * total is used by PIO mode for book keeping so introduce 172 * variable total_save as need it to calc page_order 173 */ 174 size_t total; 175 size_t total_save; 176 size_t assoc_len; 177 size_t authsize; 178 179 struct scatterlist *in_sg; 180 struct scatterlist *out_sg; 181 182 /* Buffers for copying for unaligned cases */ 183 struct scatterlist in_sgl[2]; 184 struct scatterlist out_sgl; 185 struct scatterlist *orig_out; 186 187 unsigned int in_sg_offset; 188 unsigned int out_sg_offset; 189 struct dma_chan *dma_lch_in; 190 struct dma_chan *dma_lch_out; 191 int in_sg_len; 192 int out_sg_len; 193 int pio_only; 194 const struct omap_aes_pdata *pdata; 195 }; 196 197 u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset); 198 void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value); 199 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx); 200 int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, 201 unsigned int keylen); 202 int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key, 203 unsigned int keylen); 204 int omap_aes_gcm_encrypt(struct aead_request *req); 205 int omap_aes_gcm_decrypt(struct aead_request *req); 206 int omap_aes_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize); 207 int omap_aes_4106gcm_encrypt(struct aead_request *req); 208 int omap_aes_4106gcm_decrypt(struct aead_request *req); 209 int omap_aes_4106gcm_setauthsize(struct crypto_aead *parent, 210 unsigned int authsize); 211 int omap_aes_gcm_cra_init(struct crypto_aead *tfm); 212 int omap_aes_write_ctrl(struct omap_aes_dev *dd); 213 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd); 214 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd); 215 void omap_aes_gcm_dma_out_callback(void *data); 216 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd); 217 int omap_aes_gcm_crypt_req(struct crypto_engine *engine, void *areq); 218 219 #endif 220