1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AMD Secure Processor device driver
4 *
5 * Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <[email protected]>
8 * Author: Gary R Hook <[email protected]>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/device.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/kthread.h>
19 #include <linux/sched.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/ccp.h>
24
25 #include "ccp-dev.h"
26 #include "psp-dev.h"
27 #include "hsti.h"
28
29 /* used for version string AA.BB.CC.DD */
30 #define AA GENMASK(31, 24)
31 #define BB GENMASK(23, 16)
32 #define CC GENMASK(15, 8)
33 #define DD GENMASK(7, 0)
34
35 #define MSIX_VECTORS 2
36
37 struct sp_pci {
38 int msix_count;
39 struct msix_entry msix_entry[MSIX_VECTORS];
40 };
41 static struct sp_device *sp_dev_master;
42
43 #define version_attribute_show(name, _offset) \
44 static ssize_t name##_show(struct device *d, struct device_attribute *attr, \
45 char *buf) \
46 { \
47 struct sp_device *sp = dev_get_drvdata(d); \
48 struct psp_device *psp = sp->psp_data; \
49 unsigned int val = ioread32(psp->io_regs + _offset); \
50 return sysfs_emit(buf, "%02lx.%02lx.%02lx.%02lx\n", \
51 FIELD_GET(AA, val), \
52 FIELD_GET(BB, val), \
53 FIELD_GET(CC, val), \
54 FIELD_GET(DD, val)); \
55 }
56
57 version_attribute_show(bootloader_version, psp->vdata->bootloader_info_reg)
58 static DEVICE_ATTR_RO(bootloader_version);
59 version_attribute_show(tee_version, psp->vdata->tee->info_reg)
60 static DEVICE_ATTR_RO(tee_version);
61
62 static struct attribute *psp_firmware_attrs[] = {
63 &dev_attr_bootloader_version.attr,
64 &dev_attr_tee_version.attr,
65 NULL,
66 };
67
psp_firmware_is_visible(struct kobject * kobj,struct attribute * attr,int idx)68 static umode_t psp_firmware_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
69 {
70 struct device *dev = kobj_to_dev(kobj);
71 struct sp_device *sp = dev_get_drvdata(dev);
72 struct psp_device *psp = sp->psp_data;
73 unsigned int val = 0xffffffff;
74
75 if (!psp)
76 return 0;
77
78 if (attr == &dev_attr_bootloader_version.attr &&
79 psp->vdata->bootloader_info_reg)
80 val = ioread32(psp->io_regs + psp->vdata->bootloader_info_reg);
81
82 if (attr == &dev_attr_tee_version.attr && psp->capability.tee &&
83 psp->vdata->tee->info_reg)
84 val = ioread32(psp->io_regs + psp->vdata->tee->info_reg);
85
86 /* If platform disallows accessing this register it will be all f's */
87 if (val != 0xffffffff)
88 return 0444;
89
90 return 0;
91 }
92
93 static struct attribute_group psp_firmware_attr_group = {
94 .attrs = psp_firmware_attrs,
95 .is_visible = psp_firmware_is_visible,
96 };
97
98 static const struct attribute_group *psp_groups[] = {
99 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
100 &psp_security_attr_group,
101 #endif
102 &psp_firmware_attr_group,
103 NULL,
104 };
105
sp_get_msix_irqs(struct sp_device * sp)106 static int sp_get_msix_irqs(struct sp_device *sp)
107 {
108 struct sp_pci *sp_pci = sp->dev_specific;
109 struct device *dev = sp->dev;
110 struct pci_dev *pdev = to_pci_dev(dev);
111 int v, ret;
112
113 for (v = 0; v < ARRAY_SIZE(sp_pci->msix_entry); v++)
114 sp_pci->msix_entry[v].entry = v;
115
116 ret = pci_enable_msix_range(pdev, sp_pci->msix_entry, 1, v);
117 if (ret < 0)
118 return ret;
119
120 sp_pci->msix_count = ret;
121 sp->use_tasklet = true;
122
123 sp->psp_irq = sp_pci->msix_entry[0].vector;
124 sp->ccp_irq = (sp_pci->msix_count > 1) ? sp_pci->msix_entry[1].vector
125 : sp_pci->msix_entry[0].vector;
126 return 0;
127 }
128
sp_get_msi_irq(struct sp_device * sp)129 static int sp_get_msi_irq(struct sp_device *sp)
130 {
131 struct device *dev = sp->dev;
132 struct pci_dev *pdev = to_pci_dev(dev);
133 int ret;
134
135 ret = pci_enable_msi(pdev);
136 if (ret)
137 return ret;
138
139 sp->ccp_irq = pdev->irq;
140 sp->psp_irq = pdev->irq;
141
142 return 0;
143 }
144
sp_get_irqs(struct sp_device * sp)145 static int sp_get_irqs(struct sp_device *sp)
146 {
147 struct device *dev = sp->dev;
148 int ret;
149
150 ret = sp_get_msix_irqs(sp);
151 if (!ret)
152 return 0;
153
154 /* Couldn't get MSI-X vectors, try MSI */
155 dev_notice(dev, "could not enable MSI-X (%d), trying MSI\n", ret);
156 ret = sp_get_msi_irq(sp);
157 if (!ret)
158 return 0;
159
160 /* Couldn't get MSI interrupt */
161 dev_notice(dev, "could not enable MSI (%d)\n", ret);
162
163 return ret;
164 }
165
sp_free_irqs(struct sp_device * sp)166 static void sp_free_irqs(struct sp_device *sp)
167 {
168 struct sp_pci *sp_pci = sp->dev_specific;
169 struct device *dev = sp->dev;
170 struct pci_dev *pdev = to_pci_dev(dev);
171
172 if (sp_pci->msix_count)
173 pci_disable_msix(pdev);
174 else if (sp->psp_irq)
175 pci_disable_msi(pdev);
176
177 sp->ccp_irq = 0;
178 sp->psp_irq = 0;
179 }
180
sp_pci_is_master(struct sp_device * sp)181 static bool sp_pci_is_master(struct sp_device *sp)
182 {
183 struct device *dev_cur, *dev_new;
184 struct pci_dev *pdev_cur, *pdev_new;
185
186 dev_new = sp->dev;
187 dev_cur = sp_dev_master->dev;
188
189 pdev_new = to_pci_dev(dev_new);
190 pdev_cur = to_pci_dev(dev_cur);
191
192 if (pci_domain_nr(pdev_new->bus) != pci_domain_nr(pdev_cur->bus))
193 return pci_domain_nr(pdev_new->bus) < pci_domain_nr(pdev_cur->bus);
194
195 if (pdev_new->bus->number != pdev_cur->bus->number)
196 return pdev_new->bus->number < pdev_cur->bus->number;
197
198 if (PCI_SLOT(pdev_new->devfn) != PCI_SLOT(pdev_cur->devfn))
199 return PCI_SLOT(pdev_new->devfn) < PCI_SLOT(pdev_cur->devfn);
200
201 if (PCI_FUNC(pdev_new->devfn) != PCI_FUNC(pdev_cur->devfn))
202 return PCI_FUNC(pdev_new->devfn) < PCI_FUNC(pdev_cur->devfn);
203
204 return false;
205 }
206
psp_set_master(struct sp_device * sp)207 static void psp_set_master(struct sp_device *sp)
208 {
209 if (!sp_dev_master) {
210 sp_dev_master = sp;
211 return;
212 }
213
214 if (sp_pci_is_master(sp))
215 sp_dev_master = sp;
216 }
217
psp_get_master(void)218 static struct sp_device *psp_get_master(void)
219 {
220 return sp_dev_master;
221 }
222
psp_clear_master(struct sp_device * sp)223 static void psp_clear_master(struct sp_device *sp)
224 {
225 if (sp == sp_dev_master) {
226 sp_dev_master = NULL;
227 dev_dbg(sp->dev, "Cleared sp_dev_master\n");
228 }
229 }
230
sp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)231 static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
232 {
233 struct sp_device *sp;
234 struct sp_pci *sp_pci;
235 struct device *dev = &pdev->dev;
236 void __iomem * const *iomap_table;
237 int bar_mask;
238 int ret;
239
240 ret = -ENOMEM;
241 sp = sp_alloc_struct(dev);
242 if (!sp)
243 goto e_err;
244
245 sp_pci = devm_kzalloc(dev, sizeof(*sp_pci), GFP_KERNEL);
246 if (!sp_pci)
247 goto e_err;
248
249 sp->dev_specific = sp_pci;
250 sp->dev_vdata = (struct sp_dev_vdata *)id->driver_data;
251 if (!sp->dev_vdata) {
252 ret = -ENODEV;
253 dev_err(dev, "missing driver data\n");
254 goto e_err;
255 }
256
257 ret = pcim_enable_device(pdev);
258 if (ret) {
259 dev_err(dev, "pcim_enable_device failed (%d)\n", ret);
260 goto e_err;
261 }
262
263 bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
264 ret = pcim_iomap_regions(pdev, bar_mask, "ccp");
265 if (ret) {
266 dev_err(dev, "pcim_iomap_regions failed (%d)\n", ret);
267 goto e_err;
268 }
269
270 iomap_table = pcim_iomap_table(pdev);
271 if (!iomap_table) {
272 dev_err(dev, "pcim_iomap_table failed\n");
273 ret = -ENOMEM;
274 goto e_err;
275 }
276
277 sp->io_map = iomap_table[sp->dev_vdata->bar];
278 if (!sp->io_map) {
279 dev_err(dev, "ioremap failed\n");
280 ret = -ENOMEM;
281 goto e_err;
282 }
283
284 ret = sp_get_irqs(sp);
285 if (ret)
286 goto e_err;
287
288 pci_set_master(pdev);
289 sp->set_psp_master_device = psp_set_master;
290 sp->get_psp_master_device = psp_get_master;
291 sp->clear_psp_master_device = psp_clear_master;
292
293 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
294 if (ret) {
295 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
296 if (ret) {
297 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",
298 ret);
299 goto free_irqs;
300 }
301 }
302
303 dev_set_drvdata(dev, sp);
304
305 ret = sp_init(sp);
306 if (ret)
307 goto free_irqs;
308
309 return 0;
310
311 free_irqs:
312 sp_free_irqs(sp);
313 e_err:
314 dev_notice(dev, "initialization failed\n");
315 return ret;
316 }
317
sp_pci_shutdown(struct pci_dev * pdev)318 static void sp_pci_shutdown(struct pci_dev *pdev)
319 {
320 struct device *dev = &pdev->dev;
321 struct sp_device *sp = dev_get_drvdata(dev);
322
323 if (!sp)
324 return;
325
326 sp_destroy(sp);
327 }
328
sp_pci_remove(struct pci_dev * pdev)329 static void sp_pci_remove(struct pci_dev *pdev)
330 {
331 struct device *dev = &pdev->dev;
332 struct sp_device *sp = dev_get_drvdata(dev);
333
334 if (!sp)
335 return;
336
337 sp_destroy(sp);
338
339 sp_free_irqs(sp);
340 }
341
sp_pci_suspend(struct device * dev)342 static int __maybe_unused sp_pci_suspend(struct device *dev)
343 {
344 struct sp_device *sp = dev_get_drvdata(dev);
345
346 return sp_suspend(sp);
347 }
348
sp_pci_resume(struct device * dev)349 static int __maybe_unused sp_pci_resume(struct device *dev)
350 {
351 struct sp_device *sp = dev_get_drvdata(dev);
352
353 return sp_resume(sp);
354 }
355
356 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
357 static const struct sev_vdata sevv1 = {
358 .cmdresp_reg = 0x10580, /* C2PMSG_32 */
359 .cmdbuff_addr_lo_reg = 0x105e0, /* C2PMSG_56 */
360 .cmdbuff_addr_hi_reg = 0x105e4, /* C2PMSG_57 */
361 };
362
363 static const struct sev_vdata sevv2 = {
364 .cmdresp_reg = 0x10980, /* C2PMSG_32 */
365 .cmdbuff_addr_lo_reg = 0x109e0, /* C2PMSG_56 */
366 .cmdbuff_addr_hi_reg = 0x109e4, /* C2PMSG_57 */
367 };
368
369 static const struct tee_vdata teev1 = {
370 .ring_wptr_reg = 0x10550, /* C2PMSG_20 */
371 .ring_rptr_reg = 0x10554, /* C2PMSG_21 */
372 .info_reg = 0x109e8, /* C2PMSG_58 */
373 };
374
375 static const struct tee_vdata teev2 = {
376 .ring_wptr_reg = 0x10950, /* C2PMSG_20 */
377 .ring_rptr_reg = 0x10954, /* C2PMSG_21 */
378 };
379
380 static const struct platform_access_vdata pa_v1 = {
381 .cmdresp_reg = 0x10570, /* C2PMSG_28 */
382 .cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */
383 .cmdbuff_addr_hi_reg = 0x10578, /* C2PMSG_30 */
384 .doorbell_button_reg = 0x10a24, /* C2PMSG_73 */
385 .doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
386 };
387
388 static const struct platform_access_vdata pa_v2 = {
389 .doorbell_button_reg = 0x10a24, /* C2PMSG_73 */
390 .doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
391 };
392
393 static const struct psp_vdata pspv1 = {
394 .sev = &sevv1,
395 .bootloader_info_reg = 0x105ec, /* C2PMSG_59 */
396 .feature_reg = 0x105fc, /* C2PMSG_63 */
397 .inten_reg = 0x10610, /* P2CMSG_INTEN */
398 .intsts_reg = 0x10614, /* P2CMSG_INTSTS */
399 };
400
401 static const struct psp_vdata pspv2 = {
402 .sev = &sevv2,
403 .platform_access = &pa_v1,
404 .bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
405 .feature_reg = 0x109fc, /* C2PMSG_63 */
406 .inten_reg = 0x10690, /* P2CMSG_INTEN */
407 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
408 .platform_features = PLATFORM_FEATURE_HSTI,
409 };
410
411 static const struct psp_vdata pspv3 = {
412 .tee = &teev1,
413 .platform_access = &pa_v1,
414 .cmdresp_reg = 0x10544, /* C2PMSG_17 */
415 .cmdbuff_addr_lo_reg = 0x10548, /* C2PMSG_18 */
416 .cmdbuff_addr_hi_reg = 0x1054c, /* C2PMSG_19 */
417 .bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
418 .feature_reg = 0x109fc, /* C2PMSG_63 */
419 .inten_reg = 0x10690, /* P2CMSG_INTEN */
420 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
421 .platform_features = PLATFORM_FEATURE_DBC |
422 PLATFORM_FEATURE_HSTI,
423 };
424
425 static const struct psp_vdata pspv4 = {
426 .sev = &sevv2,
427 .tee = &teev1,
428 .cmdresp_reg = 0x10544, /* C2PMSG_17 */
429 .cmdbuff_addr_lo_reg = 0x10548, /* C2PMSG_18 */
430 .cmdbuff_addr_hi_reg = 0x1054c, /* C2PMSG_19 */
431 .bootloader_info_reg = 0x109ec, /* C2PMSG_59 */
432 .feature_reg = 0x109fc, /* C2PMSG_63 */
433 .inten_reg = 0x10690, /* P2CMSG_INTEN */
434 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
435 };
436
437 static const struct psp_vdata pspv5 = {
438 .tee = &teev2,
439 .platform_access = &pa_v2,
440 .cmdresp_reg = 0x10944, /* C2PMSG_17 */
441 .cmdbuff_addr_lo_reg = 0x10948, /* C2PMSG_18 */
442 .cmdbuff_addr_hi_reg = 0x1094c, /* C2PMSG_19 */
443 .feature_reg = 0x109fc, /* C2PMSG_63 */
444 .inten_reg = 0x10510, /* P2CMSG_INTEN */
445 .intsts_reg = 0x10514, /* P2CMSG_INTSTS */
446 };
447
448 static const struct psp_vdata pspv6 = {
449 .sev = &sevv2,
450 .tee = &teev2,
451 .cmdresp_reg = 0x10944, /* C2PMSG_17 */
452 .cmdbuff_addr_lo_reg = 0x10948, /* C2PMSG_18 */
453 .cmdbuff_addr_hi_reg = 0x1094c, /* C2PMSG_19 */
454 .feature_reg = 0x109fc, /* C2PMSG_63 */
455 .inten_reg = 0x10510, /* P2CMSG_INTEN */
456 .intsts_reg = 0x10514, /* P2CMSG_INTSTS */
457 };
458
459 #endif
460
461 static const struct sp_dev_vdata dev_vdata[] = {
462 { /* 0 */
463 .bar = 2,
464 #ifdef CONFIG_CRYPTO_DEV_SP_CCP
465 .ccp_vdata = &ccpv3,
466 #endif
467 },
468 { /* 1 */
469 .bar = 2,
470 #ifdef CONFIG_CRYPTO_DEV_SP_CCP
471 .ccp_vdata = &ccpv5a,
472 #endif
473 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
474 .psp_vdata = &pspv1,
475 #endif
476 },
477 { /* 2 */
478 .bar = 2,
479 #ifdef CONFIG_CRYPTO_DEV_SP_CCP
480 .ccp_vdata = &ccpv5b,
481 #endif
482 },
483 { /* 3 */
484 .bar = 2,
485 #ifdef CONFIG_CRYPTO_DEV_SP_CCP
486 .ccp_vdata = &ccpv5a,
487 #endif
488 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
489 .psp_vdata = &pspv2,
490 #endif
491 },
492 { /* 4 */
493 .bar = 2,
494 #ifdef CONFIG_CRYPTO_DEV_SP_CCP
495 .ccp_vdata = &ccpv5a,
496 #endif
497 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
498 .psp_vdata = &pspv3,
499 #endif
500 },
501 { /* 5 */
502 .bar = 2,
503 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
504 .psp_vdata = &pspv4,
505 #endif
506 },
507 { /* 6 */
508 .bar = 2,
509 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
510 .psp_vdata = &pspv3,
511 #endif
512 },
513 { /* 7 */
514 .bar = 2,
515 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
516 .psp_vdata = &pspv5,
517 #endif
518 },
519 { /* 8 */
520 .bar = 2,
521 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
522 .psp_vdata = &pspv6,
523 #endif
524 },
525 };
526 static const struct pci_device_id sp_pci_table[] = {
527 { PCI_VDEVICE(AMD, 0x1537), (kernel_ulong_t)&dev_vdata[0] },
528 { PCI_VDEVICE(AMD, 0x1456), (kernel_ulong_t)&dev_vdata[1] },
529 { PCI_VDEVICE(AMD, 0x1468), (kernel_ulong_t)&dev_vdata[2] },
530 { PCI_VDEVICE(AMD, 0x1486), (kernel_ulong_t)&dev_vdata[3] },
531 { PCI_VDEVICE(AMD, 0x15DF), (kernel_ulong_t)&dev_vdata[4] },
532 { PCI_VDEVICE(AMD, 0x14CA), (kernel_ulong_t)&dev_vdata[5] },
533 { PCI_VDEVICE(AMD, 0x15C7), (kernel_ulong_t)&dev_vdata[6] },
534 { PCI_VDEVICE(AMD, 0x1649), (kernel_ulong_t)&dev_vdata[6] },
535 { PCI_VDEVICE(AMD, 0x17E0), (kernel_ulong_t)&dev_vdata[7] },
536 { PCI_VDEVICE(AMD, 0x156E), (kernel_ulong_t)&dev_vdata[8] },
537 /* Last entry must be zero */
538 { 0, }
539 };
540 MODULE_DEVICE_TABLE(pci, sp_pci_table);
541
542 static SIMPLE_DEV_PM_OPS(sp_pci_pm_ops, sp_pci_suspend, sp_pci_resume);
543
544 static struct pci_driver sp_pci_driver = {
545 .name = "ccp",
546 .id_table = sp_pci_table,
547 .probe = sp_pci_probe,
548 .remove = sp_pci_remove,
549 .shutdown = sp_pci_shutdown,
550 .driver.pm = &sp_pci_pm_ops,
551 .dev_groups = psp_groups,
552 };
553
sp_pci_init(void)554 int sp_pci_init(void)
555 {
556 return pci_register_driver(&sp_pci_driver);
557 }
558
sp_pci_exit(void)559 void sp_pci_exit(void)
560 {
561 pci_unregister_driver(&sp_pci_driver);
562 }
563