1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-regmap-mux.h"
23 #include "common.h"
24 #include "gdsc.h"
25 #include "reset.h"
26
27 enum {
28 DT_BI_TCXO,
29 DT_GPLL0_OUT_MAIN,
30 DT_GPLL0_OUT_MAIN_DIV,
31 };
32
33 enum {
34 P_BI_TCXO,
35 P_GPLL0_OUT_MAIN,
36 P_GPLL0_OUT_MAIN_DIV,
37 P_GPU_CC_PLL0_OUT_MAIN,
38 P_GPU_CC_PLL1_OUT_MAIN,
39 };
40
41 static const struct pll_vco lucid_ole_vco[] = {
42 { 249600000, 2300000000, 0 },
43 };
44
45 /* 560.0 MHz Configuration */
46 static const struct alpha_pll_config gpu_cc_pll0_config = {
47 .l = 0x1d,
48 .alpha = 0x2aaa,
49 .config_ctl_val = 0x20485699,
50 .config_ctl_hi_val = 0x00182261,
51 .config_ctl_hi1_val = 0x82aa299c,
52 .test_ctl_val = 0x00000000,
53 .test_ctl_hi_val = 0x00000003,
54 .test_ctl_hi1_val = 0x00009000,
55 .test_ctl_hi2_val = 0x00000034,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000005,
58 };
59
60 static struct clk_alpha_pll gpu_cc_pll0 = {
61 .offset = 0x0,
62 .vco_table = lucid_ole_vco,
63 .num_vco = ARRAY_SIZE(lucid_ole_vco),
64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
65 .clkr = {
66 .hw.init = &(const struct clk_init_data) {
67 .name = "gpu_cc_pll0",
68 .parent_data = &(const struct clk_parent_data) {
69 .index = DT_BI_TCXO,
70 },
71 .num_parents = 1,
72 .ops = &clk_alpha_pll_lucid_evo_ops,
73 },
74 },
75 };
76
77 /* 440.0 MHz Configuration */
78 static const struct alpha_pll_config gpu_cc_pll1_config = {
79 .l = 0x16,
80 .alpha = 0xeaaa,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x82aa299c,
84 .test_ctl_val = 0x00000000,
85 .test_ctl_hi_val = 0x00000003,
86 .test_ctl_hi1_val = 0x00009000,
87 .test_ctl_hi2_val = 0x00000034,
88 .user_ctl_val = 0x00000000,
89 .user_ctl_hi_val = 0x00000005,
90 };
91
92 static struct clk_alpha_pll gpu_cc_pll1 = {
93 .offset = 0x1000,
94 .vco_table = lucid_ole_vco,
95 .num_vco = ARRAY_SIZE(lucid_ole_vco),
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
97 .clkr = {
98 .hw.init = &(const struct clk_init_data) {
99 .name = "gpu_cc_pll1",
100 .parent_data = &(const struct clk_parent_data) {
101 .index = DT_BI_TCXO,
102 },
103 .num_parents = 1,
104 .ops = &clk_alpha_pll_lucid_evo_ops,
105 },
106 },
107 };
108
109 static const struct parent_map gpu_cc_parent_map_0[] = {
110 { P_BI_TCXO, 0 },
111 { P_GPLL0_OUT_MAIN, 5 },
112 { P_GPLL0_OUT_MAIN_DIV, 6 },
113 };
114
115 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
116 { .index = DT_BI_TCXO },
117 { .index = DT_GPLL0_OUT_MAIN },
118 { .index = DT_GPLL0_OUT_MAIN_DIV },
119 };
120
121 static const struct parent_map gpu_cc_parent_map_1[] = {
122 { P_BI_TCXO, 0 },
123 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
124 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
125 { P_GPLL0_OUT_MAIN, 5 },
126 { P_GPLL0_OUT_MAIN_DIV, 6 },
127 };
128
129 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
130 { .index = DT_BI_TCXO },
131 { .hw = &gpu_cc_pll0.clkr.hw },
132 { .hw = &gpu_cc_pll1.clkr.hw },
133 { .index = DT_GPLL0_OUT_MAIN },
134 { .index = DT_GPLL0_OUT_MAIN_DIV },
135 };
136
137 static const struct parent_map gpu_cc_parent_map_2[] = {
138 { P_BI_TCXO, 0 },
139 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
140 { P_GPLL0_OUT_MAIN, 5 },
141 { P_GPLL0_OUT_MAIN_DIV, 6 },
142 };
143
144 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
145 { .index = DT_BI_TCXO },
146 { .hw = &gpu_cc_pll1.clkr.hw },
147 { .index = DT_GPLL0_OUT_MAIN },
148 { .index = DT_GPLL0_OUT_MAIN_DIV },
149 };
150
151 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
152 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
153 { }
154 };
155
156 static struct clk_rcg2 gpu_cc_ff_clk_src = {
157 .cmd_rcgr = 0x9474,
158 .mnd_width = 0,
159 .hid_width = 5,
160 .parent_map = gpu_cc_parent_map_0,
161 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
162 .clkr.hw.init = &(const struct clk_init_data) {
163 .name = "gpu_cc_ff_clk_src",
164 .parent_data = gpu_cc_parent_data_0,
165 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
166 .flags = CLK_SET_RATE_PARENT,
167 .ops = &clk_rcg2_shared_ops,
168 },
169 };
170
171 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
172 F(19200000, P_BI_TCXO, 1, 0, 0),
173 F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
174 F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
175 { }
176 };
177
178 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
179 .cmd_rcgr = 0x9318,
180 .mnd_width = 0,
181 .hid_width = 5,
182 .parent_map = gpu_cc_parent_map_1,
183 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
184 .clkr.hw.init = &(const struct clk_init_data) {
185 .name = "gpu_cc_gmu_clk_src",
186 .parent_data = gpu_cc_parent_data_1,
187 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
188 .flags = CLK_SET_RATE_PARENT,
189 .ops = &clk_rcg2_shared_ops,
190 },
191 };
192
193 static struct clk_rcg2 gpu_cc_hub_clk_src = {
194 .cmd_rcgr = 0x93ec,
195 .mnd_width = 0,
196 .hid_width = 5,
197 .parent_map = gpu_cc_parent_map_2,
198 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
199 .clkr.hw.init = &(const struct clk_init_data) {
200 .name = "gpu_cc_hub_clk_src",
201 .parent_data = gpu_cc_parent_data_2,
202 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
203 .flags = CLK_SET_RATE_PARENT,
204 .ops = &clk_rcg2_shared_ops,
205 },
206 };
207
208 static struct clk_branch gpu_cc_ahb_clk = {
209 .halt_reg = 0x911c,
210 .halt_check = BRANCH_HALT_DELAY,
211 .clkr = {
212 .enable_reg = 0x911c,
213 .enable_mask = BIT(0),
214 .hw.init = &(const struct clk_init_data) {
215 .name = "gpu_cc_ahb_clk",
216 .parent_hws = (const struct clk_hw*[]) {
217 &gpu_cc_hub_clk_src.clkr.hw,
218 },
219 .num_parents = 1,
220 .flags = CLK_SET_RATE_PARENT,
221 .ops = &clk_branch2_ops,
222 },
223 },
224 };
225
226 static struct clk_branch gpu_cc_crc_ahb_clk = {
227 .halt_reg = 0x9120,
228 .halt_check = BRANCH_HALT_VOTED,
229 .clkr = {
230 .enable_reg = 0x9120,
231 .enable_mask = BIT(0),
232 .hw.init = &(const struct clk_init_data) {
233 .name = "gpu_cc_crc_ahb_clk",
234 .parent_hws = (const struct clk_hw*[]) {
235 &gpu_cc_hub_clk_src.clkr.hw,
236 },
237 .num_parents = 1,
238 .flags = CLK_SET_RATE_PARENT,
239 .ops = &clk_branch2_ops,
240 },
241 },
242 };
243
244 static struct clk_branch gpu_cc_cx_accu_shift_clk = {
245 .halt_reg = 0x9480,
246 .halt_check = BRANCH_HALT_VOTED,
247 .clkr = {
248 .enable_reg = 0x9480,
249 .enable_mask = BIT(0),
250 .hw.init = &(const struct clk_init_data) {
251 .name = "gpu_cc_cx_accu_shift_clk",
252 .ops = &clk_branch2_ops,
253 },
254 },
255 };
256
257 static struct clk_branch gpu_cc_cx_ff_clk = {
258 .halt_reg = 0x914c,
259 .halt_check = BRANCH_HALT,
260 .clkr = {
261 .enable_reg = 0x914c,
262 .enable_mask = BIT(0),
263 .hw.init = &(const struct clk_init_data) {
264 .name = "gpu_cc_cx_ff_clk",
265 .parent_hws = (const struct clk_hw*[]) {
266 &gpu_cc_ff_clk_src.clkr.hw,
267 },
268 .num_parents = 1,
269 .flags = CLK_SET_RATE_PARENT,
270 .ops = &clk_branch2_ops,
271 },
272 },
273 };
274
275 static struct clk_branch gpu_cc_cx_gmu_clk = {
276 .halt_reg = 0x913c,
277 .halt_check = BRANCH_HALT_VOTED,
278 .clkr = {
279 .enable_reg = 0x913c,
280 .enable_mask = BIT(0),
281 .hw.init = &(const struct clk_init_data) {
282 .name = "gpu_cc_cx_gmu_clk",
283 .parent_hws = (const struct clk_hw*[]) {
284 &gpu_cc_gmu_clk_src.clkr.hw,
285 },
286 .num_parents = 1,
287 .flags = CLK_SET_RATE_PARENT,
288 .ops = &clk_branch2_aon_ops,
289 },
290 },
291 };
292
293 static struct clk_branch gpu_cc_cxo_clk = {
294 .halt_reg = 0x9144,
295 .halt_check = BRANCH_HALT,
296 .clkr = {
297 .enable_reg = 0x9144,
298 .enable_mask = BIT(0),
299 .hw.init = &(const struct clk_init_data) {
300 .name = "gpu_cc_cxo_clk",
301 .ops = &clk_branch2_ops,
302 },
303 },
304 };
305
306 static struct clk_branch gpu_cc_freq_measure_clk = {
307 .halt_reg = 0x9008,
308 .halt_check = BRANCH_HALT,
309 .clkr = {
310 .enable_reg = 0x9008,
311 .enable_mask = BIT(0),
312 .hw.init = &(const struct clk_init_data) {
313 .name = "gpu_cc_freq_measure_clk",
314 .ops = &clk_branch2_ops,
315 },
316 },
317 };
318
319 static struct clk_branch gpu_cc_gx_accu_shift_clk = {
320 .halt_reg = 0x947c,
321 .halt_check = BRANCH_HALT_VOTED,
322 .clkr = {
323 .enable_reg = 0x947c,
324 .enable_mask = BIT(0),
325 .hw.init = &(const struct clk_init_data) {
326 .name = "gpu_cc_gx_accu_shift_clk",
327 .ops = &clk_branch2_ops,
328 },
329 },
330 };
331
332 static struct clk_branch gpu_cc_gx_gmu_clk = {
333 .halt_reg = 0x90bc,
334 .halt_check = BRANCH_HALT,
335 .clkr = {
336 .enable_reg = 0x90bc,
337 .enable_mask = BIT(0),
338 .hw.init = &(const struct clk_init_data) {
339 .name = "gpu_cc_gx_gmu_clk",
340 .parent_hws = (const struct clk_hw*[]) {
341 &gpu_cc_gmu_clk_src.clkr.hw,
342 },
343 .num_parents = 1,
344 .flags = CLK_SET_RATE_PARENT,
345 .ops = &clk_branch2_ops,
346 },
347 },
348 };
349
350 static struct clk_branch gpu_cc_gx_vsense_clk = {
351 .halt_reg = 0x90b0,
352 .halt_check = BRANCH_HALT_VOTED,
353 .clkr = {
354 .enable_reg = 0x90b0,
355 .enable_mask = BIT(0),
356 .hw.init = &(const struct clk_init_data) {
357 .name = "gpu_cc_gx_vsense_clk",
358 .ops = &clk_branch2_ops,
359 },
360 },
361 };
362
363 static struct clk_branch gpu_cc_hub_aon_clk = {
364 .halt_reg = 0x93e8,
365 .halt_check = BRANCH_HALT,
366 .clkr = {
367 .enable_reg = 0x93e8,
368 .enable_mask = BIT(0),
369 .hw.init = &(const struct clk_init_data) {
370 .name = "gpu_cc_hub_aon_clk",
371 .parent_hws = (const struct clk_hw*[]) {
372 &gpu_cc_hub_clk_src.clkr.hw,
373 },
374 .num_parents = 1,
375 .flags = CLK_SET_RATE_PARENT,
376 .ops = &clk_branch2_aon_ops,
377 },
378 },
379 };
380
381 static struct clk_branch gpu_cc_hub_cx_int_clk = {
382 .halt_reg = 0x9148,
383 .halt_check = BRANCH_HALT_VOTED,
384 .clkr = {
385 .enable_reg = 0x9148,
386 .enable_mask = BIT(0),
387 .hw.init = &(const struct clk_init_data) {
388 .name = "gpu_cc_hub_cx_int_clk",
389 .parent_hws = (const struct clk_hw*[]) {
390 &gpu_cc_hub_clk_src.clkr.hw,
391 },
392 .num_parents = 1,
393 .flags = CLK_SET_RATE_PARENT,
394 .ops = &clk_branch2_aon_ops,
395 },
396 },
397 };
398
399 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
400 .halt_reg = 0x9150,
401 .halt_check = BRANCH_HALT_VOTED,
402 .clkr = {
403 .enable_reg = 0x9150,
404 .enable_mask = BIT(0),
405 .hw.init = &(const struct clk_init_data) {
406 .name = "gpu_cc_memnoc_gfx_clk",
407 .ops = &clk_branch2_ops,
408 },
409 },
410 };
411
412 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
413 .halt_reg = 0x9288,
414 .halt_check = BRANCH_HALT,
415 .clkr = {
416 .enable_reg = 0x9288,
417 .enable_mask = BIT(0),
418 .hw.init = &(const struct clk_init_data) {
419 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
420 .ops = &clk_branch2_ops,
421 },
422 },
423 };
424
425 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
426 .halt_reg = 0x928c,
427 .halt_check = BRANCH_HALT,
428 .clkr = {
429 .enable_reg = 0x928c,
430 .enable_mask = BIT(0),
431 .hw.init = &(const struct clk_init_data) {
432 .name = "gpu_cc_mnd1x_1_gfx3d_clk",
433 .ops = &clk_branch2_ops,
434 },
435 },
436 };
437
438 static struct clk_branch gpu_cc_sleep_clk = {
439 .halt_reg = 0x9134,
440 .halt_check = BRANCH_HALT_VOTED,
441 .clkr = {
442 .enable_reg = 0x9134,
443 .enable_mask = BIT(0),
444 .hw.init = &(const struct clk_init_data) {
445 .name = "gpu_cc_sleep_clk",
446 .ops = &clk_branch2_ops,
447 },
448 },
449 };
450
451 static struct gdsc gpu_cc_cx_gdsc = {
452 .gdscr = 0x9108,
453 .gds_hw_ctrl = 0x953c,
454 .en_rest_wait_val = 0x2,
455 .en_few_wait_val = 0x2,
456 .clk_dis_wait_val = 0xf,
457 .pd = {
458 .name = "gpu_cc_cx_gdsc",
459 },
460 .pwrsts = PWRSTS_OFF_ON,
461 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
462 };
463
464 static struct gdsc gpu_cc_gx_gdsc = {
465 .gdscr = 0x905c,
466 .en_rest_wait_val = 0x2,
467 .en_few_wait_val = 0x2,
468 .clk_dis_wait_val = 0xf,
469 .pd = {
470 .name = "gpu_cc_gx_gdsc",
471 .power_on = gdsc_gx_do_nothing_enable,
472 },
473 .pwrsts = PWRSTS_OFF_ON,
474 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
475 };
476
477 static struct clk_regmap *gpu_cc_x1p42100_clocks[] = {
478 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
479 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
480 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
481 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
482 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
483 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
484 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
485 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
486 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
487 [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
488 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
489 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
490 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
491 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
492 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
493 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
494 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
495 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
496 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
497 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
498 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
499 };
500
501 static struct gdsc *gpu_cc_x1p42100_gdscs[] = {
502 [GPU_CX_GDSC] = &gpu_cc_cx_gdsc,
503 [GPU_GX_GDSC] = &gpu_cc_gx_gdsc,
504 };
505
506 static const struct qcom_reset_map gpu_cc_x1p42100_resets[] = {
507 [GPU_CC_ACD_BCR] = { 0x9358 },
508 [GPU_CC_CB_BCR] = { 0x93a0 },
509 [GPU_CC_CX_BCR] = { 0x9104 },
510 [GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
511 [GPU_CC_FF_BCR] = { 0x9470 },
512 [GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
513 [GPU_CC_GMU_BCR] = { 0x9314 },
514 [GPU_CC_GX_BCR] = { 0x9058 },
515 [GPU_CC_XO_BCR] = { 0x9000 },
516 };
517
518 static const struct regmap_config gpu_cc_x1p42100_regmap_config = {
519 .reg_bits = 32,
520 .reg_stride = 4,
521 .val_bits = 32,
522 .max_register = 0x9988,
523 .fast_io = true,
524 };
525
526 static struct qcom_cc_desc gpu_cc_x1p42100_desc = {
527 .config = &gpu_cc_x1p42100_regmap_config,
528 .clks = gpu_cc_x1p42100_clocks,
529 .num_clks = ARRAY_SIZE(gpu_cc_x1p42100_clocks),
530 .resets = gpu_cc_x1p42100_resets,
531 .num_resets = ARRAY_SIZE(gpu_cc_x1p42100_resets),
532 .gdscs = gpu_cc_x1p42100_gdscs,
533 .num_gdscs = ARRAY_SIZE(gpu_cc_x1p42100_gdscs),
534 };
535
536 static const struct of_device_id gpu_cc_x1p42100_match_table[] = {
537 { .compatible = "qcom,x1p42100-gpucc" },
538 { }
539 };
540 MODULE_DEVICE_TABLE(of, gpu_cc_x1p42100_match_table);
541
gpu_cc_x1p42100_probe(struct platform_device * pdev)542 static int gpu_cc_x1p42100_probe(struct platform_device *pdev)
543 {
544 struct regmap *regmap;
545 int ret;
546
547 ret = devm_pm_runtime_enable(&pdev->dev);
548 if (ret)
549 return ret;
550
551 ret = pm_runtime_resume_and_get(&pdev->dev);
552 if (ret)
553 return ret;
554
555 regmap = qcom_cc_map(pdev, &gpu_cc_x1p42100_desc);
556 if (IS_ERR(regmap)) {
557 pm_runtime_put(&pdev->dev);
558 return PTR_ERR(regmap);
559 }
560
561 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
562 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
563
564 /* Keep some clocks always enabled */
565 qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
566 qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
567 qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
568
569 ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_x1p42100_desc, regmap);
570
571 pm_runtime_put(&pdev->dev);
572
573 return ret;
574 }
575
576 static struct platform_driver gpu_cc_x1p42100_driver = {
577 .probe = gpu_cc_x1p42100_probe,
578 .driver = {
579 .name = "gpucc-x1p42100",
580 .of_match_table = gpu_cc_x1p42100_match_table,
581 },
582 };
583
584 module_platform_driver(gpu_cc_x1p42100_driver);
585
586 MODULE_DESCRIPTION("QTI GPUCC X1P42100 Driver");
587 MODULE_LICENSE("GPL");
588