1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Hyper-V specific APIC code.
5 *
6 * Copyright (C) 2018, Microsoft, Inc.
7 *
8 * Author : K. Y. Srinivasan <[email protected]>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 */
21
22 #include <linux/types.h>
23 #include <linux/vmalloc.h>
24 #include <linux/mm.h>
25 #include <linux/clockchips.h>
26 #include <linux/slab.h>
27 #include <linux/cpuhotplug.h>
28 #include <asm/hypervisor.h>
29 #include <asm/mshyperv.h>
30 #include <asm/apic.h>
31
32 #include <asm/trace/hyperv.h>
33
34 static struct apic orig_apic;
35
hv_apic_icr_read(void)36 static u64 hv_apic_icr_read(void)
37 {
38 u64 reg_val;
39
40 rdmsrl(HV_X64_MSR_ICR, reg_val);
41 return reg_val;
42 }
43
hv_apic_icr_write(u32 low,u32 id)44 static void hv_apic_icr_write(u32 low, u32 id)
45 {
46 u64 reg_val;
47
48 reg_val = SET_XAPIC_DEST_FIELD(id);
49 reg_val = reg_val << 32;
50 reg_val |= low;
51
52 wrmsrl(HV_X64_MSR_ICR, reg_val);
53 }
54
hv_apic_read(u32 reg)55 static u32 hv_apic_read(u32 reg)
56 {
57 u32 reg_val, hi;
58
59 switch (reg) {
60 case APIC_EOI:
61 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
62 (void)hi;
63 return reg_val;
64 case APIC_TASKPRI:
65 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
66 (void)hi;
67 return reg_val;
68
69 default:
70 return native_apic_mem_read(reg);
71 }
72 }
73
hv_apic_write(u32 reg,u32 val)74 static void hv_apic_write(u32 reg, u32 val)
75 {
76 switch (reg) {
77 case APIC_EOI:
78 wrmsr(HV_X64_MSR_EOI, val, 0);
79 break;
80 case APIC_TASKPRI:
81 wrmsr(HV_X64_MSR_TPR, val, 0);
82 break;
83 default:
84 native_apic_mem_write(reg, val);
85 }
86 }
87
hv_apic_eoi_write(void)88 static void hv_apic_eoi_write(void)
89 {
90 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
91
92 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
93 return;
94
95 wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0);
96 }
97
cpu_is_self(int cpu)98 static bool cpu_is_self(int cpu)
99 {
100 return cpu == smp_processor_id();
101 }
102
103 /*
104 * IPI implementation on Hyper-V.
105 */
__send_ipi_mask_ex(const struct cpumask * mask,int vector,bool exclude_self)106 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
107 bool exclude_self)
108 {
109 struct hv_send_ipi_ex *ipi_arg;
110 unsigned long flags;
111 int nr_bank = 0;
112 u64 status = HV_STATUS_INVALID_PARAMETER;
113
114 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
115 return false;
116
117 local_irq_save(flags);
118 ipi_arg = *this_cpu_ptr(hyperv_pcpu_input_arg);
119
120 if (unlikely(!ipi_arg))
121 goto ipi_mask_ex_done;
122
123 ipi_arg->vector = vector;
124 ipi_arg->reserved = 0;
125 ipi_arg->vp_set.valid_bank_mask = 0;
126
127 /*
128 * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET
129 * when the IPI is sent to all currently present CPUs.
130 */
131 if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) {
132 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
133
134 nr_bank = cpumask_to_vpset_skip(&ipi_arg->vp_set, mask,
135 exclude_self ? cpu_is_self : NULL);
136
137 /*
138 * 'nr_bank <= 0' means some CPUs in cpumask can't be
139 * represented in VP_SET. Return an error and fall back to
140 * native (architectural) method of sending IPIs.
141 */
142 if (nr_bank <= 0)
143 goto ipi_mask_ex_done;
144 } else {
145 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
146 }
147
148 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
149 ipi_arg, NULL);
150
151 ipi_mask_ex_done:
152 local_irq_restore(flags);
153 return hv_result_success(status);
154 }
155
__send_ipi_mask(const struct cpumask * mask,int vector,bool exclude_self)156 static bool __send_ipi_mask(const struct cpumask *mask, int vector,
157 bool exclude_self)
158 {
159 int cur_cpu, vcpu, this_cpu = smp_processor_id();
160 struct hv_send_ipi ipi_arg;
161 u64 status;
162 unsigned int weight;
163
164 trace_hyperv_send_ipi_mask(mask, vector);
165
166 weight = cpumask_weight(mask);
167
168 /*
169 * Do nothing if
170 * 1. the mask is empty
171 * 2. the mask only contains self when exclude_self is true
172 */
173 if (weight == 0 ||
174 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
175 return true;
176
177 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
178 if (!hv_hypercall_pg) {
179 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
180 return false;
181 }
182
183 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
184 return false;
185
186 /*
187 * From the supplied CPU set we need to figure out if we can get away
188 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
189 * highest VP number in the set is < 64. As VP numbers are usually in
190 * ascending order and match Linux CPU ids, here is an optimization:
191 * we check the VP number for the highest bit in the supplied set first
192 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
193 * a must. We will also check all VP numbers when walking the supplied
194 * CPU set to remain correct in all cases.
195 */
196 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
197 goto do_ex_hypercall;
198
199 ipi_arg.vector = vector;
200 ipi_arg.cpu_mask = 0;
201
202 for_each_cpu(cur_cpu, mask) {
203 if (exclude_self && cur_cpu == this_cpu)
204 continue;
205 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
206 if (vcpu == VP_INVAL)
207 return false;
208
209 /*
210 * This particular version of the IPI hypercall can
211 * only target up to 64 CPUs.
212 */
213 if (vcpu >= 64)
214 goto do_ex_hypercall;
215
216 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
217 }
218
219 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
220 ipi_arg.cpu_mask);
221 return hv_result_success(status);
222
223 do_ex_hypercall:
224 return __send_ipi_mask_ex(mask, vector, exclude_self);
225 }
226
__send_ipi_one(int cpu,int vector)227 static bool __send_ipi_one(int cpu, int vector)
228 {
229 int vp = hv_cpu_number_to_vp_number(cpu);
230 u64 status;
231
232 trace_hyperv_send_ipi_one(cpu, vector);
233
234 if (vp == VP_INVAL)
235 return false;
236
237 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
238 if (!hv_hypercall_pg) {
239 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
240 return false;
241 }
242
243 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
244 return false;
245
246 if (vp >= 64)
247 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
248
249 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
250 return hv_result_success(status);
251 }
252
hv_send_ipi(int cpu,int vector)253 static void hv_send_ipi(int cpu, int vector)
254 {
255 if (!__send_ipi_one(cpu, vector))
256 orig_apic.send_IPI(cpu, vector);
257 }
258
hv_send_ipi_mask(const struct cpumask * mask,int vector)259 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
260 {
261 if (!__send_ipi_mask(mask, vector, false))
262 orig_apic.send_IPI_mask(mask, vector);
263 }
264
hv_send_ipi_mask_allbutself(const struct cpumask * mask,int vector)265 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
266 {
267 if (!__send_ipi_mask(mask, vector, true))
268 orig_apic.send_IPI_mask_allbutself(mask, vector);
269 }
270
hv_send_ipi_allbutself(int vector)271 static void hv_send_ipi_allbutself(int vector)
272 {
273 hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
274 }
275
hv_send_ipi_all(int vector)276 static void hv_send_ipi_all(int vector)
277 {
278 if (!__send_ipi_mask(cpu_online_mask, vector, false))
279 orig_apic.send_IPI_all(vector);
280 }
281
hv_send_ipi_self(int vector)282 static void hv_send_ipi_self(int vector)
283 {
284 if (!__send_ipi_one(smp_processor_id(), vector))
285 orig_apic.send_IPI_self(vector);
286 }
287
hv_apic_init(void)288 void __init hv_apic_init(void)
289 {
290 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
291 pr_info("Hyper-V: Using IPI hypercalls\n");
292 /*
293 * Set the IPI entry points.
294 */
295 orig_apic = *apic;
296
297 apic_update_callback(send_IPI, hv_send_ipi);
298 apic_update_callback(send_IPI_mask, hv_send_ipi_mask);
299 apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself);
300 apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself);
301 apic_update_callback(send_IPI_all, hv_send_ipi_all);
302 apic_update_callback(send_IPI_self, hv_send_ipi_self);
303 }
304
305 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
306 pr_info("Hyper-V: Using enlightened APIC (%s mode)",
307 x2apic_enabled() ? "x2apic" : "xapic");
308 /*
309 * When in x2apic mode, don't use the Hyper-V specific APIC
310 * accessors since the field layout in the ICR register is
311 * different in x2apic mode. Furthermore, the architectural
312 * x2apic MSRs function just as well as the Hyper-V
313 * synthetic APIC MSRs, so there's no benefit in having
314 * separate Hyper-V accessors for x2apic mode. The only
315 * exception is hv_apic_eoi_write, because it benefits from
316 * lazy EOI when available, but the same accessor works for
317 * both xapic and x2apic because the field layout is the same.
318 */
319 apic_update_callback(eoi, hv_apic_eoi_write);
320 if (!x2apic_enabled()) {
321 apic_update_callback(read, hv_apic_read);
322 apic_update_callback(write, hv_apic_write);
323 apic_update_callback(icr_write, hv_apic_icr_write);
324 apic_update_callback(icr_read, hv_apic_icr_read);
325 }
326 }
327 }
328