1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _S390_TLB_H
3 #define _S390_TLB_H
4
5 /*
6 * TLB flushing on s390 is complicated. The following requirement
7 * from the principles of operation is the most arduous:
8 *
9 * "A valid table entry must not be changed while it is attached
10 * to any CPU and may be used for translation by that CPU except to
11 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
13 * table entry, or (3) make a change by means of a COMPARE AND SWAP
14 * AND PURGE instruction that purges the TLB."
15 *
16 * The modification of a pte of an active mm struct therefore is
17 * a two step process: i) invalidate the pte, ii) store the new pte.
18 * This is true for the page protection bit as well.
19 * The only possible optimization is to flush at the beginning of
20 * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
21 *
22 * Pages used for the page tables is a different story. FIXME: more
23 */
24
25 static inline void tlb_flush(struct mmu_gather *tlb);
26 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
27 struct page *page, bool delay_rmap, int page_size);
28 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb,
29 struct page *page, unsigned int nr_pages, bool delay_rmap);
30
31 #define tlb_flush tlb_flush
32 #define pte_free_tlb pte_free_tlb
33 #define pmd_free_tlb pmd_free_tlb
34 #define p4d_free_tlb p4d_free_tlb
35 #define pud_free_tlb pud_free_tlb
36
37 #include <asm/tlbflush.h>
38 #include <asm-generic/tlb.h>
39
40 /*
41 * Release the page cache reference for a pte removed by
42 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
43 * has already been freed, so just do free_page_and_swap_cache.
44 *
45 * s390 doesn't delay rmap removal.
46 */
__tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,bool delay_rmap,int page_size)47 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
48 struct page *page, bool delay_rmap, int page_size)
49 {
50 VM_WARN_ON_ONCE(delay_rmap);
51
52 free_page_and_swap_cache(page);
53 return false;
54 }
55
__tlb_remove_folio_pages(struct mmu_gather * tlb,struct page * page,unsigned int nr_pages,bool delay_rmap)56 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb,
57 struct page *page, unsigned int nr_pages, bool delay_rmap)
58 {
59 struct encoded_page *encoded_pages[] = {
60 encode_page(page, ENCODED_PAGE_BIT_NR_PAGES_NEXT),
61 encode_nr_pages(nr_pages),
62 };
63
64 VM_WARN_ON_ONCE(delay_rmap);
65 VM_WARN_ON_ONCE(page_folio(page) != page_folio(page + nr_pages - 1));
66
67 free_pages_and_swap_cache(encoded_pages, ARRAY_SIZE(encoded_pages));
68 return false;
69 }
70
tlb_flush(struct mmu_gather * tlb)71 static inline void tlb_flush(struct mmu_gather *tlb)
72 {
73 __tlb_flush_mm_lazy(tlb->mm);
74 }
75
76 /*
77 * pte_free_tlb frees a pte table and clears the CRSTE for the
78 * page table from the tlb.
79 */
pte_free_tlb(struct mmu_gather * tlb,pgtable_t pte,unsigned long address)80 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
81 unsigned long address)
82 {
83 __tlb_adjust_range(tlb, address, PAGE_SIZE);
84 tlb->mm->context.flush_mm = 1;
85 tlb->freed_tables = 1;
86 tlb->cleared_pmds = 1;
87 if (mm_alloc_pgste(tlb->mm))
88 gmap_unlink(tlb->mm, (unsigned long *)pte, address);
89 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pte));
90 }
91
92 /*
93 * pmd_free_tlb frees a pmd table and clears the CRSTE for the
94 * segment table entry from the tlb.
95 * If the mm uses a two level page table the single pmd is freed
96 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
97 * to avoid the double free of the pmd in this case.
98 */
pmd_free_tlb(struct mmu_gather * tlb,pmd_t * pmd,unsigned long address)99 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
100 unsigned long address)
101 {
102 if (mm_pmd_folded(tlb->mm))
103 return;
104 __tlb_adjust_range(tlb, address, PAGE_SIZE);
105 tlb->mm->context.flush_mm = 1;
106 tlb->freed_tables = 1;
107 tlb->cleared_puds = 1;
108 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pmd));
109 }
110
111 /*
112 * p4d_free_tlb frees a pud table and clears the CRSTE for the
113 * region second table entry from the tlb.
114 * If the mm uses a four level page table the single p4d is freed
115 * as the pgd. p4d_free_tlb checks the asce_limit against 8PB
116 * to avoid the double free of the p4d in this case.
117 */
p4d_free_tlb(struct mmu_gather * tlb,p4d_t * p4d,unsigned long address)118 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
119 unsigned long address)
120 {
121 if (mm_p4d_folded(tlb->mm))
122 return;
123 __tlb_adjust_range(tlb, address, PAGE_SIZE);
124 tlb->mm->context.flush_mm = 1;
125 tlb->freed_tables = 1;
126 tlb_remove_ptdesc(tlb, virt_to_ptdesc(p4d));
127 }
128
129 /*
130 * pud_free_tlb frees a pud table and clears the CRSTE for the
131 * region third table entry from the tlb.
132 * If the mm uses a three level page table the single pud is freed
133 * as the pgd. pud_free_tlb checks the asce_limit against 4TB
134 * to avoid the double free of the pud in this case.
135 */
pud_free_tlb(struct mmu_gather * tlb,pud_t * pud,unsigned long address)136 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
137 unsigned long address)
138 {
139 if (mm_pud_folded(tlb->mm))
140 return;
141 __tlb_adjust_range(tlb, address, PAGE_SIZE);
142 tlb->mm->context.flush_mm = 1;
143 tlb->freed_tables = 1;
144 tlb->cleared_p4ds = 1;
145 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pud));
146 }
147
148 #endif /* _S390_TLB_H */
149