1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2/*
3* Copyright 2023 Mobileye Vision Technologies Ltd.
4*/
5
6#include <dt-bindings/interrupt-controller/mips-gic.h>
7
8#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16		cpu@0 {
17			device_type = "cpu";
18			compatible = "img,i6500";
19			reg = <0>;
20			clocks = <&olb EQ5C_CPU_CORE0>;
21		};
22	};
23
24	reserved-memory {
25		#address-cells = <2>;
26		#size-cells = <2>;
27		ranges;
28
29		/* These reserved memory regions are also defined in bootmanager
30		* for configuring inbound translation for BARS, don't change
31		* these without syncing with bootmanager
32		*/
33		shmem0_reserved: shmem@804000000 {
34			reg = <0x8 0x04000000 0x0 0x1000000>;
35		};
36		shmem1_reserved: shmem@805000000 {
37			reg = <0x8 0x05000000 0x0 0x1000000>;
38		};
39		pci0_msi_reserved: pci0-msi@806000000 {
40			reg = <0x8 0x06000000 0x0 0x100000>;
41		};
42		pci1_msi_reserved: pci1-msi@806100000 {
43			reg = <0x8 0x06100000 0x0 0x100000>;
44		};
45
46		mini_coredump0_reserved: mini-coredump0@806200000 {
47			reg = <0x8 0x06200000 0x0 0x100000>;
48		};
49		mhm_reserved_0: the-mhm-reserved-0@0 {
50			reg = <0x8 0x00000000 0x0 0x0000800>;
51		};
52
53		nvram@461fe00 {
54			compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem";
55			reg = <0x0 0x0461fe00 0x0 0x200>;
56			#address-cells = <1>;
57			#size-cells = <1>;
58			no-map;
59
60			nvmem-layout {
61				compatible = "fixed-layout";
62				#address-cells = <1>;
63				#size-cells = <1>;
64
65				eth0_mac: mac@7c {
66					reg = <0x7c 0x6>;
67				};
68
69				eth1_mac: mac@82 {
70					reg = <0x82 0x6>;
71				};
72			};
73		};
74	};
75
76	aliases {
77		serial0 = &uart0;
78		serial1 = &uart1;
79		serial2 = &uart2;
80	};
81
82	cpu_intc: interrupt-controller {
83		compatible = "mti,cpu-interrupt-controller";
84		interrupt-controller;
85		#address-cells = <0>;
86		#interrupt-cells = <1>;
87	};
88
89	xtal: xtal {
90		compatible = "fixed-clock";
91		#clock-cells = <0>;
92		clock-frequency = <30000000>;
93	};
94
95	pclk: pclk {
96		compatible = "fixed-clock";
97		#clock-cells = <0>;
98		clock-frequency = <250000000>;  /* 250MHz */
99	};
100
101	tsu_clk: tsu-clk {
102		compatible = "fixed-clock";
103		#clock-cells = <0>;
104		clock-frequency = <125000000>;  /* 125MHz */
105	};
106
107	soc: soc {
108		#address-cells = <2>;
109		#size-cells = <2>;
110		ranges;
111		compatible = "simple-bus";
112
113		uart0: serial@800000 {
114			compatible = "arm,pl011", "arm,primecell";
115			reg = <0 0x800000 0x0 0x1000>;
116			reg-io-width = <4>;
117			interrupt-parent = <&gic>;
118			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
119			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
120			clock-names = "uartclk", "apb_pclk";
121			resets = <&olb 0 10>;
122			pinctrl-names = "default";
123			pinctrl-0 = <&uart0_pins>;
124		};
125
126		uart1: serial@900000 {
127			compatible = "arm,pl011", "arm,primecell";
128			reg = <0 0x900000 0x0 0x1000>;
129			reg-io-width = <4>;
130			interrupt-parent = <&gic>;
131			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
132			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
133			clock-names = "uartclk", "apb_pclk";
134			resets = <&olb 0 11>;
135			pinctrl-names = "default";
136			pinctrl-0 = <&uart1_pins>;
137		};
138
139		uart2: serial@a00000 {
140			compatible = "arm,pl011", "arm,primecell";
141			reg = <0 0xa00000 0x0 0x1000>;
142			reg-io-width = <4>;
143			interrupt-parent = <&gic>;
144			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
145			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
146			clock-names = "uartclk", "apb_pclk";
147			resets = <&olb 0 12>;
148			pinctrl-names = "default";
149			pinctrl-0 = <&uart2_pins>;
150		};
151
152		olb: system-controller@e00000 {
153			compatible = "mobileye,eyeq5-olb", "syscon";
154			reg = <0 0xe00000 0x0 0x400>;
155			#reset-cells = <2>;
156			#clock-cells = <1>;
157			clocks = <&xtal>;
158			clock-names = "ref";
159		};
160
161		gic: interrupt-controller@140000 {
162			compatible = "mti,gic";
163			reg = <0x0 0x140000 0x0 0x20000>;
164			interrupt-controller;
165			#interrupt-cells = <3>;
166
167			/*
168			* Declare the interrupt-parent even though the mti,gic
169			* binding doesn't require it, such that the kernel can
170			* figure out that cpu_intc is the root interrupt
171			* controller & should be probed first.
172			*/
173			interrupt-parent = <&cpu_intc>;
174
175			timer {
176				compatible = "mti,gic-timer";
177				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
178				clocks = <&olb EQ5C_CPU_CORE0>;
179			};
180		};
181	};
182};
183
184#include "eyeq5-pins.dtsi"
185