1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <[email protected]>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <[email protected]>
9 * Christoffer Dall <[email protected]>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/debugfs.h>
16 #include <linux/kvm_host.h>
17 #include <linux/mm.h>
18 #include <linux/printk.h>
19 #include <linux/uaccess.h>
20
21 #include <asm/arm_pmuv3.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cputype.h>
24 #include <asm/debug-monitors.h>
25 #include <asm/esr.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_emulate.h>
28 #include <asm/kvm_hyp.h>
29 #include <asm/kvm_mmu.h>
30 #include <asm/kvm_nested.h>
31 #include <asm/perf_event.h>
32 #include <asm/sysreg.h>
33
34 #include <trace/events/kvm.h>
35
36 #include "sys_regs.h"
37 #include "vgic/vgic.h"
38
39 #include "trace.h"
40
41 /*
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
49 u64 val);
50
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
52 const struct sys_reg_desc *r)
53 {
54 kvm_inject_undefined(vcpu);
55 return false;
56 }
57
bad_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r,const char * msg)58 static bool bad_trap(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r,
61 const char *msg)
62 {
63 WARN_ONCE(1, "Unexpected %s\n", msg);
64 print_sys_reg_instr(params);
65 return undef_access(vcpu, params, r);
66 }
67
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)68 static bool read_from_write_only(struct kvm_vcpu *vcpu,
69 struct sys_reg_params *params,
70 const struct sys_reg_desc *r)
71 {
72 return bad_trap(vcpu, params, r,
73 "sys_reg read to write-only register");
74 }
75
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)76 static bool write_to_read_only(struct kvm_vcpu *vcpu,
77 struct sys_reg_params *params,
78 const struct sys_reg_desc *r)
79 {
80 return bad_trap(vcpu, params, r,
81 "sys_reg write to read-only register");
82 }
83
84 #define PURE_EL2_SYSREG(el2) \
85 case el2: { \
86 *el1r = el2; \
87 return true; \
88 }
89
90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \
91 case el2: { \
92 *xlate = fn; \
93 *el1r = el1; \
94 return true; \
95 }
96
get_el2_to_el1_mapping(unsigned int reg,unsigned int * el1r,u64 (** xlate)(u64))97 static bool get_el2_to_el1_mapping(unsigned int reg,
98 unsigned int *el1r, u64 (**xlate)(u64))
99 {
100 switch (reg) {
101 PURE_EL2_SYSREG( VPIDR_EL2 );
102 PURE_EL2_SYSREG( VMPIDR_EL2 );
103 PURE_EL2_SYSREG( ACTLR_EL2 );
104 PURE_EL2_SYSREG( HCR_EL2 );
105 PURE_EL2_SYSREG( MDCR_EL2 );
106 PURE_EL2_SYSREG( HSTR_EL2 );
107 PURE_EL2_SYSREG( HACR_EL2 );
108 PURE_EL2_SYSREG( VTTBR_EL2 );
109 PURE_EL2_SYSREG( VTCR_EL2 );
110 PURE_EL2_SYSREG( RVBAR_EL2 );
111 PURE_EL2_SYSREG( TPIDR_EL2 );
112 PURE_EL2_SYSREG( HPFAR_EL2 );
113 PURE_EL2_SYSREG( HCRX_EL2 );
114 PURE_EL2_SYSREG( HFGRTR_EL2 );
115 PURE_EL2_SYSREG( HFGWTR_EL2 );
116 PURE_EL2_SYSREG( HFGITR_EL2 );
117 PURE_EL2_SYSREG( HDFGRTR_EL2 );
118 PURE_EL2_SYSREG( HDFGWTR_EL2 );
119 PURE_EL2_SYSREG( HAFGRTR_EL2 );
120 PURE_EL2_SYSREG( CNTVOFF_EL2 );
121 PURE_EL2_SYSREG( CNTHCTL_EL2 );
122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1,
123 translate_sctlr_el2_to_sctlr_el1 );
124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1,
125 translate_cptr_el2_to_cpacr_el1 );
126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1,
127 translate_ttbr0_el2_to_ttbr0_el1 );
128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL );
129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1,
130 translate_tcr_el2_to_tcr_el1 );
131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL );
132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL );
133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL );
134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL );
135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL );
136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL );
137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL );
138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL );
139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL );
140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL );
141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL );
142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL );
143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL );
144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL );
145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL );
146 default:
147 return false;
148 }
149 }
150
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
152 {
153 u64 val = 0x8badf00d8badf00d;
154 u64 (*xlate)(u64) = NULL;
155 unsigned int el1r;
156
157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
158 goto memory_read;
159
160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
161 if (!is_hyp_ctxt(vcpu))
162 goto memory_read;
163
164 /*
165 * CNTHCTL_EL2 requires some special treatment to
166 * account for the bits that can be set via CNTKCTL_EL1.
167 */
168 switch (reg) {
169 case CNTHCTL_EL2:
170 if (vcpu_el2_e2h_is_set(vcpu)) {
171 val = read_sysreg_el1(SYS_CNTKCTL);
172 val &= CNTKCTL_VALID_BITS;
173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
174 return val;
175 }
176 break;
177 }
178
179 /*
180 * If this register does not have an EL1 counterpart,
181 * then read the stored EL2 version.
182 */
183 if (reg == el1r)
184 goto memory_read;
185
186 /*
187 * If we have a non-VHE guest and that the sysreg
188 * requires translation to be used at EL1, use the
189 * in-memory copy instead.
190 */
191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
192 goto memory_read;
193
194 /* Get the current version of the EL1 counterpart. */
195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
196 if (reg >= __SANITISED_REG_START__)
197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
198
199 return val;
200 }
201
202 /* EL1 register can't be on the CPU if the guest is in vEL2. */
203 if (unlikely(is_hyp_ctxt(vcpu)))
204 goto memory_read;
205
206 if (__vcpu_read_sys_reg_from_cpu(reg, &val))
207 return val;
208
209 memory_read:
210 return __vcpu_sys_reg(vcpu, reg);
211 }
212
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
214 {
215 u64 (*xlate)(u64) = NULL;
216 unsigned int el1r;
217
218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
219 goto memory_write;
220
221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
222 if (!is_hyp_ctxt(vcpu))
223 goto memory_write;
224
225 /*
226 * Always store a copy of the write to memory to avoid having
227 * to reverse-translate virtual EL2 system registers for a
228 * non-VHE guest hypervisor.
229 */
230 __vcpu_sys_reg(vcpu, reg) = val;
231
232 switch (reg) {
233 case CNTHCTL_EL2:
234 /*
235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register.
236 * Otherwise, some of the bits are backed by
237 * CNTKCTL_EL1, while the rest is kept in memory.
238 * Yes, this is fun stuff.
239 */
240 if (vcpu_el2_e2h_is_set(vcpu))
241 write_sysreg_el1(val, SYS_CNTKCTL);
242 return;
243 }
244
245 /* No EL1 counterpart? We're done here.? */
246 if (reg == el1r)
247 return;
248
249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
250 val = xlate(val);
251
252 /* Redirect this to the EL1 version of the register. */
253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
254 return;
255 }
256
257 /* EL1 register can't be on the CPU if the guest is in vEL2. */
258 if (unlikely(is_hyp_ctxt(vcpu)))
259 goto memory_write;
260
261 if (__vcpu_write_sys_reg_to_cpu(val, reg))
262 return;
263
264 memory_write:
265 __vcpu_sys_reg(vcpu, reg) = val;
266 }
267
268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
269 #define CSSELR_MAX 14
270
271 /*
272 * Returns the minimum line size for the selected cache, expressed as
273 * Log2(bytes).
274 */
get_min_cache_line_size(bool icache)275 static u8 get_min_cache_line_size(bool icache)
276 {
277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
278 u8 field;
279
280 if (icache)
281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
282 else
283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
284
285 /*
286 * Cache line size is represented as Log2(words) in CTR_EL0.
287 * Log2(bytes) can be derived with the following:
288 *
289 * Log2(words) + 2 = Log2(bytes / 4) + 2
290 * = Log2(bytes) - 2 + 2
291 * = Log2(bytes)
292 */
293 return field + 2;
294 }
295
296 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
298 {
299 u8 line_size;
300
301 if (vcpu->arch.ccsidr)
302 return vcpu->arch.ccsidr[csselr];
303
304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
305
306 /*
307 * Fabricate a CCSIDR value as the overriding value does not exist.
308 * The real CCSIDR value will not be used as it can vary by the
309 * physical CPU which the vcpu currently resides in.
310 *
311 * The line size is determined with get_min_cache_line_size(), which
312 * should be valid for all CPUs even if they have different cache
313 * configuration.
314 *
315 * The associativity bits are cleared, meaning the geometry of all data
316 * and unified caches (which are guaranteed to be PIPT and thus
317 * non-aliasing) are 1 set and 1 way.
318 * Guests should not be doing cache operations by set/way at all, and
319 * for this reason, we trap them and attempt to infer the intent, so
320 * that we can flush the entire guest's address space at the appropriate
321 * time. The exposed geometry minimizes the number of the traps.
322 * [If guests should attempt to infer aliasing properties from the
323 * geometry (which is not permitted by the architecture), they would
324 * only do so for virtually indexed caches.]
325 *
326 * We don't check if the cache level exists as it is allowed to return
327 * an UNKNOWN value if not.
328 */
329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
330 }
331
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
333 {
334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
335 u32 *ccsidr = vcpu->arch.ccsidr;
336 u32 i;
337
338 if ((val & CCSIDR_EL1_RES0) ||
339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
340 return -EINVAL;
341
342 if (!ccsidr) {
343 if (val == get_ccsidr(vcpu, csselr))
344 return 0;
345
346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
347 if (!ccsidr)
348 return -ENOMEM;
349
350 for (i = 0; i < CSSELR_MAX; i++)
351 ccsidr[i] = get_ccsidr(vcpu, i);
352
353 vcpu->arch.ccsidr = ccsidr;
354 }
355
356 ccsidr[csselr] = val;
357
358 return 0;
359 }
360
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)361 static bool access_rw(struct kvm_vcpu *vcpu,
362 struct sys_reg_params *p,
363 const struct sys_reg_desc *r)
364 {
365 if (p->is_write)
366 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
367 else
368 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
369
370 return true;
371 }
372
373 /*
374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
375 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)376 static bool access_dcsw(struct kvm_vcpu *vcpu,
377 struct sys_reg_params *p,
378 const struct sys_reg_desc *r)
379 {
380 if (!p->is_write)
381 return read_from_write_only(vcpu, p, r);
382
383 /*
384 * Only track S/W ops if we don't have FWB. It still indicates
385 * that the guest is a bit broken (S/W operations should only
386 * be done by firmware, knowing that there is only a single
387 * CPU left in the system, and certainly not from non-secure
388 * software).
389 */
390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
391 kvm_set_way_flush(vcpu);
392
393 return true;
394 }
395
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)396 static bool access_dcgsw(struct kvm_vcpu *vcpu,
397 struct sys_reg_params *p,
398 const struct sys_reg_desc *r)
399 {
400 if (!kvm_has_mte(vcpu->kvm))
401 return undef_access(vcpu, p, r);
402
403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
404 return access_dcsw(vcpu, p, r);
405 }
406
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
408 {
409 switch (r->aarch32_map) {
410 case AA32_LO:
411 *mask = GENMASK_ULL(31, 0);
412 *shift = 0;
413 break;
414 case AA32_HI:
415 *mask = GENMASK_ULL(63, 32);
416 *shift = 32;
417 break;
418 default:
419 *mask = GENMASK_ULL(63, 0);
420 *shift = 0;
421 break;
422 }
423 }
424
425 /*
426 * Generic accessor for VM registers. Only called as long as HCR_TVM
427 * is set. If the guest enables the MMU, we stop trapping the VM
428 * sys_regs and leave it in complete control of the caches.
429 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)430 static bool access_vm_reg(struct kvm_vcpu *vcpu,
431 struct sys_reg_params *p,
432 const struct sys_reg_desc *r)
433 {
434 bool was_enabled = vcpu_has_cache_enabled(vcpu);
435 u64 val, mask, shift;
436
437 BUG_ON(!p->is_write);
438
439 get_access_mask(r, &mask, &shift);
440
441 if (~mask) {
442 val = vcpu_read_sys_reg(vcpu, r->reg);
443 val &= ~mask;
444 } else {
445 val = 0;
446 }
447
448 val |= (p->regval & (mask >> shift)) << shift;
449 vcpu_write_sys_reg(vcpu, val, r->reg);
450
451 kvm_toggle_cache(vcpu, was_enabled);
452 return true;
453 }
454
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)455 static bool access_actlr(struct kvm_vcpu *vcpu,
456 struct sys_reg_params *p,
457 const struct sys_reg_desc *r)
458 {
459 u64 mask, shift;
460
461 if (p->is_write)
462 return ignore_write(vcpu, p);
463
464 get_access_mask(r, &mask, &shift);
465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
466
467 return true;
468 }
469
470 /*
471 * Trap handler for the GICv3 SGI generation system register.
472 * Forward the request to the VGIC emulation.
473 * The cp15_64 code makes sure this automatically works
474 * for both AArch64 and AArch32 accesses.
475 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)476 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
477 struct sys_reg_params *p,
478 const struct sys_reg_desc *r)
479 {
480 bool g1;
481
482 if (!kvm_has_gicv3(vcpu->kvm))
483 return undef_access(vcpu, p, r);
484
485 if (!p->is_write)
486 return read_from_write_only(vcpu, p, r);
487
488 /*
489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
493 * group.
494 */
495 if (p->Op0 == 0) { /* AArch32 */
496 switch (p->Op1) {
497 default: /* Keep GCC quiet */
498 case 0: /* ICC_SGI1R */
499 g1 = true;
500 break;
501 case 1: /* ICC_ASGI1R */
502 case 2: /* ICC_SGI0R */
503 g1 = false;
504 break;
505 }
506 } else { /* AArch64 */
507 switch (p->Op2) {
508 default: /* Keep GCC quiet */
509 case 5: /* ICC_SGI1R_EL1 */
510 g1 = true;
511 break;
512 case 6: /* ICC_ASGI1R_EL1 */
513 case 7: /* ICC_SGI0R_EL1 */
514 g1 = false;
515 break;
516 }
517 }
518
519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
520
521 return true;
522 }
523
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)524 static bool access_gic_sre(struct kvm_vcpu *vcpu,
525 struct sys_reg_params *p,
526 const struct sys_reg_desc *r)
527 {
528 if (!kvm_has_gicv3(vcpu->kvm))
529 return undef_access(vcpu, p, r);
530
531 if (p->is_write)
532 return ignore_write(vcpu, p);
533
534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
535 return true;
536 }
537
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)538 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
539 struct sys_reg_params *p,
540 const struct sys_reg_desc *r)
541 {
542 if (p->is_write)
543 return ignore_write(vcpu, p);
544 else
545 return read_zero(vcpu, p);
546 }
547
548 /*
549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
552 * treat it separately.
553 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)554 static bool trap_loregion(struct kvm_vcpu *vcpu,
555 struct sys_reg_params *p,
556 const struct sys_reg_desc *r)
557 {
558 u32 sr = reg_to_encoding(r);
559
560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP))
561 return undef_access(vcpu, p, r);
562
563 if (p->is_write && sr == SYS_LORID_EL1)
564 return write_to_read_only(vcpu, p, r);
565
566 return trap_raz_wi(vcpu, p, r);
567 }
568
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
570 struct sys_reg_params *p,
571 const struct sys_reg_desc *r)
572 {
573 if (!p->is_write)
574 return read_from_write_only(vcpu, p, r);
575
576 kvm_debug_handle_oslar(vcpu, p->regval);
577 return true;
578 }
579
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)580 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
581 struct sys_reg_params *p,
582 const struct sys_reg_desc *r)
583 {
584 if (p->is_write)
585 return write_to_read_only(vcpu, p, r);
586
587 p->regval = __vcpu_sys_reg(vcpu, r->reg);
588 return true;
589 }
590
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)591 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
592 u64 val)
593 {
594 /*
595 * The only modifiable bit is the OSLK bit. Refuse the write if
596 * userspace attempts to change any other bit in the register.
597 */
598 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
599 return -EINVAL;
600
601 __vcpu_sys_reg(vcpu, rd->reg) = val;
602 return 0;
603 }
604
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)605 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
606 struct sys_reg_params *p,
607 const struct sys_reg_desc *r)
608 {
609 if (p->is_write) {
610 return ignore_write(vcpu, p);
611 } else {
612 p->regval = read_sysreg(dbgauthstatus_el1);
613 return true;
614 }
615 }
616
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)617 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
618 struct sys_reg_params *p,
619 const struct sys_reg_desc *r)
620 {
621 access_rw(vcpu, p, r);
622
623 kvm_debug_set_guest_ownership(vcpu);
624 return true;
625 }
626
627 /*
628 * reg_to_dbg/dbg_to_reg
629 *
630 * A 32 bit write to a debug register leave top bits alone
631 * A 32 bit read from a debug register only returns the bottom bits
632 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)633 static void reg_to_dbg(struct kvm_vcpu *vcpu,
634 struct sys_reg_params *p,
635 const struct sys_reg_desc *rd,
636 u64 *dbg_reg)
637 {
638 u64 mask, shift, val;
639
640 get_access_mask(rd, &mask, &shift);
641
642 val = *dbg_reg;
643 val &= ~mask;
644 val |= (p->regval & (mask >> shift)) << shift;
645 *dbg_reg = val;
646 }
647
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)648 static void dbg_to_reg(struct kvm_vcpu *vcpu,
649 struct sys_reg_params *p,
650 const struct sys_reg_desc *rd,
651 u64 *dbg_reg)
652 {
653 u64 mask, shift;
654
655 get_access_mask(rd, &mask, &shift);
656 p->regval = (*dbg_reg & mask) >> shift;
657 }
658
demux_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)659 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
660 {
661 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state;
662
663 switch (rd->Op2) {
664 case 0b100:
665 return &dbg->dbg_bvr[rd->CRm];
666 case 0b101:
667 return &dbg->dbg_bcr[rd->CRm];
668 case 0b110:
669 return &dbg->dbg_wvr[rd->CRm];
670 case 0b111:
671 return &dbg->dbg_wcr[rd->CRm];
672 default:
673 KVM_BUG_ON(1, vcpu->kvm);
674 return NULL;
675 }
676 }
677
trap_dbg_wb_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)678 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
679 const struct sys_reg_desc *rd)
680 {
681 u64 *reg = demux_wb_reg(vcpu, rd);
682
683 if (!reg)
684 return false;
685
686 if (p->is_write)
687 reg_to_dbg(vcpu, p, rd, reg);
688 else
689 dbg_to_reg(vcpu, p, rd, reg);
690
691 kvm_debug_set_guest_ownership(vcpu);
692 return true;
693 }
694
set_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)695 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
696 u64 val)
697 {
698 u64 *reg = demux_wb_reg(vcpu, rd);
699
700 if (!reg)
701 return -EINVAL;
702
703 *reg = val;
704 return 0;
705 }
706
get_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)707 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
708 u64 *val)
709 {
710 u64 *reg = demux_wb_reg(vcpu, rd);
711
712 if (!reg)
713 return -EINVAL;
714
715 *val = *reg;
716 return 0;
717 }
718
reset_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)719 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
720 {
721 u64 *reg = demux_wb_reg(vcpu, rd);
722
723 /*
724 * Bail early if we couldn't find storage for the register, the
725 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever
726 * being run.
727 */
728 if (!reg)
729 return 0;
730
731 *reg = rd->val;
732 return rd->val;
733 }
734
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)735 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
736 {
737 u64 amair = read_sysreg(amair_el1);
738 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
739 return amair;
740 }
741
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)742 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
743 {
744 u64 actlr = read_sysreg(actlr_el1);
745 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
746 return actlr;
747 }
748
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)749 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
750 {
751 u64 mpidr;
752
753 /*
754 * Map the vcpu_id into the first three affinity level fields of
755 * the MPIDR. We limit the number of VCPUs in level 0 due to a
756 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
757 * of the GICv3 to be able to address each CPU directly when
758 * sending IPIs.
759 */
760 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
761 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
762 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
763 mpidr |= (1ULL << 31);
764 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
765
766 return mpidr;
767 }
768
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)769 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
770 const struct sys_reg_desc *r)
771 {
772 if (kvm_vcpu_has_pmu(vcpu))
773 return 0;
774
775 return REG_HIDDEN;
776 }
777
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)778 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
779 {
780 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
781 u8 n = vcpu->kvm->arch.pmcr_n;
782
783 if (n)
784 mask |= GENMASK(n - 1, 0);
785
786 reset_unknown(vcpu, r);
787 __vcpu_sys_reg(vcpu, r->reg) &= mask;
788
789 return __vcpu_sys_reg(vcpu, r->reg);
790 }
791
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)792 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
793 {
794 reset_unknown(vcpu, r);
795 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
796
797 return __vcpu_sys_reg(vcpu, r->reg);
798 }
799
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)800 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
801 {
802 /* This thing will UNDEF, who cares about the reset value? */
803 if (!kvm_vcpu_has_pmu(vcpu))
804 return 0;
805
806 reset_unknown(vcpu, r);
807 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm);
808
809 return __vcpu_sys_reg(vcpu, r->reg);
810 }
811
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)812 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
813 {
814 reset_unknown(vcpu, r);
815 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
816
817 return __vcpu_sys_reg(vcpu, r->reg);
818 }
819
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)820 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
821 {
822 u64 pmcr = 0;
823
824 if (!kvm_supports_32bit_el0())
825 pmcr |= ARMV8_PMU_PMCR_LC;
826
827 /*
828 * The value of PMCR.N field is included when the
829 * vCPU register is read via kvm_vcpu_read_pmcr().
830 */
831 __vcpu_sys_reg(vcpu, r->reg) = pmcr;
832
833 return __vcpu_sys_reg(vcpu, r->reg);
834 }
835
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)836 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
837 {
838 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
839 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
840
841 if (!enabled)
842 kvm_inject_undefined(vcpu);
843
844 return !enabled;
845 }
846
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)847 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
848 {
849 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
850 }
851
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)852 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
853 {
854 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
855 }
856
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)857 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
858 {
859 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
860 }
861
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)862 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
863 {
864 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
865 }
866
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)867 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
868 const struct sys_reg_desc *r)
869 {
870 u64 val;
871
872 if (pmu_access_el0_disabled(vcpu))
873 return false;
874
875 if (p->is_write) {
876 /*
877 * Only update writeable bits of PMCR (continuing into
878 * kvm_pmu_handle_pmcr() as well)
879 */
880 val = kvm_vcpu_read_pmcr(vcpu);
881 val &= ~ARMV8_PMU_PMCR_MASK;
882 val |= p->regval & ARMV8_PMU_PMCR_MASK;
883 if (!kvm_supports_32bit_el0())
884 val |= ARMV8_PMU_PMCR_LC;
885 kvm_pmu_handle_pmcr(vcpu, val);
886 } else {
887 /* PMCR.P & PMCR.C are RAZ */
888 val = kvm_vcpu_read_pmcr(vcpu)
889 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
890 p->regval = val;
891 }
892
893 return true;
894 }
895
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)896 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
897 const struct sys_reg_desc *r)
898 {
899 if (pmu_access_event_counter_el0_disabled(vcpu))
900 return false;
901
902 if (p->is_write)
903 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
904 else
905 /* return PMSELR.SEL field */
906 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
907 & PMSELR_EL0_SEL_MASK;
908
909 return true;
910 }
911
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)912 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
913 const struct sys_reg_desc *r)
914 {
915 u64 pmceid, mask, shift;
916
917 BUG_ON(p->is_write);
918
919 if (pmu_access_el0_disabled(vcpu))
920 return false;
921
922 get_access_mask(r, &mask, &shift);
923
924 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
925 pmceid &= mask;
926 pmceid >>= shift;
927
928 p->regval = pmceid;
929
930 return true;
931 }
932
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)933 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
934 {
935 u64 pmcr, val;
936
937 pmcr = kvm_vcpu_read_pmcr(vcpu);
938 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
939 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
940 kvm_inject_undefined(vcpu);
941 return false;
942 }
943
944 return true;
945 }
946
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)947 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
948 u64 *val)
949 {
950 u64 idx;
951
952 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
953 /* PMCCNTR_EL0 */
954 idx = ARMV8_PMU_CYCLE_IDX;
955 else
956 /* PMEVCNTRn_EL0 */
957 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
958
959 *val = kvm_pmu_get_counter_value(vcpu, idx);
960 return 0;
961 }
962
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)963 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
964 struct sys_reg_params *p,
965 const struct sys_reg_desc *r)
966 {
967 u64 idx = ~0UL;
968
969 if (r->CRn == 9 && r->CRm == 13) {
970 if (r->Op2 == 2) {
971 /* PMXEVCNTR_EL0 */
972 if (pmu_access_event_counter_el0_disabled(vcpu))
973 return false;
974
975 idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
976 __vcpu_sys_reg(vcpu, PMSELR_EL0));
977 } else if (r->Op2 == 0) {
978 /* PMCCNTR_EL0 */
979 if (pmu_access_cycle_counter_el0_disabled(vcpu))
980 return false;
981
982 idx = ARMV8_PMU_CYCLE_IDX;
983 }
984 } else if (r->CRn == 0 && r->CRm == 9) {
985 /* PMCCNTR */
986 if (pmu_access_event_counter_el0_disabled(vcpu))
987 return false;
988
989 idx = ARMV8_PMU_CYCLE_IDX;
990 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
991 /* PMEVCNTRn_EL0 */
992 if (pmu_access_event_counter_el0_disabled(vcpu))
993 return false;
994
995 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
996 }
997
998 /* Catch any decoding mistake */
999 WARN_ON(idx == ~0UL);
1000
1001 if (!pmu_counter_idx_valid(vcpu, idx))
1002 return false;
1003
1004 if (p->is_write) {
1005 if (pmu_access_el0_disabled(vcpu))
1006 return false;
1007
1008 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
1009 } else {
1010 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
1011 }
1012
1013 return true;
1014 }
1015
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1016 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1017 const struct sys_reg_desc *r)
1018 {
1019 u64 idx, reg;
1020
1021 if (pmu_access_el0_disabled(vcpu))
1022 return false;
1023
1024 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
1025 /* PMXEVTYPER_EL0 */
1026 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
1027 reg = PMEVTYPER0_EL0 + idx;
1028 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
1029 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1030 if (idx == ARMV8_PMU_CYCLE_IDX)
1031 reg = PMCCFILTR_EL0;
1032 else
1033 /* PMEVTYPERn_EL0 */
1034 reg = PMEVTYPER0_EL0 + idx;
1035 } else {
1036 BUG();
1037 }
1038
1039 if (!pmu_counter_idx_valid(vcpu, idx))
1040 return false;
1041
1042 if (p->is_write) {
1043 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
1044 kvm_vcpu_pmu_restore_guest(vcpu);
1045 } else {
1046 p->regval = __vcpu_sys_reg(vcpu, reg);
1047 }
1048
1049 return true;
1050 }
1051
set_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1052 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
1053 {
1054 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1055
1056 __vcpu_sys_reg(vcpu, r->reg) = val & mask;
1057 return 0;
1058 }
1059
get_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1060 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
1061 {
1062 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1063
1064 *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
1065 return 0;
1066 }
1067
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1068 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1069 const struct sys_reg_desc *r)
1070 {
1071 u64 val, mask;
1072
1073 if (pmu_access_el0_disabled(vcpu))
1074 return false;
1075
1076 mask = kvm_pmu_accessible_counter_mask(vcpu);
1077 if (p->is_write) {
1078 val = p->regval & mask;
1079 if (r->Op2 & 0x1)
1080 /* accessing PMCNTENSET_EL0 */
1081 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
1082 else
1083 /* accessing PMCNTENCLR_EL0 */
1084 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
1085
1086 kvm_pmu_reprogram_counter_mask(vcpu, val);
1087 } else {
1088 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
1089 }
1090
1091 return true;
1092 }
1093
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1094 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1095 const struct sys_reg_desc *r)
1096 {
1097 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1098
1099 if (check_pmu_access_disabled(vcpu, 0))
1100 return false;
1101
1102 if (p->is_write) {
1103 u64 val = p->regval & mask;
1104
1105 if (r->Op2 & 0x1)
1106 /* accessing PMINTENSET_EL1 */
1107 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
1108 else
1109 /* accessing PMINTENCLR_EL1 */
1110 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1111 } else {
1112 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1113 }
1114
1115 return true;
1116 }
1117
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1118 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1119 const struct sys_reg_desc *r)
1120 {
1121 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1122
1123 if (pmu_access_el0_disabled(vcpu))
1124 return false;
1125
1126 if (p->is_write) {
1127 if (r->CRm & 0x2)
1128 /* accessing PMOVSSET_EL0 */
1129 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
1130 else
1131 /* accessing PMOVSCLR_EL0 */
1132 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
1133 } else {
1134 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1135 }
1136
1137 return true;
1138 }
1139
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1140 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1141 const struct sys_reg_desc *r)
1142 {
1143 u64 mask;
1144
1145 if (!p->is_write)
1146 return read_from_write_only(vcpu, p, r);
1147
1148 if (pmu_write_swinc_el0_disabled(vcpu))
1149 return false;
1150
1151 mask = kvm_pmu_accessible_counter_mask(vcpu);
1152 kvm_pmu_software_increment(vcpu, p->regval & mask);
1153 return true;
1154 }
1155
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1156 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1157 const struct sys_reg_desc *r)
1158 {
1159 if (p->is_write) {
1160 if (!vcpu_mode_priv(vcpu))
1161 return undef_access(vcpu, p, r);
1162
1163 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1164 p->regval & ARMV8_PMU_USERENR_MASK;
1165 } else {
1166 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1167 & ARMV8_PMU_USERENR_MASK;
1168 }
1169
1170 return true;
1171 }
1172
get_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1173 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1174 u64 *val)
1175 {
1176 *val = kvm_vcpu_read_pmcr(vcpu);
1177 return 0;
1178 }
1179
set_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1180 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1181 u64 val)
1182 {
1183 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
1184 struct kvm *kvm = vcpu->kvm;
1185
1186 mutex_lock(&kvm->arch.config_lock);
1187
1188 /*
1189 * The vCPU can't have more counters than the PMU hardware
1190 * implements. Ignore this error to maintain compatibility
1191 * with the existing KVM behavior.
1192 */
1193 if (!kvm_vm_has_ran_once(kvm) &&
1194 new_n <= kvm_arm_pmu_get_max_counters(kvm))
1195 kvm->arch.pmcr_n = new_n;
1196
1197 mutex_unlock(&kvm->arch.config_lock);
1198
1199 /*
1200 * Ignore writes to RES0 bits, read only bits that are cleared on
1201 * vCPU reset, and writable bits that KVM doesn't support yet.
1202 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
1203 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU.
1204 * But, we leave the bit as it is here, as the vCPU's PMUver might
1205 * be changed later (NOTE: the bit will be cleared on first vCPU run
1206 * if necessary).
1207 */
1208 val &= ARMV8_PMU_PMCR_MASK;
1209
1210 /* The LC bit is RES1 when AArch32 is not supported */
1211 if (!kvm_supports_32bit_el0())
1212 val |= ARMV8_PMU_PMCR_LC;
1213
1214 __vcpu_sys_reg(vcpu, r->reg) = val;
1215 return 0;
1216 }
1217
1218 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1219 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1220 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1221 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1222 get_dbg_wb_reg, set_dbg_wb_reg }, \
1223 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1224 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1225 get_dbg_wb_reg, set_dbg_wb_reg }, \
1226 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1227 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1228 get_dbg_wb_reg, set_dbg_wb_reg }, \
1229 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1230 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1231 get_dbg_wb_reg, set_dbg_wb_reg }
1232
1233 #define PMU_SYS_REG(name) \
1234 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1235 .visibility = pmu_visibility
1236
1237 /* Macro to expand the PMEVCNTRn_EL0 register */
1238 #define PMU_PMEVCNTR_EL0(n) \
1239 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
1240 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
1241 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1242
1243 /* Macro to expand the PMEVTYPERn_EL0 register */
1244 #define PMU_PMEVTYPER_EL0(n) \
1245 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
1246 .reset = reset_pmevtyper, \
1247 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1248
1249 /* Macro to expand the AMU counter and type registers*/
1250 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1251 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1252 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1253 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1254
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1255 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1256 const struct sys_reg_desc *rd)
1257 {
1258 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1259 }
1260
1261 /*
1262 * If we land here on a PtrAuth access, that is because we didn't
1263 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1264 * way this happens is when the guest does not have PtrAuth support
1265 * enabled.
1266 */
1267 #define __PTRAUTH_KEY(k) \
1268 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1269 .visibility = ptrauth_visibility}
1270
1271 #define PTRAUTH_KEY(k) \
1272 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1273 __PTRAUTH_KEY(k ## KEYHI_EL1)
1274
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1275 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1276 struct sys_reg_params *p,
1277 const struct sys_reg_desc *r)
1278 {
1279 enum kvm_arch_timers tmr;
1280 enum kvm_arch_timer_regs treg;
1281 u64 reg = reg_to_encoding(r);
1282
1283 switch (reg) {
1284 case SYS_CNTP_TVAL_EL0:
1285 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1286 tmr = TIMER_HPTIMER;
1287 else
1288 tmr = TIMER_PTIMER;
1289 treg = TIMER_REG_TVAL;
1290 break;
1291
1292 case SYS_CNTV_TVAL_EL0:
1293 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1294 tmr = TIMER_HVTIMER;
1295 else
1296 tmr = TIMER_VTIMER;
1297 treg = TIMER_REG_TVAL;
1298 break;
1299
1300 case SYS_AARCH32_CNTP_TVAL:
1301 case SYS_CNTP_TVAL_EL02:
1302 tmr = TIMER_PTIMER;
1303 treg = TIMER_REG_TVAL;
1304 break;
1305
1306 case SYS_CNTV_TVAL_EL02:
1307 tmr = TIMER_VTIMER;
1308 treg = TIMER_REG_TVAL;
1309 break;
1310
1311 case SYS_CNTHP_TVAL_EL2:
1312 tmr = TIMER_HPTIMER;
1313 treg = TIMER_REG_TVAL;
1314 break;
1315
1316 case SYS_CNTHV_TVAL_EL2:
1317 tmr = TIMER_HVTIMER;
1318 treg = TIMER_REG_TVAL;
1319 break;
1320
1321 case SYS_CNTP_CTL_EL0:
1322 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1323 tmr = TIMER_HPTIMER;
1324 else
1325 tmr = TIMER_PTIMER;
1326 treg = TIMER_REG_CTL;
1327 break;
1328
1329 case SYS_CNTV_CTL_EL0:
1330 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1331 tmr = TIMER_HVTIMER;
1332 else
1333 tmr = TIMER_VTIMER;
1334 treg = TIMER_REG_CTL;
1335 break;
1336
1337 case SYS_AARCH32_CNTP_CTL:
1338 case SYS_CNTP_CTL_EL02:
1339 tmr = TIMER_PTIMER;
1340 treg = TIMER_REG_CTL;
1341 break;
1342
1343 case SYS_CNTV_CTL_EL02:
1344 tmr = TIMER_VTIMER;
1345 treg = TIMER_REG_CTL;
1346 break;
1347
1348 case SYS_CNTHP_CTL_EL2:
1349 tmr = TIMER_HPTIMER;
1350 treg = TIMER_REG_CTL;
1351 break;
1352
1353 case SYS_CNTHV_CTL_EL2:
1354 tmr = TIMER_HVTIMER;
1355 treg = TIMER_REG_CTL;
1356 break;
1357
1358 case SYS_CNTP_CVAL_EL0:
1359 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1360 tmr = TIMER_HPTIMER;
1361 else
1362 tmr = TIMER_PTIMER;
1363 treg = TIMER_REG_CVAL;
1364 break;
1365
1366 case SYS_CNTV_CVAL_EL0:
1367 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1368 tmr = TIMER_HVTIMER;
1369 else
1370 tmr = TIMER_VTIMER;
1371 treg = TIMER_REG_CVAL;
1372 break;
1373
1374 case SYS_AARCH32_CNTP_CVAL:
1375 case SYS_CNTP_CVAL_EL02:
1376 tmr = TIMER_PTIMER;
1377 treg = TIMER_REG_CVAL;
1378 break;
1379
1380 case SYS_CNTV_CVAL_EL02:
1381 tmr = TIMER_VTIMER;
1382 treg = TIMER_REG_CVAL;
1383 break;
1384
1385 case SYS_CNTHP_CVAL_EL2:
1386 tmr = TIMER_HPTIMER;
1387 treg = TIMER_REG_CVAL;
1388 break;
1389
1390 case SYS_CNTHV_CVAL_EL2:
1391 tmr = TIMER_HVTIMER;
1392 treg = TIMER_REG_CVAL;
1393 break;
1394
1395 case SYS_CNTPCT_EL0:
1396 case SYS_CNTPCTSS_EL0:
1397 if (is_hyp_ctxt(vcpu))
1398 tmr = TIMER_HPTIMER;
1399 else
1400 tmr = TIMER_PTIMER;
1401 treg = TIMER_REG_CNT;
1402 break;
1403
1404 case SYS_AARCH32_CNTPCT:
1405 case SYS_AARCH32_CNTPCTSS:
1406 tmr = TIMER_PTIMER;
1407 treg = TIMER_REG_CNT;
1408 break;
1409
1410 case SYS_CNTVCT_EL0:
1411 case SYS_CNTVCTSS_EL0:
1412 if (is_hyp_ctxt(vcpu))
1413 tmr = TIMER_HVTIMER;
1414 else
1415 tmr = TIMER_VTIMER;
1416 treg = TIMER_REG_CNT;
1417 break;
1418
1419 case SYS_AARCH32_CNTVCT:
1420 case SYS_AARCH32_CNTVCTSS:
1421 tmr = TIMER_VTIMER;
1422 treg = TIMER_REG_CNT;
1423 break;
1424
1425 default:
1426 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1427 return undef_access(vcpu, p, r);
1428 }
1429
1430 if (p->is_write)
1431 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1432 else
1433 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1434
1435 return true;
1436 }
1437
access_hv_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1438 static bool access_hv_timer(struct kvm_vcpu *vcpu,
1439 struct sys_reg_params *p,
1440 const struct sys_reg_desc *r)
1441 {
1442 if (!vcpu_el2_e2h_is_set(vcpu))
1443 return undef_access(vcpu, p, r);
1444
1445 return access_arch_timer(vcpu, p, r);
1446 }
1447
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1448 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1449 s64 new, s64 cur)
1450 {
1451 struct arm64_ftr_bits kvm_ftr = *ftrp;
1452
1453 /* Some features have different safe value type in KVM than host features */
1454 switch (id) {
1455 case SYS_ID_AA64DFR0_EL1:
1456 switch (kvm_ftr.shift) {
1457 case ID_AA64DFR0_EL1_PMUVer_SHIFT:
1458 kvm_ftr.type = FTR_LOWER_SAFE;
1459 break;
1460 case ID_AA64DFR0_EL1_DebugVer_SHIFT:
1461 kvm_ftr.type = FTR_LOWER_SAFE;
1462 break;
1463 }
1464 break;
1465 case SYS_ID_DFR0_EL1:
1466 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1467 kvm_ftr.type = FTR_LOWER_SAFE;
1468 break;
1469 }
1470
1471 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1472 }
1473
1474 /*
1475 * arm64_check_features() - Check if a feature register value constitutes
1476 * a subset of features indicated by the idreg's KVM sanitised limit.
1477 *
1478 * This function will check if each feature field of @val is the "safe" value
1479 * against idreg's KVM sanitised limit return from reset() callback.
1480 * If a field value in @val is the same as the one in limit, it is always
1481 * considered the safe value regardless For register fields that are not in
1482 * writable, only the value in limit is considered the safe value.
1483 *
1484 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1485 */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1486 static int arm64_check_features(struct kvm_vcpu *vcpu,
1487 const struct sys_reg_desc *rd,
1488 u64 val)
1489 {
1490 const struct arm64_ftr_reg *ftr_reg;
1491 const struct arm64_ftr_bits *ftrp = NULL;
1492 u32 id = reg_to_encoding(rd);
1493 u64 writable_mask = rd->val;
1494 u64 limit = rd->reset(vcpu, rd);
1495 u64 mask = 0;
1496
1497 /*
1498 * Hidden and unallocated ID registers may not have a corresponding
1499 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1500 * only safe value is 0.
1501 */
1502 if (sysreg_visible_as_raz(vcpu, rd))
1503 return val ? -E2BIG : 0;
1504
1505 ftr_reg = get_arm64_ftr_reg(id);
1506 if (!ftr_reg)
1507 return -EINVAL;
1508
1509 ftrp = ftr_reg->ftr_bits;
1510
1511 for (; ftrp && ftrp->width; ftrp++) {
1512 s64 f_val, f_lim, safe_val;
1513 u64 ftr_mask;
1514
1515 ftr_mask = arm64_ftr_mask(ftrp);
1516 if ((ftr_mask & writable_mask) != ftr_mask)
1517 continue;
1518
1519 f_val = arm64_ftr_value(ftrp, val);
1520 f_lim = arm64_ftr_value(ftrp, limit);
1521 mask |= ftr_mask;
1522
1523 if (f_val == f_lim)
1524 safe_val = f_val;
1525 else
1526 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1527
1528 if (safe_val != f_val)
1529 return -E2BIG;
1530 }
1531
1532 /* For fields that are not writable, values in limit are the safe values. */
1533 if ((val & ~mask) != (limit & ~mask))
1534 return -E2BIG;
1535
1536 return 0;
1537 }
1538
pmuver_to_perfmon(u8 pmuver)1539 static u8 pmuver_to_perfmon(u8 pmuver)
1540 {
1541 switch (pmuver) {
1542 case ID_AA64DFR0_EL1_PMUVer_IMP:
1543 return ID_DFR0_EL1_PerfMon_PMUv3;
1544 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1545 return ID_DFR0_EL1_PerfMon_IMPDEF;
1546 default:
1547 /* Anything ARMv8.1+ and NI have the same value. For now. */
1548 return pmuver;
1549 }
1550 }
1551
1552 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1553 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1554
1555 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1556 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1557 const struct sys_reg_desc *r)
1558 {
1559 u32 id = reg_to_encoding(r);
1560 u64 val;
1561
1562 if (sysreg_visible_as_raz(vcpu, r))
1563 return 0;
1564
1565 val = read_sanitised_ftr_reg(id);
1566
1567 switch (id) {
1568 case SYS_ID_AA64DFR0_EL1:
1569 val = sanitise_id_aa64dfr0_el1(vcpu, val);
1570 break;
1571 case SYS_ID_AA64PFR0_EL1:
1572 val = sanitise_id_aa64pfr0_el1(vcpu, val);
1573 break;
1574 case SYS_ID_AA64PFR1_EL1:
1575 if (!kvm_has_mte(vcpu->kvm))
1576 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1577
1578 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1579 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
1580 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
1581 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
1582 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
1583 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
1584 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2);
1586 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
1587 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac);
1588 break;
1589 case SYS_ID_AA64PFR2_EL1:
1590 /* We only expose FPMR */
1591 val &= ID_AA64PFR2_EL1_FPMR;
1592 break;
1593 case SYS_ID_AA64ISAR1_EL1:
1594 if (!vcpu_has_ptrauth(vcpu))
1595 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1596 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1597 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1598 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1599 break;
1600 case SYS_ID_AA64ISAR2_EL1:
1601 if (!vcpu_has_ptrauth(vcpu))
1602 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1603 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1604 if (!cpus_have_final_cap(ARM64_HAS_WFXT) ||
1605 has_broken_cntvoff())
1606 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1607 break;
1608 case SYS_ID_AA64ISAR3_EL1:
1609 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX;
1610 break;
1611 case SYS_ID_AA64MMFR2_EL1:
1612 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1613 break;
1614 case SYS_ID_AA64MMFR3_EL1:
1615 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE |
1616 ID_AA64MMFR3_EL1_S1PIE;
1617 break;
1618 case SYS_ID_MMFR4_EL1:
1619 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1620 break;
1621 }
1622
1623 return val;
1624 }
1625
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1626 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1627 const struct sys_reg_desc *r)
1628 {
1629 return __kvm_read_sanitised_id_reg(vcpu, r);
1630 }
1631
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1632 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1633 {
1634 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r));
1635 }
1636
is_feature_id_reg(u32 encoding)1637 static bool is_feature_id_reg(u32 encoding)
1638 {
1639 return (sys_reg_Op0(encoding) == 3 &&
1640 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) &&
1641 sys_reg_CRn(encoding) == 0 &&
1642 sys_reg_CRm(encoding) <= 7);
1643 }
1644
1645 /*
1646 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1647 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID
1648 * registers KVM maintains on a per-VM basis.
1649 */
is_vm_ftr_id_reg(u32 id)1650 static inline bool is_vm_ftr_id_reg(u32 id)
1651 {
1652 if (id == SYS_CTR_EL0)
1653 return true;
1654
1655 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1656 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1657 sys_reg_CRm(id) < 8);
1658 }
1659
is_vcpu_ftr_id_reg(u32 id)1660 static inline bool is_vcpu_ftr_id_reg(u32 id)
1661 {
1662 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id);
1663 }
1664
is_aa32_id_reg(u32 id)1665 static inline bool is_aa32_id_reg(u32 id)
1666 {
1667 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1668 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1669 sys_reg_CRm(id) <= 3);
1670 }
1671
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1672 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1673 const struct sys_reg_desc *r)
1674 {
1675 u32 id = reg_to_encoding(r);
1676
1677 switch (id) {
1678 case SYS_ID_AA64ZFR0_EL1:
1679 if (!vcpu_has_sve(vcpu))
1680 return REG_RAZ;
1681 break;
1682 }
1683
1684 return 0;
1685 }
1686
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1687 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1688 const struct sys_reg_desc *r)
1689 {
1690 /*
1691 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1692 * EL. Promote to RAZ/WI in order to guarantee consistency between
1693 * systems.
1694 */
1695 if (!kvm_supports_32bit_el0())
1696 return REG_RAZ | REG_USER_WI;
1697
1698 return id_visibility(vcpu, r);
1699 }
1700
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1701 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1702 const struct sys_reg_desc *r)
1703 {
1704 return REG_RAZ;
1705 }
1706
1707 /* cpufeature ID register access trap handlers */
1708
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1709 static bool access_id_reg(struct kvm_vcpu *vcpu,
1710 struct sys_reg_params *p,
1711 const struct sys_reg_desc *r)
1712 {
1713 if (p->is_write)
1714 return write_to_read_only(vcpu, p, r);
1715
1716 p->regval = read_id_reg(vcpu, r);
1717
1718 return true;
1719 }
1720
1721 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1722 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1723 const struct sys_reg_desc *rd)
1724 {
1725 if (vcpu_has_sve(vcpu))
1726 return 0;
1727
1728 return REG_HIDDEN;
1729 }
1730
sme_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1731 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu,
1732 const struct sys_reg_desc *rd)
1733 {
1734 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP))
1735 return 0;
1736
1737 return REG_HIDDEN;
1738 }
1739
fp8_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1740 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu,
1741 const struct sys_reg_desc *rd)
1742 {
1743 if (kvm_has_fpmr(vcpu->kvm))
1744 return 0;
1745
1746 return REG_HIDDEN;
1747 }
1748
sanitise_id_aa64pfr0_el1(const struct kvm_vcpu * vcpu,u64 val)1749 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
1750 {
1751 if (!vcpu_has_sve(vcpu))
1752 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
1753
1754 /*
1755 * The default is to expose CSV2 == 1 if the HW isn't affected.
1756 * Although this is a per-CPU feature, we make it global because
1757 * asymmetric systems are just a nuisance.
1758 *
1759 * Userspace can override this as long as it doesn't promise
1760 * the impossible.
1761 */
1762 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1763 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1764 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1765 }
1766 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1767 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1768 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1769 }
1770
1771 if (kvm_vgic_global_state.type == VGIC_V3) {
1772 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1773 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1774 }
1775
1776 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
1777
1778 /*
1779 * MPAM is disabled by default as KVM also needs a set of PARTID to
1780 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some
1781 * older kernels let the guest see the ID bit.
1782 */
1783 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
1784
1785 return val;
1786 }
1787
1788 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \
1789 ({ \
1790 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \
1791 (val) &= ~reg##_##field##_MASK; \
1792 (val) |= FIELD_PREP(reg##_##field##_MASK, \
1793 min(__f_val, \
1794 (u64)SYS_FIELD_VALUE(reg, field, limit))); \
1795 (val); \
1796 })
1797
sanitise_id_aa64dfr0_el1(const struct kvm_vcpu * vcpu,u64 val)1798 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
1799 {
1800 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
1801
1802 /*
1803 * Only initialize the PMU version if the vCPU was configured with one.
1804 */
1805 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1806 if (kvm_vcpu_has_pmu(vcpu))
1807 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1808 kvm_arm_pmu_get_pmuver_limit());
1809
1810 /* Hide SPE from guests */
1811 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1812
1813 /* Hide BRBE from guests */
1814 val &= ~ID_AA64DFR0_EL1_BRBE_MASK;
1815
1816 return val;
1817 }
1818
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1819 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1820 const struct sys_reg_desc *rd,
1821 u64 val)
1822 {
1823 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val);
1824 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
1825
1826 /*
1827 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1828 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1829 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1830 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1831 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1832 *
1833 * At minimum, we're on the hook to allow values that were given to
1834 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1835 * with a more sensible NI. The value of an ID register changing under
1836 * the nose of the guest is unfortunate, but is certainly no more
1837 * surprising than an ill-guided PMU driver poking at impdef system
1838 * registers that end in an UNDEF...
1839 */
1840 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1841 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1842
1843 /*
1844 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a
1845 * nonzero minimum safe value.
1846 */
1847 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP)
1848 return -EINVAL;
1849
1850 return set_id_reg(vcpu, rd, val);
1851 }
1852
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1853 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1854 const struct sys_reg_desc *rd)
1855 {
1856 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1857 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
1858
1859 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1860 if (kvm_vcpu_has_pmu(vcpu))
1861 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
1862
1863 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
1864
1865 return val;
1866 }
1867
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1868 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1869 const struct sys_reg_desc *rd,
1870 u64 val)
1871 {
1872 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
1873 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val);
1874
1875 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1876 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1877 perfmon = 0;
1878 }
1879
1880 /*
1881 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1882 * it doesn't promise more than what the HW gives us on the
1883 * AArch64 side (as everything is emulated with that), and
1884 * that this is a PMUv3.
1885 */
1886 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
1887 return -EINVAL;
1888
1889 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8)
1890 return -EINVAL;
1891
1892 return set_id_reg(vcpu, rd, val);
1893 }
1894
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)1895 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1896 const struct sys_reg_desc *rd, u64 user_val)
1897 {
1898 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1899 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK;
1900
1901 /*
1902 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits
1903 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to
1904 * guests, but didn't add trap handling. KVM doesn't support MPAM and
1905 * always returns an UNDEF for these registers. The guest must see 0
1906 * for this field.
1907 *
1908 * But KVM must also accept values from user-space that were provided
1909 * by KVM. On CPUs that support MPAM, permit user-space to write
1910 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field.
1911 */
1912 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
1913 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
1914
1915 return set_id_reg(vcpu, rd, user_val);
1916 }
1917
set_id_aa64pfr1_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)1918 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
1919 const struct sys_reg_desc *rd, u64 user_val)
1920 {
1921 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
1922 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK;
1923
1924 /* See set_id_aa64pfr0_el1 for comment about MPAM */
1925 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
1926 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
1927
1928 return set_id_reg(vcpu, rd, user_val);
1929 }
1930
set_ctr_el0(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)1931 static int set_ctr_el0(struct kvm_vcpu *vcpu,
1932 const struct sys_reg_desc *rd, u64 user_val)
1933 {
1934 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val);
1935
1936 /*
1937 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved.
1938 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based
1939 * on what hardware reports.
1940 *
1941 * Using a VIPT software model on PIPT will lead to over invalidation,
1942 * but still correct. Hence, we can allow downgrading PIPT to VIPT,
1943 * but not the other way around. This is handled via arm64_ftr_safe_value()
1944 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value
1945 * set as VIPT.
1946 */
1947 switch (user_L1Ip) {
1948 case CTR_EL0_L1Ip_RESERVED_VPIPT:
1949 case CTR_EL0_L1Ip_RESERVED_AIVIVT:
1950 return -EINVAL;
1951 case CTR_EL0_L1Ip_VIPT:
1952 case CTR_EL0_L1Ip_PIPT:
1953 return set_id_reg(vcpu, rd, user_val);
1954 default:
1955 return -ENOENT;
1956 }
1957 }
1958
1959 /*
1960 * cpufeature ID register user accessors
1961 *
1962 * For now, these registers are immutable for userspace, so no values
1963 * are stored, and for set_id_reg() we don't allow the effective value
1964 * to be changed.
1965 */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1966 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1967 u64 *val)
1968 {
1969 /*
1970 * Avoid locking if the VM has already started, as the ID registers are
1971 * guaranteed to be invariant at that point.
1972 */
1973 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1974 *val = read_id_reg(vcpu, rd);
1975 return 0;
1976 }
1977
1978 mutex_lock(&vcpu->kvm->arch.config_lock);
1979 *val = read_id_reg(vcpu, rd);
1980 mutex_unlock(&vcpu->kvm->arch.config_lock);
1981
1982 return 0;
1983 }
1984
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1985 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1986 u64 val)
1987 {
1988 u32 id = reg_to_encoding(rd);
1989 int ret;
1990
1991 mutex_lock(&vcpu->kvm->arch.config_lock);
1992
1993 /*
1994 * Once the VM has started the ID registers are immutable. Reject any
1995 * write that does not match the final register value.
1996 */
1997 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1998 if (val != read_id_reg(vcpu, rd))
1999 ret = -EBUSY;
2000 else
2001 ret = 0;
2002
2003 mutex_unlock(&vcpu->kvm->arch.config_lock);
2004 return ret;
2005 }
2006
2007 ret = arm64_check_features(vcpu, rd, val);
2008 if (!ret)
2009 kvm_set_vm_id_reg(vcpu->kvm, id, val);
2010
2011 mutex_unlock(&vcpu->kvm->arch.config_lock);
2012
2013 /*
2014 * arm64_check_features() returns -E2BIG to indicate the register's
2015 * feature set is a superset of the maximally-allowed register value.
2016 * While it would be nice to precisely describe this to userspace, the
2017 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
2018 * writes return -EINVAL.
2019 */
2020 if (ret == -E2BIG)
2021 ret = -EINVAL;
2022 return ret;
2023 }
2024
kvm_set_vm_id_reg(struct kvm * kvm,u32 reg,u64 val)2025 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val)
2026 {
2027 u64 *p = __vm_id_reg(&kvm->arch, reg);
2028
2029 lockdep_assert_held(&kvm->arch.config_lock);
2030
2031 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm))
2032 return;
2033
2034 *p = val;
2035 }
2036
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)2037 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2038 u64 *val)
2039 {
2040 *val = 0;
2041 return 0;
2042 }
2043
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2044 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2045 u64 val)
2046 {
2047 return 0;
2048 }
2049
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2050 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2051 const struct sys_reg_desc *r)
2052 {
2053 if (p->is_write)
2054 return write_to_read_only(vcpu, p, r);
2055
2056 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0);
2057 return true;
2058 }
2059
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2060 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2061 const struct sys_reg_desc *r)
2062 {
2063 if (p->is_write)
2064 return write_to_read_only(vcpu, p, r);
2065
2066 p->regval = __vcpu_sys_reg(vcpu, r->reg);
2067 return true;
2068 }
2069
2070 /*
2071 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
2072 * by the physical CPU which the vcpu currently resides in.
2073 */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2074 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2075 {
2076 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
2077 u64 clidr;
2078 u8 loc;
2079
2080 if ((ctr_el0 & CTR_EL0_IDC)) {
2081 /*
2082 * Data cache clean to the PoU is not required so LoUU and LoUIS
2083 * will not be set and a unified cache, which will be marked as
2084 * LoC, will be added.
2085 *
2086 * If not DIC, let the unified cache L2 so that an instruction
2087 * cache can be added as L1 later.
2088 */
2089 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
2090 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
2091 } else {
2092 /*
2093 * Data cache clean to the PoU is required so let L1 have a data
2094 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
2095 * it can be marked as LoC too.
2096 */
2097 loc = 1;
2098 clidr = 1 << CLIDR_LOUU_SHIFT;
2099 clidr |= 1 << CLIDR_LOUIS_SHIFT;
2100 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
2101 }
2102
2103 /*
2104 * Instruction cache invalidation to the PoU is required so let L1 have
2105 * an instruction cache. If L1 already has a data cache, it will be
2106 * CACHE_TYPE_SEPARATE.
2107 */
2108 if (!(ctr_el0 & CTR_EL0_DIC))
2109 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
2110
2111 clidr |= loc << CLIDR_LOC_SHIFT;
2112
2113 /*
2114 * Add tag cache unified to data cache. Allocation tags and data are
2115 * unified in a cache line so that it looks valid even if there is only
2116 * one cache line.
2117 */
2118 if (kvm_has_mte(vcpu->kvm))
2119 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
2120
2121 __vcpu_sys_reg(vcpu, r->reg) = clidr;
2122
2123 return __vcpu_sys_reg(vcpu, r->reg);
2124 }
2125
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2126 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2127 u64 val)
2128 {
2129 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
2130 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
2131
2132 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
2133 return -EINVAL;
2134
2135 __vcpu_sys_reg(vcpu, rd->reg) = val;
2136
2137 return 0;
2138 }
2139
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2140 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2141 const struct sys_reg_desc *r)
2142 {
2143 int reg = r->reg;
2144
2145 if (p->is_write)
2146 vcpu_write_sys_reg(vcpu, p->regval, reg);
2147 else
2148 p->regval = vcpu_read_sys_reg(vcpu, reg);
2149 return true;
2150 }
2151
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2152 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2153 const struct sys_reg_desc *r)
2154 {
2155 u32 csselr;
2156
2157 if (p->is_write)
2158 return write_to_read_only(vcpu, p, r);
2159
2160 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
2161 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
2162 if (csselr < CSSELR_MAX)
2163 p->regval = get_ccsidr(vcpu, csselr);
2164
2165 return true;
2166 }
2167
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2168 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
2169 const struct sys_reg_desc *rd)
2170 {
2171 if (kvm_has_mte(vcpu->kvm))
2172 return 0;
2173
2174 return REG_HIDDEN;
2175 }
2176
2177 #define MTE_REG(name) { \
2178 SYS_DESC(SYS_##name), \
2179 .access = undef_access, \
2180 .reset = reset_unknown, \
2181 .reg = name, \
2182 .visibility = mte_visibility, \
2183 }
2184
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2185 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
2186 const struct sys_reg_desc *rd)
2187 {
2188 if (vcpu_has_nv(vcpu))
2189 return 0;
2190
2191 return REG_HIDDEN;
2192 }
2193
bad_vncr_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2194 static bool bad_vncr_trap(struct kvm_vcpu *vcpu,
2195 struct sys_reg_params *p,
2196 const struct sys_reg_desc *r)
2197 {
2198 /*
2199 * We really shouldn't be here, and this is likely the result
2200 * of a misconfigured trap, as this register should target the
2201 * VNCR page, and nothing else.
2202 */
2203 return bad_trap(vcpu, p, r,
2204 "trap of VNCR-backed register");
2205 }
2206
bad_redir_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2207 static bool bad_redir_trap(struct kvm_vcpu *vcpu,
2208 struct sys_reg_params *p,
2209 const struct sys_reg_desc *r)
2210 {
2211 /*
2212 * We really shouldn't be here, and this is likely the result
2213 * of a misconfigured trap, as this register should target the
2214 * corresponding EL1, and nothing else.
2215 */
2216 return bad_trap(vcpu, p, r,
2217 "trap of EL2 register redirected to EL1");
2218 }
2219
2220 #define EL2_REG(name, acc, rst, v) { \
2221 SYS_DESC(SYS_##name), \
2222 .access = acc, \
2223 .reset = rst, \
2224 .reg = name, \
2225 .visibility = el2_visibility, \
2226 .val = v, \
2227 }
2228
2229 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \
2230 SYS_DESC(SYS_##name), \
2231 .access = acc, \
2232 .reset = rst, \
2233 .reg = name, \
2234 .visibility = filter, \
2235 .val = v, \
2236 }
2237
2238 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v)
2239 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v)
2240
2241 /*
2242 * Since reset() callback and field val are not used for idregs, they will be
2243 * used for specific purposes for idregs.
2244 * The reset() would return KVM sanitised register value. The value would be the
2245 * same as the host kernel sanitised value if there is no KVM sanitisation.
2246 * The val would be used as a mask indicating writable fields for the idreg.
2247 * Only bits with 1 are writable from userspace. This mask might not be
2248 * necessary in the future whenever all ID registers are enabled as writable
2249 * from userspace.
2250 */
2251
2252 #define ID_DESC(name) \
2253 SYS_DESC(SYS_##name), \
2254 .access = access_id_reg, \
2255 .get_user = get_id_reg \
2256
2257 /* sys_reg_desc initialiser for known cpufeature ID registers */
2258 #define ID_SANITISED(name) { \
2259 ID_DESC(name), \
2260 .set_user = set_id_reg, \
2261 .visibility = id_visibility, \
2262 .reset = kvm_read_sanitised_id_reg, \
2263 .val = 0, \
2264 }
2265
2266 /* sys_reg_desc initialiser for known cpufeature ID registers */
2267 #define AA32_ID_SANITISED(name) { \
2268 ID_DESC(name), \
2269 .set_user = set_id_reg, \
2270 .visibility = aa32_id_visibility, \
2271 .reset = kvm_read_sanitised_id_reg, \
2272 .val = 0, \
2273 }
2274
2275 /* sys_reg_desc initialiser for writable ID registers */
2276 #define ID_WRITABLE(name, mask) { \
2277 ID_DESC(name), \
2278 .set_user = set_id_reg, \
2279 .visibility = id_visibility, \
2280 .reset = kvm_read_sanitised_id_reg, \
2281 .val = mask, \
2282 }
2283
2284 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */
2285 #define ID_FILTERED(sysreg, name, mask) { \
2286 ID_DESC(sysreg), \
2287 .set_user = set_##name, \
2288 .visibility = id_visibility, \
2289 .reset = kvm_read_sanitised_id_reg, \
2290 .val = (mask), \
2291 }
2292
2293 /*
2294 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
2295 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
2296 * (1 <= crm < 8, 0 <= Op2 < 8).
2297 */
2298 #define ID_UNALLOCATED(crm, op2) { \
2299 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2300 .access = access_id_reg, \
2301 .get_user = get_id_reg, \
2302 .set_user = set_id_reg, \
2303 .visibility = raz_visibility, \
2304 .reset = kvm_read_sanitised_id_reg, \
2305 .val = 0, \
2306 }
2307
2308 /*
2309 * sys_reg_desc initialiser for known ID registers that we hide from guests.
2310 * For now, these are exposed just like unallocated ID regs: they appear
2311 * RAZ for the guest.
2312 */
2313 #define ID_HIDDEN(name) { \
2314 ID_DESC(name), \
2315 .set_user = set_id_reg, \
2316 .visibility = raz_visibility, \
2317 .reset = kvm_read_sanitised_id_reg, \
2318 .val = 0, \
2319 }
2320
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2321 static bool access_sp_el1(struct kvm_vcpu *vcpu,
2322 struct sys_reg_params *p,
2323 const struct sys_reg_desc *r)
2324 {
2325 if (p->is_write)
2326 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
2327 else
2328 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
2329
2330 return true;
2331 }
2332
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2333 static bool access_elr(struct kvm_vcpu *vcpu,
2334 struct sys_reg_params *p,
2335 const struct sys_reg_desc *r)
2336 {
2337 if (p->is_write)
2338 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
2339 else
2340 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
2341
2342 return true;
2343 }
2344
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2345 static bool access_spsr(struct kvm_vcpu *vcpu,
2346 struct sys_reg_params *p,
2347 const struct sys_reg_desc *r)
2348 {
2349 if (p->is_write)
2350 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
2351 else
2352 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
2353
2354 return true;
2355 }
2356
access_cntkctl_el12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2357 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu,
2358 struct sys_reg_params *p,
2359 const struct sys_reg_desc *r)
2360 {
2361 if (p->is_write)
2362 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval;
2363 else
2364 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);
2365
2366 return true;
2367 }
2368
reset_hcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2369 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2370 {
2371 u64 val = r->val;
2372
2373 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
2374 val |= HCR_E2H;
2375
2376 return __vcpu_sys_reg(vcpu, r->reg) = val;
2377 }
2378
__el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,unsigned int (* fn)(const struct kvm_vcpu *,const struct sys_reg_desc *))2379 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu,
2380 const struct sys_reg_desc *rd,
2381 unsigned int (*fn)(const struct kvm_vcpu *,
2382 const struct sys_reg_desc *))
2383 {
2384 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd);
2385 }
2386
sve_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2387 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu,
2388 const struct sys_reg_desc *rd)
2389 {
2390 return __el2_visibility(vcpu, rd, sve_visibility);
2391 }
2392
access_zcr_el2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2393 static bool access_zcr_el2(struct kvm_vcpu *vcpu,
2394 struct sys_reg_params *p,
2395 const struct sys_reg_desc *r)
2396 {
2397 unsigned int vq;
2398
2399 if (guest_hyp_sve_traps_enabled(vcpu)) {
2400 kvm_inject_nested_sve_trap(vcpu);
2401 return true;
2402 }
2403
2404 if (!p->is_write) {
2405 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2);
2406 return true;
2407 }
2408
2409 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1;
2410 vq = min(vq, vcpu_sve_max_vq(vcpu));
2411 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2);
2412 return true;
2413 }
2414
s1poe_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2415 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu,
2416 const struct sys_reg_desc *rd)
2417 {
2418 if (kvm_has_s1poe(vcpu->kvm))
2419 return 0;
2420
2421 return REG_HIDDEN;
2422 }
2423
s1poe_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2424 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu,
2425 const struct sys_reg_desc *rd)
2426 {
2427 return __el2_visibility(vcpu, rd, s1poe_visibility);
2428 }
2429
tcr2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2430 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu,
2431 const struct sys_reg_desc *rd)
2432 {
2433 if (kvm_has_tcr2(vcpu->kvm))
2434 return 0;
2435
2436 return REG_HIDDEN;
2437 }
2438
tcr2_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2439 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu,
2440 const struct sys_reg_desc *rd)
2441 {
2442 return __el2_visibility(vcpu, rd, tcr2_visibility);
2443 }
2444
s1pie_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2445 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu,
2446 const struct sys_reg_desc *rd)
2447 {
2448 if (kvm_has_s1pie(vcpu->kvm))
2449 return 0;
2450
2451 return REG_HIDDEN;
2452 }
2453
s1pie_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2454 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu,
2455 const struct sys_reg_desc *rd)
2456 {
2457 return __el2_visibility(vcpu, rd, s1pie_visibility);
2458 }
2459
access_mdcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2460 static bool access_mdcr(struct kvm_vcpu *vcpu,
2461 struct sys_reg_params *p,
2462 const struct sys_reg_desc *r)
2463 {
2464 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2);
2465
2466 if (!access_rw(vcpu, p, r))
2467 return false;
2468
2469 /*
2470 * Request a reload of the PMU to enable/disable the counters affected
2471 * by HPME.
2472 */
2473 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME)
2474 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
2475
2476 return true;
2477 }
2478
2479 /*
2480 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and
2481 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them.
2482 * The values made visible to userspace were the register values of the boot
2483 * CPU.
2484 *
2485 * At the same time, reads from these registers at EL1 previously were not
2486 * trapped, allowing the guest to read the actual hardware value. On big-little
2487 * machines, this means the VM can see different values depending on where a
2488 * given vCPU got scheduled.
2489 *
2490 * These registers are now trapped as collateral damage from SME, and what
2491 * follows attempts to give a user / guest view consistent with the existing
2492 * ABI.
2493 */
access_imp_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2494 static bool access_imp_id_reg(struct kvm_vcpu *vcpu,
2495 struct sys_reg_params *p,
2496 const struct sys_reg_desc *r)
2497 {
2498 if (p->is_write)
2499 return write_to_read_only(vcpu, p, r);
2500
2501 switch (reg_to_encoding(r)) {
2502 case SYS_REVIDR_EL1:
2503 p->regval = read_sysreg(revidr_el1);
2504 break;
2505 case SYS_AIDR_EL1:
2506 p->regval = read_sysreg(aidr_el1);
2507 break;
2508 default:
2509 WARN_ON_ONCE(1);
2510 }
2511
2512 return true;
2513 }
2514
2515 static u64 __ro_after_init boot_cpu_midr_val;
2516 static u64 __ro_after_init boot_cpu_revidr_val;
2517 static u64 __ro_after_init boot_cpu_aidr_val;
2518
init_imp_id_regs(void)2519 static void init_imp_id_regs(void)
2520 {
2521 boot_cpu_midr_val = read_sysreg(midr_el1);
2522 boot_cpu_revidr_val = read_sysreg(revidr_el1);
2523 boot_cpu_aidr_val = read_sysreg(aidr_el1);
2524 }
2525
get_imp_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)2526 static int get_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
2527 u64 *val)
2528 {
2529 switch (reg_to_encoding(r)) {
2530 case SYS_MIDR_EL1:
2531 *val = boot_cpu_midr_val;
2532 break;
2533 case SYS_REVIDR_EL1:
2534 *val = boot_cpu_revidr_val;
2535 break;
2536 case SYS_AIDR_EL1:
2537 *val = boot_cpu_aidr_val;
2538 break;
2539 default:
2540 WARN_ON_ONCE(1);
2541 return -EINVAL;
2542 }
2543
2544 return 0;
2545 }
2546
set_imp_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)2547 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
2548 u64 val)
2549 {
2550 u64 expected;
2551 int ret;
2552
2553 ret = get_imp_id_reg(vcpu, r, &expected);
2554 if (ret)
2555 return ret;
2556
2557 return (expected == val) ? 0 : -EINVAL;
2558 }
2559
2560 #define IMPLEMENTATION_ID(reg) { \
2561 SYS_DESC(SYS_##reg), \
2562 .access = access_imp_id_reg, \
2563 .get_user = get_imp_id_reg, \
2564 .set_user = set_imp_id_reg, \
2565 }
2566
2567 /*
2568 * Architected system registers.
2569 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2570 *
2571 * Debug handling: We do trap most, if not all debug related system
2572 * registers. The implementation is good enough to ensure that a guest
2573 * can use these with minimal performance degradation. The drawback is
2574 * that we don't implement any of the external debug architecture.
2575 * This should be revisited if we ever encounter a more demanding
2576 * guest...
2577 */
2578 static const struct sys_reg_desc sys_reg_descs[] = {
2579 DBG_BCR_BVR_WCR_WVR_EL1(0),
2580 DBG_BCR_BVR_WCR_WVR_EL1(1),
2581 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2582 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2583 DBG_BCR_BVR_WCR_WVR_EL1(2),
2584 DBG_BCR_BVR_WCR_WVR_EL1(3),
2585 DBG_BCR_BVR_WCR_WVR_EL1(4),
2586 DBG_BCR_BVR_WCR_WVR_EL1(5),
2587 DBG_BCR_BVR_WCR_WVR_EL1(6),
2588 DBG_BCR_BVR_WCR_WVR_EL1(7),
2589 DBG_BCR_BVR_WCR_WVR_EL1(8),
2590 DBG_BCR_BVR_WCR_WVR_EL1(9),
2591 DBG_BCR_BVR_WCR_WVR_EL1(10),
2592 DBG_BCR_BVR_WCR_WVR_EL1(11),
2593 DBG_BCR_BVR_WCR_WVR_EL1(12),
2594 DBG_BCR_BVR_WCR_WVR_EL1(13),
2595 DBG_BCR_BVR_WCR_WVR_EL1(14),
2596 DBG_BCR_BVR_WCR_WVR_EL1(15),
2597
2598 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
2599 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
2600 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2601 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
2602 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
2603 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
2604 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
2605 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
2606 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
2607
2608 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
2609 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
2610 // DBGDTR[TR]X_EL0 share the same encoding
2611 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
2612
2613 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
2614
2615 IMPLEMENTATION_ID(MIDR_EL1),
2616 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
2617 IMPLEMENTATION_ID(REVIDR_EL1),
2618
2619 /*
2620 * ID regs: all ID_SANITISED() entries here must have corresponding
2621 * entries in arm64_ftr_regs[].
2622 */
2623
2624 /* AArch64 mappings of the AArch32 ID registers */
2625 /* CRm=1 */
2626 AA32_ID_SANITISED(ID_PFR0_EL1),
2627 AA32_ID_SANITISED(ID_PFR1_EL1),
2628 { SYS_DESC(SYS_ID_DFR0_EL1),
2629 .access = access_id_reg,
2630 .get_user = get_id_reg,
2631 .set_user = set_id_dfr0_el1,
2632 .visibility = aa32_id_visibility,
2633 .reset = read_sanitised_id_dfr0_el1,
2634 .val = ID_DFR0_EL1_PerfMon_MASK |
2635 ID_DFR0_EL1_CopDbg_MASK, },
2636 ID_HIDDEN(ID_AFR0_EL1),
2637 AA32_ID_SANITISED(ID_MMFR0_EL1),
2638 AA32_ID_SANITISED(ID_MMFR1_EL1),
2639 AA32_ID_SANITISED(ID_MMFR2_EL1),
2640 AA32_ID_SANITISED(ID_MMFR3_EL1),
2641
2642 /* CRm=2 */
2643 AA32_ID_SANITISED(ID_ISAR0_EL1),
2644 AA32_ID_SANITISED(ID_ISAR1_EL1),
2645 AA32_ID_SANITISED(ID_ISAR2_EL1),
2646 AA32_ID_SANITISED(ID_ISAR3_EL1),
2647 AA32_ID_SANITISED(ID_ISAR4_EL1),
2648 AA32_ID_SANITISED(ID_ISAR5_EL1),
2649 AA32_ID_SANITISED(ID_MMFR4_EL1),
2650 AA32_ID_SANITISED(ID_ISAR6_EL1),
2651
2652 /* CRm=3 */
2653 AA32_ID_SANITISED(MVFR0_EL1),
2654 AA32_ID_SANITISED(MVFR1_EL1),
2655 AA32_ID_SANITISED(MVFR2_EL1),
2656 ID_UNALLOCATED(3,3),
2657 AA32_ID_SANITISED(ID_PFR2_EL1),
2658 ID_HIDDEN(ID_DFR1_EL1),
2659 AA32_ID_SANITISED(ID_MMFR5_EL1),
2660 ID_UNALLOCATED(3,7),
2661
2662 /* AArch64 ID registers */
2663 /* CRm=4 */
2664 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1,
2665 ~(ID_AA64PFR0_EL1_AMU |
2666 ID_AA64PFR0_EL1_MPAM |
2667 ID_AA64PFR0_EL1_SVE |
2668 ID_AA64PFR0_EL1_RAS |
2669 ID_AA64PFR0_EL1_AdvSIMD |
2670 ID_AA64PFR0_EL1_FP)),
2671 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1,
2672 ~(ID_AA64PFR1_EL1_PFAR |
2673 ID_AA64PFR1_EL1_DF2 |
2674 ID_AA64PFR1_EL1_MTEX |
2675 ID_AA64PFR1_EL1_THE |
2676 ID_AA64PFR1_EL1_GCS |
2677 ID_AA64PFR1_EL1_MTE_frac |
2678 ID_AA64PFR1_EL1_NMI |
2679 ID_AA64PFR1_EL1_RNDR_trap |
2680 ID_AA64PFR1_EL1_SME |
2681 ID_AA64PFR1_EL1_RES0 |
2682 ID_AA64PFR1_EL1_MPAM_frac |
2683 ID_AA64PFR1_EL1_RAS_frac |
2684 ID_AA64PFR1_EL1_MTE)),
2685 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
2686 ID_UNALLOCATED(4,3),
2687 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
2688 ID_HIDDEN(ID_AA64SMFR0_EL1),
2689 ID_UNALLOCATED(4,6),
2690 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0),
2691
2692 /* CRm=5 */
2693 /*
2694 * Prior to FEAT_Debugv8.9, the architecture defines context-aware
2695 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs).
2696 * KVM does not trap + emulate the breakpoint registers, and as such
2697 * cannot support a layout that misaligns with the underlying hardware.
2698 * While it may be possible to describe a subset that aligns with
2699 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for
2700 * simplicity.
2701 *
2702 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking
2703 * of breakpoints for more details.
2704 */
2705 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1,
2706 ID_AA64DFR0_EL1_DoubleLock_MASK |
2707 ID_AA64DFR0_EL1_WRPs_MASK |
2708 ID_AA64DFR0_EL1_PMUVer_MASK |
2709 ID_AA64DFR0_EL1_DebugVer_MASK),
2710 ID_SANITISED(ID_AA64DFR1_EL1),
2711 ID_UNALLOCATED(5,2),
2712 ID_UNALLOCATED(5,3),
2713 ID_HIDDEN(ID_AA64AFR0_EL1),
2714 ID_HIDDEN(ID_AA64AFR1_EL1),
2715 ID_UNALLOCATED(5,6),
2716 ID_UNALLOCATED(5,7),
2717
2718 /* CRm=6 */
2719 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
2720 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
2721 ID_AA64ISAR1_EL1_GPA |
2722 ID_AA64ISAR1_EL1_API |
2723 ID_AA64ISAR1_EL1_APA)),
2724 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
2725 ID_AA64ISAR2_EL1_APA3 |
2726 ID_AA64ISAR2_EL1_GPA3)),
2727 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
2728 ID_AA64ISAR3_EL1_FAMINMAX)),
2729 ID_UNALLOCATED(6,4),
2730 ID_UNALLOCATED(6,5),
2731 ID_UNALLOCATED(6,6),
2732 ID_UNALLOCATED(6,7),
2733
2734 /* CRm=7 */
2735 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |
2736 ID_AA64MMFR0_EL1_TGRAN4_2 |
2737 ID_AA64MMFR0_EL1_TGRAN64_2 |
2738 ID_AA64MMFR0_EL1_TGRAN16_2 |
2739 ID_AA64MMFR0_EL1_ASIDBITS)),
2740 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
2741 ID_AA64MMFR1_EL1_HCX |
2742 ID_AA64MMFR1_EL1_TWED |
2743 ID_AA64MMFR1_EL1_XNX |
2744 ID_AA64MMFR1_EL1_VH |
2745 ID_AA64MMFR1_EL1_VMIDBits)),
2746 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
2747 ID_AA64MMFR2_EL1_EVT |
2748 ID_AA64MMFR2_EL1_FWB |
2749 ID_AA64MMFR2_EL1_IDS |
2750 ID_AA64MMFR2_EL1_NV |
2751 ID_AA64MMFR2_EL1_CCIDX)),
2752 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX |
2753 ID_AA64MMFR3_EL1_S1PIE |
2754 ID_AA64MMFR3_EL1_S1POE)),
2755 ID_SANITISED(ID_AA64MMFR4_EL1),
2756 ID_UNALLOCATED(7,5),
2757 ID_UNALLOCATED(7,6),
2758 ID_UNALLOCATED(7,7),
2759
2760 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2761 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2762 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2763
2764 MTE_REG(RGSR_EL1),
2765 MTE_REG(GCR_EL1),
2766
2767 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2768 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2769 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2770 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2771 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2772 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2773 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2774 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0,
2775 .visibility = tcr2_visibility },
2776
2777 PTRAUTH_KEY(APIA),
2778 PTRAUTH_KEY(APIB),
2779 PTRAUTH_KEY(APDA),
2780 PTRAUTH_KEY(APDB),
2781 PTRAUTH_KEY(APGA),
2782
2783 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2784 { SYS_DESC(SYS_ELR_EL1), access_elr},
2785
2786 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
2787
2788 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2789 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2790 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2791
2792 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2793 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2794 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2795 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2796 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2797 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2798 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2799 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2800
2801 MTE_REG(TFSR_EL1),
2802 MTE_REG(TFSRE0_EL1),
2803
2804 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2805 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2806
2807 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2808 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2809 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2810 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2811 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2812 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2813 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2814 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2815 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2816 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2817 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2818 /* PMBIDR_EL1 is not trapped */
2819
2820 { PMU_SYS_REG(PMINTENSET_EL1),
2821 .access = access_pminten, .reg = PMINTENSET_EL1,
2822 .get_user = get_pmreg, .set_user = set_pmreg },
2823 { PMU_SYS_REG(PMINTENCLR_EL1),
2824 .access = access_pminten, .reg = PMINTENSET_EL1,
2825 .get_user = get_pmreg, .set_user = set_pmreg },
2826 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2827
2828 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2829 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1,
2830 .visibility = s1pie_visibility },
2831 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1,
2832 .visibility = s1pie_visibility },
2833 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1,
2834 .visibility = s1poe_visibility },
2835 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2836
2837 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2838 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2839 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2840 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2841 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access },
2842 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
2843
2844 { SYS_DESC(SYS_MPAM1_EL1), undef_access },
2845 { SYS_DESC(SYS_MPAM0_EL1), undef_access },
2846 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2847 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2848
2849 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
2850 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
2851 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
2852 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
2853 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
2854 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
2855 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
2856 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
2857 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
2858 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
2859 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
2860 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
2861 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
2862 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
2863 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2864 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2865 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2866 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
2867 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
2868 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
2869 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
2870 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
2871 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2872 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
2873 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
2874
2875 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2876 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2877
2878 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2879
2880 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2881
2882 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2883
2884 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2885 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2886 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 },
2887 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2888 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2889 IMPLEMENTATION_ID(AIDR_EL1),
2890 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2891 ID_FILTERED(CTR_EL0, ctr_el0,
2892 CTR_EL0_DIC_MASK |
2893 CTR_EL0_IDC_MASK |
2894 CTR_EL0_DminLine_MASK |
2895 CTR_EL0_L1Ip_MASK |
2896 CTR_EL0_IminLine_MASK),
2897 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
2898 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
2899
2900 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
2901 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
2902 { PMU_SYS_REG(PMCNTENSET_EL0),
2903 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2904 .get_user = get_pmreg, .set_user = set_pmreg },
2905 { PMU_SYS_REG(PMCNTENCLR_EL0),
2906 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2907 .get_user = get_pmreg, .set_user = set_pmreg },
2908 { PMU_SYS_REG(PMOVSCLR_EL0),
2909 .access = access_pmovs, .reg = PMOVSSET_EL0,
2910 .get_user = get_pmreg, .set_user = set_pmreg },
2911 /*
2912 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2913 * previously (and pointlessly) advertised in the past...
2914 */
2915 { PMU_SYS_REG(PMSWINC_EL0),
2916 .get_user = get_raz_reg, .set_user = set_wi_reg,
2917 .access = access_pmswinc, .reset = NULL },
2918 { PMU_SYS_REG(PMSELR_EL0),
2919 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2920 { PMU_SYS_REG(PMCEID0_EL0),
2921 .access = access_pmceid, .reset = NULL },
2922 { PMU_SYS_REG(PMCEID1_EL0),
2923 .access = access_pmceid, .reset = NULL },
2924 { PMU_SYS_REG(PMCCNTR_EL0),
2925 .access = access_pmu_evcntr, .reset = reset_unknown,
2926 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2927 { PMU_SYS_REG(PMXEVTYPER_EL0),
2928 .access = access_pmu_evtyper, .reset = NULL },
2929 { PMU_SYS_REG(PMXEVCNTR_EL0),
2930 .access = access_pmu_evcntr, .reset = NULL },
2931 /*
2932 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2933 * in 32bit mode. Here we choose to reset it as zero for consistency.
2934 */
2935 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2936 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2937 { PMU_SYS_REG(PMOVSSET_EL0),
2938 .access = access_pmovs, .reg = PMOVSSET_EL0,
2939 .get_user = get_pmreg, .set_user = set_pmreg },
2940
2941 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0,
2942 .visibility = s1poe_visibility },
2943 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2944 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2945 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2946
2947 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2948
2949 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2950 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2951 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2952 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2953 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2954 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2955 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2956 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2957 AMU_AMEVCNTR0_EL0(0),
2958 AMU_AMEVCNTR0_EL0(1),
2959 AMU_AMEVCNTR0_EL0(2),
2960 AMU_AMEVCNTR0_EL0(3),
2961 AMU_AMEVCNTR0_EL0(4),
2962 AMU_AMEVCNTR0_EL0(5),
2963 AMU_AMEVCNTR0_EL0(6),
2964 AMU_AMEVCNTR0_EL0(7),
2965 AMU_AMEVCNTR0_EL0(8),
2966 AMU_AMEVCNTR0_EL0(9),
2967 AMU_AMEVCNTR0_EL0(10),
2968 AMU_AMEVCNTR0_EL0(11),
2969 AMU_AMEVCNTR0_EL0(12),
2970 AMU_AMEVCNTR0_EL0(13),
2971 AMU_AMEVCNTR0_EL0(14),
2972 AMU_AMEVCNTR0_EL0(15),
2973 AMU_AMEVTYPER0_EL0(0),
2974 AMU_AMEVTYPER0_EL0(1),
2975 AMU_AMEVTYPER0_EL0(2),
2976 AMU_AMEVTYPER0_EL0(3),
2977 AMU_AMEVTYPER0_EL0(4),
2978 AMU_AMEVTYPER0_EL0(5),
2979 AMU_AMEVTYPER0_EL0(6),
2980 AMU_AMEVTYPER0_EL0(7),
2981 AMU_AMEVTYPER0_EL0(8),
2982 AMU_AMEVTYPER0_EL0(9),
2983 AMU_AMEVTYPER0_EL0(10),
2984 AMU_AMEVTYPER0_EL0(11),
2985 AMU_AMEVTYPER0_EL0(12),
2986 AMU_AMEVTYPER0_EL0(13),
2987 AMU_AMEVTYPER0_EL0(14),
2988 AMU_AMEVTYPER0_EL0(15),
2989 AMU_AMEVCNTR1_EL0(0),
2990 AMU_AMEVCNTR1_EL0(1),
2991 AMU_AMEVCNTR1_EL0(2),
2992 AMU_AMEVCNTR1_EL0(3),
2993 AMU_AMEVCNTR1_EL0(4),
2994 AMU_AMEVCNTR1_EL0(5),
2995 AMU_AMEVCNTR1_EL0(6),
2996 AMU_AMEVCNTR1_EL0(7),
2997 AMU_AMEVCNTR1_EL0(8),
2998 AMU_AMEVCNTR1_EL0(9),
2999 AMU_AMEVCNTR1_EL0(10),
3000 AMU_AMEVCNTR1_EL0(11),
3001 AMU_AMEVCNTR1_EL0(12),
3002 AMU_AMEVCNTR1_EL0(13),
3003 AMU_AMEVCNTR1_EL0(14),
3004 AMU_AMEVCNTR1_EL0(15),
3005 AMU_AMEVTYPER1_EL0(0),
3006 AMU_AMEVTYPER1_EL0(1),
3007 AMU_AMEVTYPER1_EL0(2),
3008 AMU_AMEVTYPER1_EL0(3),
3009 AMU_AMEVTYPER1_EL0(4),
3010 AMU_AMEVTYPER1_EL0(5),
3011 AMU_AMEVTYPER1_EL0(6),
3012 AMU_AMEVTYPER1_EL0(7),
3013 AMU_AMEVTYPER1_EL0(8),
3014 AMU_AMEVTYPER1_EL0(9),
3015 AMU_AMEVTYPER1_EL0(10),
3016 AMU_AMEVTYPER1_EL0(11),
3017 AMU_AMEVTYPER1_EL0(12),
3018 AMU_AMEVTYPER1_EL0(13),
3019 AMU_AMEVTYPER1_EL0(14),
3020 AMU_AMEVTYPER1_EL0(15),
3021
3022 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
3023 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer },
3024 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
3025 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer },
3026 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
3027 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
3028 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
3029
3030 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer },
3031 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer },
3032 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer },
3033
3034 /* PMEVCNTRn_EL0 */
3035 PMU_PMEVCNTR_EL0(0),
3036 PMU_PMEVCNTR_EL0(1),
3037 PMU_PMEVCNTR_EL0(2),
3038 PMU_PMEVCNTR_EL0(3),
3039 PMU_PMEVCNTR_EL0(4),
3040 PMU_PMEVCNTR_EL0(5),
3041 PMU_PMEVCNTR_EL0(6),
3042 PMU_PMEVCNTR_EL0(7),
3043 PMU_PMEVCNTR_EL0(8),
3044 PMU_PMEVCNTR_EL0(9),
3045 PMU_PMEVCNTR_EL0(10),
3046 PMU_PMEVCNTR_EL0(11),
3047 PMU_PMEVCNTR_EL0(12),
3048 PMU_PMEVCNTR_EL0(13),
3049 PMU_PMEVCNTR_EL0(14),
3050 PMU_PMEVCNTR_EL0(15),
3051 PMU_PMEVCNTR_EL0(16),
3052 PMU_PMEVCNTR_EL0(17),
3053 PMU_PMEVCNTR_EL0(18),
3054 PMU_PMEVCNTR_EL0(19),
3055 PMU_PMEVCNTR_EL0(20),
3056 PMU_PMEVCNTR_EL0(21),
3057 PMU_PMEVCNTR_EL0(22),
3058 PMU_PMEVCNTR_EL0(23),
3059 PMU_PMEVCNTR_EL0(24),
3060 PMU_PMEVCNTR_EL0(25),
3061 PMU_PMEVCNTR_EL0(26),
3062 PMU_PMEVCNTR_EL0(27),
3063 PMU_PMEVCNTR_EL0(28),
3064 PMU_PMEVCNTR_EL0(29),
3065 PMU_PMEVCNTR_EL0(30),
3066 /* PMEVTYPERn_EL0 */
3067 PMU_PMEVTYPER_EL0(0),
3068 PMU_PMEVTYPER_EL0(1),
3069 PMU_PMEVTYPER_EL0(2),
3070 PMU_PMEVTYPER_EL0(3),
3071 PMU_PMEVTYPER_EL0(4),
3072 PMU_PMEVTYPER_EL0(5),
3073 PMU_PMEVTYPER_EL0(6),
3074 PMU_PMEVTYPER_EL0(7),
3075 PMU_PMEVTYPER_EL0(8),
3076 PMU_PMEVTYPER_EL0(9),
3077 PMU_PMEVTYPER_EL0(10),
3078 PMU_PMEVTYPER_EL0(11),
3079 PMU_PMEVTYPER_EL0(12),
3080 PMU_PMEVTYPER_EL0(13),
3081 PMU_PMEVTYPER_EL0(14),
3082 PMU_PMEVTYPER_EL0(15),
3083 PMU_PMEVTYPER_EL0(16),
3084 PMU_PMEVTYPER_EL0(17),
3085 PMU_PMEVTYPER_EL0(18),
3086 PMU_PMEVTYPER_EL0(19),
3087 PMU_PMEVTYPER_EL0(20),
3088 PMU_PMEVTYPER_EL0(21),
3089 PMU_PMEVTYPER_EL0(22),
3090 PMU_PMEVTYPER_EL0(23),
3091 PMU_PMEVTYPER_EL0(24),
3092 PMU_PMEVTYPER_EL0(25),
3093 PMU_PMEVTYPER_EL0(26),
3094 PMU_PMEVTYPER_EL0(27),
3095 PMU_PMEVTYPER_EL0(28),
3096 PMU_PMEVTYPER_EL0(29),
3097 PMU_PMEVTYPER_EL0(30),
3098 /*
3099 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
3100 * in 32bit mode. Here we choose to reset it as zero for consistency.
3101 */
3102 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
3103 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
3104
3105 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0),
3106 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0),
3107 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
3108 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
3109 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),
3110 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0),
3111 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
3112 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
3113 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
3114 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0),
3115 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
3116 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
3117
3118 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0,
3119 sve_el2_visibility),
3120
3121 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
3122
3123 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
3124 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
3125 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
3126 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,
3127 tcr2_el2_visibility),
3128 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
3129 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
3130
3131 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
3132 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
3133 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
3134 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
3135 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
3136 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
3137 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
3138
3139 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
3140 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi },
3141 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi },
3142 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi },
3143 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi },
3144
3145 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },
3146 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
3147 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
3148 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
3149 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
3150
3151 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
3152 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
3153
3154 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
3155 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,
3156 s1pie_el2_visibility),
3157 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
3158 s1pie_el2_visibility),
3159 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0,
3160 s1poe_el2_visibility),
3161 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
3162 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access },
3163 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },
3164 { SYS_DESC(SYS_MPAM2_EL2), undef_access },
3165 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },
3166 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },
3167 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },
3168 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },
3169 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },
3170 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },
3171 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },
3172 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },
3173
3174 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
3175 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
3176 { SYS_DESC(SYS_RMR_EL2), undef_access },
3177
3178 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0),
3179
3180 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
3181 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
3182
3183 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
3184 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
3185 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer },
3186 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0),
3187 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0),
3188
3189 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_hv_timer },
3190 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0),
3191 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0),
3192
3193 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 },
3194
3195 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer },
3196 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer },
3197 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer },
3198
3199 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer },
3200 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer },
3201 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer },
3202
3203 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
3204 };
3205
handle_at_s1e01(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3206 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3207 const struct sys_reg_desc *r)
3208 {
3209 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3210
3211 __kvm_at_s1e01(vcpu, op, p->regval);
3212
3213 return true;
3214 }
3215
handle_at_s1e2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3216 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3217 const struct sys_reg_desc *r)
3218 {
3219 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3220
3221 /* There is no FGT associated with AT S1E2A :-( */
3222 if (op == OP_AT_S1E2A &&
3223 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) {
3224 kvm_inject_undefined(vcpu);
3225 return false;
3226 }
3227
3228 __kvm_at_s1e2(vcpu, op, p->regval);
3229
3230 return true;
3231 }
3232
handle_at_s12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3233 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3234 const struct sys_reg_desc *r)
3235 {
3236 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3237
3238 __kvm_at_s12(vcpu, op, p->regval);
3239
3240 return true;
3241 }
3242
kvm_supported_tlbi_s12_op(struct kvm_vcpu * vpcu,u32 instr)3243 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr)
3244 {
3245 struct kvm *kvm = vpcu->kvm;
3246 u8 CRm = sys_reg_CRm(instr);
3247
3248 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
3249 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
3250 return false;
3251
3252 if (CRm == TLBI_CRm_nROS &&
3253 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
3254 return false;
3255
3256 return true;
3257 }
3258
handle_alle1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3259 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3260 const struct sys_reg_desc *r)
3261 {
3262 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3263
3264 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
3265 return undef_access(vcpu, p, r);
3266
3267 write_lock(&vcpu->kvm->mmu_lock);
3268
3269 /*
3270 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the
3271 * corresponding VMIDs.
3272 */
3273 kvm_nested_s2_unmap(vcpu->kvm, true);
3274
3275 write_unlock(&vcpu->kvm->mmu_lock);
3276
3277 return true;
3278 }
3279
kvm_supported_tlbi_ipas2_op(struct kvm_vcpu * vpcu,u32 instr)3280 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr)
3281 {
3282 struct kvm *kvm = vpcu->kvm;
3283 u8 CRm = sys_reg_CRm(instr);
3284 u8 Op2 = sys_reg_Op2(instr);
3285
3286 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
3287 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
3288 return false;
3289
3290 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&
3291 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
3292 return false;
3293
3294 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&
3295 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
3296 return false;
3297
3298 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&
3299 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
3300 return false;
3301
3302 return true;
3303 }
3304
3305 /* Only defined here as this is an internal "abstraction" */
3306 union tlbi_info {
3307 struct {
3308 u64 start;
3309 u64 size;
3310 } range;
3311
3312 struct {
3313 u64 addr;
3314 } ipa;
3315
3316 struct {
3317 u64 addr;
3318 u32 encoding;
3319 } va;
3320 };
3321
s2_mmu_unmap_range(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3322 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu,
3323 const union tlbi_info *info)
3324 {
3325 /*
3326 * The unmap operation is allowed to drop the MMU lock and block, which
3327 * means that @mmu could be used for a different context than the one
3328 * currently being invalidated.
3329 *
3330 * This behavior is still safe, as:
3331 *
3332 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating
3333 * the entire MMU before reusing it, which still honors the intent
3334 * of a TLBI.
3335 *
3336 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC
3337 * and ERET to the guest), other vCPUs are allowed to use stale
3338 * translations.
3339 *
3340 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and
3341 * at worst may cause more aborts for shadow stage-2 fills.
3342 *
3343 * Dropping the MMU lock also implies that shadow stage-2 fills could
3344 * happen behind the back of the TLBI. This is still safe, though, as
3345 * the L1 needs to put its stage-2 in a consistent state before doing
3346 * the TLBI.
3347 */
3348 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true);
3349 }
3350
handle_vmalls12e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3351 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3352 const struct sys_reg_desc *r)
3353 {
3354 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3355 u64 limit, vttbr;
3356
3357 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
3358 return undef_access(vcpu, p, r);
3359
3360 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3361 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm));
3362
3363 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3364 &(union tlbi_info) {
3365 .range = {
3366 .start = 0,
3367 .size = limit,
3368 },
3369 },
3370 s2_mmu_unmap_range);
3371
3372 return true;
3373 }
3374
handle_ripas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3375 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3376 const struct sys_reg_desc *r)
3377 {
3378 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3379 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3380 u64 base, range, tg, num, scale;
3381 int shift;
3382
3383 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
3384 return undef_access(vcpu, p, r);
3385
3386 /*
3387 * Because the shadow S2 structure doesn't necessarily reflect that
3388 * of the guest's S2 (different base granule size, for example), we
3389 * decide to ignore TTL and only use the described range.
3390 */
3391 tg = FIELD_GET(GENMASK(47, 46), p->regval);
3392 scale = FIELD_GET(GENMASK(45, 44), p->regval);
3393 num = FIELD_GET(GENMASK(43, 39), p->regval);
3394 base = p->regval & GENMASK(36, 0);
3395
3396 switch(tg) {
3397 case 1:
3398 shift = 12;
3399 break;
3400 case 2:
3401 shift = 14;
3402 break;
3403 case 3:
3404 default: /* IMPDEF: handle tg==0 as 64k */
3405 shift = 16;
3406 break;
3407 }
3408
3409 base <<= shift;
3410 range = __TLBI_RANGE_PAGES(num, scale) << shift;
3411
3412 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3413 &(union tlbi_info) {
3414 .range = {
3415 .start = base,
3416 .size = range,
3417 },
3418 },
3419 s2_mmu_unmap_range);
3420
3421 return true;
3422 }
3423
s2_mmu_unmap_ipa(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3424 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu,
3425 const union tlbi_info *info)
3426 {
3427 unsigned long max_size;
3428 u64 base_addr;
3429
3430 /*
3431 * We drop a number of things from the supplied value:
3432 *
3433 * - NS bit: we're non-secure only.
3434 *
3435 * - IPA[51:48]: We don't support 52bit IPA just yet...
3436 *
3437 * And of course, adjust the IPA to be on an actual address.
3438 */
3439 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;
3440 max_size = compute_tlb_inval_range(mmu, info->ipa.addr);
3441 base_addr &= ~(max_size - 1);
3442
3443 /*
3444 * See comment in s2_mmu_unmap_range() for why this is allowed to
3445 * reschedule.
3446 */
3447 kvm_stage2_unmap_range(mmu, base_addr, max_size, true);
3448 }
3449
handle_ipas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3450 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3451 const struct sys_reg_desc *r)
3452 {
3453 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3454 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3455
3456 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
3457 return undef_access(vcpu, p, r);
3458
3459 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3460 &(union tlbi_info) {
3461 .ipa = {
3462 .addr = p->regval,
3463 },
3464 },
3465 s2_mmu_unmap_ipa);
3466
3467 return true;
3468 }
3469
s2_mmu_tlbi_s1e1(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3470 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu,
3471 const union tlbi_info *info)
3472 {
3473 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding));
3474 }
3475
handle_tlbi_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3476 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3477 const struct sys_reg_desc *r)
3478 {
3479 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3480 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3481
3482 /*
3483 * If we're here, this is because we've trapped on a EL1 TLBI
3484 * instruction that affects the EL1 translation regime while
3485 * we're running in a context that doesn't allow us to let the
3486 * HW do its thing (aka vEL2):
3487 *
3488 * - HCR_EL2.E2H == 0 : a non-VHE guest
3489 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode
3490 *
3491 * We don't expect these helpers to ever be called when running
3492 * in a vEL1 context.
3493 */
3494
3495 WARN_ON(!vcpu_is_el2(vcpu));
3496
3497 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding))
3498 return undef_access(vcpu, p, r);
3499
3500 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3501 &(union tlbi_info) {
3502 .va = {
3503 .addr = p->regval,
3504 .encoding = sys_encoding,
3505 },
3506 },
3507 s2_mmu_tlbi_s1e1);
3508
3509 return true;
3510 }
3511
3512 #define SYS_INSN(insn, access_fn) \
3513 { \
3514 SYS_DESC(OP_##insn), \
3515 .access = (access_fn), \
3516 }
3517
3518 static struct sys_reg_desc sys_insn_descs[] = {
3519 { SYS_DESC(SYS_DC_ISW), access_dcsw },
3520 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
3521 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
3522
3523 SYS_INSN(AT_S1E1R, handle_at_s1e01),
3524 SYS_INSN(AT_S1E1W, handle_at_s1e01),
3525 SYS_INSN(AT_S1E0R, handle_at_s1e01),
3526 SYS_INSN(AT_S1E0W, handle_at_s1e01),
3527 SYS_INSN(AT_S1E1RP, handle_at_s1e01),
3528 SYS_INSN(AT_S1E1WP, handle_at_s1e01),
3529
3530 { SYS_DESC(SYS_DC_CSW), access_dcsw },
3531 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
3532 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
3533 { SYS_DESC(SYS_DC_CISW), access_dcsw },
3534 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
3535 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
3536
3537 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1),
3538 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1),
3539 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1),
3540 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1),
3541 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1),
3542 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1),
3543
3544 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1),
3545 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1),
3546 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1),
3547 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1),
3548
3549 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1),
3550 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1),
3551 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1),
3552 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1),
3553 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1),
3554 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1),
3555
3556 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1),
3557 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1),
3558 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1),
3559 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1),
3560
3561 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1),
3562 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1),
3563 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1),
3564 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1),
3565
3566 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1),
3567 SYS_INSN(TLBI_VAE1, handle_tlbi_el1),
3568 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1),
3569 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1),
3570 SYS_INSN(TLBI_VALE1, handle_tlbi_el1),
3571 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1),
3572
3573 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1),
3574 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1),
3575 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1),
3576 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1),
3577 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1),
3578 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1),
3579
3580 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1),
3581 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1),
3582 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1),
3583 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1),
3584
3585 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1),
3586 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1),
3587 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1),
3588 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1),
3589 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1),
3590 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1),
3591
3592 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1),
3593 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1),
3594 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1),
3595 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1),
3596
3597 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1),
3598 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1),
3599 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1),
3600 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1),
3601
3602 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1),
3603 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1),
3604 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1),
3605 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1),
3606 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1),
3607 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1),
3608
3609 SYS_INSN(AT_S1E2R, handle_at_s1e2),
3610 SYS_INSN(AT_S1E2W, handle_at_s1e2),
3611 SYS_INSN(AT_S12E1R, handle_at_s12),
3612 SYS_INSN(AT_S12E1W, handle_at_s12),
3613 SYS_INSN(AT_S12E0R, handle_at_s12),
3614 SYS_INSN(AT_S12E0W, handle_at_s12),
3615 SYS_INSN(AT_S1E2A, handle_at_s1e2),
3616
3617 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),
3618 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is),
3619 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is),
3620 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is),
3621
3622 SYS_INSN(TLBI_ALLE2OS, undef_access),
3623 SYS_INSN(TLBI_VAE2OS, undef_access),
3624 SYS_INSN(TLBI_ALLE1OS, handle_alle1is),
3625 SYS_INSN(TLBI_VALE2OS, undef_access),
3626 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is),
3627
3628 SYS_INSN(TLBI_RVAE2IS, undef_access),
3629 SYS_INSN(TLBI_RVALE2IS, undef_access),
3630
3631 SYS_INSN(TLBI_ALLE1IS, handle_alle1is),
3632 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is),
3633 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is),
3634 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is),
3635 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is),
3636 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is),
3637 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is),
3638 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is),
3639 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is),
3640 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is),
3641 SYS_INSN(TLBI_RVAE2OS, undef_access),
3642 SYS_INSN(TLBI_RVALE2OS, undef_access),
3643 SYS_INSN(TLBI_RVAE2, undef_access),
3644 SYS_INSN(TLBI_RVALE2, undef_access),
3645 SYS_INSN(TLBI_ALLE1, handle_alle1is),
3646 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is),
3647
3648 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is),
3649 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is),
3650 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is),
3651 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is),
3652
3653 SYS_INSN(TLBI_ALLE2OSNXS, undef_access),
3654 SYS_INSN(TLBI_VAE2OSNXS, undef_access),
3655 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is),
3656 SYS_INSN(TLBI_VALE2OSNXS, undef_access),
3657 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is),
3658
3659 SYS_INSN(TLBI_RVAE2ISNXS, undef_access),
3660 SYS_INSN(TLBI_RVALE2ISNXS, undef_access),
3661 SYS_INSN(TLBI_ALLE2ISNXS, undef_access),
3662 SYS_INSN(TLBI_VAE2ISNXS, undef_access),
3663
3664 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is),
3665 SYS_INSN(TLBI_VALE2ISNXS, undef_access),
3666 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is),
3667 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is),
3668 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is),
3669 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is),
3670 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is),
3671 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is),
3672 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is),
3673 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is),
3674 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is),
3675 SYS_INSN(TLBI_RVAE2OSNXS, undef_access),
3676 SYS_INSN(TLBI_RVALE2OSNXS, undef_access),
3677 SYS_INSN(TLBI_RVAE2NXS, undef_access),
3678 SYS_INSN(TLBI_RVALE2NXS, undef_access),
3679 SYS_INSN(TLBI_ALLE2NXS, undef_access),
3680 SYS_INSN(TLBI_VAE2NXS, undef_access),
3681 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is),
3682 SYS_INSN(TLBI_VALE2NXS, undef_access),
3683 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is),
3684 };
3685
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3686 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
3687 struct sys_reg_params *p,
3688 const struct sys_reg_desc *r)
3689 {
3690 if (p->is_write) {
3691 return ignore_write(vcpu, p);
3692 } else {
3693 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1);
3694 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP);
3695
3696 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |
3697 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) |
3698 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) |
3699 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) |
3700 (1 << 15) | (el3 << 14) | (el3 << 12));
3701 return true;
3702 }
3703 }
3704
3705 /*
3706 * AArch32 debug register mappings
3707 *
3708 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
3709 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
3710 *
3711 * None of the other registers share their location, so treat them as
3712 * if they were 64bit.
3713 */
3714 #define DBG_BCR_BVR_WCR_WVR(n) \
3715 /* DBGBVRn */ \
3716 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \
3717 trap_dbg_wb_reg, NULL, n }, \
3718 /* DBGBCRn */ \
3719 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \
3720 /* DBGWVRn */ \
3721 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \
3722 /* DBGWCRn */ \
3723 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n }
3724
3725 #define DBGBXVR(n) \
3726 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \
3727 trap_dbg_wb_reg, NULL, n }
3728
3729 /*
3730 * Trapped cp14 registers. We generally ignore most of the external
3731 * debug, on the principle that they don't really make sense to a
3732 * guest. Revisit this one day, would this principle change.
3733 */
3734 static const struct sys_reg_desc cp14_regs[] = {
3735 /* DBGDIDR */
3736 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
3737 /* DBGDTRRXext */
3738 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
3739
3740 DBG_BCR_BVR_WCR_WVR(0),
3741 /* DBGDSCRint */
3742 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
3743 DBG_BCR_BVR_WCR_WVR(1),
3744 /* DBGDCCINT */
3745 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
3746 /* DBGDSCRext */
3747 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
3748 DBG_BCR_BVR_WCR_WVR(2),
3749 /* DBGDTR[RT]Xint */
3750 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
3751 /* DBGDTR[RT]Xext */
3752 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
3753 DBG_BCR_BVR_WCR_WVR(3),
3754 DBG_BCR_BVR_WCR_WVR(4),
3755 DBG_BCR_BVR_WCR_WVR(5),
3756 /* DBGWFAR */
3757 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
3758 /* DBGOSECCR */
3759 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
3760 DBG_BCR_BVR_WCR_WVR(6),
3761 /* DBGVCR */
3762 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
3763 DBG_BCR_BVR_WCR_WVR(7),
3764 DBG_BCR_BVR_WCR_WVR(8),
3765 DBG_BCR_BVR_WCR_WVR(9),
3766 DBG_BCR_BVR_WCR_WVR(10),
3767 DBG_BCR_BVR_WCR_WVR(11),
3768 DBG_BCR_BVR_WCR_WVR(12),
3769 DBG_BCR_BVR_WCR_WVR(13),
3770 DBG_BCR_BVR_WCR_WVR(14),
3771 DBG_BCR_BVR_WCR_WVR(15),
3772
3773 /* DBGDRAR (32bit) */
3774 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
3775
3776 DBGBXVR(0),
3777 /* DBGOSLAR */
3778 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
3779 DBGBXVR(1),
3780 /* DBGOSLSR */
3781 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
3782 DBGBXVR(2),
3783 DBGBXVR(3),
3784 /* DBGOSDLR */
3785 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
3786 DBGBXVR(4),
3787 /* DBGPRCR */
3788 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
3789 DBGBXVR(5),
3790 DBGBXVR(6),
3791 DBGBXVR(7),
3792 DBGBXVR(8),
3793 DBGBXVR(9),
3794 DBGBXVR(10),
3795 DBGBXVR(11),
3796 DBGBXVR(12),
3797 DBGBXVR(13),
3798 DBGBXVR(14),
3799 DBGBXVR(15),
3800
3801 /* DBGDSAR (32bit) */
3802 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
3803
3804 /* DBGDEVID2 */
3805 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
3806 /* DBGDEVID1 */
3807 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
3808 /* DBGDEVID */
3809 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
3810 /* DBGCLAIMSET */
3811 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
3812 /* DBGCLAIMCLR */
3813 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
3814 /* DBGAUTHSTATUS */
3815 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
3816 };
3817
3818 /* Trapped cp14 64bit registers */
3819 static const struct sys_reg_desc cp14_64_regs[] = {
3820 /* DBGDRAR (64bit) */
3821 { Op1( 0), CRm( 1), .access = trap_raz_wi },
3822
3823 /* DBGDSAR (64bit) */
3824 { Op1( 0), CRm( 2), .access = trap_raz_wi },
3825 };
3826
3827 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
3828 AA32(_map), \
3829 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
3830 .visibility = pmu_visibility
3831
3832 /* Macro to expand the PMEVCNTRn register */
3833 #define PMU_PMEVCNTR(n) \
3834 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3835 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3836 .access = access_pmu_evcntr }
3837
3838 /* Macro to expand the PMEVTYPERn register */
3839 #define PMU_PMEVTYPER(n) \
3840 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3841 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3842 .access = access_pmu_evtyper }
3843 /*
3844 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
3845 * depending on the way they are accessed (as a 32bit or a 64bit
3846 * register).
3847 */
3848 static const struct sys_reg_desc cp15_regs[] = {
3849 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3850 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
3851 /* ACTLR */
3852 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
3853 /* ACTLR2 */
3854 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
3855 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
3856 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
3857 /* TTBCR */
3858 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
3859 /* TTBCR2 */
3860 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
3861 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
3862 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
3863 /* DFSR */
3864 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
3865 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
3866 /* ADFSR */
3867 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
3868 /* AIFSR */
3869 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
3870 /* DFAR */
3871 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
3872 /* IFAR */
3873 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
3874
3875 /*
3876 * DC{C,I,CI}SW operations:
3877 */
3878 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
3879 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
3880 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
3881
3882 /* PMU */
3883 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
3884 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
3885 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
3886 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
3887 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
3888 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
3889 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
3890 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
3891 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
3892 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
3893 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
3894 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
3895 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
3896 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
3897 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
3898 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
3899 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
3900 /* PMMIR */
3901 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
3902
3903 /* PRRR/MAIR0 */
3904 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
3905 /* NMRR/MAIR1 */
3906 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
3907 /* AMAIR0 */
3908 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
3909 /* AMAIR1 */
3910 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
3911
3912 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
3913 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
3914 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
3915 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
3916 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
3917 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
3918 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
3919 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
3920 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
3921 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3922 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3923 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
3924 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
3925 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3926 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
3927 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
3928 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
3929 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
3930 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
3931 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
3932 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
3933 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
3934
3935 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
3936
3937 /* Arch Tmers */
3938 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
3939 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
3940
3941 /* PMEVCNTRn */
3942 PMU_PMEVCNTR(0),
3943 PMU_PMEVCNTR(1),
3944 PMU_PMEVCNTR(2),
3945 PMU_PMEVCNTR(3),
3946 PMU_PMEVCNTR(4),
3947 PMU_PMEVCNTR(5),
3948 PMU_PMEVCNTR(6),
3949 PMU_PMEVCNTR(7),
3950 PMU_PMEVCNTR(8),
3951 PMU_PMEVCNTR(9),
3952 PMU_PMEVCNTR(10),
3953 PMU_PMEVCNTR(11),
3954 PMU_PMEVCNTR(12),
3955 PMU_PMEVCNTR(13),
3956 PMU_PMEVCNTR(14),
3957 PMU_PMEVCNTR(15),
3958 PMU_PMEVCNTR(16),
3959 PMU_PMEVCNTR(17),
3960 PMU_PMEVCNTR(18),
3961 PMU_PMEVCNTR(19),
3962 PMU_PMEVCNTR(20),
3963 PMU_PMEVCNTR(21),
3964 PMU_PMEVCNTR(22),
3965 PMU_PMEVCNTR(23),
3966 PMU_PMEVCNTR(24),
3967 PMU_PMEVCNTR(25),
3968 PMU_PMEVCNTR(26),
3969 PMU_PMEVCNTR(27),
3970 PMU_PMEVCNTR(28),
3971 PMU_PMEVCNTR(29),
3972 PMU_PMEVCNTR(30),
3973 /* PMEVTYPERn */
3974 PMU_PMEVTYPER(0),
3975 PMU_PMEVTYPER(1),
3976 PMU_PMEVTYPER(2),
3977 PMU_PMEVTYPER(3),
3978 PMU_PMEVTYPER(4),
3979 PMU_PMEVTYPER(5),
3980 PMU_PMEVTYPER(6),
3981 PMU_PMEVTYPER(7),
3982 PMU_PMEVTYPER(8),
3983 PMU_PMEVTYPER(9),
3984 PMU_PMEVTYPER(10),
3985 PMU_PMEVTYPER(11),
3986 PMU_PMEVTYPER(12),
3987 PMU_PMEVTYPER(13),
3988 PMU_PMEVTYPER(14),
3989 PMU_PMEVTYPER(15),
3990 PMU_PMEVTYPER(16),
3991 PMU_PMEVTYPER(17),
3992 PMU_PMEVTYPER(18),
3993 PMU_PMEVTYPER(19),
3994 PMU_PMEVTYPER(20),
3995 PMU_PMEVTYPER(21),
3996 PMU_PMEVTYPER(22),
3997 PMU_PMEVTYPER(23),
3998 PMU_PMEVTYPER(24),
3999 PMU_PMEVTYPER(25),
4000 PMU_PMEVTYPER(26),
4001 PMU_PMEVTYPER(27),
4002 PMU_PMEVTYPER(28),
4003 PMU_PMEVTYPER(29),
4004 PMU_PMEVTYPER(30),
4005 /* PMCCFILTR */
4006 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
4007
4008 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
4009 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
4010
4011 /* CCSIDR2 */
4012 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
4013
4014 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
4015 };
4016
4017 static const struct sys_reg_desc cp15_64_regs[] = {
4018 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
4019 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
4020 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
4021 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
4022 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
4023 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
4024 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer },
4025 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
4026 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
4027 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
4028 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer },
4029 };
4030
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)4031 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
4032 bool is_32)
4033 {
4034 unsigned int i;
4035
4036 for (i = 0; i < n; i++) {
4037 if (!is_32 && table[i].reg && !table[i].reset) {
4038 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n",
4039 &table[i], i, table[i].name);
4040 return false;
4041 }
4042
4043 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
4044 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n",
4045 &table[i], i, table[i - 1].name, table[i].name);
4046 return false;
4047 }
4048 }
4049
4050 return true;
4051 }
4052
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)4053 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
4054 {
4055 kvm_inject_undefined(vcpu);
4056 return 1;
4057 }
4058
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)4059 static void perform_access(struct kvm_vcpu *vcpu,
4060 struct sys_reg_params *params,
4061 const struct sys_reg_desc *r)
4062 {
4063 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
4064
4065 /* Check for regs disabled by runtime config */
4066 if (sysreg_hidden(vcpu, r)) {
4067 kvm_inject_undefined(vcpu);
4068 return;
4069 }
4070
4071 /*
4072 * Not having an accessor means that we have configured a trap
4073 * that we don't know how to handle. This certainly qualifies
4074 * as a gross bug that should be fixed right away.
4075 */
4076 BUG_ON(!r->access);
4077
4078 /* Skip instruction if instructed so */
4079 if (likely(r->access(vcpu, params, r)))
4080 kvm_incr_pc(vcpu);
4081 }
4082
4083 /*
4084 * emulate_cp -- tries to match a sys_reg access in a handling table, and
4085 * call the corresponding trap handler.
4086 *
4087 * @params: pointer to the descriptor of the access
4088 * @table: array of trap descriptors
4089 * @num: size of the trap descriptor array
4090 *
4091 * Return true if the access has been handled, false if not.
4092 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)4093 static bool emulate_cp(struct kvm_vcpu *vcpu,
4094 struct sys_reg_params *params,
4095 const struct sys_reg_desc *table,
4096 size_t num)
4097 {
4098 const struct sys_reg_desc *r;
4099
4100 if (!table)
4101 return false; /* Not handled */
4102
4103 r = find_reg(params, table, num);
4104
4105 if (r) {
4106 perform_access(vcpu, params, r);
4107 return true;
4108 }
4109
4110 /* Not handled */
4111 return false;
4112 }
4113
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)4114 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
4115 struct sys_reg_params *params)
4116 {
4117 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
4118 int cp = -1;
4119
4120 switch (esr_ec) {
4121 case ESR_ELx_EC_CP15_32:
4122 case ESR_ELx_EC_CP15_64:
4123 cp = 15;
4124 break;
4125 case ESR_ELx_EC_CP14_MR:
4126 case ESR_ELx_EC_CP14_64:
4127 cp = 14;
4128 break;
4129 default:
4130 WARN_ON(1);
4131 }
4132
4133 print_sys_reg_msg(params,
4134 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
4135 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
4136 kvm_inject_undefined(vcpu);
4137 }
4138
4139 /**
4140 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
4141 * @vcpu: The VCPU pointer
4142 * @global: &struct sys_reg_desc
4143 * @nr_global: size of the @global array
4144 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)4145 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
4146 const struct sys_reg_desc *global,
4147 size_t nr_global)
4148 {
4149 struct sys_reg_params params;
4150 u64 esr = kvm_vcpu_get_esr(vcpu);
4151 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4152 int Rt2 = (esr >> 10) & 0x1f;
4153
4154 params.CRm = (esr >> 1) & 0xf;
4155 params.is_write = ((esr & 1) == 0);
4156
4157 params.Op0 = 0;
4158 params.Op1 = (esr >> 16) & 0xf;
4159 params.Op2 = 0;
4160 params.CRn = 0;
4161
4162 /*
4163 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
4164 * backends between AArch32 and AArch64, we get away with it.
4165 */
4166 if (params.is_write) {
4167 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
4168 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
4169 }
4170
4171 /*
4172 * If the table contains a handler, handle the
4173 * potential register operation in the case of a read and return
4174 * with success.
4175 */
4176 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
4177 /* Split up the value between registers for the read side */
4178 if (!params.is_write) {
4179 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
4180 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
4181 }
4182
4183 return 1;
4184 }
4185
4186 unhandled_cp_access(vcpu, ¶ms);
4187 return 1;
4188 }
4189
4190 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
4191
4192 /*
4193 * The CP10 ID registers are architecturally mapped to AArch64 feature
4194 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
4195 * from AArch32.
4196 */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)4197 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
4198 {
4199 u8 reg_id = (esr >> 10) & 0xf;
4200 bool valid;
4201
4202 params->is_write = ((esr & 1) == 0);
4203 params->Op0 = 3;
4204 params->Op1 = 0;
4205 params->CRn = 0;
4206 params->CRm = 3;
4207
4208 /* CP10 ID registers are read-only */
4209 valid = !params->is_write;
4210
4211 switch (reg_id) {
4212 /* MVFR0 */
4213 case 0b0111:
4214 params->Op2 = 0;
4215 break;
4216 /* MVFR1 */
4217 case 0b0110:
4218 params->Op2 = 1;
4219 break;
4220 /* MVFR2 */
4221 case 0b0101:
4222 params->Op2 = 2;
4223 break;
4224 default:
4225 valid = false;
4226 }
4227
4228 if (valid)
4229 return true;
4230
4231 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
4232 params->is_write ? "write" : "read", reg_id);
4233 return false;
4234 }
4235
4236 /**
4237 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
4238 * VFP Register' from AArch32.
4239 * @vcpu: The vCPU pointer
4240 *
4241 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
4242 * Work out the correct AArch64 system register encoding and reroute to the
4243 * AArch64 system register emulation.
4244 */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)4245 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
4246 {
4247 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4248 u64 esr = kvm_vcpu_get_esr(vcpu);
4249 struct sys_reg_params params;
4250
4251 /* UNDEF on any unhandled register access */
4252 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
4253 kvm_inject_undefined(vcpu);
4254 return 1;
4255 }
4256
4257 if (emulate_sys_reg(vcpu, ¶ms))
4258 vcpu_set_reg(vcpu, Rt, params.regval);
4259
4260 return 1;
4261 }
4262
4263 /**
4264 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
4265 * CRn=0, which corresponds to the AArch32 feature
4266 * registers.
4267 * @vcpu: the vCPU pointer
4268 * @params: the system register access parameters.
4269 *
4270 * Our cp15 system register tables do not enumerate the AArch32 feature
4271 * registers. Conveniently, our AArch64 table does, and the AArch32 system
4272 * register encoding can be trivially remapped into the AArch64 for the feature
4273 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
4274 *
4275 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
4276 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
4277 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
4278 * treat undefined registers in this range as RAZ.
4279 */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)4280 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
4281 struct sys_reg_params *params)
4282 {
4283 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4284
4285 /* Treat impossible writes to RO registers as UNDEFINED */
4286 if (params->is_write) {
4287 unhandled_cp_access(vcpu, params);
4288 return 1;
4289 }
4290
4291 params->Op0 = 3;
4292
4293 /*
4294 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
4295 * Avoid conflicting with future expansion of AArch64 feature registers
4296 * and simply treat them as RAZ here.
4297 */
4298 if (params->CRm > 3)
4299 params->regval = 0;
4300 else if (!emulate_sys_reg(vcpu, params))
4301 return 1;
4302
4303 vcpu_set_reg(vcpu, Rt, params->regval);
4304 return 1;
4305 }
4306
4307 /**
4308 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
4309 * @vcpu: The VCPU pointer
4310 * @params: &struct sys_reg_params
4311 * @global: &struct sys_reg_desc
4312 * @nr_global: size of the @global array
4313 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)4314 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
4315 struct sys_reg_params *params,
4316 const struct sys_reg_desc *global,
4317 size_t nr_global)
4318 {
4319 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4320
4321 params->regval = vcpu_get_reg(vcpu, Rt);
4322
4323 if (emulate_cp(vcpu, params, global, nr_global)) {
4324 if (!params->is_write)
4325 vcpu_set_reg(vcpu, Rt, params->regval);
4326 return 1;
4327 }
4328
4329 unhandled_cp_access(vcpu, params);
4330 return 1;
4331 }
4332
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)4333 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
4334 {
4335 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
4336 }
4337
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)4338 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
4339 {
4340 struct sys_reg_params params;
4341
4342 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
4343
4344 /*
4345 * Certain AArch32 ID registers are handled by rerouting to the AArch64
4346 * system register table. Registers in the ID range where CRm=0 are
4347 * excluded from this scheme as they do not trivially map into AArch64
4348 * system register encodings, except for AIDR/REVIDR.
4349 */
4350 if (params.Op1 == 0 && params.CRn == 0 &&
4351 (params.CRm || params.Op2 == 6 /* REVIDR */))
4352 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
4353 if (params.Op1 == 1 && params.CRn == 0 &&
4354 params.CRm == 0 && params.Op2 == 7 /* AIDR */)
4355 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
4356
4357 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
4358 }
4359
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)4360 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
4361 {
4362 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
4363 }
4364
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)4365 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
4366 {
4367 struct sys_reg_params params;
4368
4369 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
4370
4371 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
4372 }
4373
4374 /**
4375 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
4376 * @vcpu: The VCPU pointer
4377 * @params: Decoded system register parameters
4378 *
4379 * Return: true if the system register access was successful, false otherwise.
4380 */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)4381 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
4382 struct sys_reg_params *params)
4383 {
4384 const struct sys_reg_desc *r;
4385
4386 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4387 if (likely(r)) {
4388 perform_access(vcpu, params, r);
4389 return true;
4390 }
4391
4392 print_sys_reg_msg(params,
4393 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
4394 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
4395 kvm_inject_undefined(vcpu);
4396
4397 return false;
4398 }
4399
idregs_debug_find(struct kvm * kvm,u8 pos)4400 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos)
4401 {
4402 unsigned long i, idreg_idx = 0;
4403
4404 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4405 const struct sys_reg_desc *r = &sys_reg_descs[i];
4406
4407 if (!is_vm_ftr_id_reg(reg_to_encoding(r)))
4408 continue;
4409
4410 if (idreg_idx == pos)
4411 return r;
4412
4413 idreg_idx++;
4414 }
4415
4416 return NULL;
4417 }
4418
idregs_debug_start(struct seq_file * s,loff_t * pos)4419 static void *idregs_debug_start(struct seq_file *s, loff_t *pos)
4420 {
4421 struct kvm *kvm = s->private;
4422 u8 *iter;
4423
4424 mutex_lock(&kvm->arch.config_lock);
4425
4426 iter = &kvm->arch.idreg_debugfs_iter;
4427 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) &&
4428 *iter == (u8)~0) {
4429 *iter = *pos;
4430 if (!idregs_debug_find(kvm, *iter))
4431 iter = NULL;
4432 } else {
4433 iter = ERR_PTR(-EBUSY);
4434 }
4435
4436 mutex_unlock(&kvm->arch.config_lock);
4437
4438 return iter;
4439 }
4440
idregs_debug_next(struct seq_file * s,void * v,loff_t * pos)4441 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos)
4442 {
4443 struct kvm *kvm = s->private;
4444
4445 (*pos)++;
4446
4447 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) {
4448 kvm->arch.idreg_debugfs_iter++;
4449
4450 return &kvm->arch.idreg_debugfs_iter;
4451 }
4452
4453 return NULL;
4454 }
4455
idregs_debug_stop(struct seq_file * s,void * v)4456 static void idregs_debug_stop(struct seq_file *s, void *v)
4457 {
4458 struct kvm *kvm = s->private;
4459
4460 if (IS_ERR(v))
4461 return;
4462
4463 mutex_lock(&kvm->arch.config_lock);
4464
4465 kvm->arch.idreg_debugfs_iter = ~0;
4466
4467 mutex_unlock(&kvm->arch.config_lock);
4468 }
4469
idregs_debug_show(struct seq_file * s,void * v)4470 static int idregs_debug_show(struct seq_file *s, void *v)
4471 {
4472 const struct sys_reg_desc *desc;
4473 struct kvm *kvm = s->private;
4474
4475 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter);
4476
4477 if (!desc->name)
4478 return 0;
4479
4480 seq_printf(s, "%20s:\t%016llx\n",
4481 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc)));
4482
4483 return 0;
4484 }
4485
4486 static const struct seq_operations idregs_debug_sops = {
4487 .start = idregs_debug_start,
4488 .next = idregs_debug_next,
4489 .stop = idregs_debug_stop,
4490 .show = idregs_debug_show,
4491 };
4492
4493 DEFINE_SEQ_ATTRIBUTE(idregs_debug);
4494
kvm_sys_regs_create_debugfs(struct kvm * kvm)4495 void kvm_sys_regs_create_debugfs(struct kvm *kvm)
4496 {
4497 kvm->arch.idreg_debugfs_iter = ~0;
4498
4499 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm,
4500 &idregs_debug_fops);
4501 }
4502
reset_vm_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4503 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg)
4504 {
4505 u32 id = reg_to_encoding(reg);
4506 struct kvm *kvm = vcpu->kvm;
4507
4508 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
4509 return;
4510
4511 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg));
4512 }
4513
reset_vcpu_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4514 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu,
4515 const struct sys_reg_desc *reg)
4516 {
4517 if (kvm_vcpu_initialized(vcpu))
4518 return;
4519
4520 reg->reset(vcpu, reg);
4521 }
4522
4523 /**
4524 * kvm_reset_sys_regs - sets system registers to reset value
4525 * @vcpu: The VCPU pointer
4526 *
4527 * This function finds the right table above and sets the registers on the
4528 * virtual CPU struct to their architecturally defined reset values.
4529 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)4530 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
4531 {
4532 struct kvm *kvm = vcpu->kvm;
4533 unsigned long i;
4534
4535 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4536 const struct sys_reg_desc *r = &sys_reg_descs[i];
4537
4538 if (!r->reset)
4539 continue;
4540
4541 if (is_vm_ftr_id_reg(reg_to_encoding(r)))
4542 reset_vm_ftr_id_reg(vcpu, r);
4543 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r)))
4544 reset_vcpu_ftr_id_reg(vcpu, r);
4545 else
4546 r->reset(vcpu, r);
4547
4548 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS)
4549 (void)__vcpu_sys_reg(vcpu, r->reg);
4550 }
4551
4552 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
4553 }
4554
4555 /**
4556 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction
4557 * trap on a guest execution
4558 * @vcpu: The VCPU pointer
4559 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)4560 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
4561 {
4562 const struct sys_reg_desc *desc = NULL;
4563 struct sys_reg_params params;
4564 unsigned long esr = kvm_vcpu_get_esr(vcpu);
4565 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4566 int sr_idx;
4567
4568 trace_kvm_handle_sys_reg(esr);
4569
4570 if (triage_sysreg_trap(vcpu, &sr_idx))
4571 return 1;
4572
4573 params = esr_sys64_to_params(esr);
4574 params.regval = vcpu_get_reg(vcpu, Rt);
4575
4576 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */
4577 if (params.Op0 == 2 || params.Op0 == 3)
4578 desc = &sys_reg_descs[sr_idx];
4579 else
4580 desc = &sys_insn_descs[sr_idx];
4581
4582 perform_access(vcpu, ¶ms, desc);
4583
4584 /* Read from system register? */
4585 if (!params.is_write &&
4586 (params.Op0 == 2 || params.Op0 == 3))
4587 vcpu_set_reg(vcpu, Rt, params.regval);
4588
4589 return 1;
4590 }
4591
4592 /******************************************************************************
4593 * Userspace API
4594 *****************************************************************************/
4595
index_to_params(u64 id,struct sys_reg_params * params)4596 static bool index_to_params(u64 id, struct sys_reg_params *params)
4597 {
4598 switch (id & KVM_REG_SIZE_MASK) {
4599 case KVM_REG_SIZE_U64:
4600 /* Any unused index bits means it's not valid. */
4601 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
4602 | KVM_REG_ARM_COPROC_MASK
4603 | KVM_REG_ARM64_SYSREG_OP0_MASK
4604 | KVM_REG_ARM64_SYSREG_OP1_MASK
4605 | KVM_REG_ARM64_SYSREG_CRN_MASK
4606 | KVM_REG_ARM64_SYSREG_CRM_MASK
4607 | KVM_REG_ARM64_SYSREG_OP2_MASK))
4608 return false;
4609 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
4610 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
4611 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
4612 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
4613 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
4614 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
4615 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
4616 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
4617 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
4618 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
4619 return true;
4620 default:
4621 return false;
4622 }
4623 }
4624
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)4625 const struct sys_reg_desc *get_reg_by_id(u64 id,
4626 const struct sys_reg_desc table[],
4627 unsigned int num)
4628 {
4629 struct sys_reg_params params;
4630
4631 if (!index_to_params(id, ¶ms))
4632 return NULL;
4633
4634 return find_reg(¶ms, table, num);
4635 }
4636
4637 /* Decode an index value, and find the sys_reg_desc entry. */
4638 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)4639 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
4640 const struct sys_reg_desc table[], unsigned int num)
4641
4642 {
4643 const struct sys_reg_desc *r;
4644
4645 /* We only do sys_reg for now. */
4646 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
4647 return NULL;
4648
4649 r = get_reg_by_id(id, table, num);
4650
4651 /* Not saved in the sys_reg array and not otherwise accessible? */
4652 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
4653 r = NULL;
4654
4655 return r;
4656 }
4657
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4658 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4659 {
4660 u32 val;
4661 u32 __user *uval = uaddr;
4662
4663 /* Fail if we have unknown bits set. */
4664 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4665 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4666 return -ENOENT;
4667
4668 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4669 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4670 if (KVM_REG_SIZE(id) != 4)
4671 return -ENOENT;
4672 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4673 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4674 if (val >= CSSELR_MAX)
4675 return -ENOENT;
4676
4677 return put_user(get_ccsidr(vcpu, val), uval);
4678 default:
4679 return -ENOENT;
4680 }
4681 }
4682
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4683 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4684 {
4685 u32 val, newval;
4686 u32 __user *uval = uaddr;
4687
4688 /* Fail if we have unknown bits set. */
4689 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4690 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4691 return -ENOENT;
4692
4693 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4694 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4695 if (KVM_REG_SIZE(id) != 4)
4696 return -ENOENT;
4697 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4698 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4699 if (val >= CSSELR_MAX)
4700 return -ENOENT;
4701
4702 if (get_user(newval, uval))
4703 return -EFAULT;
4704
4705 return set_ccsidr(vcpu, val, newval);
4706 default:
4707 return -ENOENT;
4708 }
4709 }
4710
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4711 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4712 const struct sys_reg_desc table[], unsigned int num)
4713 {
4714 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4715 const struct sys_reg_desc *r;
4716 u64 val;
4717 int ret;
4718
4719 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4720 if (!r || sysreg_hidden(vcpu, r))
4721 return -ENOENT;
4722
4723 if (r->get_user) {
4724 ret = (r->get_user)(vcpu, r, &val);
4725 } else {
4726 val = __vcpu_sys_reg(vcpu, r->reg);
4727 ret = 0;
4728 }
4729
4730 if (!ret)
4731 ret = put_user(val, uaddr);
4732
4733 return ret;
4734 }
4735
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4736 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4737 {
4738 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4739
4740 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4741 return demux_c15_get(vcpu, reg->id, uaddr);
4742
4743 return kvm_sys_reg_get_user(vcpu, reg,
4744 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4745 }
4746
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4747 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4748 const struct sys_reg_desc table[], unsigned int num)
4749 {
4750 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4751 const struct sys_reg_desc *r;
4752 u64 val;
4753 int ret;
4754
4755 if (get_user(val, uaddr))
4756 return -EFAULT;
4757
4758 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4759 if (!r || sysreg_hidden(vcpu, r))
4760 return -ENOENT;
4761
4762 if (sysreg_user_write_ignore(vcpu, r))
4763 return 0;
4764
4765 if (r->set_user) {
4766 ret = (r->set_user)(vcpu, r, val);
4767 } else {
4768 __vcpu_sys_reg(vcpu, r->reg) = val;
4769 ret = 0;
4770 }
4771
4772 return ret;
4773 }
4774
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4775 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4776 {
4777 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4778
4779 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4780 return demux_c15_set(vcpu, reg->id, uaddr);
4781
4782 return kvm_sys_reg_set_user(vcpu, reg,
4783 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4784 }
4785
num_demux_regs(void)4786 static unsigned int num_demux_regs(void)
4787 {
4788 return CSSELR_MAX;
4789 }
4790
write_demux_regids(u64 __user * uindices)4791 static int write_demux_regids(u64 __user *uindices)
4792 {
4793 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
4794 unsigned int i;
4795
4796 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
4797 for (i = 0; i < CSSELR_MAX; i++) {
4798 if (put_user(val | i, uindices))
4799 return -EFAULT;
4800 uindices++;
4801 }
4802 return 0;
4803 }
4804
sys_reg_to_index(const struct sys_reg_desc * reg)4805 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
4806 {
4807 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
4808 KVM_REG_ARM64_SYSREG |
4809 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
4810 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
4811 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
4812 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
4813 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
4814 }
4815
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)4816 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
4817 {
4818 if (!*uind)
4819 return true;
4820
4821 if (put_user(sys_reg_to_index(reg), *uind))
4822 return false;
4823
4824 (*uind)++;
4825 return true;
4826 }
4827
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)4828 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
4829 const struct sys_reg_desc *rd,
4830 u64 __user **uind,
4831 unsigned int *total)
4832 {
4833 /*
4834 * Ignore registers we trap but don't save,
4835 * and for which no custom user accessor is provided.
4836 */
4837 if (!(rd->reg || rd->get_user))
4838 return 0;
4839
4840 if (sysreg_hidden(vcpu, rd))
4841 return 0;
4842
4843 if (!copy_reg_to_user(rd, uind))
4844 return -EFAULT;
4845
4846 (*total)++;
4847 return 0;
4848 }
4849
4850 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)4851 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
4852 {
4853 const struct sys_reg_desc *i2, *end2;
4854 unsigned int total = 0;
4855 int err;
4856
4857 i2 = sys_reg_descs;
4858 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
4859
4860 while (i2 != end2) {
4861 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
4862 if (err)
4863 return err;
4864 }
4865 return total;
4866 }
4867
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)4868 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
4869 {
4870 return num_demux_regs()
4871 + walk_sys_regs(vcpu, (u64 __user *)NULL);
4872 }
4873
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)4874 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
4875 {
4876 int err;
4877
4878 err = walk_sys_regs(vcpu, uindices);
4879 if (err < 0)
4880 return err;
4881 uindices += err;
4882
4883 return write_demux_regids(uindices);
4884 }
4885
4886 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \
4887 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \
4888 sys_reg_Op1(r), \
4889 sys_reg_CRn(r), \
4890 sys_reg_CRm(r), \
4891 sys_reg_Op2(r))
4892
kvm_vm_ioctl_get_reg_writable_masks(struct kvm * kvm,struct reg_mask_range * range)4893 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range)
4894 {
4895 const void *zero_page = page_to_virt(ZERO_PAGE(0));
4896 u64 __user *masks = (u64 __user *)range->addr;
4897
4898 /* Only feature id range is supported, reserved[13] must be zero. */
4899 if (range->range ||
4900 memcmp(range->reserved, zero_page, sizeof(range->reserved)))
4901 return -EINVAL;
4902
4903 /* Wipe the whole thing first */
4904 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64)))
4905 return -EFAULT;
4906
4907 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4908 const struct sys_reg_desc *reg = &sys_reg_descs[i];
4909 u32 encoding = reg_to_encoding(reg);
4910 u64 val;
4911
4912 if (!is_feature_id_reg(encoding) || !reg->set_user)
4913 continue;
4914
4915 if (!reg->val ||
4916 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) {
4917 continue;
4918 }
4919 val = reg->val;
4920
4921 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding))))
4922 return -EFAULT;
4923 }
4924
4925 return 0;
4926 }
4927
vcpu_set_hcr(struct kvm_vcpu * vcpu)4928 static void vcpu_set_hcr(struct kvm_vcpu *vcpu)
4929 {
4930 struct kvm *kvm = vcpu->kvm;
4931
4932 if (has_vhe() || has_hvhe())
4933 vcpu->arch.hcr_el2 |= HCR_E2H;
4934 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
4935 /* route synchronous external abort exceptions to EL2 */
4936 vcpu->arch.hcr_el2 |= HCR_TEA;
4937 /* trap error record accesses */
4938 vcpu->arch.hcr_el2 |= HCR_TERR;
4939 }
4940
4941 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
4942 vcpu->arch.hcr_el2 |= HCR_FWB;
4943
4944 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
4945 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) &&
4946 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0))
4947 vcpu->arch.hcr_el2 |= HCR_TID4;
4948 else
4949 vcpu->arch.hcr_el2 |= HCR_TID2;
4950
4951 if (vcpu_el1_is_32bit(vcpu))
4952 vcpu->arch.hcr_el2 &= ~HCR_RW;
4953
4954 if (kvm_has_mte(vcpu->kvm))
4955 vcpu->arch.hcr_el2 |= HCR_ATA;
4956
4957 /*
4958 * In the absence of FGT, we cannot independently trap TLBI
4959 * Range instructions. This isn't great, but trapping all
4960 * TLBIs would be far worse. Live with it...
4961 */
4962 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4963 vcpu->arch.hcr_el2 |= HCR_TTLBOS;
4964 }
4965
kvm_calculate_traps(struct kvm_vcpu * vcpu)4966 void kvm_calculate_traps(struct kvm_vcpu *vcpu)
4967 {
4968 struct kvm *kvm = vcpu->kvm;
4969
4970 mutex_lock(&kvm->arch.config_lock);
4971 vcpu_set_hcr(vcpu);
4972 vcpu_set_ich_hcr(vcpu);
4973
4974 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
4975 /*
4976 * In general, all HCRX_EL2 bits are gated by a feature.
4977 * The only reason we can set SMPME without checking any
4978 * feature is that its effects are not directly observable
4979 * from the guest.
4980 */
4981 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME;
4982
4983 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP))
4984 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);
4985
4986 if (kvm_has_tcr2(kvm))
4987 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En;
4988
4989 if (kvm_has_fpmr(kvm))
4990 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM;
4991 }
4992
4993 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
4994 goto out;
4995
4996 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 |
4997 HFGxTR_EL2_nMAIR2_EL1 |
4998 HFGxTR_EL2_nS2POR_EL1 |
4999 HFGxTR_EL2_nACCDATA_EL1 |
5000 HFGxTR_EL2_nSMPRI_EL1_MASK |
5001 HFGxTR_EL2_nTPIDR2_EL0_MASK);
5002
5003 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
5004 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS|
5005 HFGITR_EL2_TLBIRVALE1OS |
5006 HFGITR_EL2_TLBIRVAAE1OS |
5007 HFGITR_EL2_TLBIRVAE1OS |
5008 HFGITR_EL2_TLBIVAALE1OS |
5009 HFGITR_EL2_TLBIVALE1OS |
5010 HFGITR_EL2_TLBIVAAE1OS |
5011 HFGITR_EL2_TLBIASIDE1OS |
5012 HFGITR_EL2_TLBIVAE1OS |
5013 HFGITR_EL2_TLBIVMALLE1OS);
5014
5015 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
5016 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 |
5017 HFGITR_EL2_TLBIRVALE1 |
5018 HFGITR_EL2_TLBIRVAAE1 |
5019 HFGITR_EL2_TLBIRVAE1 |
5020 HFGITR_EL2_TLBIRVAALE1IS|
5021 HFGITR_EL2_TLBIRVALE1IS |
5022 HFGITR_EL2_TLBIRVAAE1IS |
5023 HFGITR_EL2_TLBIRVAE1IS |
5024 HFGITR_EL2_TLBIRVAALE1OS|
5025 HFGITR_EL2_TLBIRVALE1OS |
5026 HFGITR_EL2_TLBIRVAAE1OS |
5027 HFGITR_EL2_TLBIRVAE1OS);
5028
5029 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP))
5030 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A;
5031
5032 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2))
5033 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP |
5034 HFGITR_EL2_ATS1E1WP);
5035
5036 if (!kvm_has_s1pie(kvm))
5037 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 |
5038 HFGxTR_EL2_nPIR_EL1);
5039
5040 if (!kvm_has_s1poe(kvm))
5041 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
5042 HFGxTR_EL2_nPOR_EL0);
5043
5044 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP))
5045 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 |
5046 HAFGRTR_EL2_RES1);
5047
5048 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) {
5049 kvm->arch.fgu[HDFGRTR_GROUP] |= (HDFGRTR_EL2_nBRBDATA |
5050 HDFGRTR_EL2_nBRBCTL |
5051 HDFGRTR_EL2_nBRBIDR);
5052 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nBRBINJ |
5053 HFGITR_EL2_nBRBIALL);
5054 }
5055
5056 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
5057 out:
5058 mutex_unlock(&kvm->arch.config_lock);
5059 }
5060
5061 /*
5062 * Perform last adjustments to the ID registers that are implied by the
5063 * configuration outside of the ID regs themselves, as well as any
5064 * initialisation that directly depend on these ID registers (such as
5065 * RES0/RES1 behaviours). This is not the place to configure traps though.
5066 *
5067 * Because this can be called once per CPU, changes must be idempotent.
5068 */
kvm_finalize_sys_regs(struct kvm_vcpu * vcpu)5069 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu)
5070 {
5071 struct kvm *kvm = vcpu->kvm;
5072
5073 guard(mutex)(&kvm->arch.config_lock);
5074
5075 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) &&
5076 irqchip_in_kernel(kvm) &&
5077 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) {
5078 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK;
5079 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK;
5080 }
5081
5082 if (vcpu_has_nv(vcpu)) {
5083 int ret = kvm_init_nv_sysregs(vcpu);
5084 if (ret)
5085 return ret;
5086 }
5087
5088 return 0;
5089 }
5090
kvm_sys_reg_table_init(void)5091 int __init kvm_sys_reg_table_init(void)
5092 {
5093 bool valid = true;
5094 unsigned int i;
5095 int ret = 0;
5096
5097 /* Make sure tables are unique and in order. */
5098 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
5099 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
5100 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
5101 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
5102 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
5103 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false);
5104
5105 if (!valid)
5106 return -EINVAL;
5107
5108 init_imp_id_regs();
5109
5110 ret = populate_nv_trap_config();
5111
5112 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++)
5113 ret = populate_sysreg_config(sys_reg_descs + i, i);
5114
5115 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++)
5116 ret = populate_sysreg_config(sys_insn_descs + i, i);
5117
5118 return ret;
5119 }
5120