1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27
28 /*
29 * In case the boot CPU is hotpluggable, we record its initial state and
30 * current state separately. Certain system registers may contain different
31 * values depending on configuration at or after reset.
32 */
33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
34 static struct cpuinfo_arm64 boot_cpu_data;
35
icache_policy_str(int l1ip)36 static inline const char *icache_policy_str(int l1ip)
37 {
38 switch (l1ip) {
39 case CTR_EL0_L1Ip_VIPT:
40 return "VIPT";
41 case CTR_EL0_L1Ip_PIPT:
42 return "PIPT";
43 default:
44 return "RESERVED/UNKNOWN";
45 }
46 }
47
48 unsigned long __icache_flags;
49
50 static const char *const hwcap_str[] = {
51 [KERNEL_HWCAP_FP] = "fp",
52 [KERNEL_HWCAP_ASIMD] = "asimd",
53 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
54 [KERNEL_HWCAP_AES] = "aes",
55 [KERNEL_HWCAP_PMULL] = "pmull",
56 [KERNEL_HWCAP_SHA1] = "sha1",
57 [KERNEL_HWCAP_SHA2] = "sha2",
58 [KERNEL_HWCAP_CRC32] = "crc32",
59 [KERNEL_HWCAP_ATOMICS] = "atomics",
60 [KERNEL_HWCAP_FPHP] = "fphp",
61 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
62 [KERNEL_HWCAP_CPUID] = "cpuid",
63 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
64 [KERNEL_HWCAP_JSCVT] = "jscvt",
65 [KERNEL_HWCAP_FCMA] = "fcma",
66 [KERNEL_HWCAP_LRCPC] = "lrcpc",
67 [KERNEL_HWCAP_DCPOP] = "dcpop",
68 [KERNEL_HWCAP_SHA3] = "sha3",
69 [KERNEL_HWCAP_SM3] = "sm3",
70 [KERNEL_HWCAP_SM4] = "sm4",
71 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
72 [KERNEL_HWCAP_SHA512] = "sha512",
73 [KERNEL_HWCAP_SVE] = "sve",
74 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
75 [KERNEL_HWCAP_DIT] = "dit",
76 [KERNEL_HWCAP_USCAT] = "uscat",
77 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
78 [KERNEL_HWCAP_FLAGM] = "flagm",
79 [KERNEL_HWCAP_SSBS] = "ssbs",
80 [KERNEL_HWCAP_SB] = "sb",
81 [KERNEL_HWCAP_PACA] = "paca",
82 [KERNEL_HWCAP_PACG] = "pacg",
83 [KERNEL_HWCAP_GCS] = "gcs",
84 [KERNEL_HWCAP_DCPODP] = "dcpodp",
85 [KERNEL_HWCAP_SVE2] = "sve2",
86 [KERNEL_HWCAP_SVEAES] = "sveaes",
87 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
88 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
89 [KERNEL_HWCAP_SVESHA3] = "svesha3",
90 [KERNEL_HWCAP_SVESM4] = "svesm4",
91 [KERNEL_HWCAP_FLAGM2] = "flagm2",
92 [KERNEL_HWCAP_FRINT] = "frint",
93 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
94 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
95 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
96 [KERNEL_HWCAP_SVEBF16] = "svebf16",
97 [KERNEL_HWCAP_I8MM] = "i8mm",
98 [KERNEL_HWCAP_BF16] = "bf16",
99 [KERNEL_HWCAP_DGH] = "dgh",
100 [KERNEL_HWCAP_RNG] = "rng",
101 [KERNEL_HWCAP_BTI] = "bti",
102 [KERNEL_HWCAP_MTE] = "mte",
103 [KERNEL_HWCAP_ECV] = "ecv",
104 [KERNEL_HWCAP_AFP] = "afp",
105 [KERNEL_HWCAP_RPRES] = "rpres",
106 [KERNEL_HWCAP_MTE3] = "mte3",
107 [KERNEL_HWCAP_SME] = "sme",
108 [KERNEL_HWCAP_SME_I16I64] = "smei16i64",
109 [KERNEL_HWCAP_SME_F64F64] = "smef64f64",
110 [KERNEL_HWCAP_SME_I8I32] = "smei8i32",
111 [KERNEL_HWCAP_SME_F16F32] = "smef16f32",
112 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
113 [KERNEL_HWCAP_SME_F32F32] = "smef32f32",
114 [KERNEL_HWCAP_SME_FA64] = "smefa64",
115 [KERNEL_HWCAP_WFXT] = "wfxt",
116 [KERNEL_HWCAP_EBF16] = "ebf16",
117 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
118 [KERNEL_HWCAP_CSSC] = "cssc",
119 [KERNEL_HWCAP_RPRFM] = "rprfm",
120 [KERNEL_HWCAP_SVE2P1] = "sve2p1",
121 [KERNEL_HWCAP_SME2] = "sme2",
122 [KERNEL_HWCAP_SME2P1] = "sme2p1",
123 [KERNEL_HWCAP_SME_I16I32] = "smei16i32",
124 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
125 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
126 [KERNEL_HWCAP_SME_F16F16] = "smef16f16",
127 [KERNEL_HWCAP_MOPS] = "mops",
128 [KERNEL_HWCAP_HBC] = "hbc",
129 [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
130 [KERNEL_HWCAP_LRCPC3] = "lrcpc3",
131 [KERNEL_HWCAP_LSE128] = "lse128",
132 [KERNEL_HWCAP_FPMR] = "fpmr",
133 [KERNEL_HWCAP_LUT] = "lut",
134 [KERNEL_HWCAP_FAMINMAX] = "faminmax",
135 [KERNEL_HWCAP_F8CVT] = "f8cvt",
136 [KERNEL_HWCAP_F8FMA] = "f8fma",
137 [KERNEL_HWCAP_F8DP4] = "f8dp4",
138 [KERNEL_HWCAP_F8DP2] = "f8dp2",
139 [KERNEL_HWCAP_F8E4M3] = "f8e4m3",
140 [KERNEL_HWCAP_F8E5M2] = "f8e5m2",
141 [KERNEL_HWCAP_SME_LUTV2] = "smelutv2",
142 [KERNEL_HWCAP_SME_F8F16] = "smef8f16",
143 [KERNEL_HWCAP_SME_F8F32] = "smef8f32",
144 [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma",
145 [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4",
146 [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2",
147 [KERNEL_HWCAP_POE] = "poe",
148 [KERNEL_HWCAP_CMPBR] = "cmpbr",
149 [KERNEL_HWCAP_FPRCVT] = "fprcvt",
150 [KERNEL_HWCAP_F8MM8] = "f8mm8",
151 [KERNEL_HWCAP_F8MM4] = "f8mm4",
152 [KERNEL_HWCAP_SVE_F16MM] = "svef16mm",
153 [KERNEL_HWCAP_SVE_ELTPERM] = "sveeltperm",
154 [KERNEL_HWCAP_SVE_AES2] = "sveaes2",
155 [KERNEL_HWCAP_SVE_BFSCALE] = "svebfscale",
156 [KERNEL_HWCAP_SVE2P2] = "sve2p2",
157 [KERNEL_HWCAP_SME2P2] = "sme2p2",
158 [KERNEL_HWCAP_SME_SBITPERM] = "smesbitperm",
159 [KERNEL_HWCAP_SME_AES] = "smeaes",
160 [KERNEL_HWCAP_SME_SFEXPA] = "smesfexpa",
161 [KERNEL_HWCAP_SME_STMOP] = "smestmop",
162 [KERNEL_HWCAP_SME_SMOP4] = "smesmop4",
163 };
164
165 #ifdef CONFIG_COMPAT
166 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
167 static const char *const compat_hwcap_str[] = {
168 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
169 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
170 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
171 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
172 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
173 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
174 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
175 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
176 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
177 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
178 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
179 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
180 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
181 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
182 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
183 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
184 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
185 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
186 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
187 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
188 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
189 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
190 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
191 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
192 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
193 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
194 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
195 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
196 };
197
198 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
199 static const char *const compat_hwcap2_str[] = {
200 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
201 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
202 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
203 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
204 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
205 [COMPAT_KERNEL_HWCAP2(SB)] = "sb",
206 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
207 };
208 #endif /* CONFIG_COMPAT */
209
c_show(struct seq_file * m,void * v)210 static int c_show(struct seq_file *m, void *v)
211 {
212 int i, j;
213 bool compat = personality(current->personality) == PER_LINUX32;
214
215 for_each_online_cpu(i) {
216 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
217 u32 midr = cpuinfo->reg_midr;
218
219 /*
220 * glibc reads /proc/cpuinfo to determine the number of
221 * online processors, looking for lines beginning with
222 * "processor". Give glibc what it expects.
223 */
224 seq_printf(m, "processor\t: %d\n", i);
225 if (compat)
226 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
227 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
228
229 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
230 loops_per_jiffy / (500000UL/HZ),
231 loops_per_jiffy / (5000UL/HZ) % 100);
232
233 /*
234 * Dump out the common processor features in a single line.
235 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
236 * rather than attempting to parse this, but there's a body of
237 * software which does already (at least for 32-bit).
238 */
239 seq_puts(m, "Features\t:");
240 if (compat) {
241 #ifdef CONFIG_COMPAT
242 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
243 if (compat_elf_hwcap & (1 << j)) {
244 /*
245 * Warn once if any feature should not
246 * have been present on arm64 platform.
247 */
248 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
249 continue;
250
251 seq_printf(m, " %s", compat_hwcap_str[j]);
252 }
253 }
254
255 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
256 if (compat_elf_hwcap2 & (1 << j))
257 seq_printf(m, " %s", compat_hwcap2_str[j]);
258 #endif /* CONFIG_COMPAT */
259 } else {
260 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
261 if (cpu_have_feature(j))
262 seq_printf(m, " %s", hwcap_str[j]);
263 }
264 seq_puts(m, "\n");
265
266 seq_printf(m, "CPU implementer\t: 0x%02x\n",
267 MIDR_IMPLEMENTOR(midr));
268 seq_printf(m, "CPU architecture: 8\n");
269 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
270 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
271 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
272 }
273
274 return 0;
275 }
276
c_start(struct seq_file * m,loff_t * pos)277 static void *c_start(struct seq_file *m, loff_t *pos)
278 {
279 return *pos < 1 ? (void *)1 : NULL;
280 }
281
c_next(struct seq_file * m,void * v,loff_t * pos)282 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
283 {
284 ++*pos;
285 return NULL;
286 }
287
c_stop(struct seq_file * m,void * v)288 static void c_stop(struct seq_file *m, void *v)
289 {
290 }
291
292 const struct seq_operations cpuinfo_op = {
293 .start = c_start,
294 .next = c_next,
295 .stop = c_stop,
296 .show = c_show
297 };
298
299
300 static const struct kobj_type cpuregs_kobj_type = {
301 .sysfs_ops = &kobj_sysfs_ops,
302 };
303
304 /*
305 * The ARM ARM uses the phrase "32-bit register" to describe a register
306 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
307 * no statement is made as to whether the upper 32 bits will or will not
308 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
309 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
310 *
311 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
312 * registers, we expose them both as 64 bit values to cater for possible
313 * future expansion without an ABI break.
314 */
315 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
316 #define CPUREGS_ATTR_RO(_name, _field) \
317 static ssize_t _name##_show(struct kobject *kobj, \
318 struct kobj_attribute *attr, char *buf) \
319 { \
320 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
321 \
322 if (info->reg_midr) \
323 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
324 else \
325 return 0; \
326 } \
327 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
328
329 CPUREGS_ATTR_RO(midr_el1, midr);
330 CPUREGS_ATTR_RO(revidr_el1, revidr);
331 CPUREGS_ATTR_RO(smidr_el1, smidr);
332
333 static struct attribute *cpuregs_id_attrs[] = {
334 &cpuregs_attr_midr_el1.attr,
335 &cpuregs_attr_revidr_el1.attr,
336 NULL
337 };
338
339 static const struct attribute_group cpuregs_attr_group = {
340 .attrs = cpuregs_id_attrs,
341 .name = "identification"
342 };
343
344 static struct attribute *sme_cpuregs_id_attrs[] = {
345 &cpuregs_attr_smidr_el1.attr,
346 NULL
347 };
348
349 static const struct attribute_group sme_cpuregs_attr_group = {
350 .attrs = sme_cpuregs_id_attrs,
351 .name = "identification"
352 };
353
cpuid_cpu_online(unsigned int cpu)354 static int cpuid_cpu_online(unsigned int cpu)
355 {
356 int rc;
357 struct device *dev;
358 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
359
360 dev = get_cpu_device(cpu);
361 if (!dev) {
362 rc = -ENODEV;
363 goto out;
364 }
365 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
366 if (rc)
367 goto out;
368 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
369 if (rc)
370 kobject_del(&info->kobj);
371 if (system_supports_sme())
372 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
373 out:
374 return rc;
375 }
376
cpuid_cpu_offline(unsigned int cpu)377 static int cpuid_cpu_offline(unsigned int cpu)
378 {
379 struct device *dev;
380 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
381
382 dev = get_cpu_device(cpu);
383 if (!dev)
384 return -ENODEV;
385 if (info->kobj.parent) {
386 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
387 kobject_del(&info->kobj);
388 }
389
390 return 0;
391 }
392
cpuinfo_regs_init(void)393 static int __init cpuinfo_regs_init(void)
394 {
395 int cpu, ret;
396
397 for_each_possible_cpu(cpu) {
398 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
399
400 kobject_init(&info->kobj, &cpuregs_kobj_type);
401 }
402
403 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
404 cpuid_cpu_online, cpuid_cpu_offline);
405 if (ret < 0) {
406 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
407 return ret;
408 }
409 return 0;
410 }
411 device_initcall(cpuinfo_regs_init);
412
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)413 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
414 {
415 unsigned int cpu = smp_processor_id();
416 u32 l1ip = CTR_L1IP(info->reg_ctr);
417
418 switch (l1ip) {
419 case CTR_EL0_L1Ip_PIPT:
420 break;
421 case CTR_EL0_L1Ip_VIPT:
422 default:
423 /* Assume aliasing */
424 set_bit(ICACHEF_ALIASING, &__icache_flags);
425 break;
426 }
427
428 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
429 }
430
__cpuinfo_store_cpu_32bit(struct cpuinfo_32bit * info)431 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
432 {
433 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
434 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
435 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
436 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
437 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
438 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
439 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
440 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
441 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
442 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
443 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
444 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
445 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
446 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
447 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
448 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
449 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
450 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
451
452 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
453 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
454 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
455 }
456
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)457 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
458 {
459 info->reg_cntfrq = arch_timer_get_cntfrq();
460 /*
461 * Use the effective value of the CTR_EL0 than the raw value
462 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
463 * with the CLIDR_EL1 fields to avoid triggering false warnings
464 * when there is a mismatch across the CPUs. Keep track of the
465 * effective value of the CTR_EL0 in our internal records for
466 * accurate sanity check and feature enablement.
467 */
468 info->reg_ctr = read_cpuid_effective_cachetype();
469 info->reg_dczid = read_cpuid(DCZID_EL0);
470 info->reg_midr = read_cpuid_id();
471 info->reg_revidr = read_cpuid(REVIDR_EL1);
472
473 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
474 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
475 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
476 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
477 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
478 info->reg_id_aa64isar3 = read_cpuid(ID_AA64ISAR3_EL1);
479 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
480 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
481 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
482 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
483 info->reg_id_aa64mmfr4 = read_cpuid(ID_AA64MMFR4_EL1);
484 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
485 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
486 info->reg_id_aa64pfr2 = read_cpuid(ID_AA64PFR2_EL1);
487 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
488 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
489 info->reg_id_aa64fpfr0 = read_cpuid(ID_AA64FPFR0_EL1);
490
491 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
492 info->reg_gmid = read_cpuid(GMID_EL1);
493
494 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
495 __cpuinfo_store_cpu_32bit(&info->aarch32);
496
497 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0))
498 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1);
499
500 if (IS_ENABLED(CONFIG_ARM64_SME) &&
501 id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
502 /*
503 * We mask out SMPS since even if the hardware
504 * supports priorities the kernel does not at present
505 * and we block access to them.
506 */
507 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
508 }
509
510 cpuinfo_detect_icache_policy(info);
511 }
512
cpuinfo_store_cpu(void)513 void cpuinfo_store_cpu(void)
514 {
515 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
516 __cpuinfo_store_cpu(info);
517 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
518 }
519
cpuinfo_store_boot_cpu(void)520 void __init cpuinfo_store_boot_cpu(void)
521 {
522 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
523 __cpuinfo_store_cpu(info);
524
525 boot_cpu_data = *info;
526 init_cpu_features(&boot_cpu_data);
527 }
528